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Merge pull request #1195 from hathach/fix-dwc2-XCVRDLY 

set DCFG_XCVRDLY when using external ULPI highspeed phy
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Ha Thach 2021-11-19 20:49:41 +07:00 committed by GitHub
parent 6f59a2ce6e 301d6b4133
commit 5d7e26d620
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 13 additions and 1 deletions
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10
src/portable/synopsys/dwc2/dcd_dwc2.c
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@ -443,7 +443,15 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
// Set max speed
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
uint32_t dcfg = dwc2->dcfg;
dcfg &= ~DCFG_DSPD_Msk;
dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
dwc2->dcfg = dcfg;
}
static bool check_dwc2(dwc2_regs_t * dwc2)

4
src/portable/synopsys/dwc2/dwc2_type.h
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@ -416,6 +416,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */
#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */
#define DCFG_XCVRDLY_Pos (14U)
#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp
#define DCFG_PERSCHIVL_Pos (24U)
#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */
#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */