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@ -70,13 +70,13 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
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return hw_endpoint_get_by_num(num, dir);
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return hw_endpoint_get_by_num(num, dir);
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}
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}
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static void _hw_endpoint_alloc(struct hw_endpoint *ep)
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static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
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{
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{
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// size must be multiple of 64
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// size must be multiple of 64
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uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
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uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
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// double buffered for Control and Bulk endpoint
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// double buffered for Control and Bulk endpoint
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if ( ep->transfer_type == TUSB_XFER_CONTROL || ep->transfer_type == TUSB_XFER_BULK)
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if ( transfer_type == TUSB_XFER_CONTROL || transfer_type == TUSB_XFER_BULK )
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{
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{
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size *= 2u;
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size *= 2u;
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}
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}
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@ -96,7 +96,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
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ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
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ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
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// Fill in endpoint control register with buffer offset
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// Fill in endpoint control register with buffer offset
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uint32_t const reg = EP_CTRL_ENABLE_BITS | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
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uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
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*ep->endpoint_control = reg;
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*ep->endpoint_control = reg;
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}
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}
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@ -177,7 +177,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
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// TODO device may change configuration (dynamic), should clear and reallocate
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// TODO device may change configuration (dynamic), should clear and reallocate
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if ( !(ep->configured) )
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if ( !(ep->configured) )
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{
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{
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_hw_endpoint_alloc(ep);
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_hw_endpoint_alloc(ep, transfer_type);
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}
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}
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}
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}
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