more clean up

This commit is contained in:
hathach 2018-03-02 14:14:32 +07:00
parent 4e9272e68a
commit 4c61471939
16 changed files with 11 additions and 1157 deletions

View File

@ -86,7 +86,7 @@
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@ -180,7 +180,7 @@
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@ -230,7 +230,7 @@
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@ -282,7 +282,7 @@
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@ -375,7 +375,7 @@
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@ -472,7 +472,7 @@
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<entry excluding="hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/sdio.c|hw/mcu/nxp/lpc43xx/keil|hw/mcu/nxp/lpc175x_6x|hw/mcu/nxp/lpc13uxx|hw/mcu/nxp/lpc11uxx|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_sct.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_emc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/debug_frmwrk.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpdma.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_adc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_lcd.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2s.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_wwdt.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_rtc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/Font5x7.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdmmc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_evrt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_ssp.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/Font5x7.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/LCDTerm.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_ssp.c|mcu/lpc13uxx|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rgu.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdif.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/LCDTerm.c|mcu/lpc175x_6x|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sct.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/debug_frmwrk.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rtc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/sdio.c|mcu/lpc11uxx|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_evrt.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_gpdma.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_adc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_i2s.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_wwdt.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_timer.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_dac.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_can.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_qei.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rit.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_pwr.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_atimer.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_dac.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_can.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_qei.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_rit.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_lcd.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/sdio.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_atimer.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

View File

@ -46,7 +46,7 @@
#ifndef _TUSB_CDCD_DEVICE_APP_H_
#define _TUSB_CDCD_DEVICE_APP_H_
#include "board.h"
#include "bsp/board.h"
#include "tusb.h"
#ifdef __cplusplus

View File

@ -46,7 +46,7 @@
#ifndef _TUSB_KEYBOARDD_DEVICE_APP_H_
#define _TUSB_KEYBOARDD_DEVICE_APP_H_
#include "board.h"
#include "bsp/board.h"
#include "tusb.h"
#ifdef __cplusplus

View File

@ -43,7 +43,7 @@
#include <stdio.h>
#include <string.h>
#include "board.h"
#include "bsp/board.h"
#include "tusb.h"
#include "msc_device_app.h"

View File

@ -46,7 +46,7 @@
#ifndef _TUSB_MOUSED_DEVICE_APP_H_
#define _TUSB_MOUSED_DEVICE_APP_H_
#include "board.h"
#include "bsp/board.h"
#include "tusb.h"
#ifdef __cplusplus

View File

@ -43,7 +43,7 @@
#ifndef _TUSB_MSCD_DEVICE_APP_H_
#define _TUSB_MSCD_DEVICE_APP_H_
#include "board.h"
#include "bsp/board.h"
#include "tusb.h"
#ifdef __cplusplus

View File

@ -1,196 +0,0 @@
/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2009 IAR Systems. All rights reserved.
*
* $Revision: 47021 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD __iar_program_start ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Ha dler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
SECTION .text:CODE:REORDER:NOROOT(1)
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK FLEX_INT0_IRQHandler
PUBWEAK FLEX_INT1_IRQHandler
PUBWEAK FLEX_INT2_IRQHandler
PUBWEAK FLEX_INT3_IRQHandler
PUBWEAK FLEX_INT4_IRQHandler
PUBWEAK FLEX_INT5_IRQHandler
PUBWEAK FLEX_INT6_IRQHandler
PUBWEAK FLEX_INT7_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK SSP1_IRQHandler
PUBWEAK I2C_IRQHandler
PUBWEAK TIMER16_0_IRQHandler
PUBWEAK TIMER16_1_IRQHandler
PUBWEAK TIMER32_0_IRQHandler
PUBWEAK TIMER32_1_IRQHandler
PUBWEAK SSP0_IRQHandler
PUBWEAK UART_IRQHandler
PUBWEAK USB_IRQHandler
PUBWEAK USB_FIQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK BOD_IRQHandler
PUBWEAK FMC_IRQHandler
PUBWEAK USBWakeup_IRQHandler
PUBWEAK Reserved_IRQHandler
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
Reserved_IRQHandler
Default_Handler:
B Default_Handler
SECTION .crp:CODE:ROOT(2)
DATA
/* Code Read Protection
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
- Copy RAM to flash command can not write to Sector 0.
- Erase command can erase Sector 0 only when all sectors
are selected for erase.
- Compare command is disabled.
- Read Memory command is disabled.
CRP2 0x87654321 - Read Memory is disabled.
- Write to RAM is disabled.
- "Go" command is disabled.
- Copy RAM to flash is disabled.
- Compare is disabled.
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
by pulling PIO0_1 LOW is disabled if a valid user code is
present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
DCD 0xFFFFFFFF
END

View File

@ -1,168 +0,0 @@
/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2012 IAR Systems. All rights reserved.
*
* $Revision: 50057 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD __iar_program_start ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD FLEX_INT0_IRQHandler ; GPIO pin interrupt 0
DCD FLEX_INT1_IRQHandler ; GPIO pin interrupt 1
DCD FLEX_INT2_IRQHandler ; GPIO pin interrupt 2
DCD FLEX_INT3_IRQHandler ; GPIO pin interrupt 3
DCD FLEX_INT4_IRQHandler ; GPIO pin interrupt 4
DCD FLEX_INT5_IRQHandler ; GPIO pin interrupt 5
DCD FLEX_INT6_IRQHandler ; GPIO pin interrupt 6
DCD FLEX_INT7_IRQHandler ; GPIO pin interrupt 7
DCD GINT0_IRQHandler ; GPIO GROUP0 interrupt
DCD GINT1_IRQHandler ; GPIO GROUP1 interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SSP1_IRQHandler ; SSP1 interrupt
DCD I2C_IRQHandler ; I2C interrupt
DCD CT16B0_IRQHandler ; CT16B0 Match 0-3, Capture 0
DCD CT16B1_IRQHandler ; CT16B1 Match 0-3, Capture 0
DCD CT32B0_IRQHandler ; CT32B0 Match 0-3, Capture 0
DCD CT32B1_IRQHandler ; CT32B1 Match 0-3, Capture 0
DCD SSP0_IRQHandler ; SSP0 interrupt
DCD USART_IRQHandler ; USART interrupt
DCD USB_IRQHandler ; USB_IRQ interrupt
DCD USB_FIQHandler ; USB_FIQ interrupt
DCD ADC_IRQHandler ; ADC interrupt
DCD WWDT_IRQHandler ; WWDT interrupt
DCD BOD_IRQHandler ; BOD interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USBWakeup_IRQHandler ; USB_WAKEUP interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK FLEX_INT0_IRQHandler
PUBWEAK FLEX_INT1_IRQHandler
PUBWEAK FLEX_INT2_IRQHandler
PUBWEAK FLEX_INT3_IRQHandler
PUBWEAK FLEX_INT4_IRQHandler
PUBWEAK FLEX_INT5_IRQHandler
PUBWEAK FLEX_INT6_IRQHandler
PUBWEAK FLEX_INT7_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK SSP1_IRQHandler
PUBWEAK I2C_IRQHandler
PUBWEAK CT16B0_IRQHandler
PUBWEAK CT16B1_IRQHandler
PUBWEAK CT32B0_IRQHandler
PUBWEAK CT32B1_IRQHandler
PUBWEAK SSP0_IRQHandler
PUBWEAK USART_IRQHandler
PUBWEAK USB_IRQHandler
PUBWEAK USB_FIQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK BOD_IRQHandler
PUBWEAK USBWakeup_IRQHandler
SECTION .text:CODE:REORDER(1)
THUMB
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WWDT_IRQHandler
BOD_IRQHandler
USBWakeup_IRQHandler
Default_Handler
B Default_Handler
END

View File

@ -1,356 +0,0 @@
;/*****************************************************************************
; * @file: startup_LPC17xx.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC17xx Device Series
; * @version: V1.03
; * @date: 09. February 2010
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD SPI_IRQHandler ; 29: SPI
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
PUBLIC CRP_Value
RSEG CRPKEY :CODE(2)
CRP_Value
DCD 0xFFFFFFFF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER(1)
WDT_IRQHandler
B WDT_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK UART2_IRQHandler
SECTION .text:CODE:REORDER(1)
UART2_IRQHandler
B UART2_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK PWM1_IRQHandler
SECTION .text:CODE:REORDER(1)
PWM1_IRQHandler
B PWM1_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK SPI_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI_IRQHandler
B SPI_IRQHandler
PUBWEAK SSP0_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP0_IRQHandler
B SSP0_IRQHandler
PUBWEAK SSP1_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP1_IRQHandler
B SSP1_IRQHandler
PUBWEAK PLL0_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL0_IRQHandler
B PLL0_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK BOD_IRQHandler
SECTION .text:CODE:REORDER(1)
BOD_IRQHandler
B BOD_IRQHandler
PUBWEAK USB_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_IRQHandler
B USB_IRQHandler
PUBWEAK CAN_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN_IRQHandler
B CAN_IRQHandler
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK I2S_IRQHandler
SECTION .text:CODE:REORDER(1)
I2S_IRQHandler
B I2S_IRQHandler
PUBWEAK ENET_IRQHandler
SECTION .text:CODE:REORDER(1)
ENET_IRQHandler
B ENET_IRQHandler
PUBWEAK RIT_IRQHandler
SECTION .text:CODE:REORDER(1)
RIT_IRQHandler
B RIT_IRQHandler
PUBWEAK MCPWM_IRQHandler
SECTION .text:CODE:REORDER(1)
MCPWM_IRQHandler
B MCPWM_IRQHandler
PUBWEAK QEI_IRQHandler
SECTION .text:CODE:REORDER(1)
QEI_IRQHandler
B QEI_IRQHandler
PUBWEAK PLL1_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL1_IRQHandler
B PLL1_IRQHandler
PUBWEAK USBActivity_IRQHandler
SECTION .text:CODE:REORDER(1)
USBActivity_IRQHandler
B USBActivity_IRQHandler
PUBWEAK CANActivity_IRQHandler
SECTION .text:CODE:REORDER(1)
CANActivity_IRQHandler
B CANActivity_IRQHandler
END

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@ -1,9 +0,0 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\..\..\..\mcu\lpc43xx\iar\FlashLPC18xx_43xx_SPIFI.flash</loader>
</pass>
</flash_board>

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@ -1,10 +0,0 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\..\..\mcu\lpc43xx\iar\FlashLPC18xx_43xx_SPIFI.out</exe>
<page>256</page>
<block>1 0x4000000</block>
<flash_base>0x14000000</flash_base>
<macro>$PROJ_DIR$\..\..\..\mcu\lpc43xx\iar\FlashLPC18xx_43xx_SPIFI.mac</macro>
<aggregate>1</aggregate>
</flash_device>

View File

@ -1,31 +0,0 @@
__Setup()
{
/* set SPIFI clock */
//LPC_CGU->BASE_SPIFI0_CLK = 1<<24 | 1<<11; /* IRC 12 MHz is good enough for us */
__writeMemory32( 1<<24 | 1<<11, 0x40051304, "Memory");
//LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
__writeMemory32( 0xF3, 0x4008618C, "Memory");
/* IO pins */
//LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
__writeMemory32( 0xD3, 0x40086190, "Memory");
__writeMemory32( 0xD3, 0x40086194, "Memory");
__writeMemory32( 0xD3, 0x40086198, "Memory");
__writeMemory32( 0xD3, 0x4008619C, "Memory");
//LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
__writeMemory32( 0x13, 0x400861A0, "Memory");
__writeMemory32(0x14000000, 0x40043100, "Memory"); // map SPIFI to shadow area at address 0
}
execUserReset()
{
__message "----- execUserReset\n";
__Setup();
}
execUserFlashInit(){
__message "----- execUserFlashInit\n";
__Setup();
}

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@ -1,18 +0,0 @@
__Setup(){
__writeMemory32((int)&__vector_table, 0x40043100, "Memory"); // map BootArea to shadow area at address 0
__writeMemory32((int)&__vector_table, 0xE000ED08, "Memory"); // map BootArea to shadow area at address 0
__message "Memory at: ", &__vector_table, " mapped to 0x00000000\n";
}
execUserReset()
{
__message "execUserReset\n";
__Setup();
__message "execUserReset Finish\n";
}
execUserFlashInit(){
__message "execUserFlashInit\n";
__Setup();
__message "execUserFlashInit Finish\n";
}

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@ -1,60 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x14000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x14000140;
define symbol __ICFEDIT_region_ROM_end__ = 0x1407FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x1001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
/********** Local SRAM Region **********/
define symbol LOCAL_SRAM_start__ = 0x10080000;
define symbol LOCAL_SRAM_end__ = 0x1008FFFF;
/** Power-Down preserved Local SRAM Region **/
define symbol PD_LOCAL_SRAM_start__ = 0x10090000;
define symbol PD_LOCAL_SRAM_end__ = 0x10091FFF;
/********** AHB SRAM Region 1 **********/
define symbol AHB_SRAM1_start__ = 0x20000000;
define symbol AHB_SRAM1_end__ = 0x20007FFF;
/********** AHB SRAM Region 2 **********/
define symbol AHB_SRAM2_start__ = 0x20008000;
define symbol AHB_SRAM2_end__ = 0x2000BFFF;
/********* ETB/AHB SRAM Region *********/
define symbol ETB_SRAM_start__ = 0x2000C000;
define symbol ETB_SRAM_end__ = 0x2000FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region LOCAL_SRAM_region = mem:[from LOCAL_SRAM_start__ to LOCAL_SRAM_end__];
define region PD_LOCAL_SRAM_region = mem:[from PD_LOCAL_SRAM_start__ to PD_LOCAL_SRAM_end__];
define region AHB_SRAM1_region = mem:[from AHB_SRAM1_start__ to AHB_SRAM1_end__];
define region AHB_SRAM2_region = mem:[from AHB_SRAM2_start__ to AHB_SRAM2_end__];
define region ETB_SRAM_region = mem:[from ETB_SRAM_start__ to ETB_SRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in LOCAL_SRAM_region { section .local_sram };
place in PD_LOCAL_SRAM_region { section .pd_local_sram };
place in AHB_SRAM2_region { section .ahb_sram2 };
place in ETB_SRAM_region { section .etb_sram };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

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@ -1,298 +0,0 @@
/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2011 IAR Systems. All rights reserved.
*
* $Revision: 50291 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 CortexM0
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD 0 ; 19 Reserved
DCD 0 ; 20 Reserved
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RITIMER_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 Reserved
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD USART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPIFI
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVENTROUTER_IRQHandler ; 58 Event Router
DCD C_CAN1_IRQHandler ; 59 CCAN1
DCD 0
DCD 0
DCD ATIMER_IRQHandler ; 62 Alarm Timer
DCD RTC_IRQHandler ; 63 RTC
DCD 0
DCD WWDT_IRQHandler ; 65 WWDT
DCD 0
DCD C_CAN0_IRQHandler ; 67 CCAN0
DCD QEI_IRQHandler ; 68 QEI
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK DAC_IRQHandler
PUBWEAK M0CORE_IRQHandler
PUBWEAK DMA_IRQHandler
PUBWEAK ETH_IRQHandler
PUBWEAK SDIO_IRQHandler
PUBWEAK LCD_IRQHandler
PUBWEAK USB0_IRQHandler
PUBWEAK USB1_IRQHandler
PUBWEAK SCT_IRQHandler
PUBWEAK RITIMER_IRQHandler
PUBWEAK TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
PUBWEAK MCPWM_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK SPI_IRQHandler
PUBWEAK ADC1_IRQHandler
PUBWEAK SSP0_IRQHandler
PUBWEAK SSP1_IRQHandler
PUBWEAK USART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK I2S0_IRQHandler
PUBWEAK I2S1_IRQHandler
PUBWEAK SPIFI_IRQHandler
PUBWEAK SGPIO_IRQHandler
PUBWEAK GPIO0_IRQHandler
PUBWEAK GPIO1_IRQHandler
PUBWEAK GPIO2_IRQHandler
PUBWEAK GPIO3_IRQHandler
PUBWEAK GPIO4_IRQHandler
PUBWEAK GPIO5_IRQHandler
PUBWEAK GPIO6_IRQHandler
PUBWEAK GPIO7_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK EVENTROUTER_IRQHandler
PUBWEAK C_CAN1_IRQHandler
PUBWEAK ATIMER_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK C_CAN0_IRQHandler
PUBWEAK QEI_IRQHandler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
SVC_Handler
B SVC_Handler
DebugMon_Handler
B DebugMon_Handler
PendSV_Handler
B PendSV_Handler
SysTick_Handler
B SysTick_Handler
HardFault_Handler
B HardFault_Handler
MemManage_Handler
B MemManage_Handler
BusFault_Handler
B BusFault_Handler
UsageFault_Handler
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
Default_IRQHandler
B Default_IRQHandler
THUMB
PUBLIC getPC
SECTION .text:CODE:REORDER(2)
getPC
MOV R0,LR
BX LR
/* CRP Section - not needed for flashless devices */
;;; SECTION .crp:CODE:ROOT(2)
;;; DATA
/* Code Read Protection
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
- Copy RAM to flash command can not write to Sector 0.
- Erase command can erase Sector 0 only when all sectors
are selected for erase.
- Compare command is disabled.
- Read Memory command is disabled.
CRP2 0x87654321 - Read Memory is disabled.
- Write to RAM is disabled.
- "Go" command is disabled.
- Copy RAM to flash is disabled.
- Compare is disabled.
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
by pulling PIO0_1 LOW is disabled if a valid user code is
present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
;;; DCD 0xFFFFFFFF
;;;
END