correct ohci endpoint address in xfer complete
This commit is contained in:
hathach
parent
4e98ce9147
commit
31077f48d2
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@ -123,6 +123,23 @@ enum {
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OHCI_INT_ON_COMPLETE_YES = 0,
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OHCI_INT_ON_COMPLETE_NO = TU_BIN8(111)
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};
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enum {
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GTD_DT_TOGGLE_CARRY = 0,
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GTD_DT_DATA0 = TU_BIT(1) | 0,
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GTD_DT_DATA1 = TU_BIT(1) | 1,
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};
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enum {
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PID_SETUP = 0,
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PID_OUT,
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PID_IN,
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};
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enum {
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PID_FROM_TD = 0,
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};
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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@ -185,10 +202,10 @@ bool hcd_init(uint8_t rhport)
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return true;
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}
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uint32_t hcd_uframe_number(uint8_t rhport)
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uint32_t hcd_frame_number(uint8_t rhport)
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{
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(void) rhport;
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return (ohci_data.frame_number_hi << 16 | OHCI_REG->frame_number) << 3;
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return (ohci_data.frame_number_hi << 16) | OHCI_REG->frame_number;
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}
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@ -248,12 +265,12 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
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//--------------------------------------------------------------------+
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
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{
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return (p_ed->ep_number == 0 ) ? TUSB_XFER_CONTROL :
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(p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
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(p_ed->is_interrupt_xfer ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
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return (p_ed->ep_number == 0 ) ? TUSB_XFER_CONTROL :
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(p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
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(p_ed->is_interrupt_xfer) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
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}
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static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval)
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static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t ep_addr, uint8_t xfer_type, uint8_t interval)
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{
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(void) interval;
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@ -263,18 +280,18 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size,
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tu_memclr(p_ed, sizeof(ohci_ed_t));
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}
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p_ed->dev_addr = dev_addr;
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p_ed->ep_number = endpoint_addr & 0x0F;
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p_ed->pid = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_IN_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
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p_ed->dev_addr = dev_addr;
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p_ed->ep_number = ep_addr & 0x0F;
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p_ed->pid = (xfer_type == TUSB_XFER_CONTROL) ? PID_FROM_TD : (tu_edpt_dir(ep_addr) ? PID_IN : PID_OUT);
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p_ed->speed = _usbh_devices[dev_addr].speed;
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p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
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p_ed->max_packet_size = max_packet_size;
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p_ed->max_packet_size = ep_size;
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p_ed->used = 1;
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p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
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}
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static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
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static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
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{
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tu_memclr(p_td, sizeof(ohci_gtd_t));
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@ -286,28 +303,7 @@ static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
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p_td->condition_code = OHCI_CCODE_NOT_ACCESSED;
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p_td->current_buffer_pointer = data_ptr;
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p_td->buffer_end = total_bytes ? (((uint8_t*) data_ptr) + total_bytes-1) : NULL;
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}
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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(void) rhport;
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ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;
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ohci_gtd_t *p_setup = &ohci_data.control[dev_addr].gtd;
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gtd_init(p_setup, (void*) setup_packet, 8);
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p_setup->index = dev_addr;
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p_setup->pid = OHCI_PID_SETUP;
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p_setup->data_toggle = TU_BIN8(10); // DATA0
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p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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//------------- Attach TDs list to Control Endpoint -------------//
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p_ed->td_head.address = (uint32_t) p_setup;
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OHCI_REG->command_status_bit.control_list_filled = 1;
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return true;
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p_td->buffer_end = total_bytes ? (data_ptr + total_bytes-1) : data_ptr;
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}
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static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
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@ -319,7 +315,7 @@ static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
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for(uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
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{
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if ( (ed_pool[i].dev_addr == dev_addr) &&
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ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == OHCI_PID_IN) )
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ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == PID_IN) )
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{
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return &ed_pool[i];
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}
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@ -430,6 +426,27 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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return true;
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}
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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(void) rhport;
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ohci_ed_t* ed = &ohci_data.control[dev_addr].ed;
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ohci_gtd_t *qtd = &ohci_data.control[dev_addr].gtd;
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gtd_init(qtd, (uint8_t*) setup_packet, 8);
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qtd->index = dev_addr;
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qtd->pid = PID_SETUP;
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qtd->data_toggle = GTD_DT_DATA0;
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qtd->delay_interrupt = 0;
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//------------- Attach TDs list to Control Endpoint -------------//
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ed->td_head.address = (uint32_t) qtd;
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OHCI_REG->command_status_bit.control_list_filled = 1;
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return true;
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}
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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(void) rhport;
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@ -437,7 +454,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// FIXME control only for now
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if ( epnum == 0 )
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{
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ohci_ed_t* ed = &ohci_data.control[dev_addr].ed;
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@ -446,9 +462,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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gtd_init(gtd, buffer, buflen);
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gtd->index = dev_addr;
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gtd->pid = dir ? OHCI_PID_IN : OHCI_PID_OUT;
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gtd->data_toggle = 3; // Both Data and Ack stage start with DATA1
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gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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gtd->pid = dir ? PID_IN : PID_OUT;
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gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
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gtd->delay_interrupt = 0;
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ed->td_head.address = (uint32_t) gtd;
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@ -462,7 +478,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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gtd_init(gtd, buffer, buflen);
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gtd->index = ed-ohci_data.ed_pool;
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gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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gtd->delay_interrupt = 0;
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td_insert_to_ed(ed, gtd);
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@ -539,7 +555,12 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
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}
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static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
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{ // 5.2.9 OHCI sample code
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{
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// 5.2.9 OHCI sample code
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// CBP is 0 mean all data is transferred
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if (current_buffer == 0) return 0;
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return (tu_align4k(buffer_end ^ current_buffer) ? 0x1000 : 0) +
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tu_offset4k(buffer_end) - tu_offset4k(current_buffer) + 1;
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}
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@ -555,16 +576,16 @@ static void done_queue_isr(uint8_t hostid)
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{
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// TODO check if td_head is iso td
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//------------- Non ISO transfer -------------//
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ohci_gtd_t * const p_qtd = (ohci_gtd_t *) td_head;
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xfer_result_t const event = (p_qtd->condition_code == OHCI_CCODE_NO_ERROR) ? XFER_RESULT_SUCCESS :
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(p_qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
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ohci_gtd_t * const qtd = (ohci_gtd_t *) td_head;
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xfer_result_t const event = (qtd->condition_code == OHCI_CCODE_NO_ERROR) ? XFER_RESULT_SUCCESS :
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(qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
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p_qtd->used = 0; // free TD
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if ( (p_qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
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qtd->used = 0; // free TD
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if ( (qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
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{
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ohci_ed_t * const p_ed = gtd_get_ed(p_qtd);
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ohci_ed_t * const ed = gtd_get_ed(qtd);
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uint32_t const xferred_bytes = p_qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) p_qtd->buffer_end, (uint32_t) p_qtd->current_buffer_pointer);
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uint32_t const xferred_bytes = qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
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// NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
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// When there is a error resulting this ED is halted, and this EP still has other queued TD
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@ -575,14 +596,14 @@ static void done_queue_isr(uint8_t hostid)
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// the TailP must be set back to NULL for processing remaining TDs
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if ((event != XFER_RESULT_SUCCESS))
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{
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p_ed->td_tail &= 0x0Ful;
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p_ed->td_tail |= tu_align16(p_ed->td_head.address); // mark halted EP as empty queue
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if ( event == XFER_RESULT_STALLED ) p_ed->is_stalled = 1;
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ed->td_tail &= 0x0Ful;
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ed->td_tail |= tu_align16(ed->td_head.address); // mark halted EP as empty queue
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if ( event == XFER_RESULT_STALLED ) ed->is_stalled = 1;
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}
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hcd_event_xfer_complete(p_ed->dev_addr,
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tu_edpt_addr(p_ed->ep_number, p_ed->pid == OHCI_PID_IN),
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xferred_bytes, event, true);
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uint8_t dir = (ed->ep_number == 0) ? (qtd->pid == PID_IN) : (ed->pid == PID_IN);
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hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
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}
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td_head = (ohci_td_item_t*) td_head->next;
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@ -631,7 +652,7 @@ void hcd_int_handler(uint8_t hostid)
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}
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//------------- Transfer Complete -------------//
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if ( int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK)
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if (int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK)
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{
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done_queue_isr(hostid);
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}
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@ -24,12 +24,6 @@
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* This file is part of the TinyUSB stack.
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*/
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/** \ingroup Group_HCD
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* @{
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* \defgroup OHCI
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* \brief OHCI driver. All documents sources mentioned here (eg section 3.5) is referring to OHCI Specs unless state otherwise
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* @{ */
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#ifndef _TUSB_OHCI_H_
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#define _TUSB_OHCI_H_
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@ -48,12 +42,6 @@ enum {
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OHCI_MAX_ITD = 4
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};
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enum {
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OHCI_PID_SETUP = 0,
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OHCI_PID_OUT,
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OHCI_PID_IN,
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};
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//--------------------------------------------------------------------+
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// OHCI Data Structure
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//--------------------------------------------------------------------+
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@ -73,7 +61,6 @@ typedef struct {
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uint32_t reserved2;
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}ohci_td_item_t;
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typedef struct TU_ATTR_ALIGNED(16)
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{
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// Word 0
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@ -105,7 +92,7 @@ typedef struct TU_ATTR_ALIGNED(16)
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// Word 0
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uint32_t dev_addr : 7;
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uint32_t ep_number : 4;
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uint32_t pid : 2; // 00b from TD, 01b Out, 10b In
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uint32_t pid : 2;
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uint32_t speed : 1;
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uint32_t skip : 1;
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uint32_t is_iso : 1;
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@ -286,6 +273,3 @@ TU_VERIFY_STATIC( sizeof(ohci_registers_t) == 0x5c, "size is not correct");
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#endif
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#endif /* _TUSB_OHCI_H_ */
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/** @} */
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/** @} */
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