Merge pull request #959 from KarlK90/gd32vf103-support-tiny-usb
[PORT] Add GD32VF103 support and Sipeed Longan Nano Board support
This commit is contained in:
Ha Thach
GitHub
commit
2bb63406e9
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@ -16,6 +16,7 @@ jobs:
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family:
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# Alphabetical order
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- 'fomu'
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- 'gd32vf103'
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steps:
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- name: Setup Python
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uses: actions/setup-python@v2
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@ -124,3 +124,6 @@
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[submodule "hw/mcu/mindmotion/mm32sdk"]
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path = hw/mcu/mindmotion/mm32sdk
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url = https://github.com/zhangslice/mm32sdk.git
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[submodule "hw/mcu/gd/nuclei-sdk"]
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path = hw/mcu/gd/nuclei-sdk
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url = https://github.com/Nuclei-Software/nuclei-sdk.git
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@ -150,11 +150,14 @@ extern uint32_t SystemCoreClock;
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//--------------------------------------------------------------------+
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// Interrupt nesting behavior configuration.
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//--------------------------------------------------------------------+
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/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in core_cmx.h */
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#ifdef __NVIC_PRIO_BITS
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#if defined(__NVIC_PRIO_BITS)
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// For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#elif defined(__ECLIC_INTCTLBITS)
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// RISC-V Bumblebee core from nuclei
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#define configPRIO_BITS __ECLIC_INTCTLBITS
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#else
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#error "This port requires __NVIC_PRIO_BITS to be defined"
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#error "FreeRTOS configPRIO_BITS to be defined"
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#endif
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/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
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@ -150,11 +150,14 @@ extern uint32_t SystemCoreClock;
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//--------------------------------------------------------------------+
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// Interrupt nesting behavior configuration.
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//--------------------------------------------------------------------+
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/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in core_cmx.h */
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#ifdef __NVIC_PRIO_BITS
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#if defined(__NVIC_PRIO_BITS)
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// For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#elif defined(__ECLIC_INTCTLBITS)
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// RISC-V Bumblebee core from nuclei
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#define configPRIO_BITS __ECLIC_INTCTLBITS
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#else
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#error "This port requires __NVIC_PRIO_BITS to be defined"
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#error "FreeRTOS configPRIO_BITS to be defined"
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#endif
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/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
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@ -130,6 +130,9 @@
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#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
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// no header needed
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#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
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#include "gd32vf103.h"
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#else
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#error "Missing MCU header"
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#endif
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@ -5,7 +5,7 @@ CFLAGS += \
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-nostdlib \
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-DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
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# Cross Compiler for RISC-V
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
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CROSS_COMPILE = riscv-none-embed-
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# All source paths should be relative to the top level.
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@ -0,0 +1,20 @@
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#ifndef _NUCLEI_SDK_HAL_H
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#define _NUCLEI_SDK_HAL_H
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#include "gd32vf103c_longan_nano.h"
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// 4 bits for interrupt level, 0 for priority.
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// level 0 = lowest priority, level 15 = highest priority.
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#define __ECLIC_INTCTLBITS 4
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#define __SYSTEM_CLOCK 72000000
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#define HXTAL_VALUE ((uint32_t)8000000)
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#define SOC_DEBUG_UART GD32_COM0
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#define DBG_KEY_UNLOCK 0x4B5A6978
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#define DBG_CMD_RESET 0x1
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#define DBG_KEY REG32(DBG + 0x0C)
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#define DBG_CMD REG32(DBG + 0x08)
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#endif
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@ -0,0 +1,13 @@
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LONGAN_NANO_SDK_BSP = $(GD32VF103_SDK_SOC)/Board/gd32vf103c_longan_nano
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LINKER_SCRIPTS = $(LONGAN_NANO_SDK_BSP)/Source/GCC
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# All source paths should be relative to the top level.
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LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
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#LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM
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SRC_C += $(LONGAN_NANO_SDK_BSP)/Source/gd32vf103c_longan_nano.c
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INC += $(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
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# Longan Nano 128k ROM 32k RAM
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JLINK_DEVICE = gd32vf103cbt6
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#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
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@ -0,0 +1,197 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "board.h"
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#include "drv_usb_hw.h"
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#include "drv_usb_dev.h"
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#include "../board.h"
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void USBFS_IRQHandler(void) { tud_int_handler(0); }
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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#define USB_NO_VBUS_PIN
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// According to GD32VF103 user manual clock tree:
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// Systick clock = AHB clock / 4.
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#define TIMER_TICKS ((SystemCoreClock / 4) / 1000)
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#define BUTTON_PORT GPIOA
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#define BUTTON_PIN GPIO_PIN_0
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#define BUTTON_STATE_ACTIVE 1
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#define UART_DEV SOC_DEBUG_UART
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#define LED_PIN LED_R
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void board_init(void) {
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/* Disable interrupts during init */
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__disable_irq();
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#if CFG_TUSB_OS == OPT_OS_NONE
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SysTick_Config(TIMER_TICKS);
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#endif
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rcu_periph_clock_enable(RCU_GPIOA);
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rcu_periph_clock_enable(RCU_GPIOB);
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rcu_periph_clock_enable(RCU_GPIOC);
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rcu_periph_clock_enable(RCU_GPIOD);
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rcu_periph_clock_enable(RCU_AF);
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#ifdef BUTTON_PIN
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gpio_init(BUTTON_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, BUTTON_PIN);
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#endif
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#ifdef LED_PIN
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gd_led_init(LED_PIN);
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#endif
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#if defined(UART_DEV)
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gd_com_init(UART_DEV);
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#endif
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/* USB D+ and D- pins don't need to be configured. */
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/* Configure VBUS Pin */
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#ifndef USB_NO_VBUS_PIN
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gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
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#endif
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/* This for ID line debug */
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// gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
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/* Enable USB OTG clock */
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usb_rcu_config();
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/* Reset USB OTG peripheral */
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rcu_periph_reset_enable(RCU_USBFSRST);
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rcu_periph_reset_disable(RCU_USBFSRST);
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/* Configure USBFS IRQ */
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ECLIC_Register_IRQ(USBFS_IRQn, ECLIC_NON_VECTOR_INTERRUPT,
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ECLIC_POSTIVE_EDGE_TRIGGER, 3, 0, NULL);
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/* Retrieve otg core registers */
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usb_gr* otg_core_regs = (usb_gr*)(USBFS_REG_BASE + USB_REG_OFFSET_CORE);
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#ifdef USB_NO_VBUS_PIN
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/* Disable VBUS sense*/
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otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
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#else
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/* Enable VBUS sense via pin PA9 */
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otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
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otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
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#endif
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/* Enable interrupts globaly */
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__enable_irq();
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}
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void gd32vf103_reset(void) {
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/* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
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* register to generate a software reset request.
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* BUT instead two undocumented registers in the debug peripheral
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* that allow issueing a software reset.
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* https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h
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*/
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DBG_KEY = DBG_KEY_UNLOCK;
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DBG_CMD = DBG_CMD_RESET;
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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void board_led_write(bool state) {
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state ? gd_led_on(LED_PIN) : gd_led_off(LED_PIN);
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}
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uint32_t board_button_read(void) {
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return BUTTON_STATE_ACTIVE == gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN);
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}
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int board_uart_read(uint8_t* buf, int len) {
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#if defined(UART_DEV)
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int rxsize = len;
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while (rxsize--) {
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*(uint8_t*)buf = usart_read(UART_DEV);
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buf++;
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}
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return len;
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#else
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(void)buf;
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(void)len;
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return 0;
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#endif
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}
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int board_uart_write(void const* buf, int len) {
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#if defined(UART_DEV)
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int txsize = len;
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while (txsize--) {
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usart_write(UART_DEV, *(uint8_t*)buf);
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buf++;
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}
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return len;
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#else
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(void)buf;
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(void)len;
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return 0;
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#endif
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void eclic_mtip_handler(void) {
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system_ticks++;
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SysTick_Reload(TIMER_TICKS);
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}
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uint32_t board_millis(void) { return system_ticks; }
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#endif
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#ifdef USE_FULL_ASSERT
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/**
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* @brief Reports the name of the source file and the source line number
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* where the assert_param error has occurred.
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* @param file: pointer to the source file name
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* @param line: assert_param error line source number
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* @retval None
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*/
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void assert_failed(char* file, uint32_t line) {
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/* USER CODE BEGIN 6 */
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/* User can add his own implementation to report the file name and line
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number,
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tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
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*/
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/* USER CODE END 6 */
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}
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#endif /* USE_FULL_ASSERT */
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@ -0,0 +1,68 @@
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# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
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#CROSS_COMPILE ?= riscv32-unknown-elf-
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# Toolchain from https://nucleisys.com/download.php
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#CROSS_COMPILE ?= riscv-nuclei-elf-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
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CROSS_COMPILE ?= riscv-none-embed-
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# Submodules
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NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
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DEPS_SUBMODULES += $(NUCLEI_SDK)
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# Nuclei-SDK paths
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GD32VF103_SDK_SOC = $(NUCLEI_SDK)/SoC/gd32vf103
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GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC)/Common/Source/Drivers
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LIBC_STUBS = $(GD32VF103_SDK_SOC)/Common/Source/Stubs
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STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
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include $(TOP)/$(BOARD_PATH)/board.mk
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SKIP_NANOLIB = 1
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CFLAGS += \
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-march=rv32imac \
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-mabi=ilp32 \
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-mcmodel=medlow \
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-mstrict-align \
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-nostdlib -nostartfiles \
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-DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
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-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
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-DGD32VF103
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# mcu driver cause following warnings
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CFLAGS += -Wno-error=unused-parameter
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SRC_C += \
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src/portable/st/synopsys/dcd_synopsys.c \
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$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
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$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
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$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
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$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
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$(LIBC_STUBS)/sbrk.c \
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$(LIBC_STUBS)/close.c \
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$(LIBC_STUBS)/isatty.c \
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$(LIBC_STUBS)/fstat.c \
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$(LIBC_STUBS)/lseek.c \
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$(LIBC_STUBS)/read.c
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SRC_S += \
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$(STARTUP_ASM)/startup_gd32vf103.S \
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$(STARTUP_ASM)/intexc_gd32vf103.S
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INC += \
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$(TOP)/$(BOARD_PATH) \
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$(TOP)/$(NUCLEI_SDK)/NMSIS/Core/Include \
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$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include \
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$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
|
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# For freeRTOS port source
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FREERTOS_PORT = RISC-V
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# For flash-jlink target
|
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JLINK_IF = jtag
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# flash target ROM bootloader
|
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flash: $(BUILD)/$(PROJECT).bin
|
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dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
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@ -0,0 +1,668 @@
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/*!
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\file system_gd32vf103.h
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\brief RISC-V Device Peripheral Access Layer Source File for
|
||||
GD32VF103 Device Series
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
|
||||
#include "board.h"
|
||||
|
||||
/* system frequency define */
|
||||
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
|
||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
||||
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
|
||||
#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE)
|
||||
|
||||
#if !defined(__SYSTEM_CLOCK)
|
||||
#define __SYSTEM_CLOCK 72000000
|
||||
#endif
|
||||
|
||||
#if __SYSTEM_CLOCK == 48000000
|
||||
#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
|
||||
static void system_clock_48m_hxtal(void);
|
||||
|
||||
#elif __SYSTEM_CLOCK == 72000000
|
||||
#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
|
||||
static void system_clock_72m_hxtal(void);
|
||||
|
||||
#elif __SYSTEM_CLOCK == 96000000
|
||||
#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
|
||||
static void system_clock_96m_hxtal(void);
|
||||
|
||||
#else
|
||||
#error No valid system clock configuration set!
|
||||
#endif
|
||||
|
||||
/* configure the system clock */
|
||||
static void system_clock_config(void);
|
||||
|
||||
/*!
|
||||
\brief configure the system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_config(void)
|
||||
{
|
||||
#if defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
||||
system_clock_48m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
system_clock_72m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
|
||||
system_clock_96m_hxtal();
|
||||
#endif /* __SYSTEM_CLOCK_HXTAL */
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief setup the microcontroller system, initialize the system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* reset the RCC clock configuration to the default reset state */
|
||||
/* enable IRC8M */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
|
||||
RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
|
||||
|
||||
/* reset HXTALEN, CKMEN, PLLEN bits */
|
||||
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
|
||||
|
||||
/* Reset HXTALBPS bit */
|
||||
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
||||
|
||||
/* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
|
||||
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
|
||||
RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
|
||||
RCU_CFG1 = 0x00000000U;
|
||||
|
||||
/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
|
||||
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
|
||||
/* disable all interrupts */
|
||||
RCU_INT = 0x00FF0000U;
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
|
||||
system_clock_config();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t scss;
|
||||
uint32_t pllsel, predv0sel, pllmf, ck_src;
|
||||
uint32_t predv0, predv1, pll1mf;
|
||||
|
||||
scss = GET_BITS(RCU_CFG0, 2, 3);
|
||||
|
||||
switch (scss)
|
||||
{
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
case SEL_IRC8M:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_HXTAL:
|
||||
SystemCoreClock = HXTAL_VALUE;
|
||||
break;
|
||||
|
||||
/* PLL is selected as CK_SYS */
|
||||
case SEL_PLL:
|
||||
/* PLL clock source selection, HXTAL or IRC8M/2 */
|
||||
pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
|
||||
|
||||
|
||||
if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){
|
||||
/* PLL clock source is IRC8M/2 */
|
||||
ck_src = IRC8M_VALUE / 2U;
|
||||
}else{
|
||||
/* PLL clock source is HXTAL */
|
||||
ck_src = HXTAL_VALUE;
|
||||
|
||||
predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
|
||||
|
||||
/* source clock use PLL1 */
|
||||
if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
|
||||
predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
|
||||
pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
|
||||
if(17U == pll1mf){
|
||||
pll1mf = 20U;
|
||||
}
|
||||
ck_src = (ck_src / predv1) * pll1mf;
|
||||
}
|
||||
predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
|
||||
ck_src /= predv0;
|
||||
}
|
||||
|
||||
/* PLL multiplication factor */
|
||||
pllmf = GET_BITS(RCU_CFG0, 18, 21);
|
||||
|
||||
if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
|
||||
pllmf |= 0x10U;
|
||||
}
|
||||
|
||||
if(pllmf >= 15U){
|
||||
pllmf += 1U;
|
||||
}else{
|
||||
pllmf += 2U;
|
||||
}
|
||||
|
||||
SystemCoreClock = ck_src * pllmf;
|
||||
|
||||
if(15U == pllmf){
|
||||
/* PLL source clock multiply by 6.5 */
|
||||
SystemCoreClock = ck_src * 6U + ck_src / 2U;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
default:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_48m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12);
|
||||
|
||||
if(HXTAL_VALUE==25000000){
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
||||
}
|
||||
|
||||
}else if(HXTAL_VALUE==8000000){
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
|
||||
|
||||
|
||||
if(HXTAL_VALUE==25000000){
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
||||
}
|
||||
|
||||
}else if(HXTAL_VALUE==8000000){
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
|
||||
}
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_96m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
if(HXTAL_VALUE==25000000){
|
||||
|
||||
/* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
||||
}
|
||||
|
||||
}else if(HXTAL_VALUE==8000000){
|
||||
/* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
|
||||
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
|
||||
}
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \defgroup NMSIS_Core_IntExcNMI_Handling Interrupt and Exception and NMI Handling
|
||||
* \brief Functions for interrupt, exception and nmi handle available in system_<device>.c.
|
||||
* \details
|
||||
* Nuclei provide a template for interrupt, exception and NMI handling. Silicon Vendor could adapat according
|
||||
* to their requirement. Silicon vendor could implement interface for different exception code and
|
||||
* replace current implementation.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
/** \brief Max exception handler number, don't include the NMI(0xFFF) one */
|
||||
#define MAX_SYSTEM_EXCEPTION_NUM 12
|
||||
/**
|
||||
* \brief Store the exception handlers for each exception ID
|
||||
* \note
|
||||
* - This SystemExceptionHandlers are used to store all the handlers for all
|
||||
* the exception codes Nuclei N/NX core provided.
|
||||
* - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11]
|
||||
* - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]
|
||||
*/
|
||||
static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1];
|
||||
|
||||
/**
|
||||
* \brief Exception Handler Function Typedef
|
||||
* \note
|
||||
* This typedef is only used internal in this system_gd32vf103.c file.
|
||||
* It is used to do type conversion for registered exception handler before calling it.
|
||||
*/
|
||||
typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp);
|
||||
|
||||
/**
|
||||
* \brief System Default Exception Handler
|
||||
* \details
|
||||
* This function provided a default exception and NMI handling code for all exception ids.
|
||||
* By default, It will just print some information for debug, Vendor can customize it according to its requirements.
|
||||
*/
|
||||
static void system_default_exception_handler(unsigned long mcause, unsigned long sp)
|
||||
{
|
||||
/* TODO: Uncomment this if you have implement printf function */
|
||||
/*printf("MCAUSE: 0x%lx\r\n", mcause);
|
||||
printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
|
||||
printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MBADADDR));*/
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize all the default core exception handlers
|
||||
* \details
|
||||
* The core exception handler for each exception id will be initialized to \ref system_default_exception_handler.
|
||||
* \note
|
||||
* Called in \ref _init function, used to initialize default exception handlers for all exception IDs
|
||||
*/
|
||||
static void Exception_Init(void)
|
||||
{
|
||||
for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) {
|
||||
SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Register an exception handler for exception code EXCn
|
||||
* \details
|
||||
* * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will be registered into SystemExceptionHandlers[EXCn-1].
|
||||
* * For EXCn == NMI_EXCn, it will be registered into SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
|
||||
* \param EXCn See \ref EXCn_Type
|
||||
* \param exc_handler The exception handler for this exception code EXCn
|
||||
*/
|
||||
void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler)
|
||||
{
|
||||
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn != 0)) {
|
||||
SystemExceptionHandlers[EXCn] = exc_handler;
|
||||
} else if (EXCn == NMI_EXCn) {
|
||||
SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] = exc_handler;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get current exception handler for exception code EXCn
|
||||
* \details
|
||||
* * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will return SystemExceptionHandlers[EXCn-1].
|
||||
* * For EXCn == NMI_EXCn, it will return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
|
||||
* \param EXCn See \ref EXCn_Type
|
||||
* \return Current exception handler for exception code EXCn, if not found, return 0.
|
||||
*/
|
||||
unsigned long Exception_Get_EXC(uint32_t EXCn)
|
||||
{
|
||||
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn != 0)) {
|
||||
return SystemExceptionHandlers[EXCn];
|
||||
} else if (EXCn == NMI_EXCn) {
|
||||
return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Common NMI and Exception handler entry
|
||||
* \details
|
||||
* This function provided a command entry for NMI and exception. Silicon Vendor could modify
|
||||
* this template implementation according to requirement.
|
||||
* \remarks
|
||||
* - RISCV provided common entry for all types of exception. This is proposed code template
|
||||
* for exception entry function, Silicon Vendor could modify the implementation.
|
||||
* - For the core_exception_handler template, we provided exception register function \ref Exception_Register_EXC
|
||||
* which can help developer to register your exception handler for specific exception number.
|
||||
*/
|
||||
uint32_t core_exception_handler(unsigned long mcause, unsigned long sp)
|
||||
{
|
||||
uint32_t EXCn = (uint32_t)(mcause & 0X00000fff);
|
||||
EXC_HANDLER exc_handler;
|
||||
|
||||
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn > 0)) {
|
||||
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn];
|
||||
} else if (EXCn == NMI_EXCn) {
|
||||
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
|
||||
} else {
|
||||
exc_handler = (EXC_HANDLER)system_default_exception_handler;
|
||||
}
|
||||
if (exc_handler != NULL) {
|
||||
exc_handler(mcause, sp);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
|
||||
|
||||
/**
|
||||
* \brief initialize eclic config
|
||||
* \details
|
||||
* Eclic need initialize after boot up, Vendor could also change the initialization
|
||||
* configuration.
|
||||
*/
|
||||
void ECLIC_Init(void)
|
||||
{
|
||||
/* TODO: Add your own initialization code here. This function will be called by main */
|
||||
ECLIC_SetMth(0);
|
||||
ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize a specific IRQ and register the handler
|
||||
* \details
|
||||
* This function set vector mode, trigger mode and polarity, interrupt level and priority,
|
||||
* assign handler for specific IRQn.
|
||||
* \param [in] IRQn NMI interrupt handler address
|
||||
* \param [in] shv \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode
|
||||
* \param [in] trig_mode see \ref ECLIC_TRIGGER_Type
|
||||
* \param [in] lvl interupt level
|
||||
* \param [in] priority interrupt priority
|
||||
* \param [in] handler interrupt handler, if NULL, handler will not be installed
|
||||
* \return -1 means invalid input parameter. 0 means successful.
|
||||
* \remarks
|
||||
* - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
|
||||
* - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed
|
||||
*/
|
||||
int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler)
|
||||
{
|
||||
if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
|
||||
|| (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* set interrupt vector mode */
|
||||
ECLIC_SetShvIRQ(IRQn, shv);
|
||||
/* set interrupt trigger mode and polarity */
|
||||
ECLIC_SetTrigIRQ(IRQn, trig_mode);
|
||||
/* set interrupt level */
|
||||
ECLIC_SetLevelIRQ(IRQn, lvl);
|
||||
/* set interrupt priority */
|
||||
ECLIC_SetPriorityIRQ(IRQn, priority);
|
||||
if (handler != NULL) {
|
||||
/* set interrupt handler entry to vector table */
|
||||
ECLIC_SetVector(IRQn, (rv_csr_t)handler);
|
||||
}
|
||||
/* enable interrupt */
|
||||
ECLIC_EnableIRQ(IRQn);
|
||||
return 0;
|
||||
}
|
||||
/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
|
||||
|
||||
/**
|
||||
* \brief early init function before main
|
||||
* \details
|
||||
* This function is executed right before main function.
|
||||
* For RISC-V gnu toolchain, _init function might not be called
|
||||
* by __libc_init_array function, so we defined a new function
|
||||
* to do initialization
|
||||
*/
|
||||
void _premain_init(void)
|
||||
{
|
||||
/* Initialize exception default handlers */
|
||||
Exception_Init();
|
||||
/* ECLIC initialization, mainly MTH and NLBIT */
|
||||
ECLIC_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief finish function after main
|
||||
* \param [in] status status code return from main
|
||||
* \details
|
||||
* This function is executed right after main function.
|
||||
* For RISC-V gnu toolchain, _fini function might not be called
|
||||
* by __libc_fini_array function, so we defined a new function
|
||||
* to do initialization
|
||||
*/
|
||||
void _postmain_fini(int status)
|
||||
{
|
||||
/* TODO: Add your own finishing code here, called after main */
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief _init function called in __libc_init_array()
|
||||
* \details
|
||||
* This `__libc_init_array()` function is called during startup code,
|
||||
* user need to implement this function, otherwise when link it will
|
||||
* error init.c:(.text.__libc_init_array+0x26): undefined reference to `_init'
|
||||
* \note
|
||||
* Please use \ref _premain_init function now
|
||||
*/
|
||||
void _init(void)
|
||||
{
|
||||
/* Don't put any code here, please use _premain_init now */
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief _fini function called in __libc_fini_array()
|
||||
* \details
|
||||
* This `__libc_fini_array()` function is called when exit main.
|
||||
* user need to implement this function, otherwise when link it will
|
||||
* error fini.c:(.text.__libc_fini_array+0x28): undefined reference to `_fini'
|
||||
* \note
|
||||
* Please use \ref _postmain_fini function now
|
||||
*/
|
||||
void _fini(void)
|
||||
{
|
||||
/* Don't put any code here, please use _postmain_fini now */
|
||||
}
|
||||
|
||||
/** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */
|
||||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7
|
||||
|
|
@ -89,7 +89,8 @@
|
|||
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX63X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX65X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX72N
|
||||
CFG_TUSB_MCU == OPT_MCU_RX72N || \
|
||||
CFG_TUSB_MCU == OPT_MCU_GD32VF103
|
||||
#define USE_LINEAR_BUFFER 0
|
||||
#else
|
||||
#define USE_LINEAR_BUFFER 1
|
||||
|
|
|
|||
|
|
@ -147,6 +147,10 @@
|
|||
//#elif TU_CHECK_MCU(MM32F327X)
|
||||
// #define DCD_ATTR_ENDPOINT_MAX not known yet
|
||||
|
||||
//------------- GigaDevice -------------//
|
||||
#elif TU_CHECK_MCU(GD32VF103)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 4
|
||||
|
||||
#else
|
||||
#warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
|
|
|
|||
|
|
@ -51,7 +51,8 @@
|
|||
CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
|
||||
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
|
||||
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS) || \
|
||||
CFG_TUSB_MCU == OPT_MCU_GD32VF103 ) \
|
||||
)
|
||||
|
||||
// EP_MAX : Max number of bi-directional endpoints including EP0
|
||||
|
|
@ -92,6 +93,30 @@
|
|||
#define EP_MAX_FS 6
|
||||
#define EP_FIFO_SIZE_FS 1280
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
|
||||
#include "synopsys_common.h"
|
||||
|
||||
// These numbers are the same for the whole GD32VF103 family.
|
||||
#define OTG_FS_IRQn 86
|
||||
#define EP_MAX_FS 4
|
||||
#define EP_FIFO_SIZE_FS 1280
|
||||
|
||||
// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
|
||||
// Interrupt Controller by Nuclei. It is nearly API compatible to the
|
||||
// NVIC used by ARM MCUs.
|
||||
#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
|
||||
|
||||
#define NVIC_EnableIRQ __eclic_enable_interrupt
|
||||
#define NVIC_DisableIRQ __eclic_disable_interrupt
|
||||
|
||||
static inline void __eclic_enable_interrupt (uint32_t irq) {
|
||||
*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
|
||||
}
|
||||
|
||||
static inline void __eclic_disable_interrupt (uint32_t irq){
|
||||
*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#error "Unsupported MCUs"
|
||||
#endif
|
||||
|
|
@ -282,6 +307,8 @@ static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
|
|||
// Turnaround timeout depends on the MCU clock
|
||||
uint32_t turnaround;
|
||||
|
||||
TU_LOG_INT(2, SystemCoreClock);
|
||||
|
||||
if ( SystemCoreClock >= 32000000U )
|
||||
turnaround = 0x6U;
|
||||
else if ( SystemCoreClock >= 27500000U )
|
||||
|
|
@ -625,6 +652,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
|||
|
||||
_allocated_fifo_words_tx += fifo_size;
|
||||
|
||||
TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
|
||||
|
||||
// DIEPTXF starts at FIFO #1.
|
||||
// Both TXFD and TXSA are in unit of 32-bit words.
|
||||
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -122,6 +122,9 @@
|
|||
// Mind Motion
|
||||
#define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327
|
||||
|
||||
// GigaDevice
|
||||
#define OPT_MCU_GD32VF103 1600 ///< GigaDevice GD32VF103
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Supported OS
|
||||
//--------------------------------------------------------------------+
|
||||
|
|
|
|||
Loading…
Reference in New Issue