more chipidea
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@ -27,10 +27,6 @@
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#ifndef _CI_HS_IMXRT_H_
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#ifndef _CI_HS_IMXRT_H_
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#define _CI_HS_IMXRT_H_
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#define _CI_HS_IMXRT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "fsl_device_registers.h"
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#include "fsl_device_registers.h"
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static const ci_hs_controller_t _ci_controller[] =
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static const ci_hs_controller_t _ci_controller[] =
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@ -44,18 +40,11 @@ static const ci_hs_controller_t _ci_controller[] =
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#endif
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#endif
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};
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};
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void dcd_int_enable(uint8_t rhport)
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#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
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{
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#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
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NVIC_EnableIRQ(_ci_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
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{
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#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
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NVIC_DisableIRQ(_ci_controller[rhport].irqnum);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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@ -27,10 +27,6 @@
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#ifndef _CI_HS_LPC18_43_H_
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#ifndef _CI_HS_LPC18_43_H_
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#define _CI_HS_LPC18_43_H_
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#define _CI_HS_LPC18_43_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// LPCOpen for 18xx & 43xx
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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#include "chip.h"
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@ -40,18 +36,10 @@ static const ci_hs_controller_t _ci_controller[] =
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{ .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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{ .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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};
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};
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void dcd_int_enable(uint8_t rhport)
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#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
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{
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#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
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NVIC_EnableIRQ(_ci_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
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{
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#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
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NVIC_DisableIRQ(_ci_controller[rhport].irqnum);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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@ -127,7 +127,7 @@ typedef struct
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volatile uint32_t ENDPTSTAT; ///< Endpoint Status
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volatile uint32_t ENDPTSTAT; ///< Endpoint Status
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volatile uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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volatile uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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volatile uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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volatile uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} ci_hs_regs_t, hcd_registers_t;
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} ci_hs_regs_t;
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typedef struct
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typedef struct
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@ -43,6 +43,9 @@
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#error "Unsupported MCUs"
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#error "Unsupported MCUs"
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#endif
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
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#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
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@ -52,9 +55,6 @@
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#define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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#define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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#endif
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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// ENDPTCTRL
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// ENDPTCTRL
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enum {
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enum {
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@ -230,6 +230,16 @@ void dcd_init(uint8_t rhport)
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dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
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dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
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}
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}
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void dcd_int_enable(uint8_t rhport)
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{
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CI_DCD_INT_ENABLE(rhport);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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CI_DCD_INT_DISABLE(rhport);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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{
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// Response with status first before changing device address
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// Response with status first before changing device address
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@ -34,47 +34,23 @@
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// INCLUDE
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// INCLUDE
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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#else
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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#endif
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#include "common/tusb_common.h"
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#include "common/tusb_common.h"
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#include "ci_hs_type.h"
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#include "portable/ehci/ehci_api.h"
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#include "portable/ehci/ehci_api.h"
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#include "ci_hs_type.h"
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "ci_hs_imxrt.h"
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#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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#include "ci_hs_lpc18_43.h"
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#else
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#error "Unsupported MCUs"
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#endif
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// TODO can be merged with dcd_controller_t
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#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
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typedef struct
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{
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uint32_t regs_base; // registers base
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const IRQn_Type irqnum; // IRQ number
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}hcd_controller_t;
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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static const hcd_controller_t _hcd_controller[] =
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{
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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{ .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
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#else
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{ .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn },
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{ .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn }
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#endif
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};
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#else
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static const hcd_controller_t _hcd_controller[] =
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{
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{ .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
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{ .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
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};
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#endif
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// Controller API
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// Controller API
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bool hcd_init(uint8_t rhport)
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bool hcd_init(uint8_t rhport)
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{
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{
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hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base;
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ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport);
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// Reset controller
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// Reset controller
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hcd_reg->USBCMD |= USBCMD_RESET;
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hcd_reg->USBCMD |= USBCMD_RESET;
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void hcd_int_enable(uint8_t rhport)
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void hcd_int_enable(uint8_t rhport)
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{
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{
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NVIC_EnableIRQ(_hcd_controller[rhport].irqnum);
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CI_HCD_INT_ENABLE(rhport);
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}
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}
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void hcd_int_disable(uint8_t rhport)
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void hcd_int_disable(uint8_t rhport)
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{
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{
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NVIC_DisableIRQ(_hcd_controller[rhport].irqnum);
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CI_HCD_INT_DISABLE(rhport);
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}
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}
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#endif
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#endif
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