added board files
This commit is contained in:
kkitayam
parent
aa1a5a11c7
commit
18be454011
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@ -0,0 +1,54 @@
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CFLAGS += \
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-nostartfiles \
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-nostdinc \
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-ffunction-sections \
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-fdata-sections \
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-mcpu=rx610 \
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-misa=v1 \
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-mlittle-endian-data \
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-DCFG_TUSB_MCU=OPT_MCU_RX63X
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# Cross Compiler for RX
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CROSS_COMPILE = rx-elf-
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ifeq ($(CMDEXE),1)
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OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
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else
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OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
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endif
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# mcu driver cause following warnings
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CFLAGS += -isystem $(OPTLIBINC)
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LIBS += -loptm -loptc
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MCU_DIR = hw/mcu/renesas/rx63n
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/$(BOARD)/r5f5631fd.ld
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SRC_C += \
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$(MCU_DIR)/vects.c
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INC += \
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$(TOP)/hw/bsp/$(BOARD) \
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$(TOP)/$(MCU_DIR)
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SRC_S += $(MCU_DIR)/start.S
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# For TinyUSB port source
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VENDOR = renesas
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CHIP_FAMILY = usba
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# For freeRTOS port source
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FREERTOS_PORT = RX600
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# For flash-jlink target
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JLINK_DEVICE = R5F5631F
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JLINK_IF = JTAG
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# For flash-pyocd target
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PYOCD_TARGET =
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# flash using jlink
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flash: flash-jlink
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@ -0,0 +1,217 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Koji Kitayama
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "../board.h"
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#include "iodefine.h"
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#include "interrupt_handlers.h"
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#define IRQ_PRIORITY_CMT0 5
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#define IRQ_PRIORITY_USBI0 5
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#define IRQ_PRIORITY_SCI0 5
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#define SYSTEM_PRCR_PRC1 (1<<1)
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#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
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#define CMT_PCLK 48000000
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#define CMT_CMCR_CKS_DIV_128 2
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#define CMT_CMCR_CMIE (1<<6)
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#define MPC_PFS_ISEL (1<<6)
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#define SCI_PCLK 48000000
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#define SCI_SSR_FER (1<<4)
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#define SCI_SSR_ORER (1<<5)
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#define SCI_SCR_TEIE (1u<<2)
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#define SCI_SCR_RE (1u<<4)
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#define SCI_SCR_TE (1u<<5)
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#define SCI_SCR_RIE (1u<<6)
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#define SCI_SCR_TIE (1u<<7)
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//--------------------------------------------------------------------+
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// SCI0 handling
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//--------------------------------------------------------------------+
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typedef struct {
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uint8_t *buf;
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uint32_t cnt;
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} sci_buf_t;
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static volatile sci_buf_t sci0_buf[2];
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void INT_Excep_SCI0_TXI0(void)
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{
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uint8_t *buf = sci0_buf[0].buf;
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uint32_t cnt = sci0_buf[0].cnt;
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if (!buf || !cnt) {
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SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
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return;
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}
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SCI0.TDR = *buf;
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if (--cnt) {
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++buf;
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} else {
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buf = NULL;
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SCI0.SCR.BIT.TIE = 0;
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SCI0.SCR.BIT.TEIE = 1;
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}
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sci0_buf[0].buf = buf;
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sci0_buf[0].cnt = cnt;
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}
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void INT_Excep_SCI0_TEI0(void)
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{
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SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
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}
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void INT_Excep_SCI0_RXI0(void)
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{
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uint8_t *buf = sci0_buf[1].buf;
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uint32_t cnt = sci0_buf[1].cnt;
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if (!buf || !cnt ||
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(SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
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sci0_buf[1].buf = NULL;
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SCI0.SSR.BYTE = 0;
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SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
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return;
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}
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*buf = SCI0.RDR;
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if (--cnt) {
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++buf;
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} else {
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buf = NULL;
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SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
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}
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sci0_buf[1].buf = buf;
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sci0_buf[1].cnt = cnt;
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}
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void INT_Excep_USB0_USBI0(void)
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{
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tud_int_handler(0);
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}
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void board_init(void)
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{
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#if CFG_TUSB_OS == OPT_OS_NONE
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/* Enable CMT0 */
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SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
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MSTP(CMT0) = 0;
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SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
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/* Setup 1ms tick timer */
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CMT0.CMCNT = 0;
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CMT0.CMCOR = CMT_PCLK / 1000 / 128;
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CMT0.CMCR.WORD = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
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IR(CMT0, CMI0) = 0;
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IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
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IEN(CMT0, CMI0) = 1;
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CMT.CMSTR0.BIT.STR0 = 1;
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#endif
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/* Unlock MPC registers */
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MPC.PWPR.BIT.B0WI = 0;
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MPC.PWPR.BIT.PFSWE = 1;
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/* LED PA0 */
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PORTA.PMR.BIT.B0 = 0U;
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PORTA.PODR.BIT.B0 = 0U;
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PORTA.PDR.BIT.B0 = 1U;
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/* UART TXD0 => P20, RXD0 => P21 */
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PORT2.PMR.BIT.B0 = 1U;
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PORT2.PCR.BIT.B0 = 1U;
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MPC.P20PFS.BYTE = 0b01010;
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PORT2.PMR.BIT.B1 = 1U;
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MPC.P21PFS.BYTE = 0b01010;
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/* USB VBUS -> P16, RXD0 => P21, TXD0 => P20 */
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PORT1.PMR.BIT.B6 = 1U;
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MPC.P16PFS.BYTE = MPC_PFS_ISEL | 0b10001;
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/* Lock MPC registers */
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MPC.PWPR.BIT.PFSWE = 0;
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MPC.PWPR.BIT.B0WI = 1;
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IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
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/* Enable SCI0 */
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SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
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MSTP(SCI0) = 0;
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SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
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SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
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IR(SCI0, RXI0) = 0;
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IR(SCI0, TXI0) = 0;
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IR(SCI0, TEI0) = 0;
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IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
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IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
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IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
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IEN(SCI0, RXI0) = 1;
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IEN(SCI0, TXI0) = 1;
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IEN(SCI0, TEI0) = 1;
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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void board_led_write(bool state)
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{
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PORTA.PODR.BIT.B0 = state ? 1 : 0;
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}
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uint32_t board_button_read(void)
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{
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return 0;
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}
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int board_uart_read(uint8_t* buf, int len)
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{
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sci0_buf[1].buf = buf;
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sci0_buf[1].cnt = len;
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SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
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while (SCI0.SCR.BIT.RE) ;
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return len - sci0_buf[1].cnt;
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}
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int board_uart_write(void const *buf, int len)
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{
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sci0_buf[0].buf = (uint8_t*)buf;
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sci0_buf[0].cnt = len;
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SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
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while (SCI0.SCR.BIT.TE) ;
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return len;
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void INT_Excep_CMT0_CMI0(void)
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{
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++system_ticks;
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}
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uint32_t board_millis(void)
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{
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return system_ticks;
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}
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#endif
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@ -0,0 +1,31 @@
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/************************************************************************/
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/* File Version: V1.00 */
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/* Date Generated: 08/07/2013 */
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/************************************************************************/
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#include "iodefine.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void HardwareSetup(void);
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#ifdef __cplusplus
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}
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#endif
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void HardwareSetup(void)
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{
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SYSTEM.PRCR.WORD = 0xA503u;
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SYSTEM.SOSCCR.BYTE = 0x01u;
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SYSTEM.MOSCWTCR.BYTE = 0x0Du;
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SYSTEM.PLLWTCR.BYTE = 0x0Eu;
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SYSTEM.PLLCR.WORD = 0x0F00u;
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SYSTEM.MOSCCR.BYTE = 0x00u;
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SYSTEM.PLLCR2.BYTE = 0x00u;
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for (unsigned i = 0; i < 2075u; ++i) __asm("nop");
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SYSTEM.SCKCR.LONG = 0x21021211u;
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SYSTEM.SCKCR2.WORD = 0x0033u;
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SYSTEM.SCKCR3.WORD = 0x0400u;
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SYSTEM.SYSCR0.WORD = 0x5A01;
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SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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SYSTEM.PRCR.WORD = 0xA500u;
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}
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@ -0,0 +1,127 @@
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__USTACK_SIZE = 0x00000200;
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__ISTACK_SIZE = 0x00000100;
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MEMORY
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{
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RAM : ORIGIN = 0x4, LENGTH = 0x3fffc
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ROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000
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}
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SECTIONS
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{
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.fvectors 0xFFFFFF80: AT(0xFFFFFF80)
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{
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KEEP(*(.fvectors))
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} > ROM
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.text 0xFFE00000: AT(0xFFE00000)
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{
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*(.text)
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*(.text.*)
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*(P)
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etext = .;
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} > ROM
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.rvectors ALIGN(4):
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{
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_rvectors_start = .;
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KEEP(*(.rvectors))
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_rvectors_end = .;
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} > ROM
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.init :
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{
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KEEP(*(.init))
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__preinit_array_start = .;
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KEEP(*(.preinit_array))
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__preinit_array_end = .;
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__init_array_start = (. + 3) & ~ 3;
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KEEP(*(.init_array))
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KEEP(*(SORT(.init_array.*)))
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__init_array_end = .;
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__fini_array_start = .;
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KEEP(*(.fini_array))
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KEEP(*(SORT(.fini_array.*)))
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__fini_array_end = .;
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} > ROM
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.fini :
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{
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KEEP(*(.fini))
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} > ROM
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.got :
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{
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*(.got)
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*(.got.plt)
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} > ROM
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.rodata :
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{
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*(.rodata)
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*(.rodata.*)
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*(C_1)
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*(C_2)
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*(C)
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_erodata = .;
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} > ROM
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.eh_frame_hdr :
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{
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*(.eh_frame_hdr)
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} > ROM
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.eh_frame :
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{
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*(.eh_frame)
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} > ROM
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.jcr :
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{
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*(.jcr)
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} > ROM
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.tors :
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{
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__CTOR_LIST__ = .;
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. = ALIGN(2);
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___ctors = .;
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*(.ctors)
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___ctors_end = .;
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__CTOR_END__ = .;
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__DTOR_LIST__ = .;
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___dtors = .;
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*(.dtors)
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___dtors_end = .;
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__DTOR_END__ = .;
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. = ALIGN(2);
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_mdata = .;
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} > ROM
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.data : AT(_mdata)
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{
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_data = .;
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*(.data)
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*(.data.*)
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*(D)
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*(D_1)
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*(D_2)
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_edata = .;
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} > RAM
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.gcc_exc :
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{
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*(.gcc_exc)
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} > RAM
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.bss :
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{
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_bss = .;
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*(.bss)
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*(.bss.**)
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*(COMMON)
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*(B)
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*(B_1)
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*(B_2)
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_ebss = .;
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_end = .;
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} > RAM
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.ustack (COPY) :
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{
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. = ALIGN(8);
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. = . + __USTACK_SIZE;
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PROVIDE(_ustack = .);
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} > RAM
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.istack (COPY) :
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{
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. = ALIGN(8);
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. = . + __ISTACK_SIZE;
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PROVIDE(_istack = .);
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} > RAM
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}
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