remove legacy blocking usbh_control_xfer()

reworking cdc host driver
This commit is contained in:
hathach 2020-11-02 09:19:34 +07:00
parent 2efdc2fb64
commit 14461beffa
4 changed files with 49 additions and 72 deletions

View File

@ -51,9 +51,14 @@ typedef struct {
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
static cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX]; static cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX];
static inline cdch_data_t* get_itf(uint8_t dev_addr)
{
return &cdch_data[dev_addr-1];
}
bool tuh_cdc_mounted(uint8_t dev_addr) bool tuh_cdc_mounted(uint8_t dev_addr)
{ {
cdch_data_t* cdc = &cdch_data[dev_addr-1]; cdch_data_t* cdc = get_itf(dev_addr);
return cdc->ep_in && cdc->ep_out; return cdc->ep_in && cdc->ep_out;
} }
@ -61,7 +66,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
{ {
if ( !tuh_cdc_mounted(dev_addr) ) return false; if ( !tuh_cdc_mounted(dev_addr) ) return false;
cdch_data_t const * p_cdc = &cdch_data[dev_addr-1]; cdch_data_t const * p_cdc = get_itf(dev_addr);
switch (pipeid) switch (pipeid)
{ {
@ -111,6 +116,27 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
return hcd_pipe_xfer(dev_addr, ep_in, p_buffer, length, is_notify); return hcd_pipe_xfer(dev_addr, ep_in, p_buffer, length, is_notify);
} }
bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb)
{
cdch_data_t const * p_cdc = get_itf(dev_addr);
tusb_control_request_t const request =
{
.bmRequestType_bit =
{
.recipient = TUSB_REQ_RCPT_INTERFACE,
.type = TUSB_REQ_TYPE_CLASS,
.direction = TUSB_DIR_OUT
},
.bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
.wValue = (rts ? 2 : 0) | (dtr ? 1 : 0),
.wIndex = p_cdc->itf_num,
.wLength = 0
};
TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, complete_cb) );
return true;
}
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// USBH-CLASS DRIVER API // USBH-CLASS DRIVER API
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
@ -132,7 +158,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
cdch_data_t * p_cdc; cdch_data_t * p_cdc;
p_desc = tu_desc_next(itf_desc); p_desc = tu_desc_next(itf_desc);
p_cdc = &cdch_data[dev_addr-1]; p_cdc = get_itf(dev_addr);
p_cdc->itf_num = itf_desc->bInterfaceNumber; p_cdc->itf_num = itf_desc->bInterfaceNumber;
p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com
@ -194,18 +220,12 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
} }
} }
// FIXME move to seperate API : connect return true;
tusb_control_request_t request = }
{
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
.bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
.wValue = 0x03, // dtr on, cst on
.wIndex = p_cdc->itf_num,
.wLength = 0
};
TU_ASSERT( usbh_control_xfer(dev_addr, &request, NULL) );
bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
{
(void) dev_addr; (void) itf_num;
return true; return true;
} }
@ -218,7 +238,7 @@ bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
void cdch_close(uint8_t dev_addr) void cdch_close(uint8_t dev_addr)
{ {
cdch_data_t * p_cdc = &cdch_data[dev_addr-1]; cdch_data_t * p_cdc = get_itf(dev_addr);
tu_memclr(p_cdc, sizeof(cdch_data_t)); tu_memclr(p_cdc, sizeof(cdch_data_t));
} }

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@ -44,6 +44,18 @@
* \defgroup CDC_Serial_Host Host * \defgroup CDC_Serial_Host Host
* @{ */ * @{ */
bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb);
static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
{
return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
}
static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
{
return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
}
/** \brief Check if device support CDC Serial interface or not /** \brief Check if device support CDC Serial interface or not
* \param[in] dev_addr device address * \param[in] dev_addr device address
* \retval true if device supports * \retval true if device supports
@ -113,6 +125,7 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
void cdch_init(void); void cdch_init(void);
bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length); bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num);
bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
void cdch_close(uint8_t dev_addr); void cdch_close(uint8_t dev_addr);

View File

@ -56,6 +56,7 @@ static usbh_class_driver_t const usbh_class_drivers[] =
.class_code = TUSB_CLASS_CDC, .class_code = TUSB_CLASS_CDC,
.init = cdch_init, .init = cdch_init,
.open = cdch_open, .open = cdch_open,
.set_config = cdch_set_config,
.xfer_cb = cdch_xfer_cb, .xfer_cb = cdch_xfer_cb,
.close = cdch_close .close = cdch_close
}, },
@ -174,9 +175,6 @@ bool tuh_init(void)
{ {
usbh_device_t * const dev = &_usbh_devices[i]; usbh_device_t * const dev = &_usbh_devices[i];
dev->control.sem_hdl = osal_semaphore_create(&dev->control.sem_def);
TU_ASSERT(dev->control.sem_hdl != NULL);
#if CFG_TUSB_OS != OPT_OS_NONE #if CFG_TUSB_OS != OPT_OS_NONE
dev->mutex = osal_mutex_create(&dev->mutexdef); dev->mutex = osal_mutex_create(&dev->mutexdef);
TU_ASSERT(dev->mutex); TU_ASSERT(dev->mutex);
@ -199,38 +197,6 @@ bool tuh_init(void)
return true; return true;
} }
//------------- USBH control transfer -------------//
// TODO remove
bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data)
{
usbh_device_t* dev = &_usbh_devices[dev_addr];
const uint8_t rhport = dev->rhport;
dev->control.request = *request;
dev->control.pipe_status = 0;
// Setup Stage
hcd_setup_send(rhport, dev_addr, (uint8_t*) &dev->control.request);
TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
// Data stage : first data toggle is always 1
if ( request->wLength )
{
hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), data, request->wLength);
TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
}
// Status : data toggle is always 1
hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
if ( XFER_RESULT_STALLED == dev->control.pipe_status ) return false;
if ( XFER_RESULT_FAILED == dev->control.pipe_status ) return false;
return true;
}
bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
{ {
uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr);
@ -291,9 +257,6 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
bool usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) bool usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
{ {
osal_semaphore_reset( _usbh_devices[dev_addr].control.sem_hdl );
//osal_mutex_reset( usbh_devices[dev_addr].control.mutex_hdl );
tusb_desc_endpoint_t ep0_desc = tusb_desc_endpoint_t ep0_desc =
{ {
.bLength = sizeof(tusb_desc_endpoint_t), .bLength = sizeof(tusb_desc_endpoint_t),
@ -349,15 +312,6 @@ void hcd_event_handler(hcd_event_t const* event, bool in_isr)
// interrupt caused by a TD (with IOC=1) in pipe of class class_code // interrupt caused by a TD (with IOC=1) in pipe of class class_code
void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
{ {
usbh_device_t* dev = &_usbh_devices[ dev_addr ];
if (0 == tu_edpt_number(ep_addr))
{
dev->control.pipe_status = result;
// usbh_devices[ pipe_hdl.dev_addr ].control.xferred_bytes = xferred_bytes; not yet neccessary
osal_semaphore_post( dev->control.sem_hdl, true ); // FIXME post within ISR
}
hcd_event_t event = hcd_event_t event =
{ {
.rhport = 0, // TODO correct rhport .rhport = 0, // TODO correct rhport

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@ -75,16 +75,6 @@ typedef struct {
volatile uint8_t state; // device state, value from enum tusbh_device_state_t volatile uint8_t state; // device state, value from enum tusbh_device_state_t
//------------- control pipe -------------//
struct {
volatile uint8_t pipe_status;
// uint8_t xferred_bytes; TODO not yet necessary
tusb_control_request_t request;
osal_semaphore_def_t sem_def;
osal_semaphore_t sem_hdl; // used to synchronize with HCD when control xfer complete
} control;
uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid) uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid ) uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )