minor rename
This commit is contained in:
hathach
parent
32742571da
commit
0e7c103e98
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@ -83,7 +83,7 @@ xfer_ctl_t xfer_status[EP_MAX][2];
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
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// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
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// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from core->GRXFSIZ
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static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
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static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size)
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@ -97,7 +97,7 @@ static void update_grxfsiz(uint8_t rhport)
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{
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(void) rhport;
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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// Determine largest EP size for RX FIFO
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uint16_t max_epsize = 0;
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@ -107,7 +107,7 @@ static void update_grxfsiz(uint8_t rhport)
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}
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// Update size of RX FIFO
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usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
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core->GRXFSIZ = calc_rx_ff_size(max_epsize);
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}
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// Setup the control endpoint 0.
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@ -115,7 +115,7 @@ static void bus_reset(uint8_t rhport)
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{
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(void) rhport;
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
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dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
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@ -186,12 +186,12 @@ static void bus_reset(uint8_t rhport)
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// are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
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// overwrite this.
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usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
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core->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
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_allocated_fifo_words_tx = 16;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
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core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
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// Fixed control EP0 size to 64 bytes
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in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
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@ -199,19 +199,19 @@ static void bus_reset(uint8_t rhport)
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out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
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usb_otg->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
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core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
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}
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// Set turn-around timeout according to link speed
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extern uint32_t SystemCoreClock;
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static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
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static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
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{
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usb_otg->GUSBCFG &= ~GUSBCFG_TRDT;
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core->GUSBCFG &= ~GUSBCFG_TRDT;
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if ( speed == TUSB_SPEED_HIGH )
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{
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// Use fixed 0x09 for Highspeed
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usb_otg->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
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core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
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}
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else
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{
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@ -240,7 +240,7 @@ static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
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turnaround = 0xFU;
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// Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
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usb_otg->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
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core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
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}
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}
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@ -370,7 +370,7 @@ void dcd_init (uint8_t rhport)
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{
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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// No HNP/SRP (no OTG support), program timeout later.
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if ( rhport == 1 )
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@ -378,23 +378,23 @@ void dcd_init (uint8_t rhport)
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// On selected MCUs HS port1 can be used with external PHY via ULPI interface
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#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
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// deactivate internal PHY
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usb_otg->GCCFG &= ~GCCFG_PWRDWN;
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core->GCCFG &= ~GCCFG_PWRDWN;
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// Init The UTMI Interface
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usb_otg->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
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core->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
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// Select default internal VBUS Indicator and Drive for ULPI
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usb_otg->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
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core->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
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#else
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usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
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core->GUSBCFG |= GUSBCFG_PHYSEL;
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#endif
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#if defined(USB_HS_PHYC)
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// Highspeed with embedded UTMI PHYC
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// Select UTMI Interface
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usb_otg->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
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usb_otg->GCCFG |= GCCFG_PHYHSEN;
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core->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
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core->GCCFG |= GCCFG_PHYHSEN;
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// Enables control of a High Speed USB PHY
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USB_HS_PHYCInit();
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@ -402,25 +402,25 @@ void dcd_init (uint8_t rhport)
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} else
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{
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// Enable internal PHY
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usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
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core->GUSBCFG |= GUSBCFG_PHYSEL;
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}
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// Reset core after selecting PHYst
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// Wait AHB IDLE, reset then wait until it is cleared
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while ((usb_otg->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
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usb_otg->GRSTCTL |= GRSTCTL_CSRST;
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while ((usb_otg->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
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while ((core->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
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core->GRSTCTL |= GRSTCTL_CSRST;
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while ((core->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
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// Restart PHY clock
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*((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
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// Clear all interrupts
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usb_otg->GINTSTS |= usb_otg->GINTSTS;
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core->GINTSTS |= core->GINTSTS;
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// Required as part of core initialization.
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// TODO: How should mode mismatch be handled? It will cause
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// the core to stop working/require reset.
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usb_otg->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
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core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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@ -431,14 +431,14 @@ void dcd_init (uint8_t rhport)
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set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
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// Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
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if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= GCCFG_PWRDWN;
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if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN;
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usb_otg->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM |
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GINTMSK_USBSUSPM | GINTMSK_WUIM |
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GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0);
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core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM |
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GINTMSK_USBSUSPM | GINTMSK_WUIM |
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GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0);
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// Enable global interrupt
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usb_otg->GAHBCFG |= GAHBCFG_GINT;
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core->GAHBCFG |= GAHBCFG_GINT;
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dcd_connect(rhport);
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}
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@ -478,15 +478,15 @@ void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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// set remote wakeup
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dev->DCTL |= DCTL_RWUSIG;
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// enable SOF to detect bus resume
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usb_otg->GINTSTS = GINTSTS_SOF;
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usb_otg->GINTMSK |= GINTMSK_SOFM;
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core->GINTSTS = GINTSTS_SOF;
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core->GINTMSK |= GINTMSK_SOFM;
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// Per specs: remote wakeup signal bit must be clear within 1-15ms
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remote_wakeup_delay();
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@ -517,7 +517,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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{
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(void) rhport;
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
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dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
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@ -539,12 +539,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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uint16_t const sz = calc_rx_ff_size(4*fifo_size);
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// If size_rx needs to be extended check if possible and if so enlarge it
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if (usb_otg->GRXFSIZ < sz)
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if (core->GRXFSIZ < sz)
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{
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TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
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// Enlarge RX FIFO
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usb_otg->GRXFSIZ = sz;
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core->GRXFSIZ = sz;
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}
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out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) |
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@ -578,7 +578,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
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// Check if free space is available
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TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
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TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= EP_FIFO_SIZE/4);
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_allocated_fifo_words_tx += fifo_size;
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@ -586,7 +586,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// DIEPTXF starts at FIFO #1.
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// Both TXFD and TXSA are in unit of 32-bit words.
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usb_otg->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
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core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
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in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
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(epnum << DIEPCTL_TXFNUM_Pos) |
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@ -605,7 +605,7 @@ void dcd_edpt_close_all (uint8_t rhport)
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{
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(void) rhport;
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// dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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// dwc2_core_t * core = GLOBAL_BASE(rhport);
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
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dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
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@ -693,7 +693,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
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{
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(void) rhport;
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
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dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
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@ -717,9 +717,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
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}
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// Flush the FIFO, and wait until we have confirmed it cleared.
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usb_otg->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
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usb_otg->GRSTCTL |= GRSTCTL_TXFFLSH;
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while((usb_otg->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
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core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
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core->GRSTCTL |= GRSTCTL_TXFFLSH;
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while((core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
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} else {
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// Only disable currently enabled non-control endpoint
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if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){
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@ -730,7 +730,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
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// anyway, and it can't be cleared by user code. If this while loop never
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// finishes, we have bigger problems than just the stack.
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dev->DCTL |= DCTL_SGONAK;
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while((usb_otg->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
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while((core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
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// Ditto here- disable the endpoint.
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out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
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@ -748,7 +748,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
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*/
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void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
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{
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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@ -760,8 +760,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
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if (dir == TUSB_DIR_IN)
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{
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uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
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uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
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uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
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uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
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// For now only the last opened endpoint can be closed without fuss.
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TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
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_allocated_fifo_words_tx -= fifo_size;
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@ -861,11 +861,11 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
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}
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static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
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// Pop control word off FIFO
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uint32_t ctl_word = usb_otg->GRXSTSP;
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uint32_t ctl_word = core->GRXSTSP;
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uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
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uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
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uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
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@ -1025,17 +1025,17 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
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void dcd_int_handler(uint8_t rhport)
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{
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dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
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dwc2_core_t * core = GLOBAL_BASE(rhport);
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dwc2_device_t * dev = DEVICE_BASE(rhport);
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dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
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dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
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uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
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uint32_t const int_status = core->GINTSTS & core->GINTMSK;
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if(int_status & GINTSTS_USBRST)
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{
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// USBRST is start of reset.
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usb_otg->GINTSTS = GINTSTS_USBRST;
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core->GINTSTS = GINTSTS_USBRST;
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bus_reset(rhport);
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}
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@ -1043,23 +1043,23 @@ void dcd_int_handler(uint8_t rhport)
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{
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||||
// ENUMDNE is the end of reset where speed of the link is detected
|
||||
|
||||
usb_otg->GINTSTS = GINTSTS_ENUMDNE;
|
||||
core->GINTSTS = GINTSTS_ENUMDNE;
|
||||
|
||||
tusb_speed_t const speed = get_speed(rhport);
|
||||
|
||||
set_turnaround(usb_otg, speed);
|
||||
set_turnaround(core, speed);
|
||||
dcd_event_bus_reset(rhport, speed, true);
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_USBSUSP)
|
||||
{
|
||||
usb_otg->GINTSTS = GINTSTS_USBSUSP;
|
||||
core->GINTSTS = GINTSTS_USBSUSP;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_WKUINT)
|
||||
{
|
||||
usb_otg->GINTSTS = GINTSTS_WKUINT;
|
||||
core->GINTSTS = GINTSTS_WKUINT;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
||||
}
|
||||
|
||||
|
|
@ -1069,22 +1069,22 @@ void dcd_int_handler(uint8_t rhport)
|
|||
if(int_status & GINTSTS_OTGINT)
|
||||
{
|
||||
// OTG INT bit is read-only
|
||||
uint32_t const otg_int = usb_otg->GOTGINT;
|
||||
uint32_t const otg_int = core->GOTGINT;
|
||||
|
||||
if (otg_int & GOTGINT_SEDET)
|
||||
{
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||
}
|
||||
|
||||
usb_otg->GOTGINT = otg_int;
|
||||
core->GOTGINT = otg_int;
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_SOF)
|
||||
{
|
||||
usb_otg->GINTSTS = GINTSTS_SOF;
|
||||
core->GINTSTS = GINTSTS_SOF;
|
||||
|
||||
// Disable SOF interrupt since currently only used for remote wakeup detection
|
||||
usb_otg->GINTMSK &= ~GINTMSK_SOFM;
|
||||
core->GINTMSK &= ~GINTMSK_SOFM;
|
||||
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||||
}
|
||||
|
|
@ -1095,13 +1095,13 @@ void dcd_int_handler(uint8_t rhport)
|
|||
// RXFLVL bit is read-only
|
||||
|
||||
// Mask out RXFLVL while reading data from FIFO
|
||||
usb_otg->GINTMSK &= ~GINTMSK_RXFLVLM;
|
||||
core->GINTMSK &= ~GINTMSK_RXFLVLM;
|
||||
|
||||
// Loop until all available packets were handled
|
||||
do
|
||||
{
|
||||
handle_rxflvl_ints(rhport, out_ep);
|
||||
} while(usb_otg->GINTSTS & GINTSTS_RXFLVL);
|
||||
} while(core->GINTSTS & GINTSTS_RXFLVL);
|
||||
|
||||
// Manage RX FIFO size
|
||||
if (_out_ep_closed)
|
||||
|
|
@ -1112,7 +1112,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
_out_ep_closed = false;
|
||||
}
|
||||
|
||||
usb_otg->GINTMSK |= GINTMSK_RXFLVLM;
|
||||
core->GINTMSK |= GINTMSK_RXFLVLM;
|
||||
}
|
||||
|
||||
// OUT endpoint interrupt handling.
|
||||
|
|
|
|||
Loading…
Reference in New Issue