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Code Issues Releases Activity

dma of lpc54114 can also execute up to 64 bytes each transfer 

There is still issue with cdc_msc_hid example
This commit is contained in:
hathach 2019-09-01 17:05:34 +07:00
parent aeea6754af
commit 074681da8b
1 changed files with 6 additions and 6 deletions
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12
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
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@ -66,15 +66,15 @@
// 2000 0000 to 203F FFFF // 2000 0000 to 203F FFFF
#define SRAM_REGION 0x20000000 #define SRAM_REGION 0x20000000
/* Although device controller are the same. DMA of /* Although device controller are the same. Somehow only LPC134x can execute
* - M0/M+ can only transfer up to nbytes = 64 * DMA with 1023 bytes for Bulk/Control. Others (11u, 51u, 54xxx) can only work
* - M3/M4 can transfer nbytes = 1023 (maximum) * with max 64 bytes
*/ */
enum { enum {
#ifdef __ARM_ARCH_6M__ // Cortex M0/M0+ #if CFG_TUSB_MCU == OPT_MCU_LPC13XX
DMA_NBYTES_MAX = 64
#else
DMA_NBYTES_MAX = 1023 DMA_NBYTES_MAX = 1023
#else
DMA_NBYTES_MAX = 64
#endif #endif
}; };