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esp32-s2_dfu
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merge saml21 + saml22 = saml2x

This commit is contained in:
hathach 2021-06-28 14:37:41 +07:00
parent 7e449b710e
commit 01987ef86c
12 changed files with 36 additions and 245 deletions
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3
.github/workflows/build.yml vendored
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@ -49,8 +49,7 @@ jobs:
- 'samd11'
- 'samd21'
- 'samd51'
- 'saml21'
- 'saml22'
- 'saml2x'
- 'stm32f0'
- 'stm32f4'
- 'stm32f7'

2
README.md
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@ -32,7 +32,7 @@ The stack supports the following MCUs:
- **Dialog:** DA1469x
- **Espressif:** ESP32-S2, ESP32-S3
- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55
- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22
- **NordicSemi:** nRF52833, nRF52840
- **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
- **NXP:**

3
docs/boards.md
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@ -47,8 +47,9 @@ This code base already had supported for a handful of following boards (sorted a
- [Microchip SAMG55 Xplained Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO)
### MicroChip SAML22
### MicroChip SAML2x
- [SAML21 Xplaind Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAML21-XPRO-B)
- [SAML22 Feather](https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather)
- [Sensor Watch](https://github.com/joeycastillo/Sensor-Watch)

163
hw/bsp/saml21/family.c
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@ -1,163 +0,0 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "sam.h"
#include "bsp/board.h"
#include "board.h"
#include "hal/include/hal_gpio.h"
#include "hal/include/hal_init.h"
#include "hpl/gclk/hpl_gclk_base.h"
#include "hpl_mclk_config.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
void USB_Handler(void)
{
tud_int_handler(0);
}
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
//--------------------------------------------------------------------+
/* Referenced GCLKs (out of 0~4), should be initialized firstly */
#define _GCLK_INIT_1ST 0x00000000
/* Not referenced GCLKs, initialized last */
#define _GCLK_INIT_LAST 0x0000001F
void board_init(void)
{
// Clock init ( follow hpl_init.c )
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_set_performance_level(2);
_osc32kctrl_init_sources();
_oscctrl_init_sources();
_mclk_init();
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_oscctrl_init_referenced_generators();
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
#endif
// Update SystemCoreClock since it is hard coded with asf4 and not correct
// Init 1ms tick timer (samd SystemCoreClock may not correct)
SystemCoreClock = CONF_CPU_FREQUENCY;
SysTick_Config(CONF_CPU_FREQUENCY / 1000);
// Led init
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_level(LED_PIN, !LED_STATE_ON);
// Button init
gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
#if CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
/* USB Clock init
* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
* for low speed and full speed operation. */
hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
hri_mclk_set_AHBMASK_USB_bit(MCLK);
hri_mclk_set_APBBMASK_USB_bit(MCLK);
// USB Pin Init
gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
gpio_set_pin_level(PIN_PA24, false);
gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
gpio_set_pin_level(PIN_PA25, false);
gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
// Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
TCC0->PER.bit.PER = 48000000 / 1000;
TCC0->CC[3].bit.CC = 48000000 / 2000;
TCC0->CTRLA.bit.ENABLE = true;
gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
gpio_set_pin_level(LED_PIN, state);
}
uint32_t board_button_read(void)
{
// button is active low
return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf; (void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
(void) buf; (void) len;
return 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif
void _init(void)
{
}

50
hw/bsp/saml21/family.mk
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@ -1,50 +0,0 @@
UF2_FAMILY_ID = 0x68ed2b88
DEPS_SUBMODULES += hw/mcu/microchip
include $(TOP)/$(BOARD_PATH)/board.mk
CFLAGS += \
-mthumb \
-mabi=aapcs \
-mcpu=cortex-m0plus \
-nostdlib -nostartfiles \
-DCONF_OSC32K_CALIB_ENABLE=0 \
-DCFG_TUSB_MCU=OPT_MCU_SAML21
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
hw/mcu/microchip/saml21/gcc/gcc/startup_saml21.c \
hw/mcu/microchip/saml21/gcc/system_saml21.c \
hw/mcu/microchip/saml21/hpl/gclk/hpl_gclk.c \
hw/mcu/microchip/saml21/hpl/mclk/hpl_mclk.c \
hw/mcu/microchip/saml21/hpl/pm/hpl_pm.c \
hw/mcu/microchip/saml21/hpl/osc32kctrl/hpl_osc32kctrl.c \
hw/mcu/microchip/saml21/hpl/oscctrl/hpl_oscctrl.c \
hw/mcu/microchip/saml21/hal/src/hal_atomic.c
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/hw/mcu/microchip/saml21/ \
$(TOP)/hw/mcu/microchip/saml21/config \
$(TOP)/hw/mcu/microchip/saml21/include \
$(TOP)/hw/mcu/microchip/saml21/hal/include \
$(TOP)/hw/mcu/microchip/saml21/hal/utils/include \
$(TOP)/hw/mcu/microchip/saml21/hpl/port \
$(TOP)/hw/mcu/microchip/saml21/hri \
$(TOP)/hw/mcu/microchip/saml21/CMSIS/Include
# For TinyUSB port source
VENDOR = microchip
CHIP_FAMILY = samd
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0
# flash using bossac at least version 1.8
# can be found in arduino15/packages/arduino/tools/bossac/
# Add it to your PATH or change BOSSAC variable to match your installation
BOSSAC = bossac
flash-bossac: $(BUILD)/$(PROJECT).bin
@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x2000 -e -w $^ -R

0
hw/bsp/saml21/boards/atsaml21_xpro/board.h → hw/bsp/saml2x/boards/atsaml21_xpro/board.h
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2
hw/bsp/saml21/boards/atsaml21_xpro/board.mk → hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
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@ -1,5 +1,7 @@
CFLAGS += -D__SAML21J18B__
SAML_VARIANT = saml21
# All source paths should be relative to the top level.
LD_FILE = $(BOARD_PATH)/saml21j18b_flash.ld

0
hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld → hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
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2
hw/bsp/saml2x/boards/saml22_feather/board.mk
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@ -1,5 +1,7 @@
CFLAGS += -D__SAML22J18A__
SAML_VARIANT = saml22
# All source paths should be relative to the top level.
LD_FILE = $(BOARD_PATH)/$(BOARD).ld

2
hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
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@ -1,5 +1,7 @@
CFLAGS += -D__SAML22J18A__
SAML_VARIANT = saml22
# All source paths should be relative to the top level.
LD_FILE = $(BOARD_PATH)/$(BOARD).ld

14
hw/bsp/saml2x/family.c
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@ -108,13 +108,13 @@ void board_init(void)
gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
// Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
TCC0->PER.bit.PER = 48000000 / 1000;
TCC0->CC[3].bit.CC = 48000000 / 2000;
TCC0->CTRLA.bit.ENABLE = true;
gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
// hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
// TCC0->PER.bit.PER = 48000000 / 1000;
// TCC0->CC[3].bit.CC = 48000000 / 2000;
// TCC0->CTRLA.bit.ENABLE = true;
//
// gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
// hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
}
//--------------------------------------------------------------------+

40
hw/bsp/saml2x/family.mk
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@ -1,8 +1,10 @@
UF2_FAMILY_ID = 0x68ed2b88
DEPS_SUBMODULES += hw/mcu/microchip
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
include $(TOP)/$(BOARD_PATH)/board.mk
MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
CFLAGS += \
-mthumb \
-mabi=aapcs \
@ -13,29 +15,25 @@ CFLAGS += \
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
hw/mcu/microchip/saml22/gcc/gcc/startup_saml22.c \
hw/mcu/microchip/saml22/gcc/system_saml22.c \
hw/mcu/microchip/saml22/hpl/gclk/hpl_gclk.c \
hw/mcu/microchip/saml22/hpl/mclk/hpl_mclk.c \
hw/mcu/microchip/saml22/hpl/pm/hpl_pm.c \
hw/mcu/microchip/saml22/hpl/osc32kctrl/hpl_osc32kctrl.c \
hw/mcu/microchip/saml22/hpl/oscctrl/hpl_oscctrl.c \
hw/mcu/microchip/saml22/hal/src/hal_atomic.c
$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
$(MCU_DIR)/gcc/system_$(SAML_VARIANT).c \
$(MCU_DIR)/hpl/gclk/hpl_gclk.c \
$(MCU_DIR)/hpl/mclk/hpl_mclk.c \
$(MCU_DIR)/hpl/pm/hpl_pm.c \
$(MCU_DIR)/hpl/osc32kctrl/hpl_osc32kctrl.c \
$(MCU_DIR)/hpl/oscctrl/hpl_oscctrl.c \
$(MCU_DIR)/hal/src/hal_atomic.c
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/hw/mcu/microchip/saml22/ \
$(TOP)/hw/mcu/microchip/saml22/config \
$(TOP)/hw/mcu/microchip/saml22/include \
$(TOP)/hw/mcu/microchip/saml22/hal/include \
$(TOP)/hw/mcu/microchip/saml22/hal/utils/include \
$(TOP)/hw/mcu/microchip/saml22/hpl/port \
$(TOP)/hw/mcu/microchip/saml22/hri \
$(TOP)/hw/mcu/microchip/saml22/CMSIS/Core/Include
# For TinyUSB port source
VENDOR = microchip
CHIP_FAMILY = samd
$(TOP)/$(MCU_DIR)/ \
$(TOP)/$(MCU_DIR)/config \
$(TOP)/$(MCU_DIR)/include \
$(TOP)/$(MCU_DIR)/hal/include \
$(TOP)/$(MCU_DIR)/hal/utils/include \
$(TOP)/$(MCU_DIR)/hpl/port \
$(TOP)/$(MCU_DIR)/hri \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0