template and source for hardware projects
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these are the hardware design files for the USB bug detector.


the purpose of the USB bug detector is to identify USB cables (or devices) with integrated circuits.


to use the USB bug detector, follow the steps provided on the back of the board:

  • insert a CR2025 or CR2032 coin cell battery in the USB bug detector for it to be operational
  • press on the RESET button to arm the test
  • the BUGGED LED should be off
  • plug the USB cable in the USB receptacle
  • if the BUGGED LED switches on, the USB cable embeds an integrated circuit (e.g. a bug)
  • if the BUGGED LED remains off, the cable is same to use

after the test, to save power, press again on the RESET button.

to ensure that the USB bug detector works, after pressing on the RESET button, press on the TEST button. this will simulate a USB plug with integrated circuit. the BUGGED LED should switch on. this also ensures the battery is not empty.

when the LED is on, the USB bug detector draws 3 mA. when the LED is off, the USB bug detector draws 64 nA. this results in a idle battery life of 419 years (for a typical 235 mAh CR2032 battery). this is more than the self life of the battery (~ 1%/year).


the board has an optional READY LED (with accompanying resistor located next to it). only populate it to debug the board. the READY LED will we on when the BUGGED LED isn't. this allows to always check if the battery is empty, but this also drains the battery even when not testing because an LED is always on.

the first prototype of the board (v0.3) offer three populating options, depending on the available NOR gate part:

  • 1x SOIC-14 package: U1+C1
  • 2x SOT23-5 pachgae: U2+C2, U3+C3
  • 2x SOT-353 package: U3+C3, U5+C5

only populate one of the options, depending on the availability of the NOR gate part. note: the Cx decoupling capacitor is not really necessary and is just present for good design.

mode of operation

and NOR-gate-based SR-latch is used. the RESET button triggers the R signal to reset the latch. when a USB cable is plugged, power is provided by the battery to the cable. if an integrated circuits is present, current will flow through. a 1 k Ohm resistor on the low side (e.g. ground) will create a voltage. if the plug draws more than 1.6 mA, the resulting 1.6 V will trigger the S signal to set the latch. the BUG LED will indicate the send SR-latch is set. the latch remains set until the RESET button is present. thus, even if the plug stops drawing power, the LED remains on.

this minimum 1.6 mA current draw is often caused by the decoupling/bypass capacitor required by integrated circuit, or accompanying voltage regulator. when charging, the capacitor acts as a short for a small time, allowing current to flow. on USB plugs with just resistors, or LEDs, the resulting current flow is not large enough.

the TEST circuit simulates an integrated circuit by putting a 100 nF capacitor across the USB receptacle.

because of the 1 k Ohm inline resistor, and limited 3.3 V provided by the battery, a maximum of 3.3 mA can be drawn by the USB plug. this is often not enough to power up integrated circuit properly, particularly if they use a radio interface. thus it is safe to use the USB bug detector on bugs, without activating it.


to be able to generate the outputs you need following software:

  • rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files)
  • QEDA: to generate footprints for the parts
  • Lepton EDA: for the schematic capture
  • pcb-rnd: for the board layout the output generation is automatized.



almost all of the symbols and footprints used in the schematic and board layout are defined in the QEDA format and generated for the CAD software. the library folder contains the QEDA parts definitions.

to install QEDA using NPM from the official repository:

sudo npm install -g qeda

to install QEDA from the sources:

git clone https://github.com/qeda/qeda
cd qeda
npm install
sudo npm install --global

to generate the parts:

rake library

this will use the parts definition (.yaml files) in the library to generate gEDA gschem/Lepton EDA symbols (.sym files) in the geda/symbols folder, and coralEDA pcb-rnd footprints (.lht files) in the coraleda/subc folder.

only the QEDA parts in subfolders within library come from the QEDA library, but the files are included in this project for simplicity and archiving purposes. all other parts are custom and written for this project.


the .sch file is the schematic source file. it has been drawn using Lepton EDA.

it uses standard symbols, and the ones in the geda/symbols/ folder. most symbols are generated by QEDA as described above.

to export the netlist (in tEDAx format):

rake netlist

to export as pdf:

rake print


to export the bill of material (as CSV):

rake bom


the .lht file is the board layout source file. it has been drawn using coralEDA pcb-rnd.

it uses the symbols from the coraleda/subc/ folder. most symbols are generated by QEDA as described above. oshw_logo.lht is just the Open Source Hardware Logo. it been generated from https://oshwlogo.cuvoodoo.info/.

to export gerber files for PCB manufacturer (and photo preview + overview document):

rake fabrication