board/pd_blocker.kicad_pcb

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(kicad_pcb (version 20211014) (generator pcbnew)
(general
(thickness 0.96184)
)
(paper "A5")
(title_block
(title "USB-C Power Delivery blocker")
(date "$date$")
(rev "$version$.$revision$")
(company "CuVoodoo")
(comment 1 "King Kévin")
(comment 2 "CERN-OHL-S")
)
(layers
(0 "F.Cu" signal)
(1 "In1.Cu" signal)
(2 "In2.Cu" signal)
(31 "B.Cu" signal)
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
)
(setup
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (thickness 0.02032))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 0.2104) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02))
(layer "In1.Cu" (type "copper") (thickness 0.0152))
(layer "dielectric 2" (type "prepreg") (thickness 0.4) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02))
(layer "In2.Cu" (type "copper") (thickness 0.0152))
(layer "dielectric 3" (type "core") (thickness 0.2104) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.02032))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints yes)
)
(pad_to_mask_clearance 0)
(grid_origin 81.3 57)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "/CC1")
(net 2 "GND")
(net 3 "/CC2")
(net 4 "VCC")
(net 5 "/VREF")
(net 6 "/VBUS1")
(net 7 "/VBUS2")
(net 8 "Net-(D2-Pad1)")
(net 9 "Net-(D2-Pad2)")
(net 10 "Net-(D3-Pad1)")
(net 11 "/TX1+")
(net 12 "/TX1-")
(net 13 "/DA+")
(net 14 "/DA-")
(net 15 "/SBU1")
(net 16 "/RX2-")
(net 17 "/RX2+")
(net 18 "/TX2+")
(net 19 "/TX2-")
(net 20 "/DB+")
(net 21 "/DB-")
(net 22 "/SBU2")
(net 23 "/RX1-")
(net 24 "/RX1+")
(net 25 "GNDPWR")
(net 26 "Net-(Q1-Pad1)")
(net 27 "/VBUS")
(net 28 "Net-(Q2-Pad1)")
(net 29 "/VOVER1")
(net 30 "/VOVER2")
(footprint "qeda:SOP65P640X120-14N" (layer "F.Cu")
(tedit 0) (tstamp 0cd5343f-062c-44b1-9497-3795c123ca12)
(at 97.4 61.5)
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