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(comment 1 "King Kévin")
(comment 2 "CERN-OHL-S")
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(text "press while booting to\nstart DFU mode\nhold while running to\nerase settings"
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(text "ESP32-S3:\nhas one UART more than ESP32-S3\nallowing second card emulation\n\nit also adds Bluetooth\nfor possiblt BT SAP feature\n\nbut it's as alterative to S2\nbecause previous PoC uses S2"
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(text "ESP32S2 strapping pins:\nIO45, internal pull-down, VDD_SPI = 3.3V\nIO46, internal pull-down, must be 0\nIO0, external pull-up, boot 1=SPI 0=download"
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(text "ESP32S3 strapping pins:\nIO3, no-pull, JTAG signal 1=USB\nIO45, internal pull-down, VDD_SPI=3.3V\nIO46, internal pull-down, 0 for download\nIO0, internal pull-up, boot 1=SPI 0=download"
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(text "pulse counter:\nESP32-S2/S3 has only one PCTN\n\nwe use a GPIO for easy clock\nactivation/stop using ISR,\ninstead of shared with PCTN\n\npulse counter control signals:\n- 1x LED controller output per precise periodic pulse\n- 1x GPIO IST input to detect end of pulse\n- 1x PCTN input to gate pulse counter"
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(text "press to\nreset MCU" (at 103.505 69.215 0)
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(text "UART:\nwe alway use UART0 for debuging\ndisabling it, including boot log, is not used\n\nESP32-S2 has 2 UARTs, allowing to simulate only one SIM\nESP32-S3 has 3 UARTs, allowing to simulate a second SIM\n\ndon't use UART1 pins IO17/IO18,\nso we can disable pins using GPIO matrix\nUART2 has no dedicated pins\n\nUART TX/RX could be shared, but requires more code\nESP32 has no half-duplex handling"
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(text "ADC:\nmax. volage is Vref = 1.1V (1.0-1.2V)\nwith 11dB attenuation it's 2.6V"
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(text "kOhm=mA\n1.2=1000\n2=580\n3=400\n4=300\n5=250\n10=130" (at 194.31 50.8 0)
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(text "press while booting to\nstart ESP download mode" (at 103.505 83.82 0)
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(text "min. 0.5A" (at 262.89 44.45 0)
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