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brd: improve USB routing

This commit is contained in:
King Kévin 2024-03-28 11:07:39 +01:00
parent 7462e5d59a
commit 64a04c3698
2 changed files with 903 additions and 717 deletions
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1571
passkey.kicad_pcb
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49
passkey.kicad_pro
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@ -57,17 +57,14 @@
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
},
{
"gap": 0.15,
"via_gap": 0.0,
"width": 0.15
}
],
"drc_exclusions": [
"annular_width|51450000|23650000|4cba8b24-e313-48b4-ba95-c576f7884c04|00000000-0000-0000-0000-000000000000",
"annular_width|51450000|25350000|7df18c58-ad9d-42a2-beb7-24719a47fa15|00000000-0000-0000-0000-000000000000",
"annular_width|51450000|29550000|841515e5-1b47-4a21-8190-999b4ec1821a|00000000-0000-0000-0000-000000000000",
"annular_width|51450000|31250000|98ebe259-acd5-45b9-bad7-3f376df1e1ab|00000000-0000-0000-0000-000000000000",
"courtyards_overlap|50159207|23500000|f0f52547-c1bb-4b8e-91e5-1f38ccc8ce9f|fe2ed533-3f51-4988-bfbf-537e793d3e56",
"courtyards_overlap|50359207|31400000|24463778-2471-4e8f-9f58-cd451882454c|688c08ea-8895-4d6e-9600-76033b1f8a87",
"silk_over_copper|51445074|32350000|4bad2e1c-19f5-45dd-aafa-138308d4fe5e|00000000-0000-0000-0000-000000000000"
],
"drc_exclusions": [],
"meta": {
"version": 2
},
@ -490,6 +487,23 @@
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Diff",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
@ -502,7 +516,7 @@
"name": "Thick",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"track_width": 0.3,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
@ -530,7 +544,20 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "Diff",
"pattern": "/D*"
},
{
"netclass": "Thick",
"pattern": "+5V"
},
{
"netclass": "Thick",
"pattern": "+3.3V"
}
]
},
"pcbnew": {
"last_paths": {