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brd: improve part placement

This commit is contained in:
King Kévin 2023-08-09 07:32:32 +02:00
parent 51eb56a1a1
commit 55e1f58680
1 changed files with 301 additions and 231 deletions
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532
RPH0002_connector.kicad_pcb
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@ -226,7 +226,7 @@
(property "ki_keywords" "connector")
(path "/52013bc4-bda1-4545-a6d9-d0b82e2825eb")
(attr through_hole)
(fp_text reference "J7" (at -2.945 4.86 90) (layer "F.SilkS")
(fp_text reference "J7" (at -2.945 4.86 180) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp 62ec95de-0dea-497b-a09b-5f8a4df10b39)
)
@ -851,7 +851,7 @@
(property "qeda_variant" "")
(path "/46ac723e-3546-4560-8065-cdebda84b007")
(attr smd)
(fp_text reference "R11" (at 0.05 -3.1) (layer "F.SilkS")
(fp_text reference "R11" (at -0.8 -2.1 90) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp 5221e5fb-9680-46e5-8a97-dbafbc717cca)
)
@ -1783,7 +1783,7 @@
(footprint "qeda:CAPC1608X92N" (layer "F.Cu")
(tstamp a6c5024b-92d9-44a7-9fec-9e5c49920f11)
(at 64.65 77.1 -90)
(at 66.1 78.5 180)
(property "Description" "100nF ±20% 50V X7R")
(property "DigiKey" "311-1335-1-ND")
(property "JLCPCB" "C14663")
@ -1797,15 +1797,15 @@
(property "qeda_variant" "")
(path "/c9112e58-2811-44c1-a351-a5dc63805414")
(attr smd)
(fp_text reference "C4" (at 0.75 -2.7 -180) (layer "F.SilkS")
(fp_text reference "C4" (at -0.1 -2.8 90) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp 1fa2db79-9c15-4217-8f0c-d628162c5c9d)
)
(fp_text value "0.1uF" (at 0 0) (layer "F.Fab")
(fp_text value "0.1uF" (at 0 0 90) (layer "F.Fab")
(effects (font (size 0.528 0.528) (thickness 0.1)))
(tstamp 96a9b50f-b2e8-4c6f-bd16-d65e33781faa)
)
(fp_text user "REF**" (at 0 0) (layer "F.Fab") hide
(fp_text user "REF**" (at 0 0 90) (layer "F.Fab") hide
(effects (font (size 0.528 0.528) (thickness 0.1)))
(tstamp e5e45869-67ed-4736-af41-51f65177bda5)
)
@ -1843,9 +1843,9 @@
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 230c0f2f-511a-4235-ac13-48cafe2c072a))
(fp_circle (center 0 0) (end 0 0.5)
(stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 81a22c0b-0e71-474f-aedc-743b4e01e7e4))
(pad "1" smd rect (at 0 -0.75 270) (size 1.25 1.1) (layers "F.Cu" "F.Paste" "F.Mask")
(pad "1" smd rect (at 0 -0.75 180) (size 1.25 1.1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 5 "-BATT") (pinfunction "L") (pintype "passive") (solder_mask_margin 0.05) (tstamp b5c69f3f-715f-4ac5-8cf0-4d1dd1e5181e))
(pad "2" smd rect (at 0 0.75 270) (size 1.25 1.1) (layers "F.Cu" "F.Paste" "F.Mask")
(pad "2" smd rect (at 0 0.75 180) (size 1.25 1.1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 9 "+3.3V") (pinfunction "R") (pintype "passive") (solder_mask_margin 0.05) (tstamp c993d34e-c3c9-4e40-b906-73129f379a89))
(model "../qeda.3dshapes/CAPC1608X92N.wrl"
(offset (xyz 0 0 0))
@ -2097,7 +2097,7 @@
(footprint "qeda:CAPC1608X92N" (layer "F.Cu")
(tstamp b69db6b3-f41a-4c06-b74d-dee399eb2143)
(at 63.975786 79.8 180)
(at 64 77.9 180)
(property "Description" "10V X5R 20%")
(property "DigiKey" "")
(property "JLCPCB" "C19702")
@ -2110,7 +2110,7 @@
(property "qeda_variant" "")
(path "/35ca9ed1-0092-4872-9c9f-9a64cbf8073b")
(attr smd)
(fp_text reference "C3" (at -0.024214 -2.8 270) (layer "F.SilkS")
(fp_text reference "C3" (at 0 -3 270) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp cf2b4f37-ab9d-494c-becc-1a736ec32f47)
)
@ -2409,7 +2409,7 @@
(property "qeda_variant" "")
(path "/90b767df-67dc-4d0f-a09c-66f102d99099")
(attr smd)
(fp_text reference "C1" (at -3.4 0.15 -90) (layer "F.SilkS")
(fp_text reference "C1" (at -3.45 -0.45 -90) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp c2725303-5163-49ad-8492-22da235da954)
)
@ -2497,7 +2497,7 @@
(property "qeda_variant" "")
(path "/0292fbc6-c0ce-4176-9ffc-62e66c0ec14a")
(attr smd)
(fp_text reference "R10" (at 0.05 3.1 -180) (layer "F.SilkS")
(fp_text reference "R10" (at -0.8 2.1 -90) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp cb5b054f-2516-4530-8421-c0fd3ad40e86)
)
@ -3545,7 +3545,7 @@
(footprint "qeda:UC1608X55N" (layer "F.Cu")
(tstamp f813a290-3bfd-4f80-b628-46e78d8ba3b2)
(at 63.9 74.75 180)
(at 66.3 75.9 90)
(property "Description" "R0603 10k 1%")
(property "DigiKey" "")
(property "JLCPCB" "")
@ -3559,15 +3559,15 @@
(property "qeda_variant" "")
(path "/57ea2a0c-e629-47e9-b578-ac1d35b0a744")
(attr smd)
(fp_text reference "R3" (at -1.85 0 90) (layer "F.SilkS")
(fp_text reference "R3" (at 3.4 1.7 90) (layer "F.SilkS")
(effects (font (size 1.2 1.2) (thickness 0.2)))
(tstamp bdfd9367-3006-462f-800c-724db03a4df5)
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(fp_text value "10k" (at 0 0 90) (layer "F.Fab")
(fp_text value "10k" (at 0 0) (layer "F.Fab")
(effects (font (size 0.528 0.528) (thickness 0.1)))
(tstamp e6796e2b-4511-4ee0-bca7-415080ed283c)
)
(fp_text user "REF**" (at 0 0 90) (layer "F.Fab") hide
(fp_text user "REF**" (at 0 0) (layer "F.Fab") hide
(effects (font (size 0.528 0.528) (thickness 0.1)))
(tstamp 694211f6-2996-4aa2-a2bf-d271eb98c207)
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@ -3605,9 +3605,9 @@
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4bc19a52-d625-41a0-b8d4-a695832f1255))
(fp_circle (center 0 0) (end 0 0.5)
(stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 3e1d97ed-bad5-4b97-add2-1c2aa34a8b24))
(pad "1" smd rect (at 0 -0.7 180) (size 1.1 0.75) (layers "F.Cu" "F.Paste" "F.Mask")
(pad "1" smd rect (at 0 -0.7 90) (size 1.1 0.75) (layers "F.Cu" "F.Paste" "F.Mask")
(net 9 "+3.3V") (pinfunction "L") (pintype "passive") (solder_mask_margin 0.05) (tstamp c2894cad-341b-40e2-9983-7b8f98e8cd37))
(pad "2" smd rect (at 0 0.7 180) (size 1.1 0.75) (layers "F.Cu" "F.Paste" "F.Mask")
(pad "2" smd rect (at 0 0.7 90) (size 1.1 0.75) (layers "F.Cu" "F.Paste" "F.Mask")
(net 2 "EN") (pinfunction "R") (pintype "passive") (solder_mask_margin 0.05) (tstamp 40923fa4-43ba-4004-9501-093804a19885))
(model "../qeda.3dshapes/UC1608X55N.wrl"
(offset (xyz 0 0 0))
@ -3761,7 +3761,7 @@
)
)
(footprint "logo:CuVoodoo" (layer "B.Cu")
(footprint "logo:CuVoodoo" locked (layer "B.Cu")
(tstamp 602f8cba-062a-4ea7-a259-88bad652e2f0)
(at 73.974999 72.925001 180)
(attr board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
@ -6119,20 +6119,19 @@
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(via (at 29.5 62.7) (size 1) (drill 0.5) (layers "F.Cu" "B.Cu") (net 1) (tstamp 24641b83-ef48-44f3-ad1e-9809341c2fb5))
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