add library to control nodric nRF24L01(+) transceivers
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/* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/* Copyright (c) 2015 King Kévin <kingkevin@cuvoodoo.info> */
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/* This library allows to communicate with a nordic semiconductor nRF24L01 2.4GHz single chip transceiver
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* this library uses the SPI bus and requires interrupts to handle the IRQ
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*/
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#include <stdint.h> // Standard Integer Types
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#include <stdlib.h> // General utilities
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#include <stdbool.h> // Boolean
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#include <string.h> // Memory utilities
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#include <avr/io.h> // AVR device-specific IO definitions
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#include <avr/interrupt.h> // Interrupts
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#include <spi.h> // SPI functions
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#include <nrf24.h> // nRF24L01 configuration
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#include <stdio.h> // Standard IO facilities
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#include <avr/pgmspace.h> // Program Space Utilities
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#if defined(IRQ_DDR) && defined(IRQ_IO)
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/* if the nRF24L01 is initialized with interrupts, watch for nrf_activity to go true
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* once true, check if transmission or reception happened using nrf24_activity(), then nrf24_tx_activity() or nrf24_rx_activity()
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* you can then check is transmission succeeded using nrf24_tx_succeeded()
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* or get the received data using nrf24_rx_data()
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* set it to false after checks are done
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*/
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volatile bool nrf24_flag = false;
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#endif
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/* stay in RX mode to receive data */
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bool rx = false;
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/* initialize the nRF24L01 */
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void nrf24_init()
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{
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// configure SPI
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spi_init(); // SPI is used to communicate with the nRF24L01
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// configure IO
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CE_DDR |= (1<<CE_IO); // set CE as output
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CE_PORT &= ~(1<<CE_IO); // disable CE (TR/RX)
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// initialise variables
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rx = false;
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// power up device
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// use spi_transfer_blocking in case global interrupt has not been enabled
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uint8_t cmd[2]; // to send commands
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_blocking(cmd,sizeof(cmd)); // read configuration
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#if defined(IRQ_DDR) && defined(IRQ_IO)
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cmd[1] &= ~(0x70); // enable interrupt by clearing MASK_RX_DR, MASK_TX_DS, MASK_MAX_RT
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#else
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cmd[1] |= (0x70); // disable interrupt by setting MASK_RX_DR, MASK_TX_DS, MASK_MAX_RT
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#endif
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cmd[1] |= (1<<1); // set PWR_UP to power up
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cmd[1] &= ~(1<<2); // set CRC to 1 byte
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//cmd[1] |= (1<<2); // set CRC to 2 byte
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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spi_transfer_blocking(cmd,sizeof(cmd)); // write configuration
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// flush TX FIFO
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_blocking(cmd,sizeof(cmd)); // read config
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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cmd[1] &= ~(1<<0); // set PRIM_RX to 0 (PTX)
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spi_transfer_blocking(cmd,sizeof(cmd)); // write config to got in PTX mode
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cmd[0] = 0xe1; // FLUSH_TX
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spi_transfer_blocking(cmd,1); // flush TX FIFO
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// flush RX FIFO
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_blocking(cmd,sizeof(cmd)); // read config
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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cmd[1] |= (1<<0); // set PRIM_RX to 1 (PRX)
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spi_transfer_blocking(cmd,sizeof(cmd)); // write config to got in PRX mode
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cmd[0] = 0xe2; // FLUSH_RX
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spi_transfer_blocking(cmd,1); // flush RX FIFO
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// clear interrupts
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cmd[0] = 0x20+0x07; // W_REGISTER command + STATUS register
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cmd[1] = 0x70; // clear interrupts
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spi_transfer_blocking(cmd,sizeof(cmd)); // clear interrupts
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// enable auto acknowledge
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cmd[0] = 0x20+0x01; // W_REGISTER command + EN_AA register
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cmd[1] = 0x3f; // enable auto for all channels
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spi_transfer_blocking(cmd,sizeof(cmd)); // write auto acknowledge
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// enable data pipes 0 (to enable acknowledgement) and 1 (to receive)
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cmd[0] = 0x20+0x02; // W_REGISTER command + EN_RXADDR register
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cmd[1] = 0x03; // enable RX pipes 0 and 1
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spi_transfer_blocking(cmd,sizeof(cmd)); // enable pipes
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// enable dynamic payload
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cmd[0] = 0x20+0x1d; // W_REGISTER command + FEATURE register
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cmd[1] = 0x04; // set EN_DPL
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spi_transfer_blocking(cmd,sizeof(cmd)); // enable dynamic payload
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cmd[0] = 0x20+0x1c; // W_REGISTER command + DYNPD register
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cmd[1] = 0x3f; // set DPL_Px
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spi_transfer_blocking(cmd,sizeof(cmd)); // enable dynamic payload on all pipes
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// set address width to 5 bytes
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cmd[0] = 0x20+0x03; // W_REGISTER command + SETUP_AW register
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cmd[1] = 0x03; // set to 5 bytes
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spi_transfer_blocking(cmd,sizeof(cmd)); // set address width
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// set RF: data rate, power
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cmd[0] = 0x00+0x06; // R_REGISTER command + RF_SETUP register
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spi_transfer_blocking(cmd,sizeof(cmd)); // read RF setup
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cmd[0] = 0x20+0x06; // W_REGISTER command + RF_SETUP register
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cmd[1] &= ~(1<<3); // set RF_DR to 1 Mbps
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//cmd[1] |= (1<<3); // set RF_DR to 2 Mbps
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cmd[1] |= (1<<2)|(1<<1); // set RF_PWR to 0 dBm (max)
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spi_transfer_blocking(cmd,sizeof(cmd)); // set RF: data rate, power
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// set re-transmit properties
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cmd[0] = 0x20+0x04; // W_REGISTER command + SETUP_RETR register
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cmd[1] = 0x1f; // set ARD to 500uS and ARC to 15
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spi_transfer_blocking(cmd,sizeof(cmd)); // set re-transmit properties
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// enable interrupt
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#if defined(IRQ_IO)
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IRQ_DDR &= ~(1<<IRQ_IO); // set IRQ as input
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#if defined(IRQ_INT) && (IRQ_INT==1) && (IRQ_IO==PD2) // INT0 interrupt
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EIMSK |= (1<<INT0); // enable interrupt for IRQ pin
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EICRA &= ~(1<<ISC00); // interrupt on falling edge
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EICRA |= (1<<ISC01); // interrupt on falling edge
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#elif defined(IRQ_INT) && (IRQ_INT==1) && (IRQ_IO==PD3) // INT1 interrupt
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EIMSK |= (1<<INT1); // enable interrupt for IRQ pin
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EICRA &= ~(1<<ISC10); // interrupt on falling edge
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EICRA |= (1<<ISC11); // interrupt on falling edge
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#else // PCINT interrupt
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PCICR |= (1<<IRQ_PCIE); // enable interrupt for IRQ port
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IRQ_PCMSK |= (1<<IRQ_IO); // enable interrupt for IRQ pin
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#endif
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nrf24_flag = false;
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#endif
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}
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/* register names */
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const char reg_00[] PROGMEM = "CONFIG";
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const char reg_01[] PROGMEM = "EN_AA";
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const char reg_02[] PROGMEM = "EN_RXADDR";
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const char reg_03[] PROGMEM = "SETUP_AW";
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const char reg_04[] PROGMEM = "SETUP_RETR";
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const char reg_05[] PROGMEM = "RF_CH";
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const char reg_06[] PROGMEM = "RF_SETUP";
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const char reg_07[] PROGMEM = "STATUS";
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const char reg_08[] PROGMEM = "OBSERVE_TX";
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const char reg_09[] PROGMEM = "CD";
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const char reg_10[] PROGMEM = "RX_ADDR_P0";
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const char reg_11[] PROGMEM = "RX_ADDR_P1";
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const char reg_12[] PROGMEM = "RX_ADDR_P2";
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const char reg_13[] PROGMEM = "RX_ADDR_P3";
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const char reg_14[] PROGMEM = "RX_ADDR_P4";
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const char reg_15[] PROGMEM = "RX_ADDR_P5";
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const char reg_16[] PROGMEM = "TX_ADDR";
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const char reg_17[] PROGMEM = "RX_PW_P0";
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const char reg_18[] PROGMEM = "RX_PW_P1";
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const char reg_19[] PROGMEM = "RX_PW_P2";
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const char reg_20[] PROGMEM = "RX_PW_P3";
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const char reg_21[] PROGMEM = "RX_PW_P4";
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const char reg_22[] PROGMEM = "RX_PW_P5";
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const char reg_23[] PROGMEM = "FIFO_STATUS";
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/* register names table */
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PGM_P const reg_names[] PROGMEM = {
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reg_00,
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reg_01,
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reg_02,
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reg_03,
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reg_04,
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reg_05,
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reg_06,
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reg_07,
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reg_08,
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reg_09,
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reg_10,
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reg_11,
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reg_12,
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reg_13,
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reg_14,
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reg_15,
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reg_16,
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reg_17,
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reg_18,
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reg_19,
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reg_20,
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reg_21,
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reg_22,
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reg_23
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};
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/* register size */
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const uint8_t reg_sizes[] PROGMEM = {1,1,1,1,1,1,1,1,1,1,5,5,1,1,1,1,5,1,1,1,1,1,1,1};
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/* dump config */
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void nrf24_dump()
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{
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uint8_t cmd[6]; // SPI nFR24L01 command
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uint8_t reg_size; // the register size
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char* str; // to print strings
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for (uint8_t i=0; i<sizeof(reg_sizes); i++) { // go through registers
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cmd[0] = 0x00+i; // R_REGISTER command + register
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reg_size = pgm_read_byte(&(reg_sizes[i]));
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spi_transfer_wait(cmd,1+reg_size); // read register
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str = malloc(strlen_PF((uint_farptr_t)pgm_read_word(&(reg_names[i]))));
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strcpy_PF(str, (uint_farptr_t)pgm_read_word(&(reg_names[i])));
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printf(str);
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free(str);
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printf(": ");
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for (uint8_t j=0; j<reg_size; j++) {
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printf("%02x ",cmd[1+j]);
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}
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printf("\n");
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}
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}
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/* set the 5 bytes TX address
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* it will be used as the destination address of the data to transmit
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* this address will also be used (in RX_ADDR_P0) to receive the ack
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*/
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void nrf24_set_tx_addr(uint8_t* addr)
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{
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uint8_t cmd[6]; // command
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cmd[0] = 0x20+0x10; // W_REGISTER command + TX_ADDR register
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memcpy(&cmd[1],addr,sizeof(cmd)-1); // copy address
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spi_transfer_wait(cmd,sizeof(cmd)); // write TX_ADDR
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cmd[0] = 0x20+0x0A; // W_REGISTER command + RX_ADDR_P0 register
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memcpy(&cmd[1],addr,sizeof(cmd)-1); // copy address (since it has been overwritten)
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spi_transfer_wait(cmd,sizeof(cmd)); // write RX_ADDR_P0
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}
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/* set the 5 bytes RX address
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* it will be used as the address of the receiving device
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* this address will be used in RX_ADDR_P1
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*/
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void nrf24_set_rx_addr(uint8_t* addr)
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{
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uint8_t cmd[6]; // command
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cmd[0] = 0x20+0x0B; // W_REGISTER command + RX_ADDR_P1 register
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memcpy(&cmd[1],addr,sizeof(cmd)-1); // copy address
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spi_transfer_wait(cmd,sizeof(cmd)); // write RX_ADDR_P1
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}
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/* set the RF channel to transmit on */
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void nrf24_set_rf_channel(uint8_t channel)
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{
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if (channel>125) {
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return;
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}
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/* verify there is space in the FIFO */
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uint8_t cmd[2]; // command
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cmd[0] = 0x20+0x05; // W_REGISTER command + RF_CH register
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cmd[1] = channel; // set channel
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spi_transfer_wait(cmd,sizeof(cmd)); // write RF_CH
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}
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/* transmit <payload> with of <length> bytes (max 32 bytes)
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* returns false if input is corrupted or FIFO is already full
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* returns true after payload is written
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*/
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bool nrf24_transmit(uint8_t* payload, uint8_t length)
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{
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if (payload==NULL || length==0 || length>32) { // ensure data and size is valid
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return false;
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}
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/* check if TX FIFO is full */
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uint8_t cmd[2]; // command
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cmd[0] = 0x00+0x17; // R_REGISTER command + FIFO_STATUS register
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spi_transfer_wait(cmd,sizeof(cmd)); // read FIFO status
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if (cmd[1]&(1<<5)) { // TX_FULL
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return false;
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}
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/* go into TX mode */
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_wait(cmd,sizeof(cmd)); // read config
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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cmd[1] &= ~(1<<0); // set PRIM_RX to 0 (PTX)
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spi_transfer_wait(cmd,sizeof(cmd)); // write config to got in PTX mode
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/* write TX payload */
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uint8_t* tx = calloc(length+1,sizeof(uint8_t));
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tx[0] = 0xa0; // W_TX_PAYLOAD command
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memcpy(&tx[1],payload,length); // copy data
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spi_transfer_wait(tx,length+1); // write TX payload
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/* start transmission */
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CE_PORT |= (1<<CE_IO); // enable CE to start transmission
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// clean memory (the payload transfer is complete at this point)
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free(tx);
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tx = NULL;
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return true;
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}
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/* put device into RX mode or disable it */
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void nrf24_enable_rx(bool enable)
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{
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rx = enable; // remember to stay in RX mode
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if (rx) {
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uint8_t cmd[2]; // SPI command
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_wait(cmd,sizeof(cmd)); // read config
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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cmd[1] |= (1<<0); // set PRIM_RX to 1 (PRX)
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spi_transfer_wait(cmd,sizeof(cmd)); // write config to got in PRX mode
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CE_PORT |= (1<<CE_IO); // enable CE to start receiving
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} else {
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uint8_t cmd[2]; // SPI command
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_wait(cmd,sizeof(cmd)); // read config
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if (cmd[1]&(1<<0)) { // currently in RX mode
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CE_PORT &= ~(1<<CE_IO); // disable CE to go to sleep
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} // do not disable if in TX mode
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}
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}
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/* handle IRQ interrupt */
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#if defined(IRQ_IO)
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#if defined(IRQ_INT) && (IRQ_INT==1) && (IRQ_IO==PD2) // INT0 interrupt
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ISR(INT0_vect)
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#elif defined(IRQ_INT) && (IRQ_INT==1) && (IRQ_IO==PD3) // INT1 interrupt
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ISR(INT1_vect)
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#else // PCINT interrupt
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ISR(IRQ_PCINT_vect)
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#endif
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{ /* RX or TX succeeded or failed */
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nrf24_flag = true; // warn user
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}
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#endif
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/* check the current status of the device
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* return nrf24_activity_t bits correspoinding to the activies
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* call it after an interrupt
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* puts device back in PRX mode if transmission completed and rx has been enabled
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* puts device back to sleep if transmission completed and rx has not been enabled
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*/
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uint8_t nrf24_activity()
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{
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uint8_t to_return = 0; // is there activity
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uint8_t cmd[2]; // SPI nFR24L01 command
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// get status
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cmd[0] = 0xff; // NOP to read STATUS
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spi_transfer_wait(cmd,1); // read STATUS register
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// clear receive interrupt
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to_return = cmd[0]&(0x70); // copy RX_DR, TS_DS, MAX_RT
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if ((cmd[0]&0x0e)<0x0b) { // payload is available based on RX_P_NO
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to_return |= RX_AVAILABLE; // warn user
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}
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if (cmd[0]&(0x70)) { // activity cause by interrupt
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cmd[0] = 0x20+0x07; // W_REGISTER command + STATUS register
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cmd[1] = 0x70; // clear interrupts
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spi_transfer_wait(cmd,2); // clear interrupt
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}
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if (to_return&TX_FAILED) { // transmission failed based on MAX_RT
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cmd[0] = 0xe1; // FLUSH_TX command
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spi_transfer_wait(cmd,1); // flush failed TX_FIFO
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}
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// verify is there is still data to transmit
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cmd[0] = 0x00+0x17; // R_REGISTER command + FIFO_STATUS register
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spi_transfer_wait(cmd,2); // read FIFO_STATUS register
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if (!(cmd[1]&(1<<4))) { // check TX_EMPTY, if not empty put is TX mode
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_wait(cmd,2); // read config
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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cmd[1] &= ~(1<<0); // set PRIM_RX to 0 (PTX)
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spi_transfer_wait(cmd,2); // write config to got in PTX mode
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CE_PORT |= (1<<CE_IO); // enable CE to start transmission
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} else if (rx) { // go in RX mode if enables (and TX FIFO is empty)
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cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
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spi_transfer_wait(cmd,2); // read config
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cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
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cmd[1] |= (1<<0); // set PRIM_RX to 1 (PRX)
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spi_transfer_wait(cmd,2); // write config to got in PRX mode
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CE_PORT |= (1<<CE_IO); // enable CE to start receiving
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} else { // nothing to send, and RX is not enabled
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CE_PORT &= ~(1<<CE_IO); // disable CE to go to sleep
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}
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return to_return;
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}
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/* verify if data is available in the RX FIFO */
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bool nrf24_data_available()
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{
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||||
uint8_t cmd[2]; // SPI nFR24L01 command
|
||||
cmd[0] = 0x00+0x17; // R_REGISTER command + FIFO_STATUS register
|
||||
spi_transfer_wait(cmd,sizeof(cmd)); // read STATUS register
|
||||
return !(cmd[1]&0x01); // not RX FIFO empty
|
||||
}
|
||||
|
||||
/* writes to received payload in provided <payload> pointer
|
||||
* returns size of received data
|
||||
* returns 0 if no data is available
|
||||
* write maximum <size> in <payload> (max payload size is 32)
|
||||
*/
|
||||
uint8_t nrf24_rx_payload(uint8_t* payload, uint8_t size)
|
||||
{
|
||||
uint8_t to_return = 0; // the size of the data
|
||||
uint8_t cmd[2]; // SPI nFR24L01 command
|
||||
cmd[0] = 0x60; // R_RX_PL_WID command
|
||||
spi_transfer_wait(cmd,2); // get size (and STATUS)
|
||||
if ((cmd[0]&0x0e)==0x0e) { // RX_FIFO empty based on RX_P_NO
|
||||
to_return = 0; // no data is available
|
||||
} else if (cmd[1]>32) { // something is wrong
|
||||
cmd[0] = 0xe2; // FLUSH_RX command
|
||||
spi_transfer_wait(cmd,1); // flush, as suggested by the note
|
||||
to_return = 0;
|
||||
} else { // data is available
|
||||
to_return = cmd[1];
|
||||
if (to_return>size) { // avoid buffer overflow
|
||||
to_return = size;
|
||||
}
|
||||
// go into RX mode
|
||||
cmd[0] = 0x00+0x00; // R_REGISTER command + CONFIG register
|
||||
spi_transfer_wait(cmd,2); // read config
|
||||
cmd[0] = 0x20+0x00; // W_REGISTER command + CONFIG register
|
||||
cmd[1] |= (1<<0); // set PRIM_RX to 1 (PRX)
|
||||
spi_transfer_wait(cmd,2); // write config to got in PRX mode
|
||||
// read RX payload
|
||||
uint8_t* data = calloc(to_return+1,sizeof(uint8_t)); // re-allocated memory to get data
|
||||
data[0] = 0x61; // R_RX_PAYLOAD command
|
||||
spi_transfer_wait(data,to_return+1); // read FIFO (automatically deleted)
|
||||
memcpy(payload,&data[1],to_return); // copy payload
|
||||
free(data); // clean memory
|
||||
data = NULL; // clean memory
|
||||
}
|
||||
|
||||
return to_return;
|
||||
}
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2015 King Kévin <kingkevin@cuvoodoo.info> */
|
||||
/* This library allows to communicate with a nordic semiconductor nRF24L01 2.4GHz single chip transceiver */
|
||||
|
||||
/* Chip Enable pin to activate TX/RX */
|
||||
#define CE_IO PB1
|
||||
#define CE_PORT PORTB
|
||||
#define CE_DDR DDRB
|
||||
#define CE_PIN PINB
|
||||
/* Interrupt ReQuest pin to activate TX/RX */
|
||||
// comment out IRQ_IO if you don't want to use interrupts
|
||||
#define IRQ_IO PD2
|
||||
#define IRQ_PORT PORTD
|
||||
#define IRQ_DDR DDRD
|
||||
#define IRQ_PIN PIND
|
||||
#define IRQ_PCIE PCIE2
|
||||
#define IRQ_PCMSK PCMSK2
|
||||
#define IRQ_PCINT_vect PCINT2_vect
|
||||
// if you use PD2 or PD3 you can use the INT0 or INT1 interrupt so to not take over a whole PORT PCINT interrupt
|
||||
#if defined(IRQ_IO) && ((IRQ_IO==PD2)||(IRQ_IO==PD3))
|
||||
// comment or set to 0 if you prefer to use PCINT interrupt
|
||||
// define and set to 1 if you prefer to use INT interrupt
|
||||
#define IRQ_INT 1
|
||||
#endif
|
||||
|
||||
#if defined(IRQ_DDR) && defined(IRQ_IO)
|
||||
/* if the nRF24L01 is initialized with interrupts, watch for nrf_activity to go true
|
||||
* once true, check if transmission or reception happened using nrf24_activity(), then nrf24_tx_activity() or nrf24_rx_activity()
|
||||
* you can then check is transmission succeeded using nrf24_tx_succeeded()
|
||||
* or get the received data using nrf24_rx_data()
|
||||
* set it to false after checks are done
|
||||
*/
|
||||
extern volatile bool nrf24_flag;
|
||||
#endif
|
||||
|
||||
/* initialize the nRF24L01 */
|
||||
void nrf24_init();
|
||||
/* set the 5 bytes TX address
|
||||
* it will be used as the destination address of the data to transmit
|
||||
* this address will also be used (in RX_ADDR_P0) to receive the ack
|
||||
*/
|
||||
void nrf24_set_tx_addr(uint8_t* addr);
|
||||
/* set the 5 bytes RX address
|
||||
* it will be used as the address of the receiving device
|
||||
* this address will be used in RX_ADDR_P1
|
||||
*/
|
||||
void nrf24_set_rx_addr(uint8_t* addr);
|
||||
/* set the RF channel to transmit on */
|
||||
void nrf24_set_rf_channel(uint8_t channel);
|
||||
/* transmit <payload> with of <length> bytes (max 32 bytes)
|
||||
* returns false if input is corrupted or FIFO is already full
|
||||
* returns true after payload is written
|
||||
*/
|
||||
bool nrf24_transmit(uint8_t* payload, uint8_t length);
|
||||
/* put device into RX mode or disable it */
|
||||
void nrf24_enable_rx(bool enable);
|
||||
/* handle IRQ interrupt */
|
||||
#if defined(IRQ_IO)
|
||||
#if defined(IRQ_INT) && (IRQ_INT==1) && (IRQ_IO==PD2) // INT0 interrupt
|
||||
ISR(INT0_vect);
|
||||
#elif defined(IRQ_INT) && (IRQ_INT==1) && (IRQ_IO==PD3) // INT1 interrupt
|
||||
ISR(INT1_vect);
|
||||
#else // PCINT interrupt
|
||||
ISR(IRQ_PCINT_vect);
|
||||
#endif
|
||||
#endif
|
||||
/* check the current status of the device
|
||||
* return nrf24_activities bits correspoinding to the activies
|
||||
* call it after an interrupt
|
||||
* puts device back in PRX mode if transmission completed and rx has been enabled
|
||||
* puts device back to sleep if transmission completed and rx has not been enabled
|
||||
*/
|
||||
enum nrf24_activities {
|
||||
TX_SUCCEEDED = (1<<5),
|
||||
TX_FAILED = (1<<4),
|
||||
RX_RECEIVED = (1<<6),
|
||||
RX_AVAILABLE = (1<<3)
|
||||
};
|
||||
uint8_t nrf24_activity();
|
||||
/* writes to received payload in provided <payload> pointer
|
||||
* returns size of received data
|
||||
* returns 0 if no data is available
|
||||
* write maximum <size> in <payload> (max payload size is 32)
|
||||
*/
|
||||
uint8_t nrf24_rx_payload(uint8_t* payload, uint8_t size);
|
||||
/* verify if data is available in the RX FIFO */
|
||||
bool nrf24_data_available();
|
||||
/* dump config */
|
||||
void nrf24_dump();
|
||||
Loading…
Reference in New Issue