stm8s.h: fix bit fields type

This commit is contained in:
King Kévin 2021-07-20 02:20:00 +02:00
parent 257b29c908
commit 45322fd017
1 changed files with 288 additions and 288 deletions

576
stm8s.h
View File

@ -94,14 +94,14 @@ typedef struct {
#define PA_DDR (*(volatile uint8_t *)(PA_BASE + 0x02))
#define PA_CR1 (*(volatile uint8_t *)(PA_BASE + 0x03))
#define PA_CR2 (*(volatile uint8_t *)(PA_BASE + 0x04))
#define PA0 (1 << 0)
#define PA1 (1 << 1)
#define PA2 (1 << 2)
#define PA3 (1 << 3)
#define PA4 (1 << 4)
#define PA5 (1 << 5)
#define PA6 (1 << 6)
#define PA7 ((uint8_t)(1 << 7))
#define PA0 (1U << 0)
#define PA1 (1U << 1)
#define PA2 (1U << 2)
#define PA3 (1U << 3)
#define PA4 (1U << 4)
#define PA5 (1U << 5)
#define PA6 (1U << 6)
#define PA7 ((uint8_t)(1U << 7))
// Block: Port B
#define PB_BASE 0x5005
#define GPIO_PB ((GPIO_type*)PB_BASE)
@ -110,14 +110,14 @@ typedef struct {
#define PB_DDR (*(volatile uint8_t *)(PB_BASE + 0x02))
#define PB_CR1 (*(volatile uint8_t *)(PB_BASE + 0x03))
#define PB_CR2 (*(volatile uint8_t *)(PB_BASE + 0x04))
#define PB0 (1 << 0)
#define PB1 (1 << 1)
#define PB2 (1 << 2)
#define PB3 (1 << 3)
#define PB4 (1 << 4)
#define PB5 (1 << 5)
#define PB6 (1 << 6)
#define PB7 ((uint8_t)(1 << 7))
#define PB0 (1U << 0)
#define PB1 (1U << 1)
#define PB2 (1U << 2)
#define PB3 (1U << 3)
#define PB4 (1U << 4)
#define PB5 (1U << 5)
#define PB6 (1U << 6)
#define PB7 ((uint8_t)(1U << 7))
// Block: Port C
#define PC_BASE 0x500A
#define GPIO_PC ((GPIO_type*)PC_BASE)
@ -126,14 +126,14 @@ typedef struct {
#define PC_DDR (*(volatile uint8_t *)(PC_BASE + 0x02))
#define PC_CR1 (*(volatile uint8_t *)(PC_BASE + 0x03))
#define PC_CR2 (*(volatile uint8_t *)(PC_BASE + 0x04))
#define PC0 (1 << 0)
#define PC1 (1 << 1)
#define PC2 (1 << 2)
#define PC3 (1 << 3)
#define PC4 (1 << 4)
#define PC5 (1 << 5)
#define PC6 (1 << 6)
#define PC7 ((uint8_t)(1 << 7))
#define PC0 (1U << 0)
#define PC1 (1U << 1)
#define PC2 (1U << 2)
#define PC3 (1U << 3)
#define PC4 (1U << 4)
#define PC5 (1U << 5)
#define PC6 (1U << 6)
#define PC7 ((uint8_t)(1U << 7))
// Block: Port D
#define PD_BASE 0x500F
#define GPIO_PD ((GPIO_type*)PD_BASE)
@ -142,14 +142,14 @@ typedef struct {
#define PD_DDR (*(volatile uint8_t *)(PD_BASE + 0x02))
#define PD_CR1 (*(volatile uint8_t *)(PD_BASE + 0x03))
#define PD_CR2 (*(volatile uint8_t *)(PD_BASE + 0x04))
#define PD0 (1 << 0)
#define PD1 (1 << 1)
#define PD2 (1 << 2)
#define PD3 (1 << 3)
#define PD4 (1 << 4)
#define PD5 (1 << 5)
#define PD6 (1 << 6)
#define PD7 ((uint8_t)(1 << 7))
#define PD0 (1U << 0)
#define PD1 (1U << 1)
#define PD2 (1U << 2)
#define PD3 (1U << 3)
#define PD4 (1U << 4)
#define PD5 (1U << 5)
#define PD6 (1U << 6)
#define PD7 ((uint8_t)(1U << 7))
// Block: Port E
#define PE_BASE 0x5014
#define GPIO_PE ((GPIO_type*)PE_BASE)
@ -158,14 +158,14 @@ typedef struct {
#define PE_DDR (*(volatile uint8_t *)(PE_BASE + 0x02))
#define PE_CR1 (*(volatile uint8_t *)(PE_BASE + 0x03))
#define PE_CR2 (*(volatile uint8_t *)(PE_BASE + 0x04))
#define PE0 (1 << 0)
#define PE1 (1 << 1)
#define PE2 (1 << 2)
#define PE3 (1 << 3)
#define PE4 (1 << 4)
#define PE5 (1 << 5)
#define PE6 (1 << 6)
#define PE7 ((uint8_t)(1 << 7))
#define PE0 (1U << 0)
#define PE1 (1U << 1)
#define PE2 (1U << 2)
#define PE3 (1U << 3)
#define PE4 (1U << 4)
#define PE5 (1U << 5)
#define PE6 (1U << 6)
#define PE7 ((uint8_t)(1U << 7))
// Block: Port F
#define PF_BASE 0x5019
#define GPIO_PF ((GPIO_type*)PF_BASE)
@ -174,14 +174,14 @@ typedef struct {
#define PF_DDR (*(volatile uint8_t *)(PF_BASE + 0x02))
#define PF_CR1 (*(volatile uint8_t *)(PF_BASE + 0x03))
#define PF_CR2 (*(volatile uint8_t *)(PF_BASE + 0x04))
#define PF0 (1 << 0)
#define PF1 (1 << 1)
#define PF2 (1 << 2)
#define PF3 (1 << 3)
#define PF4 (1 << 4)
#define PF5 (1 << 5)
#define PF6 (1 << 6)
#define PF7 ((uint8_t)(1 << 7))
#define PF0 (1U << 0)
#define PF1 (1U << 1)
#define PF2 (1U << 2)
#define PF3 (1U << 3)
#define PF4 (1U << 4)
#define PF5 (1U << 5)
#define PF6 (1U << 6)
#define PF7 ((uint8_t)(1U << 7))
// General hardware register map
// Block: Flash
@ -285,42 +285,42 @@ typedef struct {
#define FLASH_BASE 0x505A
#define FLASH ((FLASH_type*)FLASH_BASE)
#define FLASH_CR1 (*(volatile uint8_t *)(FLASH_BASE + 0x00))
#define FLASH_CR1_FIX (1 << 0)
#define FLASH_CR1_IE (1 << 1)
#define FLASH_CR1_AHALT (1 << 2)
#define FLASH_CR1_HALT (1 << 3)
#define FLASH_CR1_FIX (1U << 0)
#define FLASH_CR1_IE (1U << 1)
#define FLASH_CR1_AHALT (1U << 2)
#define FLASH_CR1_HALT (1U << 3)
#define FLASH_CR2 (*(volatile uint8_t *)(FLASH_BASE + 0x01))
#define FLASH_CR2_PRG (1 << 0)
#define FLASH_CR2_FPRG (1 << 4)
#define FLASH_CR2_ERASE (1 << 5)
#define FLASH_CR2_WPRG (1 << 6)
#define FLASH_CR2_OPT (1 << 7)
#define FLASH_CR2_PRG (1U << 0)
#define FLASH_CR2_FPRG (1U << 4)
#define FLASH_CR2_ERASE (1U << 5)
#define FLASH_CR2_WPRG (1U << 6)
#define FLASH_CR2_OPT (1U << 7)
#define FLASH_NCR2 (*(volatile uint8_t *)(FLASH_BASE + 0x02))
#define FLASH_NCR2_NPRG (1 << 0)
#define FLASH_NCR2_NFPRG (1 << 4)
#define FLASH_NCR2_NERASE (1 << 5)
#define FLASH_NCR2_NWPRG (1 << 6)
#define FLASH_NCR2_NOPT (1 << 7)
#define FLASH_NCR2_NPRG (1U << 0)
#define FLASH_NCR2_NFPRG (1U << 4)
#define FLASH_NCR2_NERASE (1U << 5)
#define FLASH_NCR2_NWPRG (1U << 6)
#define FLASH_NCR2_NOPT (1U << 7)
#define FLASH_FPR (*(volatile uint8_t *)(FLASH_BASE + 0x03))
#define FLASH_FPR_WPB0 (1 << 0)
#define FLASH_FPR_WPB1 (1 << 1)
#define FLASH_FPR_WPB2 (1 << 2)
#define FLASH_FPR_WPB3 (1 << 3)
#define FLASH_FPR_WPB4 (1 << 4)
#define FLASH_FPR_WPB5 (1 << 5)
#define FLASH_FPR_WPB0 (1U << 0)
#define FLASH_FPR_WPB1 (1U << 1)
#define FLASH_FPR_WPB2 (1U << 2)
#define FLASH_FPR_WPB3 (1U << 3)
#define FLASH_FPR_WPB4 (1U << 4)
#define FLASH_FPR_WPB5 (1U << 5)
#define FLASH_NFPR (*(volatile uint8_t *)(FLASH_BASE + 0x04))
#define FLASH_NFPR_NWPB0 (1 << 0)
#define FLASH_NFPR_NWPB1 (1 << 1)
#define FLASH_NFPR_NWPB2 (1 << 2)
#define FLASH_NFPR_NWPB3 (1 << 3)
#define FLASH_NFPR_NWPB4 (1 << 4)
#define FLASH_NFPR_NWPB5 (1 << 5)
#define FLASH_NFPR_NWPB0 (1U << 0)
#define FLASH_NFPR_NWPB1 (1U << 1)
#define FLASH_NFPR_NWPB2 (1U << 2)
#define FLASH_NFPR_NWPB3 (1U << 3)
#define FLASH_NFPR_NWPB4 (1U << 4)
#define FLASH_NFPR_NWPB5 (1U << 5)
#define FLASH_IAPSR (*(volatile uint8_t *)(FLASH_BASE + 0x05))
#define FLASH_IAPSR_WR_PG_DIS (1 << 0)
#define FLASH_IAPSR_PUL (1 << 1)
#define FLASH_IAPSR_EOP (1 << 2)
#define FLASH_IAPSR_DUL (1 << 3)
#define FLASH_IAPSR_HVOFF (1 << 6)
#define FLASH_IAPSR_WR_PG_DIS (1U << 0)
#define FLASH_IAPSR_PUL (1U << 1)
#define FLASH_IAPSR_EOP (1U << 2)
#define FLASH_IAPSR_DUL (1U << 3)
#define FLASH_IAPSR_HVOFF (1U << 6)
#define FLASH_PUKR (*(volatile uint8_t *)(FLASH_BASE + 0x08))
#define FLASH_PUKR_KEY1 0x56
#define FLASH_PUKR_KEY2 0xAE
@ -367,7 +367,7 @@ typedef struct {
#define EXTI_CR2 (*(volatile uint8_t *)(EXTI_BASE + 0x01))
#define EXTI_CR2_PEIS_OFFSET 0
#define EXTI_CR2_PEIS_MASK 0x3
#define EXTI_CR2_TLIS (1 << 2)
#define EXTI_CR2_TLIS (1U << 2)
#define EXTI_FALLING_EDGE_LOW_LEVEL 0
#define EXTI_RISING_EDGE 1
#define EXTI_FALLING_EDGE 2
@ -392,11 +392,11 @@ typedef struct {
#define RST_BASE 0x50B3
#define RST ((RST_type*)RST_BASE)
#define RST_SR (*(volatile uint8_t *)(RST_BASE + 0x00))
#define RST_SR_WWDGF (1 << 0)
#define RST_SR_IWDGF (1 << 1)
#define RST_SR_ILLOPF (1 << 2)
#define RST_SR_SWIMF (1 << 3)
#define RST_SR_EMCF (1 << 4)
#define RST_SR_WWDGF (1U << 0)
#define RST_SR_IWDGF (1U << 1)
#define RST_SR_ILLOPF (1U << 2)
#define RST_SR_SWIMF (1U << 3)
#define RST_SR_EMCF (1U << 4)
// Block: CLK
typedef union {
@ -533,15 +533,15 @@ typedef struct {
#define CLK_BASE 0x50C0
#define CLK ((CLK_type*)CLK_BASE)
#define CLK_ICKR (*(volatile uint8_t *)(CLK_BASE + 0x00))
#define CLK_ICKR_HSIEN (1 << 0)
#define CLK_ICKR_HSIRDY (1 << 1)
#define CLK_ICKR_FHW (1 << 2)
#define CLK_ICKR_LSIEN (1 << 3)
#define CLK_ICKR_LSIRDY (1 << 4)
#define CLK_ICKR_REGAH (1 << 5)
#define CLK_ICKR_HSIEN (1U << 0)
#define CLK_ICKR_HSIRDY (1U << 1)
#define CLK_ICKR_FHW (1U << 2)
#define CLK_ICKR_LSIEN (1U << 3)
#define CLK_ICKR_LSIRDY (1U << 4)
#define CLK_ICKR_REGAH (1U << 5)
#define CLK_ECKR (*(volatile uint8_t *)(CLK_BASE + 0x01))
#define CLK_ECKR_HSEEN (1 << 0)
#define CLK_ECKR_HSERDY (1 << 1)
#define CLK_ECKR_HSEEN (1U << 0)
#define CLK_ECKR_HSERDY (1U << 1)
#define CLK_CMSR (*(volatile uint8_t *)(CLK_BASE + 0x03))
#define CLK_CMSR_CKM_OFFSET 0
#define CLK_CMSR_CKM_MASK 0xff
@ -552,10 +552,10 @@ typedef struct {
#define CLK_SWR_SWI_OFFSET 0
#define CLK_SWR_SWI_MASK 0xff
#define CLK_SWCR (*(volatile uint8_t *)(CLK_BASE + 0x05))
#define CLK_SWCR_SWBSY (1 << 0)
#define CLK_SWCR_SWEN (1 << 1)
#define CLK_SWCR_SWIEN (1 << 2)
#define CLK_SWCR_SWIF (1 << 3)
#define CLK_SWCR_SWBSY (1U << 0)
#define CLK_SWCR_SWEN (1U << 1)
#define CLK_SWCR_SWIEN (1U << 2)
#define CLK_SWCR_SWIF (1U << 3)
#define CLK_CKDIVR (*(volatile uint8_t *)(CLK_BASE + 0x06))
#define CLK_CKDIVR_CPUDIV_OFFSET 0
#define CLK_CKDIVR_CPUDIV_MASK 0x7
@ -574,20 +574,20 @@ typedef struct {
#define CLK_CKDIVR_HSIDIV_DIV4 2
#define CLK_CKDIVR_HSIDIV_DIV8 3
#define CLK_PCKENR1 (*(volatile uint8_t *)(CLK_BASE + 0x07))
#define CLK_PCKENR1_I2C (1 << 0)
#define CLK_PCKENR1_SPI (1 << 1)
#define CLK_PCKENR1_I2C (1U << 0)
#define CLK_PCKENR1_SPI (1U << 1)
#define CLK_PCKENR1_UART1234 (3 << 2)
#define CLK_PCKENR1_TIM46 (1 << 4)
#define CLK_PCKENR1_TIM25 (1 << 5)
#define CLK_PCKENR1_TIM3 (1 << 6)
#define CLK_PCKENR1_TIM1 (1 << 7)
#define CLK_PCKENR1_TIM46 (1U << 4)
#define CLK_PCKENR1_TIM25 (1U << 5)
#define CLK_PCKENR1_TIM3 (1U << 6)
#define CLK_PCKENR1_TIM1 (1U << 7)
#define CLK_CSSR (*(volatile uint8_t *)(CLK_BASE + 0x08))
#define CLK_CSSR_CSSEN (1 << 0)
#define CLK_CSSR_AUX (1 << 1)
#define CLK_CSSR_CSSDIE (1 << 2)
#define CLK_CSSR_CSSD (1 << 3)
#define CLK_CSSR_CSSEN (1U << 0)
#define CLK_CSSR_AUX (1U << 1)
#define CLK_CSSR_CSSDIE (1U << 2)
#define CLK_CSSR_CSSD (1U << 3)
#define CLK_CCOR (*(volatile uint8_t *)(CLK_BASE + 0x09))
#define CLK_CCOR_CCOEN (1 << 0)
#define CLK_CCOR_CCOEN (1U << 0)
#define CLK_CCOR_CCOSEL_OFFSET 1
#define CLK_CCOR_CCOSEL_MASK 0xf
#define CLK_CCOR_CCOSEL_HSIDIV 0
@ -602,17 +602,17 @@ typedef struct {
#define CLK_CCOR_CCOSEL_CPU_DIV64 10
#define CLK_CCOR_CCOSEL_HSI 11
#define CLK_CCOR_CCOSEL_MASTER 12
#define CLK_CCOR_CCORDY (1 << 5)
#define CLK_CCOR_CCOBSY (1 << 6)
#define CLK_CCOR_CCORDY (1U << 5)
#define CLK_CCOR_CCOBSY (1U << 6)
#define CLK_PCKENR2 (*(volatile uint8_t *)(CLK_BASE + 0x0A))
#define CLK_PCKENR2_AWU (1 << 2)
#define CLK_PCKENR2_ADC (1 << 3)
#define CLK_PCKENR2_CAN (1 << 7)
#define CLK_PCKENR2_AWU (1U << 2)
#define CLK_PCKENR2_ADC (1U << 3)
#define CLK_PCKENR2_CAN (1U << 7)
#define CLK_HSITRIMR (*(volatile uint8_t *)(CLK_BASE + 0x0C))
#define CLK_HSITRIMR_OFFSET 0
#define CLK_HSITRIMR_MASK 0xf
#define CLK_SWIMCCR (*(volatile uint8_t *)(CLK_BASE + 0x0D))
#define CLK_SWIMCCR_SWIMCLK (1 << 0)
#define CLK_SWIMCCR_SWIMCLK (1U << 0)
// Block: WWDG
typedef union {
@ -652,14 +652,14 @@ typedef struct {
#define WWDG_CR (*(volatile uint8_t *)(WWDG_BASE + 0x00))
#define WWDG_CR_T_OFFSET 0
#define WWDG_CR_T_MASK 0x7f
#define WWDG_CR_T0 (1 << 0)
#define WWDG_CR_T1 (1 << 1)
#define WWDG_CR_T2 (1 << 2)
#define WWDG_CR_T3 (1 << 3)
#define WWDG_CR_T4 (1 << 4)
#define WWDG_CR_T5 (1 << 5)
#define WWDG_CR_T6 (1 << 6)
#define WWDG_CR_WDGA (1 << 7)
#define WWDG_CR_T0 (1U << 0)
#define WWDG_CR_T1 (1U << 1)
#define WWDG_CR_T2 (1U << 2)
#define WWDG_CR_T3 (1U << 3)
#define WWDG_CR_T4 (1U << 4)
#define WWDG_CR_T5 (1U << 5)
#define WWDG_CR_T6 (1U << 6)
#define WWDG_CR_WDGA (1U << 7)
#define WWDG_WR (*(volatile uint8_t *)(WWDG_BASE + 0x01))
#define WWDG_WR_W_OFFSET 0
#define WWDG_WR_W_MASK 0x7f
@ -742,9 +742,9 @@ typedef struct {
#define AWU_BASE 0x50F0
#define AWU ((AWU_type*)AWU_BASE)
#define AWU_CSR (*(volatile uint8_t *)(AWU_BASE + 0x00))
#define AWU_CSR_MSR (1 << 0)
#define AWU_CSR_AWUEN (1 << 4)
#define AWU_CSR_AWUF (1 << 5)
#define AWU_CSR_MSR (1U << 0)
#define AWU_CSR_AWUEN (1U << 4)
#define AWU_CSR_AWUF (1U << 5)
#define AWU_APR (*(volatile uint8_t *)(AWU_BASE + 0x01))
#define AWU_TBR (*(volatile uint8_t *)(AWU_BASE + 0x02))
@ -1016,46 +1016,46 @@ typedef struct {
#define I2C_BASE 0x5210
#define I2C ((I2C_type*)I2C_BASE)
#define I2C_CR1 (*(volatile uint8_t *)(I2C_BASE + 0x00))
#define I2C_CR1_PE (1 << 0)
#define I2C_CR1_ENGC (1 << 6)
#define I2C_CR1_NOSTRETCH (1 << 7)
#define I2C_CR1_PE (1U << 0)
#define I2C_CR1_ENGC (1U << 6)
#define I2C_CR1_NOSTRETCH (1U << 7)
#define I2C_CR2 (*(volatile uint8_t *)(I2C_BASE + 0x01))
#define I2C_CR2_START (1 << 0)
#define I2C_CR2_STOP (1 << 1)
#define I2C_CR2_ACK (1 << 2)
#define I2C_CR2_POS (1 << 3)
#define I2C_CR2_SWRST (1 << 7)
#define I2C_CR2_START (1U << 0)
#define I2C_CR2_STOP (1U << 1)
#define I2C_CR2_ACK (1U << 2)
#define I2C_CR2_POS (1U << 3)
#define I2C_CR2_SWRST (1U << 7)
#define I2C_FREQR (*(volatile uint8_t *)(I2C_BASE + 0x02))
#define I2C_OARL (*(volatile uint8_t *)(I2C_BASE + 0x03))
#define I2C_OARL_ARR0 (1 << 0)
#define I2C_OARL_ARR0 (1U << 0)
#define I2C_OARH (*(volatile uint8_t *)(I2C_BASE + 0x04))
#define I2C_OARH_ADDCONF (1 << 6)
#define I2C_OARH_ADDMODE (1 << 7)
#define I2C_OARH_ADDCONF (1U << 6)
#define I2C_OARH_ADDMODE (1U << 7)
#define I2C_DR (*(volatile uint8_t *)(I2C_BASE + 0x06))
#define I2C_SR1 (*(volatile uint8_t *)(I2C_BASE + 0x07))
#define I2C_SR1_SB (1 << 0)
#define I2C_SR1_ADDR (1 << 1)
#define I2C_SR1_BTF (1 << 2)
#define I2C_SR1_ADD10 (1 << 3)
#define I2C_SR1_STOPF (1 << 4)
#define I2C_SR1_RXNE (1 << 6)
#define I2C_SR1_TXE (1 << 7)
#define I2C_SR1_SB (1U << 0)
#define I2C_SR1_ADDR (1U << 1)
#define I2C_SR1_BTF (1U << 2)
#define I2C_SR1_ADD10 (1U << 3)
#define I2C_SR1_STOPF (1U << 4)
#define I2C_SR1_RXNE (1U << 6)
#define I2C_SR1_TXE (1U << 7)
#define I2C_SR2 (*(volatile uint8_t *)(I2C_BASE + 0x08))
#define I2C_SR2_BERR (1 << 0)
#define I2C_SR2_ARLO (1 << 1)
#define I2C_SR2_AF (1 << 2)
#define I2C_SR2_OVR (1 << 3)
#define I2C_SR2_WUFH (1 << 5)
#define I2C_SR2_BERR (1U << 0)
#define I2C_SR2_ARLO (1U << 1)
#define I2C_SR2_AF (1U << 2)
#define I2C_SR2_OVR (1U << 3)
#define I2C_SR2_WUFH (1U << 5)
#define I2C_SR3 (*(volatile uint8_t *)(I2C_BASE + 0x09))
#define I2C_SR3_MSL (1 << 0)
#define I2C_SR3_BUSY (1 << 1)
#define I2C_SR3_TRA (1 << 2)
#define I2C_SR3_GENCALL (1 << 4)
#define I2C_SR3_DUALF (1 << 7)
#define I2C_SR3_MSL (1U << 0)
#define I2C_SR3_BUSY (1U << 1)
#define I2C_SR3_TRA (1U << 2)
#define I2C_SR3_GENCALL (1U << 4)
#define I2C_SR3_DUALF (1U << 7)
#define I2C_ITR (*(volatile uint8_t *)(I2C_BASE + 0x0A))
#define I2C_ITR_ITERREN (1 << 0)
#define I2C_ITR_ITEVTEN (1 << 1)
#define I2C_ITR_ITBUFEN (1 << 2)
#define I2C_ITR_ITERREN (1U << 0)
#define I2C_ITR_ITEVTEN (1U << 1)
#define I2C_ITR_ITBUFEN (1U << 2)
#define I2C_CCRL (*(volatile uint8_t *)(I2C_BASE + 0x0B))
#define I2C_CCRH (*(volatile uint8_t *)(I2C_BASE + 0x0C))
#define I2C_CCRH_DUTY (1U << 6)
@ -2386,36 +2386,36 @@ typedef struct {
// Block: TIM2
#define TIM2_CR1 (*(volatile uint8_t *)(TIM2_BASE + 0x00))
#define TIM2_CR1_CEN (1 << 0)
#define TIM2_CR1_UDIS (1 << 1)
#define TIM2_CR1_URS (1 << 2)
#define TIM2_CR1_OPM (1 << 3)
#define TIM2_CR1_APRE (1 << 7)
#define TIM2_CR1_CEN (1U << 0)
#define TIM2_CR1_UDIS (1U << 1)
#define TIM2_CR1_URS (1U << 2)
#define TIM2_CR1_OPM (1U << 3)
#define TIM2_CR1_APRE (1U << 7)
#define TIM2_IER (*(volatile uint8_t *)(TIM2_BASE + 0x03))
#define TIM2_IER_UIE (1 << 0)
#define TIM2_IER_CC1IE (1 << 1)
#define TIM2_IER_CC2IE (1 << 2)
#define TIM2_IER_CC3IE (1 << 3)
#define TIM2_IER_TIE (1 << 6)
#define TIM2_IER_UIE (1U << 0)
#define TIM2_IER_CC1IE (1U << 1)
#define TIM2_IER_CC2IE (1U << 2)
#define TIM2_IER_CC3IE (1U << 3)
#define TIM2_IER_TIE (1U << 6)
#define TIM2_SR1 (*(volatile uint8_t *)(TIM2_BASE + 0x04))
#define TIM2_SR1_UIF (1 << 0)
#define TIM2_SR1_CC1IF (1 << 1)
#define TIM2_SR1_CC2IF (1 << 2)
#define TIM2_SR1_CC3IF (1 << 3)
#define TIM2_SR1_TIF (1 << 6)
#define TIM2_SR1_UIF (1U << 0)
#define TIM2_SR1_CC1IF (1U << 1)
#define TIM2_SR1_CC2IF (1U << 2)
#define TIM2_SR1_CC3IF (1U << 3)
#define TIM2_SR1_TIF (1U << 6)
#define TIM2_SR2 (*(volatile uint8_t *)(TIM2_BASE + 0x05))
#define TIM2_SR2_CC1OF (1 << 1)
#define TIM2_SR2_CC2OF (1 << 2)
#define TIM2_SR2_CC3OF (1 << 3)
#define TIM2_SR2_CC1OF (1U << 1)
#define TIM2_SR2_CC2OF (1U << 2)
#define TIM2_SR2_CC3OF (1U << 3)
#define TIM2_EGR (*(volatile uint8_t *)(TIM2_BASE + 0x06))
#define TIM2_EGR_CC1G (1 << 1)
#define TIM2_EGR_CC2G (1 << 2)
#define TIM2_EGR_CC3G (1 << 3)
#define TIM2_EGR_TG (1 << 6)
#define TIM2_EGR_CC1G (1U << 1)
#define TIM2_EGR_CC2G (1U << 2)
#define TIM2_EGR_CC3G (1U << 3)
#define TIM2_EGR_TG (1U << 6)
#define TIM2_CCMR1 (*(volatile uint8_t *)(TIM2_BASE + 0x07))
#define TIM2_CCMR1_CC1S_OFFSET 0
#define TIM2_CCMR1_CC1S_MASK 0x3
#define TIM2_CCMR1_CC1PE (1 << 3)
#define TIM2_CCMR1_CC1PE (1U << 3)
#define TIM2_CCMR1_OC1M_OFFSET 4
#define TIM2_CCMR1_OC1M_MASK 0x7
#define TIM2_CCMR1_CC1S_OFFSET 0
@ -2427,7 +2427,7 @@ typedef struct {
#define TIM2_CCMR2 (*(volatile uint8_t *)(TIM2_BASE + 0x08))
#define TIM2_CCMR2_CC2S_OFFSET 0
#define TIM2_CCMR2_CC2S_MASK 0x3
#define TIM2_CCMR2_CC2PE (1 << 3)
#define TIM2_CCMR2_CC2PE (1U << 3)
#define TIM2_CCMR2_OC2M_OFFSET 4
#define TIM2_CCMR2_OC2M_MASK 0x7
#define TIM2_CCMR2_CC2S_OFFSET 0
@ -2439,7 +2439,7 @@ typedef struct {
#define TIM2_CCMR3 (*(volatile uint8_t *)(TIM2_BASE + 0x09))
#define TIM2_CCMR3_CC3S_OFFSET 0
#define TIM2_CCMR3_CC3S_MASK 0x3
#define TIM2_CCMR3_CC3PE (1 << 3)
#define TIM2_CCMR3_CC3PE (1U << 3)
#define TIM2_CCMR3_OC3M_OFFSET 4
#define TIM2_CCMR3_OC3M_MASK 0x7
#define TIM2_CCMR3_CC3S_OFFSET 0
@ -2449,13 +2449,13 @@ typedef struct {
#define TIM2_CCMR3_IC3F_OFFSET 4
#define TIM2_CCMR3_IC3F_MASK 0xf
#define TIM2_CCER1 (*(volatile uint8_t *)(TIM2_BASE + 0x0A))
#define TIM2_CCER1_CC1E (1 << 0)
#define TIM2_CCER1_CC1P (1 << 1)
#define TIM2_CCER1_CC2E (1 << 4)
#define TIM2_CCER1_CC2P (1 << 5)
#define TIM2_CCER1_CC1E (1U << 0)
#define TIM2_CCER1_CC1P (1U << 1)
#define TIM2_CCER1_CC2E (1U << 4)
#define TIM2_CCER1_CC2P (1U << 5)
#define TIM2_CCER2 (*(volatile uint8_t *)(TIM2_BASE + 0x0B))
#define TIM2_CCER2_CC3E (1 << 0)
#define TIM2_CCER2_CC3P (1 << 1)
#define TIM2_CCER2_CC3E (1U << 0)
#define TIM2_CCER2_CC3P (1U << 1)
#define TIM2_CNTRH (*(volatile uint8_t *)(TIM2_BASE + 0x0C))
#define TIM2_CNTRL (*(volatile uint8_t *)(TIM2_BASE + 0x0D))
#define TIM2_PSCR (*(volatile uint8_t *)(TIM2_BASE + 0x0E))
@ -2472,36 +2472,36 @@ typedef struct {
// Block: TIM3
#define TIM3_CR1 (*(volatile uint8_t *)(TIM3_BASE + 0x00))
#define TIM3_CR1_CEN (1 << 0)
#define TIM3_CR1_UDIS (1 << 1)
#define TIM3_CR1_URS (1 << 2)
#define TIM3_CR1_OPM (1 << 3)
#define TIM3_CR1_APRE (1 << 7)
#define TIM3_CR1_CEN (1U << 0)
#define TIM3_CR1_UDIS (1U << 1)
#define TIM3_CR1_URS (1U << 2)
#define TIM3_CR1_OPM (1U << 3)
#define TIM3_CR1_APRE (1U << 7)
#define TIM3_IER (*(volatile uint8_t *)(TIM3_BASE + 0x01))
#define TIM3_IER_UIE (1 << 0)
#define TIM3_IER_CC1IE (1 << 1)
#define TIM3_IER_CC2IE (1 << 2)
#define TIM3_IER_CC3IE (1 << 3)
#define TIM3_IER_TIE (1 << 6)
#define TIM3_IER_UIE (1U << 0)
#define TIM3_IER_CC1IE (1U << 1)
#define TIM3_IER_CC2IE (1U << 2)
#define TIM3_IER_CC3IE (1U << 3)
#define TIM3_IER_TIE (1U << 6)
#define TIM3_SR1 (*(volatile uint8_t *)(TIM3_BASE + 0x02))
#define TIM3_SR1_UIF (1 << 0)
#define TIM3_SR1_CC1IF (1 << 1)
#define TIM3_SR1_CC2IF (1 << 2)
#define TIM3_SR1_CC3IF (1 << 3)
#define TIM3_SR1_TIF (1 << 6)
#define TIM3_SR1_UIF (1U << 0)
#define TIM3_SR1_CC1IF (1U << 1)
#define TIM3_SR1_CC2IF (1U << 2)
#define TIM3_SR1_CC3IF (1U << 3)
#define TIM3_SR1_TIF (1U << 6)
#define TIM3_SR2 (*(volatile uint8_t *)(TIM3_BASE + 0x03))
#define TIM3_SR2_CC1OF (1 << 1)
#define TIM3_SR2_CC2OF (1 << 2)
#define TIM3_SR2_CC3OF (1 << 3)
#define TIM3_SR2_CC1OF (1U << 1)
#define TIM3_SR2_CC2OF (1U << 2)
#define TIM3_SR2_CC3OF (1U << 3)
#define TIM3_EGR (*(volatile uint8_t *)(TIM3_BASE + 0x04))
#define TIM3_EGR_CC1G (1 << 1)
#define TIM3_EGR_CC2G (1 << 2)
#define TIM3_EGR_CC3G (1 << 3)
#define TIM3_EGR_TG (1 << 6)
#define TIM3_EGR_CC1G (1U << 1)
#define TIM3_EGR_CC2G (1U << 2)
#define TIM3_EGR_CC3G (1U << 3)
#define TIM3_EGR_TG (1U << 6)
#define TIM3_CCMR1 (*(volatile uint8_t *)(TIM3_BASE + 0x05))
#define TIM3_CCMR1_CC1S_OFFSET 0
#define TIM3_CCMR1_CC1S_MASK 0x3
#define TIM3_CCMR1_CC1PE (1 << 3)
#define TIM3_CCMR1_CC1PE (1U << 3)
#define TIM3_CCMR1_OC1M_OFFSET 4
#define TIM3_CCMR1_OC1M_MASK 0x7
#define TIM3_CCMR1_CC1S_OFFSET 0
@ -2513,7 +2513,7 @@ typedef struct {
#define TIM3_CCMR2 (*(volatile uint8_t *)(TIM3_BASE + 0x06))
#define TIM3_CCMR2_CC2S_OFFSET 0
#define TIM3_CCMR2_CC2S_MASK 0x3
#define TIM3_CCMR2_CC2PE (1 << 3)
#define TIM3_CCMR2_CC2PE (1U << 3)
#define TIM3_CCMR2_OC2M_OFFSET 4
#define TIM3_CCMR2_OC2M_MASK 0x7
#define TIM3_CCMR2_CC2S_OFFSET 0
@ -2523,10 +2523,10 @@ typedef struct {
#define TIM3_CCMR2_IC2F_OFFSET 4
#define TIM3_CCMR2_IC2F_MASK 0xf
#define TIM3_CCER1 (*(volatile uint8_t *)(TIM3_BASE + 0x07))
#define TIM3_CCER1_CC1E (1 << 0)
#define TIM3_CCER1_CC1P (1 << 1)
#define TIM3_CCER1_CC2E (1 << 4)
#define TIM3_CCER1_CC2P (1 << 5)
#define TIM3_CCER1_CC1E (1U << 0)
#define TIM3_CCER1_CC1P (1U << 1)
#define TIM3_CCER1_CC2E (1U << 4)
#define TIM3_CCER1_CC2P (1U << 5)
#define TIM3_CNTRH (*(volatile uint8_t *)(TIM3_BASE + 0x08))
#define TIM3_CNTRL (*(volatile uint8_t *)(TIM3_BASE + 0x09))
#define TIM3_PSCR (*(volatile uint8_t *)(TIM3_BASE + 0x0A))
@ -2550,11 +2550,11 @@ typedef struct {
// Block: TIM5
#define TIM5_CR1 (*(volatile uint8_t *)(TIM5_BASE + 0x00))
#define TIM5_CR1_CEN (1 << 0)
#define TIM5_CR1_UDIS (1 << 1)
#define TIM5_CR1_URS (1 << 2)
#define TIM5_CR1_OPM (1 << 3)
#define TIM5_CR1_APRE (1 << 7)
#define TIM5_CR1_CEN (1U << 0)
#define TIM5_CR1_UDIS (1U << 1)
#define TIM5_CR1_URS (1U << 2)
#define TIM5_CR1_OPM (1U << 3)
#define TIM5_CR1_APRE (1U << 7)
#define TIM5_CR2 (*(volatile uint8_t *)(TIM5_BASE + 0x01))
#define TIM5_CR2_MMS_OFFSET 4
#define TIM5_CR2_MMS_MASK 0x07
@ -2563,32 +2563,32 @@ typedef struct {
#define TIM5_SMCR_SMS_MASK 0x07
#define TIM5_SMCR_TS_OFFSET 4
#define TIM5_SMCR_TS_MASK 0x07
#define TIM5_SMCR_MSM (1 << 7)
#define TIM5_SMCR_MSM (1U << 7)
#define TIM5_IER (*(volatile uint8_t *)(TIM5_BASE + 0x03))
#define TIM5_IER_UIE (1 << 0)
#define TIM5_IER_CC1IE (1 << 1)
#define TIM5_IER_CC2IE (1 << 2)
#define TIM5_IER_CC3IE (1 << 3)
#define TIM5_IER_TIE (1 << 6)
#define TIM5_IER_UIE (1U << 0)
#define TIM5_IER_CC1IE (1U << 1)
#define TIM5_IER_CC2IE (1U << 2)
#define TIM5_IER_CC3IE (1U << 3)
#define TIM5_IER_TIE (1U << 6)
#define TIM5_SR1 (*(volatile uint8_t *)(TIM5_BASE + 0x04))
#define TIM5_SR1_UIF (1 << 0)
#define TIM5_SR1_CC1IF (1 << 1)
#define TIM5_SR1_CC2IF (1 << 2)
#define TIM5_SR1_CC3IF (1 << 3)
#define TIM5_SR1_TIF (1 << 6)
#define TIM5_SR1_UIF (1U << 0)
#define TIM5_SR1_CC1IF (1U << 1)
#define TIM5_SR1_CC2IF (1U << 2)
#define TIM5_SR1_CC3IF (1U << 3)
#define TIM5_SR1_TIF (1U << 6)
#define TIM5_SR2 (*(volatile uint8_t *)(TIM5_BASE + 0x05))
#define TIM5_SR2_CC1OF (1 << 1)
#define TIM5_SR2_CC2OF (1 << 2)
#define TIM5_SR2_CC3OF (1 << 3)
#define TIM5_SR2_CC1OF (1U << 1)
#define TIM5_SR2_CC2OF (1U << 2)
#define TIM5_SR2_CC3OF (1U << 3)
#define TIM5_EGR (*(volatile uint8_t *)(TIM5_BASE + 0x06))
#define TIM5_EGR_CC1G (1 << 1)
#define TIM5_EGR_CC2G (1 << 2)
#define TIM5_EGR_CC3G (1 << 3)
#define TIM5_EGR_TG (1 << 6)
#define TIM5_EGR_CC1G (1U << 1)
#define TIM5_EGR_CC2G (1U << 2)
#define TIM5_EGR_CC3G (1U << 3)
#define TIM5_EGR_TG (1U << 6)
#define TIM5_CCMR1 (*(volatile uint8_t *)(TIM5_BASE + 0x07))
#define TIM5_CCMR1_CC1S_OFFSET 0
#define TIM5_CCMR1_CC1S_MASK 0x3
#define TIM5_CCMR1_CC1PE (1 << 3)
#define TIM5_CCMR1_CC1PE (1U << 3)
#define TIM5_CCMR1_OC1M_OFFSET 4
#define TIM5_CCMR1_OC1M_MASK 0x7
#define TIM5_CCMR1_CC1S_OFFSET 0
@ -2600,7 +2600,7 @@ typedef struct {
#define TIM5_CCMR2 (*(volatile uint8_t *)(TIM5_BASE + 0x08))
#define TIM5_CCMR2_CC2S_OFFSET 0
#define TIM5_CCMR2_CC2S_MASK 0x3
#define TIM5_CCMR2_CC2PE (1 << 3)
#define TIM5_CCMR2_CC2PE (1U << 3)
#define TIM5_CCMR2_OC2M_OFFSET 4
#define TIM5_CCMR2_OC2M_MASK 0x7
#define TIM5_CCMR2_CC2S_OFFSET 0
@ -2612,7 +2612,7 @@ typedef struct {
#define TIM5_CCMR3 (*(volatile uint8_t *)(TIM5_BASE + 0x09))
#define TIM5_CCMR3_CC3S_OFFSET 0
#define TIM5_CCMR3_CC3S_MASK 0x3
#define TIM5_CCMR3_CC3PE (1 << 3)
#define TIM5_CCMR3_CC3PE (1U << 3)
#define TIM5_CCMR3_OC3M_OFFSET 4
#define TIM5_CCMR3_OC3M_MASK 0x7
#define TIM5_CCMR3_CC3S_OFFSET 0
@ -2622,13 +2622,13 @@ typedef struct {
#define TIM5_CCMR3_IC3F_OFFSET 4
#define TIM5_CCMR3_IC3F_MASK 0xf
#define TIM5_CCER1 (*(volatile uint8_t *)(TIM5_BASE + 0x0A))
#define TIM5_CCER1_CC1E (1 << 0)
#define TIM5_CCER1_CC1P (1 << 1)
#define TIM5_CCER1_CC2E (1 << 4)
#define TIM5_CCER1_CC2P (1 << 5)
#define TIM5_CCER1_CC1E (1U << 0)
#define TIM5_CCER1_CC1P (1U << 1)
#define TIM5_CCER1_CC2E (1U << 4)
#define TIM5_CCER1_CC2P (1U << 5)
#define TIM5_CCER2 (*(volatile uint8_t *)(TIM5_BASE + 0x0B))
#define TIM5_CCER2_CC3E (1 << 0)
#define TIM5_CCER2_CC3P (1 << 1)
#define TIM5_CCER2_CC3E (1U << 0)
#define TIM5_CCER2_CC3P (1U << 1)
#define TIM5_CNTRH (*(volatile uint8_t *)(TIM5_BASE + 0x0C))
#define TIM5_CNTRL (*(volatile uint8_t *)(TIM5_BASE + 0x0D))
#define TIM5_PSCR (*(volatile uint8_t *)(TIM5_BASE + 0x0E))
@ -2918,13 +2918,13 @@ typedef struct {
#define CPU_SPH (*(volatile uint8_t *)(CPU_BASE + 0x08))
#define CPU_SPL (*(volatile uint8_t *)(CPU_BASE + 0x09))
#define CPU_CCR (*(volatile uint8_t *)(CPU_BASE + 0x0A))
#define CPU_CCR_C (1 << 0)
#define CPU_CCR_Z (1 << 1)
#define CPU_CCR_N (1 << 2)
#define CPU_CCR_I0 (1 << 3)
#define CPU_CCR_H (1 << 4)
#define CPU_CCR_I1 (1 << 5)
#define CPU_CCR_V (1 << 7)
#define CPU_CCR_C (1U << 0)
#define CPU_CCR_Z (1U << 1)
#define CPU_CCR_N (1U << 2)
#define CPU_CCR_I0 (1U << 3)
#define CPU_CCR_H (1U << 4)
#define CPU_CCR_I1 (1U << 5)
#define CPU_CCR_V (1U << 7)
typedef union {
struct {
@ -3396,46 +3396,46 @@ typedef struct {
#define NUBC NOPT1
#define OPT2 (*(volatile uint8_t *)(OPT_BASE + 0x03))
#define AFR OPT2
#define AFR_AFR0 (1 << 0)
#define AFR_AFR1 (1 << 1)
#define AFR_AFR2 (1 << 2)
#define AFR_AFR3 (1 << 3)
#define AFR_AFR4 (1 << 4)
#define AFR_AFR5 (1 << 5)
#define AFR_AFR6 (1 << 6)
#define AFR_AFR7 (1 << 7)
#define AFR_AFR0 (1U << 0)
#define AFR_AFR1 (1U << 1)
#define AFR_AFR2 (1U << 2)
#define AFR_AFR3 (1U << 3)
#define AFR_AFR4 (1U << 4)
#define AFR_AFR5 (1U << 5)
#define AFR_AFR6 (1U << 6)
#define AFR_AFR7 (1U << 7)
#define NOPT2 (*(volatile uint8_t *)(OPT_BASE + 0x04))
#define NAFR NOPT2
#define AFR_NAFR0 (1 << 0)
#define AFR_NAFR1 (1 << 1)
#define AFR_NAFR2 (1 << 2)
#define AFR_NAFR3 (1 << 3)
#define AFR_NAFR4 (1 << 4)
#define AFR_NAFR5 (1 << 5)
#define AFR_NAFR6 (1 << 6)
#define AFR_NAFR7 (1 << 7)
#define AFR_NAFR0 (1U << 0)
#define AFR_NAFR1 (1U << 1)
#define AFR_NAFR2 (1U << 2)
#define AFR_NAFR3 (1U << 3)
#define AFR_NAFR4 (1U << 4)
#define AFR_NAFR5 (1U << 5)
#define AFR_NAFR6 (1U << 6)
#define AFR_NAFR7 (1U << 7)
#define OPT3 (*(volatile uint8_t *)(OPT_BASE + 0x05))
#define OPT3_WWDG_HALT (1 << 0)
#define OPT3_WWDG_HW (1 << 1)
#define OPT3_IWDG_HW (1 << 2)
#define OPT3_LSI_EN (1 << 3)
#define OPT3_HSI_TRIM (1 << 4)
#define OPT3_WWDG_HALT (1U << 0)
#define OPT3_WWDG_HW (1U << 1)
#define OPT3_IWDG_HW (1U << 2)
#define OPT3_LSI_EN (1U << 3)
#define OPT3_HSI_TRIM (1U << 4)
#define NOPT3 (*(volatile uint8_t *)(OPT_BASE + 0x06))
#define NOPT3_NWWDG_HALT (1 << 0)
#define NOPT3_NWWDG_HW (1 << 1)
#define NOPT3_NIWDG_HW (1 << 2)
#define NOPT3_NLSI_EN (1 << 3)
#define NOPT3_NHSI_TRIM (1 << 4)
#define NOPT3_NWWDG_HALT (1U << 0)
#define NOPT3_NWWDG_HW (1U << 1)
#define NOPT3_NIWDG_HW (1U << 2)
#define NOPT3_NLSI_EN (1U << 3)
#define NOPT3_NHSI_TRIM (1U << 4)
#define OPT4 (*(volatile uint8_t *)(OPT_BASE + 0x07))
#define OPT4_PRS_C0 (1 << 0)
#define OPT4_PRS_C1 (1 << 1)
#define OPT4_CKAWU_SEL (1 << 2)
#define OPT4_EXT_CLK (1 << 3)
#define OPT4_PRS_C0 (1U << 0)
#define OPT4_PRS_C1 (1U << 1)
#define OPT4_CKAWU_SEL (1U << 2)
#define OPT4_EXT_CLK (1U << 3)
#define NOPT4 (*(volatile uint8_t *)(OPT_BASE + 0x08))
#define NOPT4_NPRS_C0 (1 << 0)
#define NOPT4_NPRS_C1 (1 << 1)
#define NOPT4_NCKAWU_SEL (1 << 2)
#define NOPT4_NEXT_CLK (1 << 3)
#define NOPT4_NPRS_C0 (1U << 0)
#define NOPT4_NPRS_C1 (1U << 1)
#define NOPT4_NCKAWU_SEL (1U << 2)
#define NOPT4_NEXT_CLK (1U << 3)
#define OPT5 (*(volatile uint8_t *)(OPT_BASE + 0x09))
#define HSECNT OPT5
#define NOPT5 (*(volatile uint8_t *)(OPT_BASE + 0x0A))