add I²C master library
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i2c_master.c
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428
i2c_master.c
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/** library to communicate using I²C as master
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @copyright SPDX-License-Identifier: GPL-3.0-or-later
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* @date 2017-2021
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* @note the I²C peripheral is not well specified and does not cover all cases. The following complexity is the best I could do to cope with it
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*/
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/* standard libraries */
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#include <stdint.h> // standard integer types
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#include <stdbool.h> // boolean types
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#include <stdlib.h> // general utilities
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/* own libraries */
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#include "stm8s.h" // STM8S definitions
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#include "i2c_master.h" // I²C header and definitions
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#include "main.h"
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bool i2c_master_setup(bool fast)
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{
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// configure I²C peripheral
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if (!i2c_master_check_signals()) { // check the signal lines
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return false;
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}
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I2C_FREQR = 16; // the peripheral frequency (must match CPU frequency)
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if (fast) {
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I2C_CCRL = 0x2; // set SCL at 320 kHz (for less error)
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I2C_CCRH = (I2C_CCRH_FS | I2C_CCRH_DUTY); // set fast speed mode
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I2C_CCRH = (1U << 7); // set fast speed mode
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} else {
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I2C_CCRL = 0x50; // set SCL at 100 kHz
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I2C_CCRH = 0; // set standard speed mode
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}
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I2C_CR1 |= I2C_CR1_PE; // enable I²C peripheral
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return true;
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}
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void i2c_master_release(void)
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{
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I2C_CR1 &= ~I2C_CR1_PE; // disable I²C peripheral
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}
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bool i2c_master_check_signals(void)
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{
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i2c_master_release(); // ensure PB4/PB5 are not used as alternate function
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GPIO_PB->CR1.reg &= ~(PB4 | PB5); // operate in open-drain mode
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GPIO_PB->DDR.reg |= (PB4 | PB5); // set SCL/SDA as output to test pull-up
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GPIO_PB->ODR.reg |= PB4; // ensure SCL is high
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GPIO_PB->ODR.reg &= ~PB5; // set SDA low (start condition)
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for (volatile uint8_t t = 0; t < 10; t++); // wait 10 us
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GPIO_PB->ODR.reg |= PB5; // set SDA high (stop condition)
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for (volatile uint8_t t = 0; t < 10; t++); // wait 10 us for pull-up to take effect
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GPIO_PB->DDR.reg &= ~(PB4 | PB5); // set SCL/SDA as input before it is used as alternate function by the peripheral
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return ((GPIO_PB->IDR.reg & PB4) && (GPIO_PB->IDR.reg & PB5)); // test if both lines are up
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}
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void i2c_master_reset(void)
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{
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I2C_CR2 |= I2C_CR2_STOP; // release lines
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// don't check if BUSY is cleared since its state might be erroneous
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// rewriting I2C_CR2 before I2C_CR2_STOP is cleared might cause a second STOP, but at this point we don't care
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I2C_CR2 |= I2C_CR2_SWRST; // reset peripheral, in case we got stuck and the dog bit
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while ((0 == (GPIO_PB->IDR.reg & PB4) && (0 == (GPIO_PB->IDR.reg & PB5)))); // wait for SDA/SCL line to be released
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I2C_CR2 &= ~I2C_CR2_SWRST; // release reset
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I2C_CR1 &= ~I2C_CR1_PE; // disable I²C peripheral to clear some bits
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I2C_CR1 |= I2C_CR1_PE; // re-enable I²C peripheral (must be done before any other register is written)
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}
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enum i2c_master_rc i2c_master_start(void)
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{
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// send (re-)start condition
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if (I2C_CR2 & (I2C_CR2_START | I2C_CR2_STOP)) { // ensure start or stop operations are not in progress
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return I2C_MASTER_RC_START_STOP_IN_PROGESS;
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}
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I2C_CR2 |= I2C_CR2_START; // sent start condition
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while ((I2C_CR2 & I2C_CR2_START) && !(I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until start condition has been accepted and cleared
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (!(I2C_SR1 & I2C_SR1_SB)) { // the start bit has not been set
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (!(I2C_SR3 & I2C_SR3_MSL)) { // verify if in master mode
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return I2C_MASTER_RC_NOT_MASTER;
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}
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return I2C_MASTER_RC_NONE;
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}
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/** wait until stop is sent and bus is released
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* @return I²C return code
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*/
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static enum i2c_master_rc i2c_master_wait_stop(void)
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{
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while ((I2C_CR2 & I2C_CR2_STOP) && !(I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO))); // wait until stop condition is accepted and cleared
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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// this time we can't use I2C_CR2_STOP to check for timeout
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if (I2C_SR3 & I2C_SR3_MSL) { // ensure we are not in master mode anymore
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_SR3 & I2C_SR3_BUSY) { // ensure bus is released
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (!i2c_master_check_signals()) { // ensure lines are released
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return I2C_MASTER_RC_BUS_ERROR;
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}
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return I2C_MASTER_RC_NONE;
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}
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enum i2c_master_rc i2c_master_stop(void)
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{
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// sanity check
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if (!(I2C_SR3 & I2C_SR3_BUSY)) { // ensure bus is not already released
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return I2C_MASTER_RC_NONE; // bus has probably already been released
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}
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if (I2C_CR2 & (I2C_CR2_START | I2C_CR2_STOP)) { // ensure start or stop operations are not in progress
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return I2C_MASTER_RC_START_STOP_IN_PROGESS;
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}
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I2C_CR2 |= I2C_CR2_STOP; // send stop to release bus
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return i2c_master_wait_stop();
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}
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enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, bool write)
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{
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if (!(I2C_SR1 & I2C_SR1_SB)) { // start condition has not been sent yet
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enum i2c_master_rc rc = i2c_master_start(); // send start condition
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if (I2C_MASTER_RC_NONE != rc) {
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return rc;
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}
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}
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if (!(I2C_SR3 & I2C_SR3_MSL)) { // I²C device is not in master mode
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return I2C_MASTER_RC_NOT_MASTER;
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}
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// select slave
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I2C_SR2 &= ~(I2C_SR2_AF); // clear acknowledgement failure
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if (!address_10bit) { // 7-bit address
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I2C_DR = (slave << 1) | (write ? 0 : 1); // select slave, with read/write flag
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while (!(I2C_SR1 & I2C_SR1_ADDR) && !(I2C_SR2 & (I2C_SR2_AF | I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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} else { // 10-bit address
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// send first part of address
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I2C_DR = 11110000 | (((slave >> 8 ) & 0x3) << 1); // send first header (11110xx0, where xx are 2 MSb of slave address)
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while (!(I2C_SR1 & I2C_SR1_ADD10) && !(I2C_SR2 & (I2C_SR2_AF | I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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// send second part of address
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I2C_SR2 &= ~(I2C_SR2_AF); // clear acknowledgement failure
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I2C_DR = (slave & 0xff); // send remaining of address
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while (!(I2C_SR1 & I2C_SR1_ADDR) && !(I2C_SR2 & (I2C_SR2_AF | I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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// go into receive mode if necessary
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if (!write) {
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enum i2c_master_rc rc = i2c_master_start(); // send start condition
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if (I2C_MASTER_RC_NONE != rc) {
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return rc;
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}
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// send first part of address with receive flag
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I2C_SR2 &= ~(I2C_SR2_AF); // clear acknowledgement failure
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I2C_DR = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
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while (!(I2C_SR1 & I2C_SR1_ADDR) && !(I2C_SR2 & (I2C_SR2_AF | I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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}
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}
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// verify if we are in the right mode
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if (write && !(I2C_SR3 & I2C_SR3_TRA)) {
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return I2C_MASTER_RC_NOT_TRANSMIT;
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} else if (!write && (I2C_SR3 & I2C_SR3_TRA)) {
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return I2C_MASTER_RC_NOT_RECEIVE;
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}
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return I2C_MASTER_RC_NONE;
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}
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enum i2c_master_rc i2c_master_read(uint8_t* data, uint16_t data_size)
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{
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if (NULL == data || 0 == data_size) { // no data to read
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return I2C_MASTER_RC_OTHER; // we indicate an error because we don't send a stop
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}
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if (!(I2C_SR3 & I2C_SR3_MSL)) { // I²C device is not in master mode
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return I2C_MASTER_RC_NOT_MASTER;
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}
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// we can't check if the address phase it over since ADDR has been cleared when checking for mode
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if (I2C_SR3 & I2C_SR3_TRA) { // ensure we are in receive mode
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return I2C_MASTER_RC_NOT_RECEIVE;
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}
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// read data
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for (uint16_t i = 0; i < data_size; i++) { // read bytes
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// set (N)ACK (EV6_3, EV6_1)
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if (1 == data_size - i) { // prepare to sent NACK for last byte
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I2C_CR2 &= ~(I2C_CR2_ACK); // disable ACK
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I2C_CR2 |= I2C_CR2_STOP; // prepare to send the stop
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} else {
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I2C_CR2 |= I2C_CR2_ACK; // enable ACK
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}
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while (!(I2C_SR1 & I2C_SR1_RXNE) && !(I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO))); // wait until data is received (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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data[i] = I2C_DR; // read the received byte
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}
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return i2c_master_wait_stop();
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}
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enum i2c_master_rc i2c_master_write(const uint8_t* data, uint16_t data_size)
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{
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if (NULL == data || 0 == data_size) { // no data to read
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return I2C_MASTER_RC_NONE; // we don't indicate an error because the stop is done seperatly
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}
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if (!(I2C_SR3 & I2C_SR3_MSL)) { // I²C device is not in master mode
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return I2C_MASTER_RC_NOT_MASTER;
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}
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// we can't check if the address phase it over since ADDR has been cleared when checking for mode
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if (!(I2C_SR3 & I2C_SR3_TRA)) { // ensure we are in transmit mode
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return I2C_MASTER_RC_NOT_TRANSMIT;
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}
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// write data
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for (uint16_t i = 0; i < data_size; i++) { // write bytes
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I2C_SR2 &= ~(I2C_SR2_AF); // clear acknowledgement failure
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I2C_DR = data[i]; // send byte
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while (!(I2C_SR1 & I2C_SR1_TXE) && !(I2C_SR2 & (I2C_SR2_AF | I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until byte has been transmitted
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (I2C_SR2 & I2C_SR2_AF) { // data has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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}
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while (!(I2C_SR1 & I2C_SR1_BTF) && !(I2C_SR2 & (I2C_SR2_AF | I2C_SR2_BERR | I2C_SR2_ARLO)) && !(I2C_CR2 & I2C_CR2_STOP)); // wait until last byte has been transmitted
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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}
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if (I2C_SR2 & I2C_SR2_AF) { // data has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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return I2C_MASTER_RC_NONE;
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}
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enum i2c_master_rc i2c_master_slave_read(uint16_t slave, bool address_10bit, uint8_t* data, uint16_t data_size)
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{
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
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rc = i2c_master_start(); // send (re-)start condition
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if (I2C_MASTER_RC_NONE != rc) {
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return rc;
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}
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rc = i2c_master_select_slave(slave, address_10bit, false); // select slave to read
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if (I2C_MASTER_RC_NONE != rc) {
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goto error;
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}
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if (NULL != data && data_size > 0) { // only read data if needed
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rc = i2c_master_read(data, data_size); // read data (includes stop)
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if (I2C_MASTER_RC_NONE != rc) {
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goto error;
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}
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} else {
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i2c_master_stop(); // sent stop condition
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}
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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if (I2C_MASTER_RC_NONE != rc) {
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i2c_master_stop(); // sent stop condition
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}
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return rc;
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}
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enum i2c_master_rc i2c_master_slave_write(uint16_t slave, bool address_10bit, const uint8_t* data, uint16_t data_size)
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{
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
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rc = i2c_master_start(); // send (re-)start condition
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if (I2C_MASTER_RC_NONE != rc) {
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return rc;
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}
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rc = i2c_master_select_slave(slave, address_10bit, true); // select slave to write
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if (I2C_MASTER_RC_NONE != rc) {
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goto error;
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}
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if (NULL != data && data_size > 0) { // write data only is some is available
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rc = i2c_master_write(data, data_size); // write data
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if (I2C_MASTER_RC_NONE != rc) {
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goto error;
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}
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}
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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i2c_master_stop(); // sent stop condition
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return rc;
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}
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enum i2c_master_rc i2c_master_address_read(uint16_t slave, bool address_10bit, const uint8_t* address, uint16_t address_size, uint8_t* data, uint16_t data_size)
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{
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
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rc = i2c_master_start(); // send (re-)start condition
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if (I2C_MASTER_RC_NONE != rc) {
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return rc;
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}
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rc = i2c_master_select_slave(slave, address_10bit, true); // select slave to write
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if (I2C_MASTER_RC_NONE != rc) {
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goto error;
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}
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// write address
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||||
if (NULL != address && address_size > 0) {
|
||||
rc = i2c_master_write(address, address_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// read data
|
||||
if (NULL != data && data_size > 0) {
|
||||
rc = i2c_master_start(); // send re-start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(slave, address_10bit, false); // select slave to read
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
rc = i2c_master_read(data, data_size); // read memory (includes stop)
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
} else {
|
||||
i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
|
||||
rc = I2C_MASTER_RC_NONE;
|
||||
error:
|
||||
if (I2C_MASTER_RC_NONE != rc) { // only send stop on error
|
||||
i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_address_write(uint16_t slave, bool address_10bit, const uint8_t* address, uint16_t address_size, const uint8_t* data, uint16_t data_size)
|
||||
{
|
||||
if (UINT16_MAX - address_size < data_size) { // prevent integer overflow
|
||||
return I2C_MASTER_RC_OTHER;
|
||||
}
|
||||
if (address_size > 0 && NULL == address) {
|
||||
return I2C_MASTER_RC_OTHER;
|
||||
}
|
||||
if (data_size > 0 && NULL == data) {
|
||||
return I2C_MASTER_RC_OTHER;
|
||||
}
|
||||
|
||||
enum i2c_master_rc rc; // to store I²C return codes
|
||||
rc = i2c_master_start(); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (address_size && address) {
|
||||
rc = i2c_master_write(address, address_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
if (data_size && data) {
|
||||
rc = i2c_master_write(data, data_size); // send memory data
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
rc = I2C_MASTER_RC_NONE; // all went fine
|
||||
error:
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
i2c_master_stop();
|
||||
} else {
|
||||
rc = i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
112
i2c_master.h
Normal file
112
i2c_master.h
Normal file
@ -0,0 +1,112 @@
|
||||
/** library to communicate using I²C as master
|
||||
* @file
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @copyright SPDX-License-Identifier: GPL-3.0-or-later
|
||||
* @date 2017-2021
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/** I²C return codes */
|
||||
enum i2c_master_rc {
|
||||
I2C_MASTER_RC_NONE = 0, /**< no error */
|
||||
I2C_MASTER_RC_START_STOP_IN_PROGESS, /**< a start or stop condition is already in progress */
|
||||
I2C_MASTER_RC_NOT_MASTER, /**< not in master mode */
|
||||
I2C_MASTER_RC_NOT_TRANSMIT, /**< not in transmit mode */
|
||||
I2C_MASTER_RC_NOT_RECEIVE, /**< not in receive mode */
|
||||
I2C_MASTER_RC_NOT_READY, /**< slave is not read (previous operations has been NACKed) */
|
||||
I2C_MASTER_RC_NAK, /**< not acknowledge received */
|
||||
I2C_MASTER_RC_BUS_ERROR, /**< an error on the I²C bus occurred */
|
||||
I2C_MASTER_RC_TIMEOUT, /**< a timeout has occurred because an operation has not completed in the expected time */
|
||||
I2C_MASTER_RC_OTHER, /** any other error (does not have to be I²C related) */
|
||||
};
|
||||
|
||||
/** setup I²C peripheral
|
||||
* @param[in] fast if Standard mode (Sm) is used for frequencies at 100 kHz, and Fast mode (Fm) is used for frequencies at 320 kHz
|
||||
* @return if I²C bus is ready to be used (same as i2c_master_check_signals)
|
||||
*/
|
||||
bool i2c_master_setup(bool fast);
|
||||
/** release I²C peripheral */
|
||||
void i2c_master_release(void);
|
||||
/** reset I²C peripheral, fixing any locked state
|
||||
* @warning the I²C peripheral needs to be re-setup
|
||||
* @note to be used after failed start or stop, and bus error
|
||||
*/
|
||||
void i2c_master_reset(void);
|
||||
/** check if SDA and SCL signals are pulled high
|
||||
* @return if SDA and SCL signals are pulled high
|
||||
*/
|
||||
bool i2c_master_check_signals(void);
|
||||
/** send start condition
|
||||
* @return I2C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_start(void);
|
||||
/** select I²C slave device
|
||||
* @warning a start condition should be sent before this operation
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] write this transaction will be followed by a read (false) or write (true) operation
|
||||
* @return I²C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, bool write);
|
||||
/** read data over I²C
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I²C return code
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @note a stop condition will be sent at the end (I²C does not permit multiple reads, and this is necessary for 1-byte transfer)
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_read(uint8_t* data, uint16_t data_size);
|
||||
/** write data over I²C
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I²C return code
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @note no stop condition is sent at the end, allowing multiple writes
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_write(const uint8_t* data, uint16_t data_size);
|
||||
/** sent stop condition
|
||||
* @param[in] i2c I²C base address
|
||||
* @return I²C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_stop(void);
|
||||
/** read data from slave device
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_slave_read(uint16_t slave, bool address_10bit, uint8_t* data, uint16_t data_size);
|
||||
/** write data to slave device
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_slave_write(uint16_t slave, bool address_10bit, const uint8_t* data, uint16_t data_size);
|
||||
/** read data at specific address from an I²C memory slave
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to read from
|
||||
* @param[in] address_size address size in bytes
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_address_read(uint16_t slave, bool address_10bit, const uint8_t* address, uint16_t address_size, uint8_t* data, uint16_t data_size);
|
||||
/** write data at specific address on an I²C memory slave
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to write to
|
||||
* @param[in] address_size address size in bytes
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_address_write(uint16_t slave, bool address_10bit, const uint8_t* address, uint16_t address_size, const uint8_t* data, uint16_t data_size);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user