From 098d439471fb04b0e2e317356e468cb5d66901d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?King=20K=C3=A9vin?= Date: Mon, 16 Aug 2021 16:28:10 +0200 Subject: [PATCH] i2c_master: make error checking simpler --- i2c_master.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/i2c_master.c b/i2c_master.c index 51aef39..e2de25e 100644 --- a/i2c_master.c +++ b/i2c_master.c @@ -94,7 +94,7 @@ enum i2c_master_rc i2c_master_start(void) I2C_SR2 = 0; // clear error flags rim(); // enable interrupts while ((I2C_CR2 & I2C_CR2_START) || !(I2C_SR1 & I2C_SR1_SB) || !(I2C_SR3 & I2C_SR3_MSL)) { // wait until start condition has been accepted, send, and we are in aster mode - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { + if (I2C_SR2) { return I2C_MASTER_RC_BUS_ERROR; } if (I2C_CR2 & I2C_CR2_STOP) { @@ -114,7 +114,7 @@ static enum i2c_master_rc i2c_master_wait_stop(void) { I2C_SR2 = 0; // clear error flags while (I2C_CR2 & I2C_CR2_STOP) { // wait until stop condition is accepted and cleared - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { + if (I2C_SR2) { return I2C_MASTER_RC_BUS_ERROR; } // there is no interrupt flag we can use here @@ -168,14 +168,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b I2C_SR2 = 0; // clear error flags rim(); // enable interrupts while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error) - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { - return I2C_MASTER_RC_BUS_ERROR; - } if (I2C_CR2 & I2C_CR2_STOP) { return I2C_MASTER_RC_TIMEOUT; } if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged return I2C_MASTER_RC_NAK; + } else if (I2C_SR2) { + return I2C_MASTER_RC_BUS_ERROR; } I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts wfi(); // got to sleep to prevent EMI causing glitches @@ -186,14 +185,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b I2C_SR2 = 0; // clear error flags rim(); // enable interrupts while (!(I2C_SR1 & I2C_SR1_ADD10)) { // wait until address is transmitted (or error) - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { - return I2C_MASTER_RC_BUS_ERROR; - } if (I2C_CR2 & I2C_CR2_STOP) { return I2C_MASTER_RC_TIMEOUT; } if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged return I2C_MASTER_RC_NAK; + } else if (I2C_SR2) { + return I2C_MASTER_RC_BUS_ERROR; } I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts wfi(); // got to sleep to prevent EMI causing glitches @@ -204,14 +202,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b I2C_SR2 = 0; // clear error flags rim(); // enable interrupts while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error) - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { - return I2C_MASTER_RC_BUS_ERROR; - } if (I2C_CR2 & I2C_CR2_STOP) { return I2C_MASTER_RC_TIMEOUT; } if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged return I2C_MASTER_RC_NAK; + } else if (I2C_SR2) { + return I2C_MASTER_RC_BUS_ERROR; } I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts wfi(); // got to sleep to prevent EMI causing glitches @@ -227,14 +224,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b I2C_DR = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address) I2C_SR2 = 0; // clear error flags while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error) - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { - return I2C_MASTER_RC_BUS_ERROR; - } if (I2C_CR2 & I2C_CR2_STOP) { return I2C_MASTER_RC_TIMEOUT; } if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged return I2C_MASTER_RC_NAK; + } else if (I2C_SR2) { + return I2C_MASTER_RC_BUS_ERROR; } I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts wfi(); // got to sleep to prevent EMI causing glitches @@ -278,7 +274,7 @@ enum i2c_master_rc i2c_master_read(uint8_t* data, uint16_t data_size) } rim(); // enable interrupts while (!(I2C_SR1 & I2C_SR1_RXNE)) { // wait until data is received (or error) - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { + if (I2C_SR2) { // an error occurred return I2C_MASTER_RC_BUS_ERROR; } I2C_ITR = (I2C_ITR_ITBUFEN | I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable all I²C interrupts @@ -312,14 +308,13 @@ enum i2c_master_rc i2c_master_write(const uint8_t* data, uint16_t data_size) rim(); // enable interrupts while (!(I2C_SR1 & I2C_SR1_TXE)) { // wait until byte has been transmitted IWDG->KR.fields.KEY = IWDG_KR_KEY_REFRESH; // reset watchdog - if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) { - return I2C_MASTER_RC_BUS_ERROR; - } if (I2C_CR2 & I2C_CR2_STOP) { return I2C_MASTER_RC_TIMEOUT; } if (I2C_SR2 & I2C_SR2_AF) { // data has not been acknowledged return I2C_MASTER_RC_NAK; + } else if (I2C_SR2) { + return I2C_MASTER_RC_BUS_ERROR; } I2C_ITR = (I2C_ITR_ITBUFEN | I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable all I²C interrupts wfi(); // got to sleep to prevent EMI causing glitches