309 lines
16 KiB
C
309 lines
16 KiB
C
/* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/** library to communicate using I2C as master (code)
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* @file i2c_master.c
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017
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* @note peripherals used: I2C @ref i2c_master_i2c, timer @ref i2c_master_timer
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*/
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/* standard libraries */
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#include <stdint.h> // standard integer types
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#include <stdio.h> // standard I/O facilities
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#include <stdlib.h> // general utilities
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/* STM32 (including CM3) libraries */
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#include <libopencm3/stm32/rcc.h> // real-time control clock library
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#include <libopencm3/stm32/gpio.h> // general purpose input output library
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#include <libopencm3/stm32/i2c.h> // I2C library
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#include <libopencm3/stm32/timer.h> // timer utilities
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#include "global.h" // global utilities
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#include "i2c_master.h" // I2C header and definitions
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/** @defgroup i2c_master_i2c I2C peripheral used to communicate
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* @{
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*/
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#define I2C_MASTER_I2C 2 /**< I2C peripheral */
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/** @} */
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/** @defgroup i2c_master_timer timer peripheral used for timeouts
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* @{
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*/
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#define I2C_MASTER_TIMER 4 /**< timer peripheral */
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#define I2C_MASTER_TIMEOUT 4 /**< timeout factor (compared to expected time) */
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/** @} */
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void i2c_master_setup(bool fast)
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{
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// configure I2C peripheral
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rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
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gpio_set(I2C_SCL_PORT(I2C_MASTER_I2C), I2C_SCL_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
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gpio_set_mode(I2C_SCL_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SCL_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
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rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
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gpio_set(I2C_SDA_PORT(I2C_MASTER_I2C), I2C_SDA_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
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gpio_set_mode(I2C_SDA_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SDA_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
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rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
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rcc_periph_clock_enable(RCC_I2C(I2C_MASTER_I2C)); // enable clock for I2C peripheral
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i2c_reset(I2C(I2C_MASTER_I2C)); // reset configuration
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i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // I2C needs to be disable to be configured
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i2c_set_clock_frequency(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
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if (fast) {
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i2c_set_fast_mode(I2C(I2C_MASTER_I2C));
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i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(400000*2)); // set Thigh/Tlow to generate frequency of 400 kHz
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i2c_set_trise(I2C(I2C_MASTER_I2C), (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 300 kHz is 300 ns
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} else {
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i2c_set_standard_mode(I2C(I2C_MASTER_I2C)); // the DS1307 has a maximum I2C SCL freq if 100 kHz (corresponding to the standard mode)
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i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(100000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
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i2c_set_trise(I2C(I2C_MASTER_I2C), (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 100 kHz is 1000 ns (~1 MHz)
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}
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i2c_peripheral_enable(I2C(I2C_MASTER_I2C)); // enable I2C after configuration completed
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// configure time for timeouts
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rcc_periph_clock_enable(RCC_TIM(I2C_MASTER_TIMER)); // enable clock for timer block
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timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer state
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timer_set_mode(TIM(I2C_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
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timer_one_shot_mode(TIM(I2C_MASTER_TIMER)); // stop counter after update event (we only need to one timeout and reset before next operation)
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if (fast) {
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timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/400000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
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} else {
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timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/100000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
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}
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timer_set_period(TIM(I2C_MASTER_TIMER), I2C_MASTER_TIMEOUT*9); // use factor to wait for all 9 bits to be transmitted
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timer_update_on_overflow(TIM(I2C_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as timeout)
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// wait one transaction for the signal to be stable (some slave have issues when an I2C transaction immediately follows)
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while ( !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF));
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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}
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bool i2c_master_read(uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
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{
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// sanity check
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if (address==NULL || address_size==0 || data==NULL || data_size==0) { // input data is erroneous
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return false;
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}
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if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
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return false;
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}
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if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
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return false;
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}
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bool to_return = false; // return if read succeeded
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// send start condition
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i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // verify if in master mode
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goto error;
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}
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// select slave
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i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, I2C_WRITE); // select slave
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
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goto error;
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}
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// send address
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for (size_t i=0; i<address_size; i++) {
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i2c_send_data(I2C(I2C_MASTER_I2C), address[i]); // send memory address we want to read
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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}
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// switch to read mode
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i2c_send_start(I2C(I2C_MASTER_I2C)); // send restart condition to switch from write to read mode
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, I2C_READ); // select slave
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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if ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
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goto error;
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}
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// read data
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for (size_t i=0; i<data_size; i++) { // read bytes
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if (i==data_size-1) { // prepare to sent NACK for last byte
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i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK received to stop slave transmission
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i2c_send_stop(I2C(I2C_MASTER_I2C)); // send STOP after receiving byte
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} else {
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i2c_enable_ack(I2C(I2C_MASTER_I2C)); // ACK received byte to continue slave transmission
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}
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_RxNE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been received
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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data[i] = i2c_get_data(I2C(I2C_MASTER_I2C)); // read received byte
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}
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to_return = true;
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error:
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if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // release bus if busy
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// i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
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}
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i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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}
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return to_return;
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}
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bool i2c_master_write(uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
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{
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// sanity check
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if (address==NULL || address_size==0 || data==NULL || data_size==0) { // input data is erroneous
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return false;
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}
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if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
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return false;
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}
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if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
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return false;
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}
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bool to_return = false; // return if read succeeded
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// send start condition
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i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // verify if in master mode
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goto error;
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}
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// select slave
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i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, I2C_WRITE); // select slave
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
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goto error;
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}
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// send address
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for (size_t i=0; i<address_size; i++) {
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i2c_send_data(I2C(I2C_MASTER_I2C), address[i]); // send memory address we want to read
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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}
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// write data
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for (size_t i=0; i<data_size; i++) { // write bytes
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i2c_send_data(I2C(I2C_MASTER_I2C), data[i]); // send byte to be written in memory
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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goto error;
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}
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}
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to_return = true;
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error:
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if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // release bus if busy
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i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
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}
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
|
while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
|
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
|
}
|
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return to_return;
|
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}
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