/** library to communicate using SMBus as master * @file * @author King Kévin * @copyright SPDX-License-Identifier: GPL-3.0-or-later * @date 2017-2020 * @note peripherals used: I²C/SMBus @ref smbus_master_i2c */ /* standard libraries */ #include // standard integer types #include // general utilities /* STM32 (including CM3) libraries */ #include // SysTick library #include // assert utilities #include // real-time control clock library #include // general purpose input output library #include // SMBus library /* own libraries */ #include "global.h" // global utilities #include "smbus_master.h" // SMBus header and definitions /** @defgroup smbus_master_i2c I²C/SMBus peripheral used for SMBus communication * @{ */ #define SMBUS_MASTER_I2C 3 /**< I²C peripheral ID */ #define SMBUS_MASTER_SCL PA8 /**< GPIO pin for SMBus SCL */ #define SMBUS_MASTER_SCL_AF GPIO_AF4 /**< GPIO pin alternate funtion for SMBus SCL */ #define SMBUS_MASTER_SDA PB4 /**< GPIO pin for SMBus SDA */ #define SMBUS_MASTER_SDA_AF GPIO_AF9 /**< GPIO pin alternate funtion for SMBus SDA */ /** @} */ /** if Packet Error Code is used */ static bool smbus_master_pec = false; void smbus_master_setup(uint8_t frequency, bool pec) { // configure SMBus peripheral rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SCL)); // enable clock for SMBus I/O peripheral gpio_set(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_PIN(SMBUS_MASTER_SCL)); // already put signal high to avoid small pulse gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL pin to alternate function gpio_set_output_options(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL pin output as open-drain gpio_set_af(GPIO_PORT(SMBUS_MASTER_SCL), SMBUS_MASTER_SCL_AF, GPIO_PIN(SMBUS_MASTER_SCL)); // set alternate function to SMBus SCL pin rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SDA)); // enable clock for SMBus I/O peripheral gpio_set(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_PIN(SMBUS_MASTER_SDA)); // already put signal high to avoid small pulse gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA pin to alternate function gpio_set_output_options(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA pin output as open-drain gpio_set_af(GPIO_PORT(SMBUS_MASTER_SDA), SMBUS_MASTER_SDA_AF, GPIO_PIN(SMBUS_MASTER_SDA)); // set alternate function to SMBus SDA pin rcc_periph_clock_enable(RCC_I2C(SMBUS_MASTER_I2C)); // enable clock for SMBus peripheral i2c_reset(I2C(SMBUS_MASTER_I2C)); // reset peripheral domain i2c_peripheral_disable(I2C(SMBUS_MASTER_I2C)); // SMBus needs to be disable to be configured I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // reset peripheral I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // clear peripheral reset if (frequency < 10) { // enforce minimum SMBus frequency frequency = 10; } else if (frequency > 100) { // enforce maximum SMBus frequency frequency = 100; } i2c_set_clock_frequency(I2C(SMBUS_MASTER_I2C), rcc_apb1_frequency / 1000000); // configure the peripheral clock to the APB1 freq (where it is connected to) // use standard mode for frequencies below 100 kHz i2c_set_standard_mode(I2C(SMBUS_MASTER_I2C)); // set standard mode (Sm) i2c_set_ccr(I2C(SMBUS_MASTER_I2C), rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency of 100 kHz i2c_set_trise(I2C(SMBUS_MASTER_I2C), (1000 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz) I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SMBUS; // set I²C peripheral in SMBus mode (not host type, not using ARP) smbus_master_pec = pec; // remember if PEC is used if (smbus_master_pec) { I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_ENPEC; // enable PEC calculation } i2c_peripheral_enable(I2C(SMBUS_MASTER_I2C)); // enable SMBus after configuration completed } void smbus_master_release(void) { i2c_reset(I2C(SMBUS_MASTER_I2C)); // reset SMBus peripheral configuration i2c_peripheral_disable(I2C(SMBUS_MASTER_I2C)); // disable SMBus peripheral rcc_periph_clock_disable(RCC_I2C(SMBUS_MASTER_I2C)); // disable clock for SMBus peripheral gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL pin back to input gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA pin back to input } bool smbus_master_check_signals(void) { // enable GPIOs to read SDA and SCL rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SDA)); // enable clock for SMBus I/O peripheral rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SCL)); // enable clock for SMBus I/O peripheral // pull SDA and SDC low to check if there are pull-up resistors const uint32_t sda_moder = GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SDA)); // backup port configuration const uint32_t sda_pupdr = GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SDA)); // backup port configuration const uint32_t scl_moder = GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SCL)); // backup port configuration const uint32_t scl_pupdr = GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SCL)); // backup port configuration gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA to input and pull down (weak) to check if there is an external pull up (strong) gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL to input and pull down (weak) to check if there is an external pull up (strong) sleep_us(100); // let signal settle const bool to_return = (gpio_get(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_PIN(SMBUS_MASTER_SCL)) && gpio_get(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_PIN(SMBUS_MASTER_SDA))); // check if the signals are still pulled high by external stronger pull-up resistors GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SDA)) = sda_moder; // restore port configuration GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SDA)) = sda_pupdr; // restore port configuration GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SCL)) = scl_moder; // restore port configuration GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SCL)) = scl_pupdr; // restore port configuration return to_return; } void smbus_master_reset(void) { i2c_peripheral_disable(I2C(SMBUS_MASTER_I2C)); // disable SMBus peripheral I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // reset device I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // reset device i2c_peripheral_enable(I2C(SMBUS_MASTER_I2C)); // re-enable device } enum smbus_master_rc smbus_master_start(void) { bool retry = true; // retry after reset if first try failed enum smbus_master_rc to_return; // return code uint16_t sr1; // read register once, since reading/writing other registers or other events clears some flags try: to_return = SMBUS_MASTER_RC_NONE; // return code // send (re-)start condition if (I2C_CR1(I2C(SMBUS_MASTER_I2C)) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress return SMBUS_MASTER_RC_START_STOP_IN_PROGESS; } // prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of SMBus peripheral in master mode after a misplaced Stop) systick_counter_disable(); // disable SysTick to reconfigure it systick_set_frequency(500, rcc_ahb_frequency); // set timer to 2 ms (that should be long enough to send a start condition) systick_clear(); // reset SysTick (set to 0) systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag systick_get_countflag(); // reset flag (set when counter is going for 1 to 0) i2c_send_start(I2C(SMBUS_MASTER_I2C)); // send start condition to start transaction bool timeout = false; // remember if the timeout has been reached systick_counter_enable(); // start timer while ((I2C_CR1(I2C(SMBUS_MASTER_I2C)) & I2C_CR1_START) && !((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared timeout |= systick_get_countflag(); // verify if timeout has been reached } sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // be sure to get the current value if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) { to_return = SMBUS_MASTER_RC_BUS_ERROR; } while (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_SB | I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && SMBUS_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted timeout |= systick_get_countflag(); // verify if timeout has been reached } sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // be sure to get the current value if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) { to_return = SMBUS_MASTER_RC_BUS_ERROR; } else if (!(sr1 & I2C_SR1_SB)) { // the start bit has not been set although we the peripheral is not busy anymore to_return = SMBUS_MASTER_RC_BUS_ERROR; } else if (!(sr1 & I2C_SR2_MSL)) { // verify if in master mode to_return = SMBUS_MASTER_RC_NOT_MASTER; } else if (timeout) { // timeout has been reached, i.e. the peripheral hangs to_return = SMBUS_MASTER_RC_NOT_MASTER; } if (SMBUS_MASTER_RC_NOT_MASTER == to_return && retry) { // error happened retry = false; // don't retry a second time I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // assert peripheral reset I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // release peripheral reset goto try; } systick_counter_disable(); // we don't need to timer anymore return to_return; } /** wait until stop is sent and bus is released * @return SMBus return code */ static enum smbus_master_rc smbus_master_wait_stop(void) { enum smbus_master_rc to_return = SMBUS_MASTER_RC_NONE; // return code // prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of SMBus peripheral in master mode after a misplaced Stop) systick_counter_disable(); // disable SysTick to reconfigure it systick_set_frequency(500, rcc_ahb_frequency); // set timer to 2 ms (that should be long enough to send a stop condition) systick_clear(); // reset SysTick (set to 0) systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag systick_get_countflag(); // reset flag (set when counter is going for 1 to 0) bool timeout = false; // remember if the timeout has been reached systick_counter_enable(); // start timer while ((I2C_CR1(I2C(SMBUS_MASTER_I2C)) & I2C_CR1_STOP) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared timeout |= systick_get_countflag(); // verify if timeout has been reached } if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) { to_return = SMBUS_MASTER_RC_BUS_ERROR; } while ((I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_MSL) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode) timeout |= systick_get_countflag(); // verify if timeout has been reached } if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) { to_return = SMBUS_MASTER_RC_BUS_ERROR; } while ((I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_BUSY) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR)) && !timeout) { // wait until peripheral is not busy anymore timeout |= systick_get_countflag(); // verify if timeout has been reached } if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) { to_return = SMBUS_MASTER_RC_BUS_ERROR; } while ((0 == gpio_get(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_PIN(SMBUS_MASTER_SCL)) || 0 == gpio_get(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_PIN(SMBUS_MASTER_SDA))) && !timeout) { // wait until lines are really high again timeout |= systick_get_countflag(); // verify if timeout has been reached } if (timeout) { // I2C_CR1_STOP could also be used to detect a timeout, but I'm not sure when if (SMBUS_MASTER_RC_NONE == to_return) { to_return = SMBUS_MASTER_RC_TIMEOUT; // indicate timeout only when no more specific error has occurred } I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // assert peripheral reset I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // release peripheral reset } systick_counter_disable(); // we don't need to timer anymore return to_return; } enum smbus_master_rc smbus_master_stop(void) { // sanity check if (!(I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_BUSY)) { // release if not busy return SMBUS_MASTER_RC_NONE; // bus has probably already been released } if (I2C_CR1(I2C(SMBUS_MASTER_I2C)) & (I2C_CR1_START)) { // ensure start operation is not in progress return SMBUS_MASTER_RC_START_STOP_IN_PROGESS; // the stop is sent after a } if (!((I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_TRA))) { // if we are in receiver mode i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // disable ACK to be able to close the communication } if (!(I2C_CR1(I2C(SMBUS_MASTER_I2C)) & (I2C_CR1_STOP))) { // only send start if not already in progress i2c_send_stop(I2C(SMBUS_MASTER_I2C)); // send stop to release bus } return smbus_master_wait_stop(); } enum smbus_master_rc smbus_master_select_slave(uint8_t slave, bool write) { enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes uint16_t sr1, sr2; // read register once, since reading/writing other registers or other events clears some flags if (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & I2C_SR1_SB)) { // start condition has not been sent rc = smbus_master_start(); // send start condition if (SMBUS_MASTER_RC_NONE != rc) { return rc; } } if (!((sr2 = I2C_SR2(I2C(SMBUS_MASTER_I2C))) & I2C_SR2_MSL)) { // SMBus device is not in master mode return SMBUS_MASTER_RC_NOT_MASTER; } // select slave I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure i2c_send_7bit_address(I2C(SMBUS_MASTER_I2C), slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag while (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) { return SMBUS_MASTER_RC_BUS_ERROR; } if (sr1 & I2C_SR1_AF) { // address has not been acknowledged return SMBUS_MASTER_RC_NAK; } // do not check I2C_SR2_TRA to verify if we really are in transmit or receive mode since reading SR2 also clears ADDR and starting the read/write transaction return SMBUS_MASTER_RC_NONE; } enum smbus_master_rc smbus_master_read(uint8_t* data, size_t data_size) { // sanity check if (NULL == data || 0 == data_size) { // no data to read return SMBUS_MASTER_RC_NONE; } if (smbus_master_pec && SIZE_MAX - 1 < data_size) { // too much data to send (we need one more byte to send the PEC) return SMBUS_MASTER_RC_OTHER; } // SMBus start condition check uint16_t sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // read once if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected return SMBUS_MASTER_RC_NOT_READY; } if (sr1 & I2C_SR1_AF) { // check if the previous transaction went well return SMBUS_MASTER_RC_NOT_READY; } // prepare (N)ACK (EV6_3 in RM0008) if (1 == data_size) { i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // NACK after first byte } else { i2c_enable_ack(I2C(SMBUS_MASTER_I2C)); // NAK after next byte } uint16_t sr2 = I2C_SR2(I2C(SMBUS_MASTER_I2C)); // reading SR2 will also also clear ADDR in SR1 and start the transaction if (!(sr2 & I2C_SR2_MSL)) { // SMBus device is not master return SMBUS_MASTER_RC_NOT_MASTER; } if ((sr2 & I2C_SR2_TRA)) { // SMBus device not in receiver mode return SMBUS_MASTER_RC_NOT_RECEIVE; } // read data if (smbus_master_pec) { // we want to read the PEC data_size++; // add one byte to read the PEC I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_SR1_PECERR; // clear flag } for (size_t i = 0; i < data_size; i++) { // read bytes // set (N)ACK (EV6_3, EV6_1) if (1 == data_size - i) { // prepare to sent NACK for last byte i2c_send_stop(I2C(SMBUS_MASTER_I2C)); // already indicate we will send a stop (required to not send an ACK, and this must happen before the byte is transferred, see errata) if (smbus_master_pec) { I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_PEC; // prepare to receive PEC } i2c_nack_current(I2C(SMBUS_MASTER_I2C)); // (N)ACK current byte i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // NACK received byte to stop slave transmission } else if (2 == data_size - i) { // prepare to sent NACK for second last byte i2c_nack_next(I2C(SMBUS_MASTER_I2C)); // NACK next byte i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // NACK received byte to stop slave transmission } else { i2c_enable_ack(I2C(SMBUS_MASTER_I2C)); // ACK received byte to continue slave transmission } while (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_RxNE | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) { return SMBUS_MASTER_RC_BUS_ERROR; } if (!smbus_master_pec || i < data_size - 1) { // don't save the PEC data[i] = i2c_get_data(I2C(SMBUS_MASTER_I2C)); // read received byte } } if (smbus_master_pec) { // check if the PEC is correct if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & I2C_SR1_PECERR) { return SMBUS_MASTER_RC_PECERR; } } return smbus_master_stop(); } enum smbus_master_rc smbus_master_write(const uint8_t* data, size_t data_size) { // sanity check if (NULL == data || 0 == data_size) { // no data to write return SMBUS_MASTER_RC_NONE; } // SMBus start condition check uint16_t sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // read once if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected return SMBUS_MASTER_RC_NOT_READY; } if (sr1 & I2C_SR1_AF) { // check if the previous transaction went well return SMBUS_MASTER_RC_NOT_READY; } // master check uint16_t sr2 = I2C_SR2(I2C(SMBUS_MASTER_I2C)); // reading SR2 will also also clear ADDR in SR1 and start the transaction if (!(sr2 & I2C_SR2_MSL)) { // SMBus device is not master return SMBUS_MASTER_RC_NOT_MASTER; } if (!(sr2 & I2C_SR2_TRA)) { // SMBus device not in transmitter mode return SMBUS_MASTER_RC_NOT_TRANSMIT; } // write data for (size_t i = 0; i < data_size; i++) { // write bytes I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure i2c_send_data(I2C(SMBUS_MASTER_I2C), data[i]); // send byte to be written in memory while (!(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_TxE | I2C_SR1_AF)) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been transmitted if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) { return SMBUS_MASTER_RC_BUS_ERROR; } if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & I2C_SR1_AF) { // data has not been acknowledged return SMBUS_MASTER_RC_NAK; } } return SMBUS_MASTER_RC_NONE; } enum smbus_master_rc smbus_master_slave_read(uint8_t slave, uint8_t* data, size_t data_size) { enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes rc = smbus_master_start(); // send (re-)start condition if (SMBUS_MASTER_RC_NONE != rc) { return rc; } rc = smbus_master_select_slave(slave, false); // select slave to read if (SMBUS_MASTER_RC_NONE != rc) { goto error; } if (NULL != data && data_size > 0) { // only read data if needed rc = smbus_master_read(data, data_size); // read data (includes stop) if (SMBUS_MASTER_RC_NONE != rc) { goto error; } } else { smbus_master_stop(); // sent stop condition } rc = SMBUS_MASTER_RC_NONE; // all went well error: if (SMBUS_MASTER_RC_NONE != rc) { smbus_master_stop(); // sent stop condition } return rc; } enum smbus_master_rc smbus_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size) { enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes rc = smbus_master_start(); // send (re-)start condition if (SMBUS_MASTER_RC_NONE != rc) { return rc; } // select slave to write rc = smbus_master_select_slave(slave, true); if (SMBUS_MASTER_RC_NONE != rc) { goto error; } // write data only is some is available if (NULL != data && data_size > 0) { rc = smbus_master_write(data, data_size); // write data if (SMBUS_MASTER_RC_NONE != rc) { goto error; } } // send optional PEC if (smbus_master_pec) { I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_PEC; // start transmitting PEC while ((I2C_CR1(I2C(SMBUS_MASTER_I2C)) & I2C_CR1_PEC) && // PEC is still being transmitted !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_AF)) && // no NAK received !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // no bus error received if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) { // bus error has been received return SMBUS_MASTER_RC_BUS_ERROR; } if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & I2C_SR1_AF) { // no ACK received return SMBUS_MASTER_RC_NAK; } } rc = SMBUS_MASTER_RC_NONE; // all went well error: smbus_master_stop(); // sent stop condition return rc; } enum smbus_master_rc smbus_master_command_read(uint8_t slave, uint8_t command, uint8_t* data, size_t data_size) { enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes rc = smbus_master_start(); // send (re-)start condition if (SMBUS_MASTER_RC_NONE != rc) { return rc; } rc = smbus_master_select_slave(slave, true); // select slave to write if (SMBUS_MASTER_RC_NONE != rc) { goto error; } // write command rc = smbus_master_write(&command, 1); // send memory address if (SMBUS_MASTER_RC_NONE != rc) { goto error; } // read data if (NULL != data && data_size > 0) { rc = smbus_master_start(); // send re-start condition if (SMBUS_MASTER_RC_NONE != rc) { return rc; } rc = smbus_master_select_slave(slave, false); // select slave to read if (SMBUS_MASTER_RC_NONE != rc) { goto error; } rc = smbus_master_read(data, data_size); // read memory (includes stop) if (SMBUS_MASTER_RC_NONE != rc) { goto error; } } else { smbus_master_stop(); // sent stop condition } rc = SMBUS_MASTER_RC_NONE; error: if (SMBUS_MASTER_RC_NONE != rc) { // only send stop on error smbus_master_stop(); // sent stop condition } return rc; } enum smbus_master_rc smbus_master_command_write(uint8_t slave, uint8_t command, const uint8_t* data, size_t data_size) { if (SIZE_MAX - 1 < data_size) { // prevent integer overflow return SMBUS_MASTER_RC_OTHER; } if (data_size > 0 && NULL == data) { return SMBUS_MASTER_RC_OTHER; } uint8_t buffer[1 + data_size]; // single buffer to write command and all data buffer[0] = command; // save command in buffer if (data) { for (size_t i = 0; i < data_size; i++) { buffer[1 + i] = data[i]; } } return smbus_master_slave_write(slave, buffer, 1 + data_size); // send command and data }