diff --git a/lib/swd.c b/lib/swd.c index a4756ee..e227be0 100644 --- a/lib/swd.c +++ b/lib/swd.c @@ -219,7 +219,7 @@ uint64_t swd_transaction(uint64_t output, uint8_t bit_count, bool write) void swd_line_reset(void) { - swd_transaction(~0ULL, 50 + 1, true); // sent high for at least 50 cycle to issue line reset and put target in reset state + swd_transaction(~0ULL, 50 + 2, true); // sent high for at least 50 cycle to issue line reset and put target in reset state } void swd_jtag_to_swd(void) @@ -284,7 +284,7 @@ void swd_jtag_to_ds(void) void swd_swd_to_ds(void) { - swd_transaction(~0ULL, 50 + 1, true); // place SWD TAP is reset state + swd_line_reset(); // place SWD TAP is reset state swd_transaction(0xE3BC, 16, true); // send SWD-to-DS select sequence } @@ -380,7 +380,7 @@ const char* swd_dpidr_partno(uint16_t designer, uint8_t partno) /** interrupt service routine called for timer * * this is just acting as a shift register - * the host will write data on the falling edge, and read data just before the rising edge (we could also do it on the rising edge) + * the host will write data on the falling edge (-5 ns < Tos < 5 ns), and read data just before the rising edge (Tis > 4 ns) * the target will read and write data signal on clock rising edge * this phase shift is not very clear in the standard, but explains the line turn-round cycle when switching between writing and reading. * diff --git a/lib/swd.h b/lib/swd.h index 13a7bbe..e306582 100644 --- a/lib/swd.h +++ b/lib/swd.h @@ -65,14 +65,14 @@ enum swd_a_ap_jtagap_e { SWD_A_AP_JTAGAP_PSTA = 0x8, /**< Port Status Register (access: RW) */ }; -/** ACk acknowledge response +/** ACK acknowledge response * @implements ARM IHI 0074A B4.2 SWD protocol operation */ enum swd_ack_e { SWD_ACK_OK = 0x1, /**< Successful operation */ SWD_ACK_WAIT = 0x2, /**< Wait for response */ SWD_ACK_FAULT = 0x4, /**< Fault */ - SWD_ACK_ERROR = 0x7, /**< Error (pulled-up line not driven) */ + SWD_ACK_NOREPLY = 0x7, /**< Error (pulled-up line not driven) */ }; /** Activation codes