add 1-Wire master software implementation library from thermo-regulator project
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/* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/** library for 1-wire protocol as master (code)
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* @file onewire_master.c
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017
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* @note peripherals used: timer @ref onewire_master_timer, GPIO @ref onewire_master_gpio
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* @warning this library does not support parasite power mode
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*/
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/* standard libraries */
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#include <stdint.h> // standard integer types
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#include <stdbool.h> // boolean type
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#include <stdlib.h> // memory utilities
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/* STM32 (including CM3) libraries */
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#include <libopencmsis/core_cm3.h> // Cortex M3 utilities
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#include <libopencm3/cm3/nvic.h> // interrupt handler
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#include <libopencm3/stm32/rcc.h> // real-time control clock library
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#include <libopencm3/stm32/gpio.h> // general purpose input output library
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#include <libopencm3/stm32/timer.h> // timer library
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/* own libraries */
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#include "global.h" // help macros
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#include "onewire_master.h" // own definitions
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/** @defgroup onewire_master_timer timer used to measure 1-wire signal timing
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* @{
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*/
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#define ONEWIRE_MASTER_TIMER 2 /**< timer ID */
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/** @} */
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/** @defgroup onewire_master_gpio GPIO used for 1-wire signal
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* @note use external pull-up resistor on pin
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* @{
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*/
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#define ONEWIRE_MASTER_PORT A /**< GPIO port */
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#define ONEWIRE_MASTER_PIN 4 /**< GPIO pin */
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/** @} */
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/** state of 1-Wire communication */
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volatile enum {
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ONEWIRE_STATE_IDLE, /**< no current communication */
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ONEWIRE_STATE_DONE, /**< communication complete */
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ONEWIRE_STATE_ERROR, /**< communication error */
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ONEWIRE_STATE_MASTER_RESET, /**< reset pulse started */
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ONEWIRE_STATE_SLAVE_PRESENCE, /**< waiting for slave response to reset pulse */
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ONEWIRE_STATE_MASTER_WRITE, /**< master is writing bits */
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ONEWIRE_STATE_MASTER_READ, /**< master is reading bits */
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ONEWIRE_MAX /** to count the number of possible states */
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} onewire_master_state = ONEWIRE_STATE_IDLE;
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volatile bool slave_presence = false; /**< if slaves have been detected */
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uint8_t* buffer = NULL; /**< input/output buffer for read/write commands/functions */
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size_t buffer_size = 0; /**< size of buffer in bits */
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volatile size_t buffer_bit = 0; /**< number of bits read/written */
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void onewire_master_setup(void)
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{
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// setup GPIO with external interrupt
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rcc_periph_clock_enable(RCC_GPIO(ONEWIRE_MASTER_PORT)); // enable clock for GPIO peripheral
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gpio_set_mode(GPIO(ONEWIRE_MASTER_PORT), GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO(ONEWIRE_MASTER_PIN)); // setup GPIO pin as output (master starts communication before slave replies)
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // idle is high (using pull-up resistor)
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// setup timer to generate/measure signal timing
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rcc_periph_clock_enable(RCC_TIM(ONEWIRE_MASTER_TIMER)); // enable clock for timer peripheral
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timer_reset(TIM(ONEWIRE_MASTER_TIMER)); // reset timer state
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timer_set_mode(TIM(ONEWIRE_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
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timer_set_prescaler(TIM(ONEWIRE_MASTER_TIMER), 1-1); // don't use prescale since this 16 bits timer allows to wait > 480 us used for the reset pulse ( 1/(72E6/1/(2**16))=910us )
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// use comparator to time signal (without using the output), starting at slot start
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timer_set_oc_value(TIM(ONEWIRE_MASTER_TIMER), TIM_OC1, 1*(rcc_ahb_frequency/1000000)); // use compare function to time master pulling low (1 < Tlowr < 15)
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timer_set_oc_value(TIM(ONEWIRE_MASTER_TIMER), TIM_OC2, 7*(rcc_ahb_frequency/1000000)); // use compare function to read of write (1 < Trw < 15)
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timer_set_oc_value(TIM(ONEWIRE_MASTER_TIMER), TIM_OC3, 62*(rcc_ahb_frequency/1000000)); // use compare function to end time slot (60 < Tslot < 120), this will be followed by a recovery time (end of timer)
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timer_set_oc_value(TIM(ONEWIRE_MASTER_TIMER), TIM_OC4, 120*(rcc_ahb_frequency/1000000)); // use compare function to detect slave presence (60 < Tpdl < 240)
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF); // clear update (overflow) flag
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timer_update_on_overflow(TIM(ONEWIRE_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as start time or timeout)
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_UIE); // enable update interrupt for overflow
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nvic_enable_irq(NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)); // catch interrupt in service routine
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slave_presence = false; // reset state
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onewire_master_state = ONEWIRE_STATE_IDLE; // reset state
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}
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bool onewire_master_reset(void)
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{
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// prepare timer
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer to reconfigure it
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timer_set_counter(TIM(ONEWIRE_MASTER_TIMER),0); // reset counter
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timer_set_period(TIM(ONEWIRE_MASTER_TIMER), 490*(rcc_ahb_frequency/1000000)); // set timeout to > 480 us (490)
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slave_presence = false; // reset state
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onewire_master_state = ONEWIRE_STATE_MASTER_RESET; // set new state
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gpio_clear(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal low to start reset (it's not important if it was low in the first place since the reset pulse has no maximum time)
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timer_enable_counter(TIM(ONEWIRE_MASTER_TIMER)); // start timer
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while (onewire_master_state!=ONEWIRE_STATE_DONE && onewire_master_state!=ONEWIRE_STATE_ERROR) { // wait until reset procedure completed
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__WFI(); // go to sleep
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}
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if (ONEWIRE_STATE_ERROR==onewire_master_state) { // an error occurred
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return false;
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}
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return slave_presence;
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}
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/** write bits on 1-Wire bus
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* @warning buffer_size must be set to the number of bits to write and buffer must contain the data to write
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* @return if write succeeded
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*/
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static bool onewire_master_write(void)
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{
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buffer_bit = 0; // reset bit index
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onewire_master_state = ONEWIRE_STATE_MASTER_WRITE; // set new state
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// prepare timer
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer to reconfigure it
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timer_set_counter(TIM(ONEWIRE_MASTER_TIMER),0); // reset counter
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timer_set_period(TIM(ONEWIRE_MASTER_TIMER), TIM_CCR3(TIM(ONEWIRE_MASTER_TIMER))+5*(rcc_ahb_frequency/1000000)); // set time for new time slot (Trec>1, after time slot end)
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // enable compare interrupt for bit setting
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // enable compare interrupt for end of time slow
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// start writing
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gpio_clear(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal low to start slot
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timer_enable_counter(TIM(ONEWIRE_MASTER_TIMER)); // start timer
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while (onewire_master_state!=ONEWIRE_STATE_DONE && onewire_master_state!=ONEWIRE_STATE_ERROR) { // wait until reset procedure completed
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__WFI(); // go to sleep
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}
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if (ONEWIRE_STATE_ERROR==onewire_master_state) { // an error occurred
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return false;
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}
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return true;
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}
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/** read bits on 1-Wire bus
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* @warning buffer_size must be set to the number of bits to read
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* @return if read succeeded
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*/
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static bool onewire_master_read(void)
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{
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if (0==buffer_size) { // check input
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return false;
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}
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if (!(buffer=realloc(buffer, (buffer_size-1)/8+1))) { // allocate memory
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return false; // error in memory allocation
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}
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buffer_bit = 0; // reset bit index
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onewire_master_state = ONEWIRE_STATE_MASTER_READ; // set new state
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// prepare timer
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timer_set_counter(TIM(ONEWIRE_MASTER_TIMER),0); // reset counter
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC1IE); // enable compare interrupt for stop pulling low
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // enable compare interrupt for bit setting
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // enable compare interrupt for end of time slow
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// start reading
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gpio_clear(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal low to start slot
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timer_enable_counter(TIM(ONEWIRE_MASTER_TIMER)); // start timer
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while (onewire_master_state!=ONEWIRE_STATE_DONE && onewire_master_state!=ONEWIRE_STATE_ERROR) { // wait until reset procedure completed
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__WFI(); // go to sleep
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}
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if (ONEWIRE_STATE_ERROR==onewire_master_state) { // an error occurred
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return false;
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}
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return true;
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}
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uint8_t onewire_master_crc(uint8_t* data, size_t size)
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{
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if (NULL==data || 0==size) { // check input
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return 0; // wrong input
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}
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uint8_t crc = 0x00; // initial value
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for (uint8_t i=0; i<size; i++) { // go through every byte
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crc ^= data[i]; // XOR byte
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for (uint8_t b=0; b<8; b++) { // go through every bit
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if (crc&0x01) { // least significant bit is set (we are using the reverse way)
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crc = (crc>>1)^0x8C; // // shift to the right (for the next bit) and XOR with (reverse) polynomial
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} else {
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crc >>= 1; // just shift right (for the next bit)
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}
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}
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}
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return crc;
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}
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bool onewire_master_function_read(uint8_t function, uint8_t* data, size_t bits)
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{
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// send function command
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buffer_size = 8; // function command is only one byte
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if (!(buffer=realloc(buffer, (buffer_size-1)/8+1))) { // allocate memory
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return false; // error in memory allocation
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}
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buffer[0] = function; // set function command
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if (!onewire_master_write()) { // send command
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return false; // an error occurred
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}
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if (NULL==data || 0==bits) { // there is no data to read
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return true; // operation completed
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}
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// read data
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buffer_size = bits; // save number of bits to read
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if (!onewire_master_read()) { // read bits from slave
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return false; // an error occurred
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}
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// copy data to user buffer
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for (uint8_t i=0; i<bits/8; i++) { // copy bytes
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data[i] = buffer[i]; // copy data
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}
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// copy remaining bits
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switch (bits%8) {
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case 1:
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data[(bits-1)/8] = data[(bits-1)/8]&0x01;
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break;
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case 2:
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data[(bits-1)/8] = data[(bits-1)/8]&0x03;
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break;
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case 3:
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data[(bits-1)/8] = data[(bits-1)/8]&0x07;
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break;
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case 4:
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data[(bits-1)/8] = data[(bits-1)/8]&0x0f;
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break;
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case 5:
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data[(bits-1)/8] = data[(bits-1)/8]&0x1f;
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break;
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case 6:
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data[(bits-1)/8] = data[(bits-1)/8]&0x3f;
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break;
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case 7:
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data[(bits-1)/8] = data[(bits-1)/8]&0x7f;
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break;
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case 0: // no bits remaining
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break;
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}
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return true;
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}
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bool onewire_master_function_write(uint8_t function, uint8_t* data, size_t bits)
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{
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// send function command
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buffer_size = 8; // function command is only one byte
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if (!(buffer=realloc(buffer, (buffer_size-1)/8+1))) { // allocate memory
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return false; // error in memory allocation
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}
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buffer[0] = function; // set function command
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if (!onewire_master_write()) { // send command
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return false; // an error occurred
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}
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if (NULL==data || 0==bits) { // there is no data to read
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return true; // operation completed
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}
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// copy data from user buffer
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buffer_size = bits; // save number of bits to write
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if (!(buffer=realloc(buffer, (buffer_size-1)/8+1))) { // allocate memory
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return false; // error in memory allocation
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}
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for (uint8_t i=0; i<(buffer_size-1)/8+1; i++) { // copy bytes
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buffer[i] = data[i]; // copy data
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}
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// write data
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if (!onewire_master_write()) { // read bits from slave
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return false; // an error occurred
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}
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return true;
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}
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uint64_t onewire_master_rom_read(void)
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{
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uint8_t rom_code[8] = {0}; // to store 64 bits ROM code
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if (!onewire_master_function_read(0x33, rom_code, 64)) { // read ROM code (I'm cheating because the ROM command isn't a function command, but it works the same way in the end)
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return 0; // an error occurred
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}
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if (onewire_master_crc(rom_code, LENGTH(rom_code))) { // verify checksum
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return 0; // checksum is wrong (not 0)
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}
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// return ROM code
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uint64_t code = 0;
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for (size_t i=0; i<8; i++) {
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code += (uint64_t)rom_code[i]<<(8*i); // add byte
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}
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return code;
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}
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bool onewire_master_rom_search(uint64_t* code, bool alarm)
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{
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static uint8_t conflict_last = 64; // on which bit has the conflict been detected (64 means there hasn't been)
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uint8_t conflict_current = 64; // to remember on which bit the last unknown conflict has been detected
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// send SEARCH ROM command
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uint8_t command = 0xf0; // SEARCH ROM command
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if (alarm) { // looking only for ROM codes for slaves in alarm state
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command = 0xec; // use ALARM SEARCH ROM command instead
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}
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if (!onewire_master_function_read(command, NULL, 0)) { // send SEARCH ROM command
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goto end; // an error occurred
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}
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if (conflict_last>=64) { // no previous conflict has been detected
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*code = 0; // restart search codes
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}
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for (uint8_t bit=0; bit<64; bit++) { // go through all 64 bits ROM code
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buffer_size = 2; // read two first bits to detect conflict
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if (!onewire_master_read()) { // read ROM ID from slave
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goto end; // an error occurred
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}
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switch (buffer[0]&0x03) { // check 2 bits received
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case 0: // collision detected
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if (bit==conflict_last) { // this conflict is known
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*code |= (((uint64_t)1)<<bit); // use 0 as next bit
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} else { // unknown conflict
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conflict_current = bit; // remember conflict
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*code &= ~(((uint64_t)1)<<bit); // use 1 as next bit
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}
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break;
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case 1: // no conflict, valid bit is 1
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*code |= (((uint64_t)1)<<bit); // remember valid bit 1
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break;
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case 2: // no conflict, valid bit is 0
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*code &= ~(((uint64_t)1)<<bit); // remember valid bit 0
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break;
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default: // two 1's indicate there is no slave
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goto end; // an error has occurred
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}
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buffer_size = 1; // to send next bit
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if (!(buffer=realloc(buffer, 1))) { // allocate memory
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goto end; // an error has occurred
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}
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buffer[0] = (*code>>bit); // set bit to send
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if (!onewire_master_write()) { // send bit
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goto end; // an error has occurred
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}
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}
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// verify ROM code
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uint8_t rom_code[8] = {0}; // to store ROM code
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for (uint8_t i=0; i<LENGTH(rom_code); i++) {
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rom_code[i] = *code>>(8*i); // split and save last code in ROM code
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}
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if (onewire_master_crc(rom_code, LENGTH(rom_code))) { // verify checksum
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*code = 0; // return the last code found since it's valid
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}
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end:
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conflict_last = conflict_current; // update the last seen and unknown conflict
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if (conflict_current<64) { // we have seen an unknown conflict
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return true; // tell there are more slaves
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} else { // no conflict seen
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return false; // no more slaves
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}
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}
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bool onewire_master_rom_skip(void)
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{
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if (!onewire_master_function_write(0xcc, NULL, 0)) { // send SKIP ROM command
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return false; // an error occurred
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}
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return true;
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}
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bool onewire_master_rom_match(uint64_t code)
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{
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uint8_t rom_code[8] = {0}; // to store ROM code
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for (uint8_t i=0; i<LENGTH(rom_code); i++) {
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rom_code[i] = code>>(8*i); // split and save code in ROM code
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}
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if (!onewire_master_function_write(0x55, rom_code, 64)) { // send MATCH ROM command with ROM code
|
||||
return false; // an error occurred
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/** interrupt service routine called for timer */
|
||||
void TIM_ISR(ONEWIRE_MASTER_TIMER)(void)
|
||||
{
|
||||
if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF)) { // overflow update event happened
|
||||
timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
switch (onewire_master_state) {
|
||||
case ONEWIRE_STATE_MASTER_RESET: // reset pulse has been started
|
||||
timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF); // clear output compare flag
|
||||
timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // enable compare interrupt for presence detection
|
||||
gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // set signal high again for slaves to respond
|
||||
onewire_master_state = ONEWIRE_STATE_SLAVE_PRESENCE; // set new state
|
||||
break;
|
||||
case ONEWIRE_STATE_SLAVE_PRESENCE: // waiting for slave presence but none received
|
||||
timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // disable compare interrupt for presence detection
|
||||
onewire_master_state = ONEWIRE_STATE_DONE; // go to next state
|
||||
break;
|
||||
case ONEWIRE_STATE_MASTER_READ: // end of time slot and recovery time for reading bit
|
||||
case ONEWIRE_STATE_MASTER_WRITE: // end of time slot and recovery time for writing bit
|
||||
if (buffer_bit<buffer_size) { // check if byte to read/write are remaining
|
||||
gpio_clear(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal low to start next slot
|
||||
} else { // all bytes read/written
|
||||
timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC1IE); // disable compare interrupt for master pull low
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt for read/write bit
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // disable compare interrupt for end of slot
|
||||
onewire_master_state = ONEWIRE_STATE_DONE; // set end state
|
||||
}
|
||||
break;
|
||||
default: // unknown state for this stage
|
||||
timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable all compare interrupt
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // disable all compare interrupt
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // disable all compare interrupt
|
||||
gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high (idle state)
|
||||
onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
|
||||
}
|
||||
} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF)) { // compare event happened for master pull low end
|
||||
timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF); // clear flag
|
||||
switch (onewire_master_state) {
|
||||
case ONEWIRE_STATE_MASTER_READ: // master has to read a bit
|
||||
gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high to end time slot
|
||||
break;
|
||||
default: // unknown state for this stage
|
||||
break; // let the overflow handle the error if any
|
||||
}
|
||||
} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF)) { // compare event happened for bit sampling/setting
|
||||
timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF); // clear flag
|
||||
switch (onewire_master_state) {
|
||||
case ONEWIRE_STATE_MASTER_WRITE: // master has to write a bit
|
||||
if (buffer_bit<buffer_size) { // check if byte to send are remaining
|
||||
if (buffer[buffer_bit/8]&(1<<(buffer_bit%8))) { // check bit (LSb first)
|
||||
gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // set signal high again to write "1"
|
||||
}
|
||||
buffer_bit++; // got to next bit
|
||||
} else {
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt
|
||||
onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
|
||||
}
|
||||
break;
|
||||
case ONEWIRE_STATE_MASTER_READ: // master has to read a bit set by slave
|
||||
if (buffer_bit<buffer_size) { // check if byte to send are remaining
|
||||
if (gpio_get(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN))) { // check if the slave kept it low
|
||||
buffer[buffer_bit/8] |= (1<<(buffer_bit%8)); // save bit "1"
|
||||
} else {
|
||||
buffer[buffer_bit/8] &= ~(1<<(buffer_bit%8)); // save bit "0"
|
||||
}
|
||||
buffer_bit++; // got to next bit
|
||||
} else {
|
||||
timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt
|
||||
onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
|
||||
}
|
||||
break;
|
||||
default: // unknown state for this stage
|
||||
break; // let the overflow handle the error if any
|
||||
}
|
||||
} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF)) { // compare event happened for end to time slot
|
||||
timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF); // clear flag
|
||||
gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high to end time slot
|
||||
} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF)) { // compare event happened for slave presence detection
|
||||
timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF); // clear flag
|
||||
if (gpio_get(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN))) { // check is a slave let its presence know by pulling low
|
||||
slave_presence = false; // remember no slave(s) responded
|
||||
} else {
|
||||
slave_presence = true; // remember slave(s) responded
|
||||
}
|
||||
} else { // no other interrupt should occur
|
||||
while (true); // unhandled exception: wait for the watchdog to bite
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
/** library for 1-wire protocol as master (API)
|
||||
* @file onewire_master.c
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @date 2017
|
||||
* @note peripherals used: timer @ref onewire_master_timer, GPIO @ref onewire_master_gpio
|
||||
* @warning this library does not support parasite power mode
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/** setup 1-wire peripheral */
|
||||
void onewire_master_setup(void);
|
||||
/** send reset pulse
|
||||
* @return if slaves have indicated their presence
|
||||
*/
|
||||
bool onewire_master_reset(void);
|
||||
/** compute CRC for 1-Wire
|
||||
* @note this CRC-8 uses normal polynomial 0x31, reverse polynomial 0x8C, start value 0x00
|
||||
* @param[in] data bytes on which to calculate CRC checksum on
|
||||
* @param[in] size number of bytes in data
|
||||
* @return computed CRC checksum
|
||||
*/
|
||||
uint8_t onewire_master_crc(uint8_t* data, size_t size);
|
||||
/** send READ ROM command
|
||||
* @note user needs to send reset pulse before
|
||||
* @return ROM code read
|
||||
*/
|
||||
uint64_t onewire_master_rom_read(void);
|
||||
/** send SEARCH ROM command
|
||||
* @note user needs to send reset pulse before
|
||||
* @warning undefined behaviour if a ROM code different than the last found is provided
|
||||
* @param[in,out] code use 0 to start search ROM code from scratch, or last know value to search next; writes back next ROM code found, or 0 if error occurred
|
||||
* @param[in] alarm search only for ROM codes for slaves with an alarm flag set
|
||||
* @return if an additional slave has been detected
|
||||
*/
|
||||
bool onewire_master_rom_search(uint64_t* code, bool alarm);
|
||||
/** send SKIP ROM command (all slaves on the bus will be selected)
|
||||
* @note user needs to send reset pulse before
|
||||
* @return if operation succeeded
|
||||
*/
|
||||
bool onewire_master_rom_skip(void);
|
||||
/** send MATCH ROM command to select a specific slave
|
||||
* @note user needs to send reset pulse before
|
||||
* @param[in] code ROM code of slave to select
|
||||
* @return if operation succeeded
|
||||
*/
|
||||
bool onewire_master_rom_match(uint64_t code);
|
||||
/** issue function and read data
|
||||
* @note user needs to send a ROM command before
|
||||
* @param[in] function function command to send
|
||||
* @param[out] data buffer to save read bits (NULL if only the function command should be sent)
|
||||
* @param[in] bits number of bits to read (0 if only the function command should be sent)
|
||||
* @return if operation succeeded
|
||||
*/
|
||||
bool onewire_master_function_read(uint8_t function, uint8_t* data, size_t bits);
|
||||
/** issue function and write data
|
||||
* @note user needs to send a ROM command before
|
||||
* @param[in] function function command to send
|
||||
* @param[out] data data to write (NULL if only the function command should be sent)
|
||||
* @param[in] bits number of bits to write (0 if only the function command should be sent)
|
||||
* @return if operation succeeded
|
||||
*/
|
||||
bool onewire_master_function_write(uint8_t function, uint8_t* data, size_t bits);
|
||||
Loading…
Reference in New Issue