From 334d8564ff5a3997d70c50734189004f987ef2a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?King=20K=C3=A9vin?= Date: Mon, 22 Mar 2021 11:26:35 +0100 Subject: [PATCH] swd: use signal as open-drain instead of push-pull, only to make is level shifter compatible --- lib/swd.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/lib/swd.c b/lib/swd.c index fe16e7b..5ea5cba 100644 --- a/lib/swd.c +++ b/lib/swd.c @@ -177,11 +177,13 @@ bool swd_set_pins(uint32_t swclk_port, uint32_t swclk_pin, uint32_t swdio_port, rcc_periph_clock_enable(swd_swclk_rcc); // enable clock for GPIO peripheral for clock signal gpio_set(swd_swclk_port, swd_swclk_pin); // inactive clock is high gpio_mode_setup(swd_swclk_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, swd_swclk_pin); // the host controls the clock - gpio_set_output_options(swd_swclk_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, swd_swclk_pin); // set SWCLK pin output as push-pull + //gpio_set_output_options(swd_swclk_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, swd_swclk_pin); // set SWCLK pin output as push-pull + gpio_set_output_options(swd_swclk_port, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, swd_swclk_pin); // set SWCLK pin output as open-drain (with external pull-up) rcc_periph_clock_enable(swd_swdio_rcc); // enable clock for GPIO peripheral for data signal gpio_set(swd_swdio_port, swd_swdio_pin); // inactive data is high (resetting the target when clock is active) gpio_mode_setup(swd_swdio_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, swd_swdio_pin); // the data signal is half duplex, with the host controlling who is driving the data signal when - gpio_set_output_options(swd_swdio_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, swd_swdio_pin); // set SWDIO pin output as push-pull + //gpio_set_output_options(swd_swdio_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, swd_swdio_pin); // set SWDIO pin output as push-pull + gpio_set_output_options(swd_swdio_port, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, swd_swdio_pin); // set SWDIO pin output as open-drain (with external pull-up) return true; } @@ -203,7 +205,8 @@ uint64_t swd_transaction(uint64_t output, uint8_t bit_count, bool write) gpio_mode_setup(swd_swdio_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, swd_swdio_pin); // we drive the data signal to output data swd_bits_out = output; // set data to output } else { - gpio_mode_setup(swd_swdio_port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, swd_swdio_pin); // the target will drive the data signal, we just pull it up + //gpio_mode_setup(swd_swdio_port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, swd_swdio_pin); // the target will drive the data signal, we just pull it up + gpio_mode_setup(swd_swdio_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, swd_swdio_pin); // the target will drive the data signal, and there is an external pull-up swd_bits_out = ~0ULL; // set the value so we pull up } swd_bits_in = 0; // reset input buffer @@ -459,7 +462,9 @@ void TIM_ISR(SWD_TIMER)(void) swd_bits_out &= ~(1ULL << swd_bits_i); // clear bit } swd_bits_i++; + gpio_set_output_options(swd_swclk_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, swd_swclk_pin); // we need an extremely sharp rising edge gpio_set(swd_swclk_port, swd_swclk_pin); // output rising clock edge + gpio_set_output_options(swd_swclk_port, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, swd_swclk_pin); // go back to open-drain once we are high } edge_falling = !edge_falling; // remember opposite upcoming edge } else { // no other interrupt should occur