From 215b37f3a505606e42ffef82e1baf6abae16b873 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?King=20K=C3=A9vin?= <kingkevin@cuvoodoo.info>
Date: Tue, 4 May 2021 11:28:05 +0200
Subject: [PATCH] add 74HC595 shift register

---
 ic/ic_shift-register_nxp_74hc595.yaml | 52 +++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 ic/ic_shift-register_nxp_74hc595.yaml

diff --git a/ic/ic_shift-register_nxp_74hc595.yaml b/ic/ic_shift-register_nxp_74hc595.yaml
new file mode 100644
index 0000000..3c181a1
--- /dev/null
+++ b/ic/ic_shift-register_nxp_74hc595.yaml
@@ -0,0 +1,52 @@
+name: 74HC595
+alias: 74HCT595
+variations: SO, SSOP, TSSOP
+# the DHVQFN variation is not defined because Qeda (and IPC7351) do not specify QFN with pin 1 on left middle and marking on bottom left corner (a custom footprint would be required)
+description: 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
+datasheet: https://assets.nexperia.com/documents/data-sheet/74HC_HCT595.pdf
+keywords: IC, Digital, Shift Register
+
+pinout:
+  Q:
+    Q0: 15
+    Q1: 1
+    Q2: 2
+    Q3: 3
+    Q4: 4
+    Q5: 5
+    Q6: 6
+    Q7: 7
+  Q7S: 9
+  MR: 10
+  SHCP: 11
+  STCP: 12
+  OE: 13
+  DS: 14
+  VCC: 16
+  GND: 8
+
+properties:
+  input: MR, SHCP, STCP, OE, DS
+  output: Q, Q7S
+  power: VCC
+  ground: GND
+  inverted: MR, OE
+
+schematic:
+  symbol: IC
+  left: DS, SHCP, MR, STCP, OE
+  right: Q, Q7S
+  top: VCC
+  bottom: GND
+
+housing@SO:
+  suffix: D
+  outline: NXP SOT109-1
+
+housing@SSOP:
+  suffix: DB
+  outline: NXP SOT338-1
+
+housing@TSSOP:
+  suffix: PW
+  outline: NXP SOT403-1