From c4566c4d2ba5219e6c2ea821912b888d0270ff07 Mon Sep 17 00:00:00 2001 From: Gabriel Chouinard Date: Tue, 5 Sep 2023 21:28:13 -0400 Subject: [PATCH] Enable instruction cache for stm32u5 boards --- hw/bsp/stm32u5/boards/stm32u575nucleo/board.h | 2 +- hw/bsp/stm32u5/family.c | 3 +++ hw/bsp/stm32u5/family.mk | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h index 75e8a0d6a..54a6d4cd7 100644 --- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h @@ -61,7 +61,7 @@ static inline void board_clock_init(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /* Enable Power Clock*/ + /* Enable Power Clock */ __HAL_RCC_PWR_CLK_ENABLE(); /** Configure the main internal regulator output voltage diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index a30d886aa..c1fe3f412 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -60,6 +60,9 @@ void board_init(void) UART_CLK_EN(); + /* Enable Instruction cache */ + HAL_ICACHE_Enable(); + #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 9174fe96a..dace63a51 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -20,6 +20,7 @@ SRC_C += \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \