From 787229a35e20e488b642e879e4f068571e9488df Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 2 Jul 2023 23:39:43 +0700
Subject: [PATCH] add etm trace for 6m5

---
 hw/bsp/ra/boards/ra6m5_ek/board.h            | 19 ++++++++---
 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 35 ++++++++++++++++++++
 hw/bsp/ra/family.c                           |  5 +++
 3 files changed, 54 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug

diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
index 4a1527f93..9c9bb6dcf 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -38,11 +38,20 @@ extern "C" {
 #define BUTTON_STATE_ACTIVE   0
 
 const ioport_pin_cfg_t board_pin_cfg[] = {
-  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+    { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+    { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+    { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
+    { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+
+    #ifdef TRACE_ETM
+    // ETM Trace
+    { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    #endif
 };
 
 #ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
new file mode 100644
index 000000000..fa55d40b2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -0,0 +1,35 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.AddSvdFile ("Cortex-M33.svd");
+  Project.AddSvdFile ("./R7FA6M5BH.svd");
+
+  Project.SetDevice ("R7FA6M5BH");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+}
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 82d7a60c5..f7c5e36f9 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -87,6 +87,11 @@ void board_init(void)
   /* Configure pins. */
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
+#ifdef TRACE_ETM
+  // Enable trace clock with div 1 (100 Mhz)
+  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk;
+#endif
+
   board_led_write(false);
 
   /* Enable USB_BASE */