diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c index 1b28b668a..d5c93222c 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v12.0 processor: MIMXRT1011xxxxx package_id: MIMXRT1011DAE5A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 14.0.0 board: MIMXRT1010-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h index 119fd94bd..cc627cf6a 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h @@ -36,36 +36,36 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c b/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c index 6216d99c8..2d869b56e 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.1 +product: Pins v14.0 processor: MIMXRT1011xxxxx package_id: MIMXRT1011DAE5A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 14.0.0 board: MIMXRT1010-EVK external_user_signals: {} pin_labels: diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex index de0a2f75d..ef551731a 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex +++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex @@ -1,5 +1,5 @@ - + MIMXRT1011xxxxx MIMXRT1011DAE5A @@ -19,19 +19,20 @@ false - + - 13.0.2 + 14.0.0 + @@ -93,13 +94,13 @@ - + - 13.0.2 + 14.0.0 diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h index 0b6b462e7..303935517 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h @@ -24,11 +24,10 @@ * This file is part of the TinyUSB stack. */ +#ifndef BOARD_MIMXRT1170_EVKB_H_ +#define BOARD_MIMXRT1170_EVKB_H_ -#ifndef BOARD_H_ -#define BOARD_H_ - -// required since iMX RT10xx SDK include this file for board size +// required since iMXRT MCUX-SDK include this file for board size #define BOARD_FLASH_SIZE (0x1000000U) // LED: IOMUXC_GPIO_AD_04_GPIO9_IO03 @@ -45,4 +44,4 @@ #define UART_PORT LPUART1 #define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT -#endif /* BOARD_H_ */ +#endif diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c index b9953a456..88b3b3770 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c @@ -11,11 +11,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v12.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 14.0.1 board: MIMXRT1170-EVKB * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -275,6 +275,7 @@ void BOARD_BootClockRUN(void) { clock_root_config_t rootCfg = {0}; +#if !defined(SKIP_DCDC_CONFIGURATION) || (!SKIP_DCDC_CONFIGURATION) /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */ DCDC_BootIntoDCM(DCDC); @@ -288,7 +289,8 @@ void BOARD_BootClockRUN(void) /* Set 1.125V for production samples to align with data sheet requirement */ DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V); } -#endif +#endif /* SKIP_DCDC_ADJUSTMENT */ +#endif /* SKIP_DCDC_CONFIGURATION */ #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE) /* Check if FBB need to be enabled in OverDrive(OD) mode */ @@ -333,7 +335,7 @@ void BOARD_BootClockRUN(void) /* Init OSC RC 400M */ CLOCK_OSC_EnableOscRc400M(); - CLOCK_OSC_GateOscRc400M(true); + CLOCK_OSC_GateOscRc400M(false); /* Init OSC RC 48M */ CLOCK_OSC_EnableOsc48M(true); diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h index 82d2cf83c..4a4d35eaa 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h @@ -42,144 +42,144 @@ void BOARD_InitBootClocks(void); #endif /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL -#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL -#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL -#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL -#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL -#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL -#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL -#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL -#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL -#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL -#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL -#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL /* Clock consumers of ADC1_CLK_ROOT output : LPADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL /* Clock consumers of ADC2_CLK_ROOT output : LPADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */ +#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */ +#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL /* Clock consumers of CAN3_CLK_ROOT output : CAN3 */ +#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL /* Clock consumers of CCM_CLKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL /* Clock consumers of CCM_CLKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG3, RTWDOG4 */ +#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL /* Clock consumers of CSI2_CLK_ROOT output : MIPI_CSI2RX */ +#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL /* Clock consumers of CSI2_ESC_CLK_ROOT output : MIPI_CSI2RX */ +#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL /* Clock consumers of CSI2_UI_CLK_ROOT output : MIPI_CSI2RX */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL /* Clock consumers of CSI_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL /* Clock consumers of CSSYS_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL /* Clock consumers of CSTRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL /* Clock consumers of ELCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL /* Clock consumers of EMV1_CLK_ROOT output : EMVSIM1 */ +#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL /* Clock consumers of EMV2_CLK_ROOT output : EMVSIM2 */ +#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL /* Clock consumers of ENET1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL /* Clock consumers of ENET2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL /* Clock consumers of ENET_1G_REF_CLK output : ENET_1G */ +#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL /* Clock consumers of ENET_1G_TX_CLK output : ENET_1G */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL /* Clock consumers of ENET_25M_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL /* Clock consumers of ENET_QOS_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL /* Clock consumers of ENET_QOS_REF_CLK output : ENET_QOS */ +#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL /* Clock consumers of ENET_QOS_TX_CLK output : ENET_QOS */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL /* Clock consumers of ENET_TIMER1_CLK_ROOT output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL /* Clock consumers of ENET_TIMER2_CLK_ROOT output : ENET_1G */ +#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL /* Clock consumers of ENET_TIMER3_CLK_ROOT output : ENET_QOS */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL /* Clock consumers of GC355_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL /* Clock consumers of GPT3_CLK_ROOT output : GPT3 */ +#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT3_ipg_clk_highfreq output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL /* Clock consumers of GPT4_CLK_ROOT output : GPT4 */ +#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT4_ipg_clk_highfreq output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL /* Clock consumers of GPT5_CLK_ROOT output : GPT5 */ +#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT5_ipg_clk_highfreq output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL /* Clock consumers of GPT6_CLK_ROOT output : GPT6 */ +#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT6_ipg_clk_highfreq output : N/A */ +#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL /* Clock consumers of LCDIFV2_CLK_ROOT output : LCDIFV2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL /* Clock consumers of LPI2C1_CLK_ROOT output : LPI2C1 */ +#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL /* Clock consumers of LPI2C2_CLK_ROOT output : LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL /* Clock consumers of LPI2C3_CLK_ROOT output : LPI2C3 */ +#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL /* Clock consumers of LPI2C4_CLK_ROOT output : LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL /* Clock consumers of LPI2C5_CLK_ROOT output : LPI2C5 */ +#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL /* Clock consumers of LPI2C6_CLK_ROOT output : LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL /* Clock consumers of LPSPI1_CLK_ROOT output : LPSPI1 */ +#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL /* Clock consumers of LPSPI2_CLK_ROOT output : LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL /* Clock consumers of LPSPI3_CLK_ROOT output : LPSPI3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL /* Clock consumers of LPSPI4_CLK_ROOT output : LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL /* Clock consumers of LPSPI5_CLK_ROOT output : LPSPI5 */ +#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL /* Clock consumers of LPSPI6_CLK_ROOT output : LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL /* Clock consumers of LPUART10_CLK_ROOT output : LPUART10 */ +#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL /* Clock consumers of LPUART11_CLK_ROOT output : LPUART11 */ +#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL /* Clock consumers of LPUART12_CLK_ROOT output : LPUART12 */ +#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL /* Clock consumers of LPUART1_CLK_ROOT output : LPUART1 */ +#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL /* Clock consumers of LPUART2_CLK_ROOT output : LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL /* Clock consumers of LPUART3_CLK_ROOT output : LPUART3 */ +#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL /* Clock consumers of LPUART4_CLK_ROOT output : LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL /* Clock consumers of LPUART5_CLK_ROOT output : LPUART5 */ +#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL /* Clock consumers of LPUART6_CLK_ROOT output : LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL /* Clock consumers of LPUART7_CLK_ROOT output : LPUART7 */ +#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL /* Clock consumers of LPUART8_CLK_ROOT output : LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL /* Clock consumers of LPUART9_CLK_ROOT output : LPUART9 */ +#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL /* Clock consumers of M4_CLK_ROOT output : ARM, DMA1, DMAMUX1, SSARC_HP, SSARC_LP, XRDC2_D0, XRDC2_D1 */ +#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL /* Clock consumers of M4_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL /* Clock consumers of M7_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL /* Clock consumers of MIC_CLK_ROOT output : ASRC, PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL /* Clock consumers of MIPI_DSI_TX_CLK_ESC_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL /* Clock consumers of MIPI_ESC_CLK_ROOT output : DSI_HOST */ +#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL /* Clock consumers of MIPI_REF_CLK_ROOT output : DSI_HOST */ +#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL /* Clock consumers of MQS_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : SPDIF, TMPSNS, USBPHY1, USBPHY2 */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : GPIO13, RTWDOG3, RTWDOG4 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL /* Clock consumers of OSC_RC_16M output : CCM, DCDC, EWM, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6, SSARC_LP */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL /* Clock consumers of OSC_RC_48M output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL /* Clock consumers of OSC_RC_48M_DIV2 output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL /* Clock consumers of PLL_VIDEO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL /* Clock consumers of PLL_VIDEO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL /* Clock consumers of PLL_VIDEO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL /* Clock consumers of SAI1_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL /* Clock consumers of SAI2_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL /* Clock consumers of SAI3_CLK_ROOT output : ASRC, SPDIF */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL /* Clock consumers of SAI4_CLK_ROOT output : ASRC, SPDIF */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /******************************************************************************* diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c index b70a7c5bd..81ffb35e3 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.1 +product: Pins v14.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 14.0.1 board: MIMXRT1170-EVKB external_user_signals: {} pin_labels: diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex index 9b87a805d..e68b9ea7e 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex @@ -1,5 +1,5 @@ - + MIMXRT1176xxxxx MIMXRT1176DVMAA @@ -19,17 +19,18 @@ false - + - 13.0.2 + 14.0.1 + @@ -103,13 +104,13 @@ - + - 13.0.2 + 14.0.1 @@ -373,10 +374,7 @@ - - - - + 13.0.2 c_array diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index a9ba00305..8ed72aa19 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -64,7 +64,30 @@ TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; // //--------------------------------------------------------------------+ -static void init_usb_phy(USBPHY_Type* usb_phy) { +// unify naming convention +#if !defined(USBPHY1) && defined(USBPHY) + #define USBPHY1 USBPHY +#endif + +static void init_usb_phy(uint8_t usb_id) { + USBPHY_Type* usb_phy; + + if (usb_id == 0) { + usb_phy = USBPHY1; + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); + } + #ifdef USBPHY2 + else if (usb_id == 1) { + usb_phy = USBPHY2; + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); + } + #endif + else { + return; + } + // Enable PHY support for Low speed device + LS via FS Hub usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; @@ -122,22 +145,9 @@ void board_init(void) //------------- USB -------------// // Note: RT105x RT106x and later have dual USB controllers. - - // Clock - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); - -#ifdef USBPHY1 - init_usb_phy(USBPHY1); -#else - init_usb_phy(USBPHY); -#endif - + init_usb_phy(0); // USB0 #ifdef USBPHY2 - // USB1 - CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); - init_usb_phy(USBPHY2); + init_usb_phy(1); // USB1 #endif }