diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index f0b01b43d..917c83d74 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -142,8 +142,7 @@ jobs:
- name: Create flash.sh
run: |
- #echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
- echo > flash.sh 'pyocd flash -t rp2040 $1'
+ echo > flash.sh 'cmdout=$(openocd -f "interface/cmsis-dap.cfg" -f "target/rp2040.cfg" -c "adapter speed 5000" -c "program $1 reset exit")'
echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
chmod +x flash.sh
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 844a03443..12173fb63 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -32,6 +32,7 @@ jobs:
matrix:
family:
# Alphabetical order
+ - 'mcx'
- 'imxrt'
steps:
- name: Setup Python
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 7dacd0003..a80ebed3c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,8 +2,9 @@
-
-
+
+
+
@@ -29,6 +30,8 @@
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml
new file mode 100644
index 000000000..70cfeea53
--- /dev/null
+++ b/.idea/runConfigurations/rt1010_jlink.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010_nxplink.xml b/.idea/runConfigurations/rt1010_nxplink.xml
deleted file mode 100644
index cf3bf842f..000000000
--- a/.idea/runConfigurations/rt1010_nxplink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1060_nxplink.xml b/.idea/runConfigurations/rt1060_nxplink.xml
deleted file mode 100644
index d3303bdb6..000000000
--- a/.idea/runConfigurations/rt1060_nxplink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 6fb98afb8..4071ec326 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -8,8 +8,16 @@ repos:
hooks:
- id: check-yaml
- id: trailing-whitespace
+ exclude: |
+ (?x)^(
+ hw/bsp/mcx/sdk/
+ )
- id: end-of-file-fixer
- exclude: ^.idea/
+ exclude: |
+ (?x)^(
+ .idea/|
+ hw/bsp/mcx/sdk/
+ )
- id: forbid-submodules
- repo: https://github.com/codespell-project/codespell
@@ -17,7 +25,11 @@ repos:
hooks:
- id: codespell
args: [-w]
- exclude: ^lib/
+ exclude: |
+ (?x)^(
+ lib/|
+ hw/bsp/mcx/sdk/
+ )
- repo: local
hooks:
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 10a1f4c26..89cfceeeb 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -24,7 +24,7 @@ family_add_subdirectory(midi_test)
family_add_subdirectory(msc_dual_lun)
# FIXME temp skip net_lwip_webserver for imxrt for now
-if (NOT ${FAMILY} STREQUAL "imxrt")
+if (NOT ${FAMILY} STREQUAL "imxrt" AND NOT ${FAMILY} STREQUAL "mcx")
family_add_subdirectory(net_lwip_webserver)
endif()
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index cd195a19b..35210dbae 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -44,7 +44,7 @@
TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
#include "chip.h"
-#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
#include "fsl_device_registers.h"
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 442aba955..d2d675332 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -135,6 +135,13 @@ function(family_add_default_example_warnings TARGET)
endif()
endfunction()
+
+# add_custom_command(TARGET ${TARGET} POST_BUILD
+# COMMAND ${CMAKE_OBJCOPY} -O ihex $ ${TARGET}.hex
+# COMMAND ${CMAKE_OBJCOPY} -O binary $ ${TARGET}.bin
+# COMMENT "Creating ${TARGET}.hex and ${TARGET}.bin"
+# )
+
# Add flash jlink target
function(family_flash_jlink TARGET)
if (NOT DEFINED JLINKEXE)
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 5261e5810..ade744aa5 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -1,8 +1,4 @@
-if (TARGET _imxrt_family_inclusion_marker)
- return()
-endif ()
-
-add_library(_imxrt_family_inclusion_marker INTERFACE)
+include_guard()
if (NOT BOARD)
message(FATAL_ERROR "BOARD not specified")
@@ -87,6 +83,11 @@ function(family_configure_target TARGET)
# set output name to .elf
set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+ # run size after build
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${TOOLCHAIN_SIZE} $
+ )
+
# TOP is path to root directory
set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
new file mode 100644
index 000000000..b540012a4
--- /dev/null
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC18S37)
+
+set(JLINK_DEVICE LPC18S37)
+set(PYOCD_TARGET LPC18S37)
+set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
+
+function(update_board TARGET)
+ # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake
new file mode 100644
index 000000000..1efeafd12
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC1857)
+
+set(JLINK_DEVICE LPC1857)
+set(PYOCD_TARGET LPC1857)
+set(NXPLINK_DEVICE LPC1857:MCB1857)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
+
+function(update_board TARGET)
+ # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
new file mode 100644
index 000000000..059408fe9
--- /dev/null
+++ b/hw/bsp/lpc18/family.cmake
@@ -0,0 +1,155 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/../gcc/cr_startup_lpc18xx.c
+ ${SDK_DIR}/src/chip_18xx_43xx.c
+ ${SDK_DIR}/src/clock_18xx_43xx.c
+ ${SDK_DIR}/src/gpio_18xx_43xx.c
+ ${SDK_DIR}/src/sysinit_18xx_43xx.c
+ ${SDK_DIR}/src/uart_18xx_43xx.c
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -nostdlib
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ __USE_LPCOPEN
+ CORE_M3
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/inc
+ ${SDK_DIR}/inc/config_18xx
+ )
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${TOOLCHAIN})
+ MESSAGE(FATAL_ERROR "LD_FILE_${TOOLCHAIN} not defined")
+ endif ()
+
+ if (TOOLCHAIN STREQUAL "gcc")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_gcc}"
+ "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map"
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ else ()
+ # TODO support IAR
+ endif ()
+endif () # BOARD_TARGET
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+ # set output name to .elf
+ set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+ # run size after build
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${TOOLCHAIN_SIZE} $
+ )
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # TinyUSB Port
+ ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+ ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+ ${TOP}/src/portable/ehci/ehci.c
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ #---------- TinyUSB ----------
+ # tinyusb target is built for each example since it depends on example's tusb_config.h
+ set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+ add_library(${TARGET}-tinyusb_config INTERFACE)
+
+ target_include_directories(${TARGET}-tinyusb_config INTERFACE
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+ CFG_TUSB_MCU=OPT_MCU_LPC18XX
+ )
+
+ # tinyusb's CMakeList.txt
+ add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+ # group target (not yet supported by clion)
+ set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+ PROPERTIES FOLDER ${TARGET}_sub
+ )
+
+ #---------- Flash ----------
+ family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_add_freertos TARGET)
+ # freertos_config
+ add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
+
+ ## freertos
+ if (NOT TARGET freertos_kernel)
+ add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+ endif ()
+
+ # Add FreeRTOS option to tinyusb_config
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+ CFG_TUSB_OS=OPT_OS_FREERTOS
+ )
+ # link tinyusb with freeRTOS kernel
+ target_link_libraries(${TARGET}-tinyusb PUBLIC
+ freertos_kernel
+ )
+ target_link_libraries(${TARGET} PUBLIC
+ freertos_kernel
+ )
+endfunction()
+
+function(family_configure_device_example TARGET)
+ family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+ family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+ family_configure_target(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 611c88eb5..3aeda5b2d 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -1,8 +1,4 @@
-if (TARGET _lpc55_family_inclusion_marker)
- return()
-endif ()
-
-add_library(_lpc55_family_inclusion_marker INTERFACE)
+include_guard()
if (NOT BOARD)
message(FATAL_ERROR "BOARD not specified")
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4c6058d27
--- /dev/null
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 2
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+
+ /*According to reference manual, device mode setting has to be set by access usb host register */
+ CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock
+ USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
+ CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
+
+ /* enable USB Device clock */
+ CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
+#endif
+
+#if PORT_SUPPORT_DEVICE(1)
+ // Port1 is High Speed
+
+ // Power
+ SPC0->ACTIVE_VDELAY = 0x0500;
+ /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
+ SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+ SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+ SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+ /* Wait until it is done */
+ while (SPC0->SC & SPC_SC_BUSY_MASK) {}
+ if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+ SCG0->TRIM_LOCK = 0x5a5a0001U;
+ SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+ /* wait LDO ready */
+ while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
+ }
+ SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+ SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+ /* xtal = 20 ~ 30MHz */
+ SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+ SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+ while (1) {
+ if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+ break;
+ }
+ }
+
+ // Clock
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+ CLOCK_EnableClock(kCLOCK_UsbHs);
+ CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+ CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
+ CLOCK_EnableUsbhsClock();
+
+ // USB PHY
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+ USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+
+ // Enable PHY support for Low speed device + LS via FS Hub
+ USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+ // Enable all power for normal operation
+ USBPHY->PWD = 0;
+
+ // TX Timing
+ uint32_t phytx = USBPHY->TX;
+ phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+ phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
+ //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+ USBPHY->TX = phytx;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+ GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+
+#ifdef NEOPIXEL_PIN
+ if (state) {
+ sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
+ sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
+ } else {
+ sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
+ sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
+ }
+ sctpix_show();
+#endif
+}
+
+uint32_t board_button_read(void)
+{
+#ifdef BUTTON_GPIO
+ return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+ (void) buf; (void) len;
+ return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+ LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+ return len;
+#else
+ (void) buf; (void) len;
+ return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+ return system_ticks;
+}
+#endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
new file mode 100644
index 000000000..e4bc11be5
--- /dev/null
+++ b/hw/bsp/mcx/family.cmake
@@ -0,0 +1,179 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+# TOP is path to root directory
+set(TOP ${CMAKE_CURRENT_LIST_DIR}/../../..)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ # external driver
+ #lib/sct_neopixel/sct_neopixel.c
+
+ # driver
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+ # mcu
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+ )
+# target_compile_definitions(${BOARD_TARGET} PUBLIC
+# )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ # driver
+ # mcu
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${SDK_DIR}/devices/${MCU_VARIANT}
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+ )
+ update_board(${BOARD_TARGET})
+
+ if (TOOLCHAIN STREQUAL "gcc")
+ target_sources(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+ )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ # linker file
+ "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+ # link map
+ "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map"
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ else ()
+ # TODO support IAR
+ endif ()
+endif () # BOARD_TARGET
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+ # set output name to .elf
+ set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+ # run size after build
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${TOOLCHAIN_SIZE} $
+ )
+
+ # TOP is path to root directory
+ set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # TinyUSB Port
+ ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ #---------- TinyUSB ----------
+ # tinyusb target is built for each example since it depends on example's tusb_config.h
+ set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+ add_library(${TARGET}-tinyusb_config INTERFACE)
+
+ target_include_directories(${TARGET}-tinyusb_config INTERFACE
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+ CFG_TUSB_MCU=OPT_MCU_MCXN9
+ )
+
+ # tinyusb's CMakeList.txt
+ add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+ # group target (not yet supported by clion)
+ set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+ PROPERTIES FOLDER ${TARGET}_sub
+ )
+
+ #---------- Flash ----------
+ # use MCUXpresso GUI Flash Tool to flash the elf
+
+# set(REDLINK_EXE /usr/local/LinkServer/binaries/crt_emu_cm_redlink)
+# add_custom_target(${TARGET}-redlink
+# DEPENDS ${TARGET}
+# COMMAND ${REDLINK_EXE} --flash-load-exec $ --vendor NXP -p MCXN947 --bootromstall
+# 0x50000040 -CoreIndex=0 --flash-driver= -x ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-dir
+# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-hashing
+# )
+
+ #family_flash_jlink(${TARGET})
+ #family_flash_nxplink(${TARGET})
+ #family_flash_pyocd(${TARGET})
+endfunction()
+
+
+function(family_add_freertos TARGET)
+ # freertos_config
+ if (NOT TARGET freertos_config)
+ add_library(freertos_config INTERFACE)
+ target_include_directories(freertos_config SYSTEM INTERFACE
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig
+ )
+ endif()
+
+ ## freertos
+ if (NOT TARGET freertos_kernel)
+ add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+ endif ()
+
+ # Add FreeRTOS option to tinyusb_config
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+ CFG_TUSB_OS=OPT_OS_FREERTOS
+ )
+ # link tinyusb with freeRTOS kernel
+ target_link_libraries(${TARGET}-tinyusb PUBLIC
+ freertos_kernel
+ )
+ target_link_libraries(${TARGET} PUBLIC
+ freertos_kernel
+ )
+endfunction()
+
+function(family_configure_device_example TARGET)
+ family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+ family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+ family_configure_target(${TARGET})
+endfunction()
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
new file mode 100644
index 000000000..2cd4c2448
--- /dev/null
+++ b/hw/bsp/mcx/family.mk
@@ -0,0 +1,48 @@
+UF2_FAMILY_ID = 0x2abc77ec
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m33
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+
+# Default to Highspeed PORT1
+PORT ?= 1
+
+CFLAGS += \
+ -flto \
+ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+ -DBOARD_TUD_RHPORT=$(PORT) \
+
+ifeq ($(PORT), 1)
+ $(info "PORT1 High Speed")
+ CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+else
+ $(info "PORT0 Full Speed")
+endif
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+
+# All source paths should be relative to the top level.
+LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+
+SRC_C += \
+ src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
+ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+
+SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 9c43478e8..1156a171b 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -1,8 +1,4 @@
-if (TARGET _nrf_family_inclusion_marker)
- return()
-endif ()
-
-add_library(_nrf_family_inclusion_marker INTERFACE)
+include_guard()
if (NOT BOARD)
message(FATAL_ERROR "BOARD not specified")
@@ -89,6 +85,11 @@ function(family_configure_target TARGET)
# set output name to .elf
set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+ # run size after build
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${TOOLCHAIN_SIZE} $
+ )
+
# TOP is path to root directory
set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index ba8976a8c..9c2933983 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -59,14 +59,6 @@
#define TUP_USBIP_OHCI
#define TUP_OHCI_RHPORTS 2
-#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
- // TODO USB0 has 6, USB1 has 4
- #define TUP_USBIP_CHIPIDEA_HS
- #define TUP_USBIP_EHCI
-
- #define TUP_DCD_ENDPOINT_MAX 6
- #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 FS
-
#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
#define TUP_DCD_ENDPOINT_MAX 5
@@ -78,12 +70,28 @@
// TODO USB0 has 5, USB1 has 6
#define TUP_DCD_ENDPOINT_MAX 6
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
+ // USB0 has 6 with HS PHY, USB1 has 4 only FS
+ #define TUP_USBIP_CHIPIDEA_HS
+ #define TUP_USBIP_EHCI
+
+ #define TUP_DCD_ENDPOINT_MAX 6
+ #define TUP_RHPORT_HIGHSPEED 1
+
+#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
+ // NOTE: MCXN943 port 1 use chipidea HS, port 0 use chipidea FS
+ #define TUP_USBIP_CHIPIDEA_HS
+ #define TUP_USBIP_EHCI
+
+ #define TUP_DCD_ENDPOINT_MAX 8
+ #define TUP_RHPORT_HIGHSPEED 1
+
#elif TU_CHECK_MCU(OPT_MCU_MIMXRT)
#define TUP_USBIP_CHIPIDEA_HS
#define TUP_USBIP_EHCI
#define TUP_DCD_ENDPOINT_MAX 8
- #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 HS
+ #define TUP_RHPORT_HIGHSPEED 1
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
#define TUP_USBIP_CHIPIDEA_FS
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 00419ff05..f82b8633d 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -102,6 +102,22 @@ typedef struct TU_ATTR_ALIGNED(4)
//TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct");
+//--------------------------------------------------------------------+
+// Memory API
+//--------------------------------------------------------------------+
+
+// clean/flush data cache: write cache -> memory.
+// Required before an DMA TX transfer to make sure data is in memory
+void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
+// invalidate data cache: mark cache as invalid, next read will read from memory
+// Required BOTH before and after an DMA RX transfer
+void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
+// clean and invalidate data cache
+// Required before an DMA transfer where memory is both read/write by DMA
+void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 607926a65..ceff893bd 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -46,18 +46,44 @@ static const ci_hs_controller_t _ci_controller[] =
{
// RT1010 and RT1020 only has 1 USB controller
#if FSL_FEATURE_SOC_USBHS_COUNT == 1
- { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+ { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
#else
- { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
- { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+ { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn},
+ { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn}
#endif
};
+#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
+
+//------------- DCD -------------//
#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+//------------- HCD -------------//
#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+//------------- DCache -------------//
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uint32_t addr) {
+ return !(0x20000000 <= addr && addr < 0x20100000);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void* addr, uint32_t data_size) {
+ if (imxrt_is_cache_mem((uint32_t) addr)) {
+ SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
+ }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void* addr, uint32_t data_size) {
+ if (imxrt_is_cache_mem((uint32_t) addr)) {
+ SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+ }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+ if (imxrt_is_cache_mem((uint32_t) addr)) {
+ SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
+ }
+}
#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 8c2e7dfa6..2e84c93e7 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -32,10 +32,12 @@
static const ci_hs_controller_t _ci_controller[] =
{
- { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
- { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+ { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
+ { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
};
+#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
+
#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
diff --git a/src/portable/chipidea/ci_hs/ci_hs_mcx.h b/src/portable/chipidea/ci_hs/ci_hs_mcx.h
new file mode 100644
index 000000000..f940f4a9d
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/ci_hs_mcx.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_HS_MCX_H_
+#define _CI_HS_MCX_H_
+
+#include "fsl_device_registers.h"
+
+// NOTE: MCX N9 has 2 different USB Controller
+// - USB0 is KHCI FullSpeed
+// - USB1 is ChipIdea HighSpeed, therefore rhport = 1 is actually index 0
+
+static const ci_hs_controller_t _ci_controller[] = {
+ {.reg_base = USBHS1__USBC_BASE, .irqnum = USB1_HS_IRQn}
+};
+
+TU_ATTR_ALWAYS_INLINE static inline ci_hs_regs_t* CI_HS_REG(uint8_t port) {
+ (void) port;
+ return ((ci_hs_regs_t*) _ci_controller[0].reg_base);
+}
+
+#define CI_DCD_INT_ENABLE(_p) do { (void) _p; NVIC_EnableIRQ (_ci_controller[0].irqnum); } while (0)
+#define CI_DCD_INT_DISABLE(_p) do { (void) _p; NVIC_DisableIRQ(_ci_controller[0].irqnum); } while (0)
+
+#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 31b5a012d..2f3aa3694 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -31,13 +31,21 @@
extern "C" {
#endif
+// DCCPARAMS
+enum {
+ DCCPARAMS_DEN_MASK = 0x1Fu, ///< DEN bit 4:0
+};
+
// USBCMD
enum {
USBCMD_RUN_STOP = TU_BIT(0),
USBCMD_RESET = TU_BIT(1),
USBCMD_SETUP_TRIPWIRE = TU_BIT(13),
- USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-// Interrupt Threshold bit 23:16
+ USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14), // This bit is used as a semaphore to ensure the to proper addition of a
+ // new dTD to an active (primed) endpoint’s linked list. This bit is set and
+ // cleared by software during the process of adding a new dTD
+
+ USBCMD_INTR_THRESHOLD_MASK = 0x00FF0000u, // Interrupt Threshold bit 23:16
};
// PORTSC1
@@ -72,6 +80,7 @@ enum {
// USBMode
enum {
+ USBMOD_CM_MASK = TU_BIT(0) | TU_BIT(1),
USBMODE_CM_DEVICE = 2,
USBMODE_CM_HOST = 3,
@@ -134,7 +143,6 @@ typedef struct
{
uint32_t reg_base;
uint32_t irqnum;
- uint8_t ep_count; // Max bi-directional Endpoints
}ci_hs_controller_t;
#ifdef __cplusplus
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 9be79a2f1..850c82e43 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -28,35 +28,53 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_HS)
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
#include "device/dcd.h"
#include "ci_hs_type.h"
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
#include "ci_hs_imxrt.h"
-#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
+
+ void dcd_dcache_clean(void* addr, uint32_t data_size) {
+ imxrt_dcache_clean(addr, data_size);
+ }
+
+ void dcd_dcache_invalidate(void* addr, uint32_t data_size) {
+ imxrt_dcache_invalidate(addr, data_size);
+ }
+
+ void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+ imxrt_dcache_clean_invalidate(addr, data_size);
+ }
+
+#else
+
+#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
+ // MCX N9 only port 1 use this controller
+ #include "ci_hs_mcx.h"
#else
#error "Unsupported MCUs"
#endif
+ TU_ATTR_WEAK void dcd_dcache_clean(void* addr, uint32_t data_size) {
+ (void) addr; (void) data_size;
+ }
+
+ TU_ATTR_WEAK void dcd_dcache_invalidate(void* addr, uint32_t data_size) {
+ (void) addr; (void) data_size;
+ }
+
+ TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+ (void) addr; (void) data_size;
+ }
+#endif
+
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
-
-// Clean means to push any cached changes to RAM and invalidate "removes" the
-// entry from the cache.
-#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
- #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
-#else
- #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
-#endif
-
-
// ENDPTCTRL
enum {
ENDPTCTRL_STALL = TU_BIT(0),
@@ -160,6 +178,16 @@ typedef struct {
CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
static dcd_data_t _dcd_data;
+//--------------------------------------------------------------------+
+// Prototypes and Helper Functions
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE
+static inline uint8_t ci_ep_count(ci_hs_regs_t const* dcd_reg)
+{
+ return dcd_reg->DCCPARAMS & DCCPARAMS_DEN_MASK;
+}
+
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
@@ -174,7 +202,8 @@ static void bus_reset(uint8_t rhport)
// endpoint type of the unused direction must be changed from the control type to any other
// type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
// for the data PID tracking on the active endpoint.
- for( uint8_t i=1; i < _ci_controller[rhport].ep_count; i++)
+ uint8_t const ep_count = ci_ep_count(dcd_reg);
+ for( uint8_t i=1; i < ep_count; i++)
{
dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
}
@@ -202,7 +231,7 @@ static void bus_reset(uint8_t rhport)
_dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
- CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+ dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
}
void dcd_init(uint8_t rhport)
@@ -211,26 +240,34 @@ void dcd_init(uint8_t rhport)
ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+ TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX, );
+
// Reset controller
dcd_reg->USBCMD |= USBCMD_RESET;
while( dcd_reg->USBCMD & USBCMD_RESET ) {}
// Set mode to device, must be set immediately after reset
- dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+ uint32_t usbmode = dcd_reg->USBMODE & ~USBMOD_CM_MASK;
+ usbmode |= USBMODE_CM_DEVICE;
+ dcd_reg->USBMODE = usbmode;
+
dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
#if !TUD_OPT_HIGH_SPEED
dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
#endif
- CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+ dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
dcd_reg->USBSTS = dcd_reg->USBSTS;
dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
- dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
- dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
+ uint32_t usbcmd = dcd_reg->USBCMD;
+ usbcmd &= ~USBCMD_INTR_THRESHOLD_MASK; // Interrupt Threshold Interval = 0
+ usbcmd |= USBCMD_RUN_STOP; // run
+
+ dcd_reg->USBCMD = usbcmd;
}
void dcd_int_enable(uint8_t rhport)
@@ -286,7 +323,7 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
{
// Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
// address to 32-byte boundaries. Buffer must be word aligned
- CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
+ dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
tu_memclr(p_qtd, sizeof(dcd_qtd_t));
@@ -343,8 +380,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+ ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+
// Must not exceed max endpoint number
- TU_ASSERT( epnum < _ci_controller[rhport].ep_count );
+ TU_ASSERT(epnum < ci_ep_count(dcd_reg));
//------------- Prepare Queue Head -------------//
dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
@@ -359,11 +398,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
- CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+ dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
// Enable EP Control
- ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
-
uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
if ( dir == TUSB_DIR_OUT )
@@ -382,7 +419,8 @@ void dcd_edpt_close_all (uint8_t rhport)
ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
// Disable all non-control endpoints
- for( uint8_t epnum=1; epnum < _ci_controller[rhport].ep_count; epnum++)
+ uint8_t const ep_count = ci_ep_count(dcd_reg);
+ for (uint8_t epnum = 1; epnum < ep_count; epnum++)
{
_dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
_dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
@@ -420,7 +458,7 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
// flush cache
- CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+ dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
if ( epnum == 0 )
{
@@ -498,7 +536,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
}
}
- CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
+ dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
}
else
{
@@ -611,7 +649,7 @@ void dcd_int_handler(uint8_t rhport)
if (int_status & INTR_USB)
{
// Make sure we read the latest version of _dcd_data.
- CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+ dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index ab6a42e11..8c27abbf6 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -42,28 +42,17 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
#include "ci_hs_imxrt.h"
- // check if memory is cacheable i.e not in DTCM
- TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) {
- return !(0x20000000 <= addr && addr < 0x20100000);
- }
-
void hcd_dcache_clean(void* addr, uint32_t data_size) {
- if (is_cache_mem((uint32_t) addr)) {
- SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
- }
+ imxrt_dcache_clean(addr, data_size);
}
void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
- if (is_cache_mem((uint32_t) addr)) {
- SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
- }
+ imxrt_dcache_invalidate(addr, data_size);
}
-void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
- if (is_cache_mem((uint32_t) addr)) {
- SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
+ void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+ imxrt_dcache_clean_invalidate(addr, data_size);
}
-}
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h"
@@ -75,8 +64,6 @@ void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
-
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 852e7f4fe..2b25eee9d 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -163,22 +163,15 @@ static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t
static inline ehci_link_t* list_next (ehci_link_t const *p_link);
TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) {
- (void) addr;
- (void) data_size;
+ (void) addr; (void) data_size;
}
-// invalidate data cache: mark cache as invalid, next read will read from memory
-// Required BOTH before and after an DMA RX transfer
TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
- (void) addr;
- (void) data_size;
+ (void) addr; (void) data_size;
}
-// clean and invalidate data cache
-// Required before an DMA transfer where memory is both read/write by DMA
TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
- (void) addr;
- (void) data_size;
+ (void) addr; (void) data_size;
}
//--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 4f3f3a985..948c9edf3 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -166,6 +166,10 @@
// WCH
#define OPT_MCU_CH32V307 2200 ///< WCH CH32V307
+
+// NXP LPC MCX
+#define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series
+
// Helper to check if configured MCU is one of listed
// Apply _TU_CHECK_MCU with || as separator to list of input
#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m)
@@ -274,7 +278,7 @@
// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
// to generate unaligned access code.
// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
-#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+#if TUD_OPT_HIGH_SPEED && TU_CHECK_MCU(OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX)
#define TUP_MCU_STRICT_ALIGN 1
#else
#define TUP_MCU_STRICT_ALIGN 0
diff --git a/tools/cmake/cpu/cortex-m3.cmake b/tools/cmake/cpu/cortex-m3.cmake
new file mode 100644
index 000000000..b740ee44c
--- /dev/null
+++ b/tools/cmake/cpu/cortex-m3.cmake
@@ -0,0 +1,10 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ list(APPEND TOOLCHAIN_COMMON_FLAGS
+ -mthumb
+ -mcpu=cortex-m3
+ )
+
+ set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "")
+else ()
+ # TODO support IAR
+endif ()
diff --git a/tools/cmake/cpu/cortex-m33.cmake b/tools/cmake/cpu/cortex-m33.cmake
index fbd5027b1..26c91a64f 100644
--- a/tools/cmake/cpu/cortex-m33.cmake
+++ b/tools/cmake/cpu/cortex-m33.cmake
@@ -3,10 +3,11 @@ if (TOOLCHAIN STREQUAL "gcc")
-mthumb
-mcpu=cortex-m33
-mfloat-abi=hard
- -mfpu=fpv5-d16
+ #-mfpu=fpv5-d16
+ -mfpu=fpv5-sp-d16
)
- set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
+ set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
else ()
# TODO support IAR
endif ()
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
index c7b6cff98..5f25d637b 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/tools/cmake/toolchain/arm_gcc.cmake
@@ -3,6 +3,8 @@ set(CMAKE_SYSTEM_NAME Generic)
set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
+
+set(TOOLCHAIN_SIZE "arm-none-eabi-size" CACHE INTERNAL "")
set(GCC_ELF2BIN "arm-none-eabi-objcopy")
set_property(GLOBAL PROPERTY ELF2BIN ${GCC_ELF2BIN})
diff --git a/tools/get_deps.py b/tools/get_deps.py
index be5738dc1..f499562cb 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -24,7 +24,7 @@ deps_optional = {
'hw/mcu/nordic/nrfx' : ['2527e3c8449cfd38aee41598e8af8492f410ed15', 'https://github.com/NordicSemiconductor/nrfx.git' ],
'hw/mcu/nuvoton' : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git' ],
'hw/mcu/nxp/lpcopen' : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git' ],
- 'hw/mcu/nxp/mcux-sdk' : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git' ],
+ 'hw/mcu/nxp/mcux-sdk' : ['950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'https://github.com/hathach/mcux-sdk.git' ],
'hw/mcu/nxp/nxp_sdk' : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git' ],
'hw/mcu/raspberry_pi/Pico-PIO-USB' : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git' ],
'hw/mcu/renesas/fsp' : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git' ],
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
index 2ea3a0753..3d12b01fd 100644
--- a/tools/make/cpu/cortex-m33.mk
+++ b/tools/make/cpu/cortex-m33.mk
@@ -3,7 +3,9 @@ ifeq ($(TOOLCHAIN),gcc)
-mthumb \
-mcpu=cortex-m33 \
-mfloat-abi=hard \
- -mfpu=fpv5-d16 \
+ -mfpu=fpv5-sp-d16 \
+
+ #-mfpu=fpv5-d16 \
#set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure