diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 6ac7ad015..8a91ee630 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -73,7 +73,7 @@ jobs:
run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
- run: python3 tools/build_family.py ${{ matrix.family }}
+ run: python3 tools/build_make.py ${{ matrix.family }}
- name: Linker Map
run: |
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 171c1fec3..402b89e0a 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -66,7 +66,7 @@ jobs:
run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
- run: python3 tools/build_family.py ${{ matrix.family }}
+ run: python3 tools/build_make.py ${{ matrix.family }}
- name: Linker Map
run: |
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index c62056940..60c5feef3 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -71,7 +71,7 @@ jobs:
run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
- run: python3 tools/build_family.py ${{ matrix.family }}
+ run: python3 tools/build_make.py ${{ matrix.family }}
- name: Linker Map
run: |
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 66b98a71b..1cc4f8132 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -71,7 +71,7 @@ jobs:
run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
- run: python3 tools/build_family.py ${{ matrix.family }}
+ run: python3 tools/build_make.py ${{ matrix.family }}
- name: Linker Map
run: |
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 8ec549072..dfc6b672f 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -72,7 +72,7 @@ jobs:
run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
- run: python3 tools/build_family.py ${{ matrix.family }}
+ run: python3 tools/build_make.py ${{ matrix.family }}
- name: Linker Map
run: |
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index cb879a705..f6a42cf0a 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -51,4 +51,4 @@ jobs:
run: python3 tools/get_deps.py stm32f4
- name: Build
- run: python3 tools/build_family.py stm32f4 stm32f411disco
+ run: python3 tools/build_make.py stm32f4 stm32f411disco
diff --git a/.gitignore b/.gitignore
index c665d6c73..e6ccec736 100644
--- a/.gitignore
+++ b/.gitignore
@@ -81,6 +81,7 @@ hw/mcu/st/stm32u5xx_hal_driver
hw/mcu/st/stm32wbxx_hal_driver
hw/mcu/ti
hw/mcu/wch/ch32v307
+hw/mcu/wch/ch32f20x
lib/CMSIS_5
lib/FreeRTOS-Kernel
lib/lwip
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 97e503033..101f08078 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -63,7 +63,7 @@
-
+
diff --git a/README.rst b/README.rst
index bb1555a1a..f400c3ec6 100644
--- a/README.rst
+++ b/README.rst
@@ -143,7 +143,7 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l
+--------------+------------------------------------------------------------+
| ValentyUSB | eptri |
+--------------+------------------------------------------------------------+
-| WCH | CH32V307 |
+| WCH | CH32F20x, CH32V307, |
+--------------+------------------------------------------------------------+
Docs
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index 130527e2c..d532a3a1e 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -56,6 +56,7 @@ hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/
hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8
hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5
hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 17761f5cf9dbbf2dcf665b7c04934188add20082
+hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.git 77c4095087e5ed2c548ec9058e655d0b8757663b
lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 20285262657d1b482d132d20d755c8c330d55c1f
lib/FreeRTOS-Kernel https://github.com/FreeRTOS/FreeRTOS-Kernel.git def7d2df2b0506d3d249334974f51e427c17a41c
lib/lwip https://github.com/lwip-tcpip/lwip.git 159e31b689577dbf69cf0683bbaffbd71fa5ee10
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 76b1d993e..983640dd3 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -129,6 +129,8 @@ Supported MCUs
| ValentyUSB | eptri | ✔ | ✖ | ✖ | eptri | |
+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
| WCH | CH32V307 | ✔ | | ✔ | ch32v307 | |
+| +-----------------------+--------+------+-----------+-------------------+--------------+
+| | CH32F20x | ✔ | | ✔ | ch32f205 | |
+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
@@ -435,4 +437,5 @@ Tomu
WCH
---
-- `CH32V307V-R1-1v0 `
+- `CH32V307V-R1-1v0 `__
+- `CH32F205R-R0-1v0 `__
diff --git a/tools/cmake/cpu/cortex-m0.cmake b/examples/build_system/cmake/cpu/cortex-m0.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m0.cmake
rename to examples/build_system/cmake/cpu/cortex-m0.cmake
diff --git a/tools/cmake/cpu/cortex-m0plus.cmake b/examples/build_system/cmake/cpu/cortex-m0plus.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m0plus.cmake
rename to examples/build_system/cmake/cpu/cortex-m0plus.cmake
diff --git a/tools/cmake/cpu/cortex-m23.cmake b/examples/build_system/cmake/cpu/cortex-m23.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m23.cmake
rename to examples/build_system/cmake/cpu/cortex-m23.cmake
diff --git a/tools/cmake/cpu/cortex-m3.cmake b/examples/build_system/cmake/cpu/cortex-m3.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m3.cmake
rename to examples/build_system/cmake/cpu/cortex-m3.cmake
diff --git a/tools/cmake/cpu/cortex-m33.cmake b/examples/build_system/cmake/cpu/cortex-m33.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m33.cmake
rename to examples/build_system/cmake/cpu/cortex-m33.cmake
diff --git a/tools/cmake/cpu/cortex-m4.cmake b/examples/build_system/cmake/cpu/cortex-m4.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m4.cmake
rename to examples/build_system/cmake/cpu/cortex-m4.cmake
diff --git a/tools/cmake/cpu/cortex-m7.cmake b/examples/build_system/cmake/cpu/cortex-m7.cmake
similarity index 100%
rename from tools/cmake/cpu/cortex-m7.cmake
rename to examples/build_system/cmake/cpu/cortex-m7.cmake
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake
similarity index 97%
rename from tools/cmake/toolchain/arm_gcc.cmake
rename to examples/build_system/cmake/toolchain/arm_gcc.cmake
index cefa9d2ce..7680d75ab 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake
@@ -29,7 +29,7 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS
-fno-strict-aliasing
)
-set(TOOLCHAIN_EXE_LINKER_FLAGS
+list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
-Wl,--print-memory-usage
-Wl,--gc-sections
-Wl,--cref
diff --git a/tools/cmake/toolchain/arm_iar.cmake b/examples/build_system/cmake/toolchain/arm_iar.cmake
similarity index 100%
rename from tools/cmake/toolchain/arm_iar.cmake
rename to examples/build_system/cmake/toolchain/arm_iar.cmake
diff --git a/tools/cmake/toolchain/set_flags.cmake b/examples/build_system/cmake/toolchain/set_flags.cmake
similarity index 100%
rename from tools/cmake/toolchain/set_flags.cmake
rename to examples/build_system/cmake/toolchain/set_flags.cmake
diff --git a/tools/make/cpu/arm1176.mk b/examples/build_system/make/cpu/arm1176.mk
similarity index 100%
rename from tools/make/cpu/arm1176.mk
rename to examples/build_system/make/cpu/arm1176.mk
diff --git a/tools/make/cpu/cortex-a53.mk b/examples/build_system/make/cpu/cortex-a53.mk
similarity index 100%
rename from tools/make/cpu/cortex-a53.mk
rename to examples/build_system/make/cpu/cortex-a53.mk
diff --git a/tools/make/cpu/cortex-a72.mk b/examples/build_system/make/cpu/cortex-a72.mk
similarity index 100%
rename from tools/make/cpu/cortex-a72.mk
rename to examples/build_system/make/cpu/cortex-a72.mk
diff --git a/tools/make/cpu/cortex-m0.mk b/examples/build_system/make/cpu/cortex-m0.mk
similarity index 100%
rename from tools/make/cpu/cortex-m0.mk
rename to examples/build_system/make/cpu/cortex-m0.mk
diff --git a/tools/make/cpu/cortex-m0plus.mk b/examples/build_system/make/cpu/cortex-m0plus.mk
similarity index 100%
rename from tools/make/cpu/cortex-m0plus.mk
rename to examples/build_system/make/cpu/cortex-m0plus.mk
diff --git a/examples/build_system/make/cpu/cortex-m23.mk b/examples/build_system/make/cpu/cortex-m23.mk
new file mode 100644
index 000000000..29542d8e8
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m23.mk
@@ -0,0 +1,14 @@
+ifeq ($(TOOLCHAIN),gcc)
+ CFLAGS += \
+ -mthumb \
+ -mcpu=cortex-m23 \
+ -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),iar)
+ # IAR Flags
+ CFLAGS += --cpu cortex-m23
+ ASFLAGS += --cpu cortex-m23
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM23
diff --git a/tools/make/cpu/cortex-m3.mk b/examples/build_system/make/cpu/cortex-m3.mk
similarity index 100%
rename from tools/make/cpu/cortex-m3.mk
rename to examples/build_system/make/cpu/cortex-m3.mk
diff --git a/tools/make/cpu/cortex-m33.mk b/examples/build_system/make/cpu/cortex-m33.mk
similarity index 100%
rename from tools/make/cpu/cortex-m33.mk
rename to examples/build_system/make/cpu/cortex-m33.mk
diff --git a/tools/make/cpu/cortex-m4.mk b/examples/build_system/make/cpu/cortex-m4.mk
similarity index 100%
rename from tools/make/cpu/cortex-m4.mk
rename to examples/build_system/make/cpu/cortex-m4.mk
diff --git a/tools/make/cpu/cortex-m7.mk b/examples/build_system/make/cpu/cortex-m7.mk
similarity index 100%
rename from tools/make/cpu/cortex-m7.mk
rename to examples/build_system/make/cpu/cortex-m7.mk
diff --git a/examples/make.mk b/examples/build_system/make/make.mk
similarity index 89%
rename from examples/make.mk
rename to examples/build_system/make/make.mk
index 448d7883d..e1113aa52 100644
--- a/examples/make.mk
+++ b/examples/build_system/make/make.mk
@@ -2,19 +2,15 @@
# Common make definition for all examples
# ---------------------------------------
-# Supported toolchain: gcc, iar
-TOOLCHAIN ?= gcc
-
#-------------- TOP and CURRENT_PATH ------------
-# Set TOP to be the path to get from the current directory (where make was
-# invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
-# the name of this makefile relative to where make was invoked.
+# Set TOP to be the path to get from the current directory (where make was invoked) to the top of the tree.
+# $(lastword $(MAKEFILE_LIST)) returns the name of this makefile relative to where make was invoked.
THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
-# strip off /tools/top.mk to get for example ../../..
+# strip off /examples/build_system/make to get for example ../../..
# and Set TOP to an absolute path
-TOP = $(abspath $(subst make.mk,..,$(THIS_MAKEFILE)))
+TOP = $(abspath $(subst make.mk,../../..,$(THIS_MAKEFILE)))
# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
@@ -38,7 +34,6 @@ __check_defined = \
$(if $(value $1),, \
$(error Undefined make flag: $1$(if $2, ($2))))
-
# Build directory
BUILD := _build/$(BOARD)
@@ -73,7 +68,10 @@ else
SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
endif
-#-------------- Cross Compiler ------------
+#-------------- Toolchain ------------
+
+# Supported toolchain: gcc, iar
+TOOLCHAIN ?= gcc
# Can be set by board, default to ARM GCC
CROSS_COMPILE ?= arm-none-eabi-
@@ -139,8 +137,8 @@ endif
# CPU specific flags
ifdef CPU_CORE
-include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+ include ${TOP}/examples/build_system/make/cpu/$(CPU_CORE).mk
endif
# toolchain specific
-include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN).mk
+include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk
diff --git a/examples/rules.mk b/examples/build_system/make/rules.mk
similarity index 98%
rename from examples/rules.mk
rename to examples/build_system/make/rules.mk
index 227849a18..b02665cdd 100644
--- a/examples/rules.mk
+++ b/examples/build_system/make/rules.mk
@@ -37,7 +37,7 @@ vpath %.c . $(TOP)
vpath %.s . $(TOP)
vpath %.S . $(TOP)
-include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN)_rules.mk
+include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN)_rules.mk
OBJ_DIRS = $(sort $(dir $(OBJ)))
diff --git a/tools/make/toolchain/arm_gcc.mk b/examples/build_system/make/toolchain/arm_gcc.mk
similarity index 83%
rename from tools/make/toolchain/arm_gcc.mk
rename to examples/build_system/make/toolchain/arm_gcc.mk
index bba0607df..b87657f53 100644
--- a/tools/make/toolchain/arm_gcc.mk
+++ b/examples/build_system/make/toolchain/arm_gcc.mk
@@ -9,6 +9,9 @@ GDB = $(CROSS_COMPILE)gdb
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
+CC_VERSION := $(shell $(CC) -dumpversion)
+CC_VERSION_MAJOR = $(firstword $(subst ., ,$(CC_VERSION)))
+
# ---------------------------------------
# Compiler Flags
# ---------------------------------------
@@ -65,7 +68,12 @@ LDFLAGS += \
-Wl,-cref \
-Wl,-gc-sections \
-# Some toolchain such as renesas rx does not support --print-memory-usage flags
+# renesas rx does not support --print-memory-usage flags
ifneq ($(FAMILY),rx)
LDFLAGS += -Wl,--print-memory-usage
endif
+
+# from version 12
+ifeq ($(shell expr $(CC_VERSION_MAJOR) \>= 12),1)
+LDFLAGS += -Wl,--no-warn-rwx-segment
+endif
diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/examples/build_system/make/toolchain/arm_gcc_rules.mk
similarity index 95%
rename from tools/make/toolchain/arm_gcc_rules.mk
rename to examples/build_system/make/toolchain/arm_gcc_rules.mk
index b76d4aec3..d295879d9 100644
--- a/tools/make/toolchain/arm_gcc_rules.mk
+++ b/examples/build_system/make/toolchain/arm_gcc_rules.mk
@@ -31,10 +31,6 @@ ifdef LD_FILE_GCC
LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE_GCC)
endif
-ifneq ($(SKIP_NANOLIB), 1)
-LDFLAGS += --specs=nosys.specs --specs=nano.specs
-endif
-
ASFLAGS += $(CFLAGS)
LIBS_GCC ?= -lgcc -lm -lnosys
diff --git a/tools/make/toolchain/arm_iar.mk b/examples/build_system/make/toolchain/arm_iar.mk
similarity index 100%
rename from tools/make/toolchain/arm_iar.mk
rename to examples/build_system/make/toolchain/arm_iar.mk
diff --git a/tools/make/toolchain/arm_iar_rules.mk b/examples/build_system/make/toolchain/arm_iar_rules.mk
similarity index 100%
rename from tools/make/toolchain/arm_iar_rules.mk
rename to examples/build_system/make/toolchain/arm_iar_rules.mk
diff --git a/examples/device/audio_4_channel_mic/Makefile b/examples/device/audio_4_channel_mic/Makefile
index 8ee6a01ec..2c825bbf7 100644
--- a/examples/device/audio_4_channel_mic/Makefile
+++ b/examples/device/audio_4_channel_mic/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -11,4 +11,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_test/Makefile b/examples/device/audio_test/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/audio_test/Makefile
+++ b/examples/device/audio_test/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_test_multi_rate/Makefile b/examples/device/audio_test_multi_rate/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/audio_test_multi_rate/Makefile
+++ b/examples/device/audio_test_multi_rate/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/board_test/Makefile b/examples/device/board_test/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/board_test/Makefile
+++ b/examples/device/board_test/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_dual_ports/Makefile b/examples/device/cdc_dual_ports/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/cdc_dual_ports/Makefile
+++ b/examples/device/cdc_dual_ports/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_msc/Makefile b/examples/device/cdc_msc/Makefile
index 429959e70..0c2e37180 100644
--- a/examples/device/cdc_msc/Makefile
+++ b/examples/device/cdc_msc/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -12,4 +12,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 84c833fb5..13f336f99 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
FREERTOS_SRC = lib/FreeRTOS-Kernel
FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
@@ -43,4 +43,4 @@ CFLAGS_GCC += -Wno-error=cast-qual
# FreeRTOS (lto + Os) linker issue
LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_uac2/Makefile b/examples/device/cdc_uac2/Makefile
index b7a8302ce..21dcdb0b2 100644
--- a/examples/device/cdc_uac2/Makefile
+++ b/examples/device/cdc_uac2/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -13,4 +13,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/dfu/Makefile b/examples/device/dfu/Makefile
index b3f2cc588..52a24cdb0 100644
--- a/examples/device/dfu/Makefile
+++ b/examples/device/dfu/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -11,4 +11,4 @@ EXAMPLE_SOURCE = \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/dfu_runtime/Makefile b/examples/device/dfu_runtime/Makefile
index da088ea6b..1b4d398cf 100644
--- a/examples/device/dfu_runtime/Makefile
+++ b/examples/device/dfu_runtime/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/dynamic_configuration/Makefile b/examples/device/dynamic_configuration/Makefile
index da088ea6b..1b4d398cf 100644
--- a/examples/device/dynamic_configuration/Makefile
+++ b/examples/device/dynamic_configuration/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
index b3f2cc588..52a24cdb0 100644
--- a/examples/device/hid_boot_interface/Makefile
+++ b/examples/device/hid_boot_interface/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -11,4 +11,4 @@ EXAMPLE_SOURCE = \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_composite/Makefile b/examples/device/hid_composite/Makefile
index da088ea6b..1b4d398cf 100644
--- a/examples/device/hid_composite/Makefile
+++ b/examples/device/hid_composite/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index a892e7d1d..add9e9814 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -1,6 +1,6 @@
DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-include ../../make.mk
+include ../../build_system/make/make.mk
FREERTOS_SRC = lib/FreeRTOS-Kernel
FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
@@ -44,4 +44,4 @@ CFLAGS_GCC += -Wno-error=cast-qual
# FreeRTOS (lto + Os) linker issue
LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_generic_inout/Makefile b/examples/device/hid_generic_inout/Makefile
index da088ea6b..1b4d398cf 100644
--- a/examples/device/hid_generic_inout/Makefile
+++ b/examples/device/hid_generic_inout/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_multiple_interface/Makefile b/examples/device/hid_multiple_interface/Makefile
index da088ea6b..1b4d398cf 100644
--- a/examples/device/hid_multiple_interface/Makefile
+++ b/examples/device/hid_multiple_interface/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/midi_test/Makefile b/examples/device/midi_test/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/midi_test/Makefile
+++ b/examples/device/midi_test/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/msc_dual_lun/Makefile b/examples/device/msc_dual_lun/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/msc_dual_lun/Makefile
+++ b/examples/device/msc_dual_lun/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index 90b429d00..22426ba0d 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -1,6 +1,6 @@
DEPS_SUBMODULES += lib/lwip
-include ../../make.mk
+include ../../build_system/make/make.mk
# suppress warning caused by lwip
CFLAGS_GCC += \
@@ -67,4 +67,4 @@ SRC_C += \
lib/networking/dnserver.c \
lib/networking/rndis_reports.c
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/uac2_headset/Makefile b/examples/device/uac2_headset/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/uac2_headset/Makefile
+++ b/examples/device/uac2_headset/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/usbtmc/Makefile b/examples/device/usbtmc/Makefile
index da088ea6b..1b4d398cf 100644
--- a/examples/device/usbtmc/Makefile
+++ b/examples/device/usbtmc/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
index 90d174c32..d698a848d 100644
--- a/examples/device/video_capture/Makefile
+++ b/examples/device/video_capture/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
ifeq ($(DISABLE_MJPEG),1)
CFLAGS += -DCFG_EXAMPLE_VIDEO_DISABLE_MJPEG
@@ -15,4 +15,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/webusb_serial/Makefile b/examples/device/webusb_serial/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/device/webusb_serial/Makefile
+++ b/examples/device/webusb_serial/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/dual/host_hid_to_device_cdc/Makefile b/examples/dual/host_hid_to_device_cdc/Makefile
index 95c88e7e8..2c2168f5d 100644
--- a/examples/dual/host_hid_to_device_cdc/Makefile
+++ b/examples/dual/host_hid_to_device_cdc/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -15,4 +15,4 @@ SRC_C += \
src/host/hub.c \
src/host/usbh.c
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 161f8c774..0235e08c3 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -10,4 +10,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 15b8a5b31..213c02f9c 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -13,4 +13,4 @@ EXAMPLE_SOURCE = \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
index a9670b4f2..5351a6248 100644
--- a/examples/host/cdc_msc_hid_freertos/Makefile
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
FREERTOS_SRC = lib/FreeRTOS-Kernel
FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
@@ -31,4 +31,4 @@ SRC_C += \
SRC_S += \
$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index e7f603f25..1377f1f90 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -11,4 +11,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index 8319d3c2b..c7d6a7cae 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
FATFS_PATH = lib/fatfs/source
@@ -24,4 +24,4 @@ SRC_C += \
# suppress warning caused by fatfs
CFLAGS += -Wno-error=cast-qual
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/typec/power_delivery/Makefile b/examples/typec/power_delivery/Makefile
index 2a3d854fb..7fa475da5 100644
--- a/examples/typec/power_delivery/Makefile
+++ b/examples/typec/power_delivery/Makefile
@@ -1,4 +1,4 @@
-include ../../make.mk
+include ../../build_system/make/make.mk
INC += \
src \
@@ -8,4 +8,4 @@ INC += \
EXAMPLE_SOURCE += $(wildcard src/*.c)
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 562792625..23b4b6628 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -44,13 +44,12 @@
// If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
#if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
-
#include "SEGGER_RTT.h"
-TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) {
+TU_ATTR_USED int sys_write(int fhdl, const char *buf, size_t count) {
(void) fhdl;
SEGGER_RTT_Write(0, (const char *) buf, (int) count);
- return count;
+ return (int) count;
}
TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
@@ -63,10 +62,9 @@ TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
#elif defined(LOGGER_SWO)
// Logging with SWO for ARM Cortex
-
#include "board_mcu.h"
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
+TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) {
(void) fhdl;
uint8_t const* buf8 = (uint8_t const*) buf;
@@ -87,7 +85,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
#else
// Default logging with on-board UART
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
+TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) {
(void) fhdl;
return board_uart_write(buf, (int) count);
}
@@ -100,6 +98,16 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
#endif
+//TU_ATTR_USED int _close(int fhdl) {
+// (void) fhdl;
+// return 0;
+//}
+
+//TU_ATTR_USED int _fstat(int file, struct stat *st) {
+// memset(st, 0, sizeof(*st));
+// st->st_mode = S_IFCHR;
+//}
+
int board_getchar(void) {
char c;
return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index e5d2bb608..4ce5c4139 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -161,6 +161,9 @@
#elif CFG_TUSB_MCU == OPT_MCU_TM4C123
#include "TM4C123.h"
+#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X
+ #include "ch32f20x.h"
+
#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
// no header needed
diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
new file mode 100644
index 000000000..d5849bddb
--- /dev/null
+++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
@@ -0,0 +1,59 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED: need to wire pin LED1 to PC0 in the P1 header
+#define LED_PORT GPIOC
+#define LED_PIN GPIO_Pin_1
+#define LED_STATE_ON 0
+#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// Button: need to wire pin KEY to PC1 in the P1 header
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_Pin_0
+#define BUTTON_STATE_ACTIVE 0
+#define BUTTON_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// UART
+#define UART_DEV USART2
+#define UART_DEV_IRQn USART2_IRQn
+#define UART_DEV_IRQHandler USART2_IRQHandler
+#define UART_DEV_GPIO_PORT GPIOA
+#define UART_DEV_TX_PIN GPIO_Pin_2
+#define UART_DEV_CLK_EN() do { \
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); \
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); \
+ } while(0)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
new file mode 100644
index 000000000..f0e9bf30f
--- /dev/null
+++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
@@ -0,0 +1,7 @@
+LD_FILE = $(FAMILY_PATH)/ch32f205.ld
+
+SRC_S += \
+ $(FAMILY_PATH)/startup_gcc_ch32f20x_d8c.s
+
+CFLAGS += \
+ -DCH32F20x_D8C
diff --git a/hw/bsp/ch32f20x/ch32f205.ld b/hw/bsp/ch32f20x/ch32f205.ld
new file mode 100644
index 000000000..7c8d04cc5
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f205.ld
@@ -0,0 +1,111 @@
+ENTRY(Reset_Handler)
+
+_Min_Heap_Size = 0x200;
+_Min_Stack_Size = 0x400;
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+SECTIONS
+{
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector))
+ . = ALIGN(4);
+ } >FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ *(.text)
+ *(.text*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ _etext = .;
+ } >FLASH
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } >FLASH
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+ _sidata = LOADADDR(.data);
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM AT> FLASH
+ . = ALIGN(4);
+ .bss :
+ {
+ _sbss = .;
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ __bss_end__ = _ebss;
+ } >RAM
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ __HeapStart = .;
+ . = . + _Min_Heap_Size;
+ __HeapEnd = .;
+ __StackLimit = .;
+ . = . + _Min_Stack_Size;
+ __StackTop = .;
+ . = ALIGN(4);
+ } >RAM
+_estack = __StackTop;
+_sstack = __StackLimit;
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/ch32f20x/ch32f20x_conf.h b/hw/bsp/ch32f20x/ch32f20x_conf.h
new file mode 100644
index 000000000..05199ff95
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_conf.h
@@ -0,0 +1,39 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32f20x_conf.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/08/08
+ * Description : Library configuration file.
+ *********************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
+ *******************************************************************************/
+#ifndef __CH32F20x_CONF_H
+#define __CH32F20x_CONF_H
+
+#include "ch32f20x_adc.h"
+#include "ch32f20x_bkp.h"
+#include "ch32f20x_can.h"
+#include "ch32f20x_crc.h"
+#include "ch32f20x_dac.h"
+#include "ch32f20x_dbgmcu.h"
+#include "ch32f20x_dma.h"
+#include "ch32f20x_exti.h"
+#include "ch32f20x_flash.h"
+#include "ch32f20x_fsmc.h"
+#include "ch32f20x_gpio.h"
+#include "ch32f20x_i2c.h"
+#include "ch32f20x_iwdg.h"
+#include "ch32f20x_pwr.h"
+#include "ch32f20x_rcc.h"
+#include "ch32f20x_rtc.h"
+#include "ch32f20x_sdio.h"
+#include "ch32f20x_spi.h"
+#include "ch32f20x_tim.h"
+#include "ch32f20x_usart.h"
+#include "ch32f20x_wwdg.h"
+#include "ch32f20x_it.h"
+#include "ch32f20x_misc.h"
+
+#endif /* __CH32F20x_CONF_H */
diff --git a/hw/bsp/ch32f20x/ch32f20x_it.c b/hw/bsp/ch32f20x/ch32f20x_it.c
new file mode 100644
index 000000000..94e28e380
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_it.c
@@ -0,0 +1,35 @@
+#include "ch32f20x_it.h"
+
+#include "ch32f20x.h"
+
+/* -------------------------------------------------------------------------- */
+
+void NMI_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void MemManage_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void BusFault_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void UsageFault_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void DebugMon_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
diff --git a/hw/bsp/ch32f20x/ch32f20x_it.h b/hw/bsp/ch32f20x/ch32f20x_it.h
new file mode 100644
index 000000000..34f3bbf96
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_it.h
@@ -0,0 +1,25 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name : ch32f20x_it.h
+* Author : WCH
+* Version : V1.0.0
+* Date : 2021/08/08
+* Description : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32F20xIT_H
+#define __CH32F20xIT_H
+
+#include "ch32f20x.h"
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+
+
+#endif /* __CH32F20xIT_H */
diff --git a/hw/bsp/ch32f20x/core_cm3.h b/hw/bsp/ch32f20x/core_cm3.h
new file mode 100644
index 000000000..c35a4eec3
--- /dev/null
+++ b/hw/bsp/ch32f20x/core_cm3.h
@@ -0,0 +1,11 @@
+/* There is core_cm3.h wrapper just to avoid warnings from CMSIS headers */
+/* if you want use original file add to make file:
+ INC += \
+ $(TOP)/$(CH32F20X_SDK_SRC)/CMSIS
+*/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+
+#include <../../CMSIS/core_cm3.h>
+
+#pragma GCC diagnostic pop
diff --git a/hw/bsp/ch32f20x/debug_uart.c b/hw/bsp/ch32f20x/debug_uart.c
new file mode 100644
index 000000000..a595eb6f7
--- /dev/null
+++ b/hw/bsp/ch32f20x/debug_uart.c
@@ -0,0 +1,105 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#include
+
+#include "board.h"
+#include "debug_uart.h"
+
+#define UART_RINGBUFFER_SIZE_TX 64
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
+
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
+static unsigned int tx_produce = 0;
+static volatile unsigned int tx_consume = 0;
+
+void UART_DEV_IRQHandler(void)
+{
+ if(USART_GetITStatus(UART_DEV, USART_IT_TC) != RESET) {
+ USART_ClearITPendingBit(UART_DEV, USART_IT_TC);
+
+ if(tx_consume != tx_produce) {
+ USART_SendData(UART_DEV, tx_buf[tx_consume]);
+ tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
+ }
+ }
+}
+
+void uart_write(char c)
+{
+ unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
+
+ NVIC_DisableIRQ(UART_DEV_IRQn);
+ if((tx_consume != tx_produce) || (USART_GetFlagStatus(UART_DEV, USART_FLAG_TXE) == RESET)) {
+ tx_buf[tx_produce] = c;
+ tx_produce = tx_produce_next;
+ } else {
+ USART_SendData(UART_DEV, c);
+ }
+ NVIC_EnableIRQ(UART_DEV_IRQn);
+}
+
+void uart_sync(void)
+{
+ while(tx_consume != tx_produce) {
+ //Waiting for transfer complete
+ }
+}
+
+void usart_printf_init(uint32_t baudrate)
+{
+ tx_produce = 0;
+ tx_consume = 0;
+
+ UART_DEV_CLK_EN();
+
+ GPIO_InitTypeDef gpio_config = {
+ .GPIO_Pin = UART_DEV_TX_PIN,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ .GPIO_Mode = GPIO_Mode_AF_PP,
+ };
+ GPIO_Init(UART_DEV_GPIO_PORT, &gpio_config);
+
+ USART_InitTypeDef uart_config = {
+ .USART_BaudRate = baudrate,
+ .USART_WordLength = USART_WordLength_8b,
+ .USART_StopBits = USART_StopBits_1,
+ .USART_Parity = USART_Parity_No,
+ .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+ .USART_Mode = USART_Mode_Tx,
+ };
+
+ USART_Init(UART_DEV, &uart_config);
+ USART_ITConfig(UART_DEV, USART_IT_TC, ENABLE);
+ USART_Cmd(UART_DEV, ENABLE);
+
+ NVIC_InitTypeDef nvic_config = {
+ .NVIC_IRQChannel = UART_DEV_IRQn,
+ .NVIC_IRQChannelPreemptionPriority = 1,
+ .NVIC_IRQChannelSubPriority = 3,
+ .NVIC_IRQChannelCmd = ENABLE,
+ };
+ NVIC_Init(&nvic_config);
+}
diff --git a/hw/bsp/ch32f20x/debug_uart.h b/hw/bsp/ch32f20x/debug_uart.h
new file mode 100644
index 000000000..10284cf6f
--- /dev/null
+++ b/hw/bsp/ch32f20x/debug_uart.h
@@ -0,0 +1,31 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include
+
+void uart_write(char c);
+void uart_sync(void);
+void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c
new file mode 100644
index 000000000..9717832d6
--- /dev/null
+++ b/hw/bsp/ch32f20x/family.c
@@ -0,0 +1,141 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stdio.h"
+#include "debug_uart.h"
+
+#include "ch32f20x.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+void USBHS_IRQHandler(void)
+{
+ tud_int_handler(0);
+}
+
+void board_init(void) {
+
+ /* Disable interrupts during init */
+ __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+ SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USBHS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+ usart_printf_init(115200);
+
+ // USB HS Clock config
+ RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+ RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+ RCC_USBHSConfig(RCC_USBPLL_Div2);
+ RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+ RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+
+ // LED
+ LED_CLOCK_EN();
+ GPIO_InitTypeDef led_pin_config = {
+ .GPIO_Pin = LED_PIN,
+ .GPIO_Mode = GPIO_Mode_Out_OD,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ };
+ GPIO_Init(LED_PORT, &led_pin_config);
+
+ // Button
+ BUTTON_CLOCK_EN();
+ GPIO_InitTypeDef button_pin_config = {
+ .GPIO_Pin = BUTTON_PIN,
+ .GPIO_Mode = GPIO_Mode_IPU,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ };
+ GPIO_Init(BUTTON_PORT, &button_pin_config);
+
+ /* Enable interrupts globally */
+ __enable_irq();
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+ return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void)
+{
+ __asm("BKPT #0\n");
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+ GPIO_WriteBit(LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+ return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+ int txsize = len;
+ while ( txsize-- )
+ {
+ uart_write(*(uint8_t const*) buf);
+ buf++;
+ }
+ return len;
+}
diff --git a/hw/bsp/ch32f20x/family.mk b/hw/bsp/ch32f20x/family.mk
new file mode 100644
index 000000000..c08451b9c
--- /dev/null
+++ b/hw/bsp/ch32f20x/family.mk
@@ -0,0 +1,30 @@
+# Submodules
+CH32F20X_SDK = hw/mcu/wch/ch32f20x
+DEPS_SUBMODULES += $(CH32F20X_SDK)
+
+# WCH-SDK paths
+CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m3
+
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_CH32F20X \
+ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+SRC_C += \
+ src/portable/wch/dcd_ch32_usbhs.c \
+ $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_gpio.c \
+ $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_misc.c \
+ $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_rcc.c \
+ $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_usart.c
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(CH32F20X_SDK_SRC)/StdPeriphDriver/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
+
+flash: flash-stlink
diff --git a/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
new file mode 100644
index 000000000..2ecac2ac1
--- /dev/null
+++ b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
@@ -0,0 +1,493 @@
+/**
+ ******************************************************************************
+ * @file startup_gcc_ch32f20x_d8c.s
+ * @author Denis Krasutski
+ * @brief CH32F205 Devices vector table
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m3
+.thumb
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section. defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.section .text.Reset_Handler
+.weak Reset_Handler
+.type Reset_Handler, %function
+Reset_Handler:
+ /* set stack pointer */
+ ldr sp, =_estack
+ /* Call the clock system initialization function.*/
+ bl SystemInit
+ /* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+ /* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+ /* Call static constructors */
+ bl __libc_init_array
+ /* Call the application's entry point.*/
+ bl main
+ bx lr
+ .size Reset_Handler, .-Reset_Handler
+
+.section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+/*******************************************************************************
+ External Interrupts
+*******************************************************************************/
+.word WWDG_IRQHandler
+.word PVD_IRQHandler
+.word TAMPER_IRQHandler
+.word RTC_IRQHandler
+.word FLASH_IRQHandler
+.word RCC_IRQHandler
+.word EXTI0_IRQHandler
+.word EXTI1_IRQHandler
+.word EXTI2_IRQHandler
+.word EXTI3_IRQHandler
+.word EXTI4_IRQHandler
+.word DMA1_Channel1_IRQHandler
+.word DMA1_Channel2_IRQHandler
+.word DMA1_Channel3_IRQHandler
+.word DMA1_Channel4_IRQHandler
+.word DMA1_Channel5_IRQHandler
+.word DMA1_Channel6_IRQHandler
+.word DMA1_Channel7_IRQHandler
+.word ADC1_2_IRQHandler
+.word USB_HP_CAN1_TX_IRQHandler
+.word USB_LP_CAN1_RX0_IRQHandler
+.word CAN1_RX1_IRQHandler
+.word CAN1_SCE_IRQHandler
+.word EXTI9_5_IRQHandler
+.word TIM1_BRK_IRQHandler
+.word TIM1_UP_IRQHandler
+.word TIM1_TRG_COM_IRQHandler
+.word TIM1_CC_IRQHandler
+.word TIM2_IRQHandler
+.word TIM3_IRQHandler
+.word TIM4_IRQHandler
+.word I2C1_EV_IRQHandler
+.word I2C1_ER_IRQHandler
+.word I2C2_EV_IRQHandler
+.word I2C2_ER_IRQHandler
+.word SPI1_IRQHandler
+.word SPI2_IRQHandler
+.word USART1_IRQHandler
+.word USART2_IRQHandler
+.word USART3_IRQHandler
+.word EXTI15_10_IRQHandler
+.word RTCAlarm_IRQHandler
+.word 0
+.word TIM8_BRK_IRQHandler
+.word TIM8_UP_IRQHandler
+.word TIM8_TRG_COM_IRQHandler
+.word TIM8_CC_IRQHandler
+.word RNG_IRQHandler
+.word FSMC_IRQHandler
+.word SDIO_IRQHandler
+.word TIM5_IRQHandler
+.word SPI3_IRQHandler
+.word UART4_IRQHandler
+.word UART5_IRQHandler
+.word TIM6_IRQHandler
+.word TIM7_IRQHandler
+.word DMA2_Channel1_IRQHandler
+.word DMA2_Channel2_IRQHandler
+.word DMA2_Channel3_IRQHandler
+.word DMA2_Channel4_IRQHandler
+.word DMA2_Channel5_IRQHandler
+.word ETH_IRQHandler
+.word ETH_WKUP_IRQHandler
+.word CAN2_TX_IRQHandler
+.word CAN2_RX0_IRQHandler
+.word CAN2_RX1_IRQHandler
+.word CAN2_SCE_IRQHandler
+.word OTG_FS_IRQHandler
+.word USBHSWakeup_IRQHandler
+.word USBHS_IRQHandler
+.word DVP_IRQHandler
+.word UART6_IRQHandler
+.word UART7_IRQHandler
+.word UART8_IRQHandler
+.word TIM9_BRK_IRQHandler
+.word TIM9_UP_IRQHandler
+.word TIM9_TRG_COM_IRQHandler
+.word TIM9_CC_IRQHandler
+.word TIM10_BRK_IRQHandler
+.word TIM10_UP_IRQHandler
+.word TIM10_TRG_COM_IRQHandler
+.word TIM10_CC_IRQHandler
+.word DMA2_Channel6_IRQHandler
+.word DMA2_Channel7_IRQHandler
+.word DMA2_Channel8_IRQHandler
+.word DMA2_Channel9_IRQHandler
+.word DMA2_Channel10_IRQHandler
+.word DMA2_Channel11_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases
+*
+*******************************************************************************/
+.weak NMI_Handler
+.thumb_set NMI_Handler,Default_Handler
+
+.weak HardFault_Handler
+.thumb_set HardFault_Handler,Default_Handler
+
+.weak MemManage_Handler
+.thumb_set MemManage_Handler,Default_Handler
+
+.weak BusFault_Handler
+.thumb_set BusFault_Handler,Default_Handler
+
+.weak UsageFault_Handler
+.thumb_set UsageFault_Handler,Default_Handler
+
+.weak SVC_Handler
+.thumb_set SVC_Handler,Default_Handler
+
+.weak DebugMon_Handler
+.thumb_set DebugMon_Handler,Default_Handler
+
+.weak PendSV_Handler
+.thumb_set PendSV_Handler,Default_Handler
+
+.weak SysTick_Handler
+.thumb_set SysTick_Handler,Default_Handler
+
+.weak WWDG_IRQHandler
+.thumb_set WWDG_IRQHandler,Default_Handler
+
+.weak PVD_IRQHandler
+.thumb_set PVD_IRQHandler,Default_Handler
+
+.weak TAMPER_IRQHandler
+.thumb_set TAMPER_IRQHandler,Default_Handler
+
+.weak RTC_IRQHandler
+.thumb_set RTC_IRQHandler,Default_Handler
+
+.weak FLASH_IRQHandler
+.thumb_set FLASH_IRQHandler,Default_Handler
+
+.weak RCC_IRQHandler
+.thumb_set RCC_IRQHandler,Default_Handler
+
+.weak EXTI0_IRQHandler
+.thumb_set EXTI0_IRQHandler,Default_Handler
+
+.weak EXTI1_IRQHandler
+.thumb_set EXTI1_IRQHandler,Default_Handler
+
+.weak EXTI2_IRQHandler
+.thumb_set EXTI2_IRQHandler,Default_Handler
+
+.weak EXTI3_IRQHandler
+.thumb_set EXTI3_IRQHandler,Default_Handler
+
+.weak EXTI4_IRQHandler
+.thumb_set EXTI4_IRQHandler,Default_Handler
+
+.weak DMA1_Channel1_IRQHandler
+.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+.weak DMA1_Channel2_IRQHandler
+.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+.weak DMA1_Channel3_IRQHandler
+.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+.weak DMA1_Channel4_IRQHandler
+.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+.weak DMA1_Channel5_IRQHandler
+.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+.weak DMA1_Channel6_IRQHandler
+.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+.weak DMA1_Channel7_IRQHandler
+.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+.weak ADC1_2_IRQHandler
+.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+.weak USB_HP_CAN1_TX_IRQHandler
+.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+.weak USB_LP_CAN1_RX0_IRQHandler
+.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+.weak CAN1_RX1_IRQHandler
+.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+.weak CAN1_SCE_IRQHandler
+.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+.weak EXTI9_5_IRQHandler
+.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+.weak TIM1_BRK_IRQHandler
+.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+.weak TIM1_UP_IRQHandler
+.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+.weak TIM1_TRG_COM_IRQHandler
+.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM1_CC_IRQHandler
+.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+.weak TIM2_IRQHandler
+.thumb_set TIM2_IRQHandler,Default_Handler
+
+.weak TIM3_IRQHandler
+.thumb_set TIM3_IRQHandler,Default_Handler
+
+.weak TIM4_IRQHandler
+.thumb_set TIM4_IRQHandler,Default_Handler
+
+.weak I2C1_EV_IRQHandler
+.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+.weak I2C1_ER_IRQHandler
+.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+.weak I2C2_EV_IRQHandler
+.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+.weak I2C2_ER_IRQHandler
+.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+.weak SPI1_IRQHandler
+.thumb_set SPI1_IRQHandler,Default_Handler
+
+.weak SPI2_IRQHandler
+.thumb_set SPI2_IRQHandler,Default_Handler
+
+.weak USART1_IRQHandler
+.thumb_set USART1_IRQHandler,Default_Handler
+
+.weak USART2_IRQHandler
+.thumb_set USART2_IRQHandler,Default_Handler
+
+.weak USART3_IRQHandler
+.thumb_set USART3_IRQHandler,Default_Handler
+
+.weak EXTI15_10_IRQHandler
+.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+.weak RTCAlarm_IRQHandler
+.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+.weak TIM8_BRK_IRQHandler
+.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+.weak TIM8_UP_IRQHandler
+.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+.weak TIM8_TRG_COM_IRQHandler
+.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM8_CC_IRQHandler
+.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+.weak RNG_IRQHandler
+.thumb_set RNG_IRQHandler,Default_Handler
+
+.weak FSMC_IRQHandler
+.thumb_set FSMC_IRQHandler,Default_Handler
+
+.weak SDIO_IRQHandler
+.thumb_set SDIO_IRQHandler,Default_Handler
+
+.weak TIM5_IRQHandler
+.thumb_set TIM5_IRQHandler,Default_Handler
+
+.weak SPI3_IRQHandler
+.thumb_set SPI3_IRQHandler,Default_Handler
+
+.weak UART4_IRQHandler
+.thumb_set UART4_IRQHandler,Default_Handler
+
+.weak UART5_IRQHandler
+.thumb_set UART5_IRQHandler,Default_Handler
+
+.weak TIM6_IRQHandler
+.thumb_set TIM6_IRQHandler,Default_Handler
+
+.weak TIM7_IRQHandler
+.thumb_set TIM7_IRQHandler,Default_Handler
+
+.weak DMA2_Channel1_IRQHandler
+.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+.weak DMA2_Channel2_IRQHandler
+.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+.weak DMA2_Channel3_IRQHandler
+.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+.weak DMA2_Channel4_IRQHandler
+.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+.weak DMA2_Channel5_IRQHandler
+.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+.weak ETH_IRQHandler
+.thumb_set ETH_IRQHandler,Default_Handler
+
+.weak ETH_WKUP_IRQHandler
+.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+.weak CAN2_TX_IRQHandler
+.thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+.weak CAN2_RX0_IRQHandler
+.thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+.weak CAN2_RX1_IRQHandler
+.thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+.weak CAN2_SCE_IRQHandler
+.thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+.weak OTG_FS_IRQHandler
+.thumb_set OTG_FS_IRQHandler,Default_Handler
+
+.weak USBHSWakeup_IRQHandler
+.thumb_set USBHSWakeup_IRQHandler,Default_Handler
+
+.weak USBHS_IRQHandler
+.thumb_set USBHS_IRQHandler,Default_Handler
+
+.weak DVP_IRQHandler
+.thumb_set DVP_IRQHandler,Default_Handler
+
+.weak UART6_IRQHandler
+.thumb_set UART6_IRQHandler,Default_Handler
+
+.weak UART7_IRQHandler
+.thumb_set UART7_IRQHandler,Default_Handler
+
+.weak UART8_IRQHandler
+.thumb_set UART8_IRQHandler,Default_Handler
+
+.weak TIM9_BRK_IRQHandler
+.thumb_set TIM9_BRK_IRQHandler,Default_Handler
+
+.weak TIM9_UP_IRQHandler
+.thumb_set TIM9_UP_IRQHandler,Default_Handler
+
+.weak TIM9_TRG_COM_IRQHandler
+.thumb_set TIM9_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM9_CC_IRQHandler
+.thumb_set TIM9_CC_IRQHandler,Default_Handler
+
+.weak TIM10_BRK_IRQHandler
+.thumb_set TIM10_BRK_IRQHandler,Default_Handler
+
+.weak TIM10_UP_IRQHandler
+.thumb_set TIM10_UP_IRQHandler,Default_Handler
+
+.weak TIM10_TRG_COM_IRQHandler
+.thumb_set TIM10_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM10_CC_IRQHandler
+.thumb_set TIM10_CC_IRQHandler,Default_Handler
+
+.weak DMA2_Channel6_IRQHandler
+.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+.weak DMA2_Channel7_IRQHandler
+.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+.weak DMA2_Channel8_IRQHandler
+.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
+
+.weak DMA2_Channel9_IRQHandler
+.thumb_set DMA2_Channel9_IRQHandler,Default_Handler
+
+.weak DMA2_Channel10_IRQHandler
+.thumb_set DMA2_Channel10_IRQHandler,Default_Handler
+
+.weak DMA2_Channel11_IRQHandler
+.thumb_set DMA2_Channel11_IRQHandler,Default_Handler
diff --git a/hw/bsp/ch32f20x/system_ch32f20x.c b/hw/bsp/ch32f20x/system_ch32f20x.c
new file mode 100644
index 000000000..0a59b9287
--- /dev/null
+++ b/hw/bsp/ch32f20x/system_ch32f20x.c
@@ -0,0 +1,1122 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name : system_ch32f20x.c
+* Author : WCH
+* Version : V1.0.0
+* Date : 2021/08/08
+* Description : CH32F20x Device Peripheral Access Layer System Source File.
+* For CH32F208 HSE = 32Mhz
+* For others HSE = 8Mhz
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32f20x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+
+//#define SYSCLK_FREQ_HSE HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE 48000000
+//#define SYSCLK_FREQ_56MHz_HSE 56000000
+//#define SYSCLK_FREQ_72MHz_HSE 72000000
+#define SYSCLK_FREQ_96MHz_HSE 96000000
+//#define SYSCLK_FREQ_120MHz_HSE 120000000
+//#define SYSCLK_FREQ_144MHz_HSE 144000000
+//#define SYSCLK_FREQ_HSI HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI 48000000
+//#define SYSCLK_FREQ_56MHz_HSI 56000000
+//#define SYSCLK_FREQ_72MHz_HSI 72000000
+//#define SYSCLK_FREQ_96MHz_HSI 96000000
+//#define SYSCLK_FREQ_120MHz_HSI 120000000
+//#define SYSCLK_FREQ_144MHz_HSI 144000000
+
+
+/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
+/* #define VECT_TAB_SRAM */
+
+/* Vector Table base offset field This value must be a multiple of 0x200 */
+#define VECT_TAB_OFFSET 0x0
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* system_private_function_proto_types */
+static void SetSysClock( void );
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+
+/*********************************************************************
+ * @fn SystemInit
+ *
+ * @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
+ * the PLL and update the SystemCoreClock variable.
+ *
+ * @return none
+ */
+void SystemInit( void )
+{
+ RCC->CTLR |= ( uint32_t )0x00000001;
+
+#ifdef CH32F20x_D8C
+ RCC->CFGR0 &= ( uint32_t )0xF8FF0000;
+#else
+ RCC->CFGR0 &= ( uint32_t )0xF0FF0000;
+#endif
+
+ RCC->CTLR &= ( uint32_t )0xFEF6FFFF;
+ RCC->CTLR &= ( uint32_t )0xFFFBFFFF;
+ RCC->CFGR0 &= ( uint32_t )0xFF80FFFF;
+#ifdef CH32F20x_D8C
+ RCC->CTLR &= ( uint32_t )0xEBFFFFFF;
+ RCC->INTR = 0x00FF0000;
+ RCC->CFGR2 = 0x00000000;
+#else
+ RCC->INTR = 0x009F0000;
+#endif
+
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/*********************************************************************
+ * @fn SystemCoreClockUpdate
+ *
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return none
+ */
+void SystemCoreClockUpdate( void )
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+ uint8_t Pll_6_5 = 0;
+
+#if defined (CH32F20x_D8C)
+ uint8_t Pll2mull = 0;
+
+#endif
+
+ tmp = RCC->CFGR0 & RCC_SWS;
+
+ switch( tmp )
+ {
+ case 0x00:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04:
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08:
+ pllmull = RCC->CFGR0 & RCC_PLLMULL;
+ pllsource = RCC->CFGR0 & RCC_PLLSRC;
+ pllmull = ( pllmull >> 18 ) + 2;
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ if( pllmull == 17 )
+ {
+ pllmull = 18;
+ }
+#else
+ if( pllmull == 2 )
+ {
+ pllmull = 18;
+ }
+ if( pllmull == 15 )
+ {
+ pllmull = 13; /* *6.5 */
+ Pll_6_5 = 1;
+ }
+ if( pllmull == 16 )
+ {
+ pllmull = 15;
+ }
+ if( pllmull == 17 )
+ {
+ pllmull = 16;
+ }
+#endif
+
+ if( pllsource == 0x00 )
+ {
+ if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) SystemCoreClock = HSI_VALUE * pllmull;
+ else SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+#if defined (CH32F20x_D8C)
+ if(RCC->CFGR2 & (1<<16)){ /* PLL2 */
+ SystemCoreClock = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */
+
+ Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8);
+
+ if(Pll2mull == 0) SystemCoreClock = (SystemCoreClock * 5)>>1;
+ else if(Pll2mull == 1) SystemCoreClock = (SystemCoreClock * 25)>>1;
+ else if(Pll2mull == 15) SystemCoreClock = SystemCoreClock * 20;
+ else SystemCoreClock = SystemCoreClock * (Pll2mull + 2);
+
+ SystemCoreClock = SystemCoreClock/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */
+ }
+ else{/* HSE */
+ SystemCoreClock = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */
+ }
+
+ SystemCoreClock = SystemCoreClock * pllmull;
+#else
+
+#if defined (CH32F20x_D8W)
+ if((RCC->CFGR0 & (3<<22)) == (3<<22))
+ {
+ SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+ }
+ else
+#endif
+ if( ( RCC->CFGR0 & RCC_PLLXTPRE ) != ( uint32_t )RESET )
+ {
+#ifdef CH32F20x_D8W
+ SystemCoreClock = ( ( HSE_VALUE >> 2 ) >> 1 ) * pllmull;
+#else
+ SystemCoreClock = ( HSE_VALUE >> 1 ) * pllmull;
+#endif
+ }
+ else
+ {
+#ifdef CH32F20x_D8W
+ SystemCoreClock = ( HSE_VALUE >> 2 ) * pllmull;
+#else
+ SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+
+ }
+#endif
+ }
+
+ if( Pll_6_5 == 1 ) SystemCoreClock = ( SystemCoreClock / 2 );
+
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ tmp = AHBPrescTable[( ( RCC->CFGR0 & RCC_HPRE ) >> 4 )];
+ SystemCoreClock >>= tmp;
+}
+
+
+
+/*********************************************************************
+ * @fn SetSysClock
+ *
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClock( void )
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+ SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+ SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+ SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+ SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+ SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+ SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+ SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+ SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+ SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+ SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+ SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+ SetSysClockTo144_HSI();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ * source (default after reset)
+ */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn SetSysClockToHSE
+ *
+ * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockToHSE( void )
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+ RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ }
+ while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+ if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+ {
+ HSEStatus = ( uint32_t )0x01;
+ }
+ else
+ {
+ HSEStatus = ( uint32_t )0x00;
+ }
+
+ if( HSEStatus == ( uint32_t )0x01 )
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
+
+ /* Select HSE as system clock source
+ * CH32F20x_D6 (HSE=8Mhz)
+ * CH32F20x_D8 (HSE=8Mhz)
+ * CH32F20x_D8W (HSE=32Mhz)
+ */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x04 )
+ {
+ }
+ }
+ else
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo48_HSE
+ *
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo48_HSE( void )
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+ RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ }
+ while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+ if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+ {
+ HSEStatus = ( uint32_t )0x01;
+ }
+ else
+ {
+ HSEStatus = ( uint32_t )0x00;
+ }
+
+ if( HSEStatus == ( uint32_t )0x01 )
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz)
+ * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz)
+ * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz(HSE=32Mhz)
+ */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo56_HSE
+ *
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo56_HSE( void )
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ }
+ while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+ if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+ {
+ HSEStatus = ( uint32_t )0x01;
+ }
+ else
+ {
+ HSEStatus = ( uint32_t )0x00;
+ }
+
+ if( HSEStatus == ( uint32_t )0x01 )
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz)
+ * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz)
+ * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz(HSE=32Mhz)
+ */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo72_HSE
+ *
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo72_HSE( void )
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ }
+ while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+ if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+ {
+ HSEStatus = ( uint32_t )0x01;
+ }
+ else
+ {
+ HSEStatus = ( uint32_t )0x00;
+ }
+
+ if( HSEStatus == ( uint32_t )0x01 )
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz)
+ * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz)
+ * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz(HSE=32Mhz)
+ */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo96_HSE
+ *
+ * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo96_HSE( void )
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ }
+ while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+ if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+ {
+ HSEStatus = ( uint32_t )0x01;
+ }
+ else
+ {
+ HSEStatus = ( uint32_t )0x00;
+ }
+
+ if( HSEStatus == ( uint32_t )0x01 )
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz)
+ * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz)
+ * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz(HSE=32Mhz)
+ */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo120_HSE
+ *
+ * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+#if defined (CH32F20x_D8W)
+ RCC->CFGR0 |= (uint32_t)(3<<22);
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz)
+ * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz)
+ * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz(HSE=32Mhz)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+
+
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo144_HSE
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo144_HSE( void )
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ }
+ while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+ if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+ {
+ HSEStatus = ( uint32_t )0x01;
+ }
+ else
+ {
+ HSEStatus = ( uint32_t )0x00;
+ }
+
+ if( HSEStatus == ( uint32_t )0x01 )
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz)
+ * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz)
+ * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz(HSE=32Mhz)
+ */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo48_HSI
+ *
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo48_HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo56_HSI
+ *
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo56_HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo72_HSI
+ *
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo72_HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo96_HSI
+ *
+ * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo96_HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo120_HSI
+ *
+ * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo144_HSI
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo144_HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18 );
+#else
+ RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN );
+#endif
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+ RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+ {
+ }
+}
+
+
+#endif
diff --git a/hw/bsp/ch32f20x/system_ch32f20x.h b/hw/bsp/ch32f20x/system_ch32f20x.h
new file mode 100644
index 000000000..cf2f5328b
--- /dev/null
+++ b/hw/bsp/ch32f20x/system_ch32f20x.h
@@ -0,0 +1,25 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name : system_ch32f20x.h
+* Author : WCH
+* Version : V1.0.0
+* Date : 2021/08/08
+* Description : CH32F20x Device Peripheral Access Layer System Header File.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32F20x_H
+#define __SYSTEM_CH32F20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F20x_SYSTEM_H */
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 4b06cf429..07e57f04c 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -28,8 +28,10 @@ CFLAGS += \
-Xlinker --gc-sections \
-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
- src/portable/wch/ch32v307/dcd_usbhs.c \
+ src/portable/wch/dcd_ch32_usbhs.c \
$(CH32V307_SDK_SRC)/Core/core_riscv.c \
$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \
$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
index 1f7bc1588..980b1a361 100644
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ b/hw/bsp/da14695_dk_usb/board.mk
@@ -1,3 +1,5 @@
+MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
+
CFLAGS += \
-flto \
-mthumb \
@@ -11,7 +13,7 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-DCFG_TUD_ENDPOINT0_SIZE=8\
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
index f9bf480de..5282f93a3 100644
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ b/hw/bsp/da1469x_dk_pro/board.mk
@@ -1,3 +1,5 @@
+MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
+
CFLAGS += \
-flto \
-mthumb \
@@ -11,7 +13,7 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-DCFG_TUD_ENDPOINT0_SIZE=8\
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
index 9062483b0..3596e5414 100644
--- a/hw/bsp/f1c100s/board.mk
+++ b/hw/bsp/f1c100s/board.mk
@@ -1,5 +1,5 @@
+MCU_DIR = hw/mcu/allwinner/f1c100s
DEPS_SUBMODULES += hw/mcu/allwinner
-
DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
CFLAGS += \
@@ -18,8 +18,8 @@ CFLAGS += \
$(DEFINES)
LD_FILE = hw/mcu/allwinner/f1c100s/f1c100s.ld
-LDFLAGS += -nostdlib -lgcc
-MCU_DIR = hw/mcu/allwinner/f1c100s
+# TODO may skip nanolib
+LDFLAGS += -nostdlib -lgcc -specs=nosys.specs -specs=nano.specs
SRC_C += \
src/portable/sunxi/dcd_sunxi_musb.c \
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index eec42160e..930237fea 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -201,6 +201,9 @@ function(family_configure_common TARGET RTOS)
# Generate linker map file
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map")
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+ target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
+ endif ()
endif()
# ETM Trace option
@@ -289,13 +292,11 @@ function(family_configure_device_example TARGET RTOS)
family_configure_example(${TARGET} ${RTOS})
endfunction()
-
# Configure host example with RTOS
function(family_configure_host_example TARGET RTOS)
family_configure_example(${TARGET} ${RTOS})
endfunction()
-
# Configure host + device example with RTOS
function(family_configure_dual_usb_example TARGET RTOS)
family_configure_example(${TARGET} ${RTOS})
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index d0b819120..f8a3c9ebf 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -1,3 +1,6 @@
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
+CROSS_COMPILE = riscv-none-embed-
+
CFLAGS += \
-flto \
-march=rv32i \
@@ -5,8 +8,7 @@ CFLAGS += \
-nostdlib \
-DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE = riscv-none-embed-
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = $(FAMILY_PATH)/fomu.ld
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index ecde39611..090014754 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -13,7 +13,7 @@ set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE})
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 90d566cfb..c6adcba5a 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -5,8 +5,8 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m7
-
MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE}
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
CFLAGS += \
-D__ARMVFP__=0 \
@@ -26,7 +26,7 @@ endif
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough -Wno-error=redundant-decls
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_flexspi_nor.ld
diff --git a/hw/bsp/kinetis_k32l2/family.mk b/hw/bsp/kinetis_k32l2/family.mk
index 357485762..0bfd57d29 100644
--- a/hw/bsp/kinetis_k32l2/family.mk
+++ b/hw/bsp/kinetis_k32l2/family.mk
@@ -9,6 +9,8 @@ CPU_CORE ?= cortex-m0plus
CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32L
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/nxp/khci/dcd_khci.c \
src/portable/nxp/khci/hcd_khci.c \
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index 4151979a0..6d9b65df0 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -12,7 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
index edb2f3366..e331d82b7 100644
--- a/hw/bsp/kinetis_kl/family.mk
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -9,6 +9,7 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_KINETIS_KL \
LDFLAGS += \
+ -specs=nosys.specs -specs=nano.specs \
-Wl,--defsym,__stack_size__=0x400 \
-Wl,--defsym,__heap_size__=0
diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
index dee85da90..ce07ff450 100644
--- a/hw/bsp/lpc11/family.mk
+++ b/hw/bsp/lpc11/family.mk
@@ -11,6 +11,8 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
$(MCU_DIR)/../gcc/cr_startup_lpc$(MCU_DRV).c \
diff --git a/hw/bsp/lpc13/family.mk b/hw/bsp/lpc13/family.mk
index 10cf4969d..6964dc48a 100644
--- a/hw/bsp/lpc13/family.mk
+++ b/hw/bsp/lpc13/family.mk
@@ -14,6 +14,8 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# startup.c and lpc_types.h cause following errors
CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index 9f489832f..28ab1db7b 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -12,6 +12,8 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk
index 44b406d90..67d5e14b5 100644
--- a/hw/bsp/lpc17/family.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -18,7 +18,7 @@ CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
# caused by freeRTOS port !!
CFLAGS += -Wno-error=maybe-uninitialized
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
SRC_C += \
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 74a794bde..78f4c510b 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -11,7 +11,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 9d0f85c20..c36c903ae 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -1,4 +1,5 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3
@@ -13,7 +14,7 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
SRC_C += \
src/portable/chipidea/ci_hs/dcd_ci_hs.c \
diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
index 56eb37a2f..fce9772b6 100644
--- a/hw/bsp/lpc40/family.cmake
+++ b/hw/bsp/lpc40/family.cmake
@@ -7,7 +7,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk
index c11325890..fa76789e3 100644
--- a/hw/bsp/lpc40/family.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -15,6 +15,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
SRC_C += \
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake
index 608fc4ca3..f66da98aa 100644
--- a/hw/bsp/lpc43/family.cmake
+++ b/hw/bsp/lpc43/family.cmake
@@ -7,7 +7,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC43XX CACHE INTERNAL "")
diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk
index 55d86e955..f24385139 100644
--- a/hw/bsp/lpc43/family.mk
+++ b/hw/bsp/lpc43/family.mk
@@ -18,6 +18,8 @@ CFLAGS += \
-Wno-error=cast-qual \
-Wno-error=incompatible-pointer-types \
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/chipidea/ci_hs/dcd_ci_hs.c \
src/portable/chipidea/ci_hs/hcd_ci_hs.c \
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index df5a9958e..c8ee29dbc 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -13,6 +13,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index cdd513fe4..287b437fb 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -12,7 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 46a5f7930..9b5eac18d 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -3,6 +3,7 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
CFLAGS += \
-flto \
@@ -22,7 +23,7 @@ endif
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
SRC_C += \
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index dce197b2d..75dabfe5a 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -12,7 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index a87fa5acf..1b97c43e4 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -4,6 +4,7 @@ DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m33
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
# Default to Highspeed PORT1
PORT ?= 1
@@ -27,7 +28,7 @@ endif
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index b3a4a846e..13d1d44ef 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -12,7 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index e384aa8eb..526effdfb 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -17,6 +17,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index d5b6e315a..3981e4e41 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -13,6 +13,8 @@ CFLAGS += \
# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \
$(SDK_DIR)/mm32f327x/MM32F327x/Source/system_mm32f327x.c \
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index b5ade6a52..6fcb22457 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -12,6 +12,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=cast-qual -Wno-error=format=
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld
LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
deleted file mode 100644
index 99c1f194c..000000000
--- a/hw/bsp/ngx4330/board.mk
+++ /dev/null
@@ -1,47 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
- -nostdlib \
- -DCORE_M4 \
- -D__USE_LPCOPEN \
- -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
-
-SRC_C += \
- src/portable/chipidea/ci_hs/dcd_ci_hs.c \
- src/portable/chipidea/ci_hs/hcd_ci_hs.c \
- src/portable/ehci/ehci.c \
- $(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
- $(MCU_DIR)/src/chip_18xx_43xx.c \
- $(MCU_DIR)/src/clock_18xx_43xx.c \
- $(MCU_DIR)/src/gpio_18xx_43xx.c \
- $(MCU_DIR)/src/sysinit_18xx_43xx.c \
- $(MCU_DIR)/src/uart_18xx_43xx.c \
- $(MCU_DIR)/src/fpu_init.c
-
-INC += \
- $(TOP)/$(MCU_DIR)/inc \
- $(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4330
-JLINK_IF = swd
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
deleted file mode 100644
index bd84e449b..000000000
--- a/hw/bsp/ngx4330/ngx4330.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board_api.h"
-
-#define LED_PORT 1
-#define LED_PIN 12
-#define LED_STATE_ON 0
-
-#define BUTTON_PORT 0
-#define BUTTON_PIN 7
-#define BUTTON_STATE_ACTIVE 0
-
-#define BOARD_UART_PORT LPC_USART0
-#define BOARD_UART_PIN_PORT 0x0f
-#define BOARD_UART_PIN_TX 10 // PF.10 : UART0_TXD
-#define BOARD_UART_PIN_RX 11 // PF.11 : UART0_RXD
-
-#ifdef BOARD_TUD_RHPORT
- #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
-#else
- #define PORT_SUPPORT_DEVICE(_n) 0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
- #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n)
-#else
- #define PORT_SUPPORT_HOST(_n) 0
-#endif
-
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
-/* System configuration variables used by chip driver */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
- // LED P2.12 as GPIO 1.12
- {2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
-
- // Button P2.7 as GPIO 0.7
- {2, 7, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
-
- // USB
- {2, 6, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)}, // USB1_PWR_EN
- {2, 5, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, // USB1_VBUS
- {1, 7, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)}, // USB0_PWRN_EN
-
- // SPIFI
- {3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
- {3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
- {3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
- {3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
- {3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
- {3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
- extern void (* const g_pfnVectors[])(void);
- unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
- *pSCB_VTOR = (unsigned int) g_pfnVectors;
-
-#if __FPU_USED == 1
- fpuInit();
-#endif
-#endif // __USE_LPCOPEN
-
- // Set up pinmux
- Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
- //------------- Set up clock -------------//
- Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IRC, true, false); // change SPIFI to IRC during clock programming
- LPC_SPIFI->CTRL |= SPIFI_CTRL_FBCLK(1); // and set FBCLK in SPIFI controller
-
- Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
-
- /* Reset and enable 32Khz oscillator */
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
- LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
- /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
- Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
- Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-
- /* Setup system base clocks and initial states. This won't enable and
- disable individual clocks, but sets up the base clock sources for
- each individual peripheral clock. */
- Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
-}
-
-void board_init(void)
-{
- SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
- // 1ms tick timer
- SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
- // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
- NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
- Chip_GPIO_Init(LPC_GPIO_PORT);
-
- // LED
- Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
-
- // Button
- Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-#if 0
- //------------- UART -------------//
- scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
- scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
-
- UART_CFG_Type UARTConfigStruct;
- UART_ConfigStructInit(&UARTConfigStruct);
- UARTConfigStruct.Baud_rate = CFG_BOARD_UART_BAUDRATE;
- UARTConfigStruct.Clock_Speed = 0;
-
- UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
- UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
-#endif
-
- //------------- USB -------------//
- enum {
- USBMODE_DEVICE = 2,
- USBMODE_HOST = 3
- };
-
- enum {
- USBMODE_VBUS_LOW = 0,
- USBMODE_VBUS_HIGH = 1
- };
-
- /* USB0
- * For USB Device operation; insert jumpers in position 1-2 in JP17/JP18/JP19. GPIO28 controls USB
- * connect functionality and LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted
- * by default. LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
- * sensing.
- * For USB Host operation; insert jumpers in position 2-3 in JP17/JP18/JP19. USB Host power is
- * controlled via distribution switch U20 (found in schematic page 11). Signal GPIO26 is active low and
- * enables +5V on VBUS2. LED35 light whenever +5V is present on VBUS2. GPIO55 is connected to
- * status feedback from the distribution switch. GPIO54 is used for VBUS sensing. 15Kohm pull-down
- * resistors are always active
- */
- Chip_USB0_Init();
-
- /* USB1
- * When USB channel #1 is used as USB Host, 15Kohm pull-down resistors are needed on the USB data
- * signals. These are activated inside the USB OTG chip (U31), and this has to be done via the I2C
- * interface of GPIO52/GPIO53.
- * J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
- * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
- * since SJ5 is normally connected between pin 1-2. LED34 lights green when +5V is available on J20.
- * JP15 shall not be inserted. JP16 has no effect
- *
- * When USB channel #1 is used as USB Device, a 1.5Kohm pull-up resistor is needed on the USB DP
- * data signal. There are two methods to create this. JP15 is inserted and the pull-up resistor is always
- * enabled. Alternatively, the pull-up resistor is activated inside the USB OTG chip (U31), and this has to
- * be done via the I2C interface of GPIO52/GPIO53. In the latter case, JP15 shall not be inserted.
- * J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
- * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
- * of VBUS can be read via U31.
- * JP16 shall not be inserted.
- */
- Chip_USB1_Init();
-// Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 6); /* GPIO5[6] = USB1_PWR_EN */
-// Chip_GPIO_SetPinState(LPC_GPIO_PORT, 5, 6, true); /* GPIO5[6] output high */
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
- #if PORT_SUPPORT_DEVICE(0)
- tud_int_handler(0);
- #endif
-
- #if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0, true);
- #endif
-}
-
-void USB1_IRQHandler(void)
-{
- #if PORT_SUPPORT_DEVICE(1)
- tud_int_handler(1);
- #endif
-
- #if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1, true);
- #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
- Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
- return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
- //return UART_ReceiveByte(BOARD_UART_PORT);
- (void) buf; (void) len;
- return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
- //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
- (void) buf; (void) len;
- return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
- return system_ticks;
-}
-#endif
diff --git a/hw/bsp/ngx4330/ngx4330.ld b/hw/bsp/ngx4330/ngx4330.ld
deleted file mode 100644
index 300869c20..000000000
--- a/hw/bsp/ngx4330/ngx4330.ld
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * Copyright (c) 2008-2013 Code Red Technologies Ltd,
- * Copyright 2015, 2018-2019 NXP
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC4330
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Sep 9, 2019 12:09:49 PM
- */
-
-MEMORY
-{
- /* Define each memory region */
- RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */
- RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */
- RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
- RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
- RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
- SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */
-}
-
- /* Define a symbol for the top of each memory region */
- __base_RamLoc128 = 0x10000000 ; /* RamLoc128 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */
- __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */
- __base_RamLoc72 = 0x10080000 ; /* RamLoc72 */
- __base_RAM2 = 0x10080000 ; /* RAM2 */
- __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */
- __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */
- __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
- __base_RAM3 = 0x20000000 ; /* RAM3 */
- __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
- __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
- __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
- __base_RAM4 = 0x20008000 ; /* RAM4 */
- __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
- __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
- __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
- __base_RAM5 = 0x2000c000 ; /* RAM5 */
- __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
- __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
- __base_SPIFI = 0x14000000 ; /* SPIFI */
- __base_Flash = 0x14000000 ; /* Flash */
- __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */
- __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
- /* MAIN TEXT SECTION */
- .text : ALIGN(4)
- {
- FILL(0xff)
- __vectors_start__ = ABSOLUTE(.) ;
- KEEP(*(.isr_vector))
- /* Global Section Table */
- . = ALIGN(4) ;
- __section_table_start = .;
- __data_section_table = .;
- LONG(LOADADDR(.data));
- LONG( ADDR(.data));
- LONG( SIZEOF(.data));
- LONG(LOADADDR(.data_RAM2));
- LONG( ADDR(.data_RAM2));
- LONG( SIZEOF(.data_RAM2));
- LONG(LOADADDR(.data_RAM3));
- LONG( ADDR(.data_RAM3));
- LONG( SIZEOF(.data_RAM3));
- LONG(LOADADDR(.data_RAM4));
- LONG( ADDR(.data_RAM4));
- LONG( SIZEOF(.data_RAM4));
- LONG(LOADADDR(.data_RAM5));
- LONG( ADDR(.data_RAM5));
- LONG( SIZEOF(.data_RAM5));
- __data_section_table_end = .;
- __bss_section_table = .;
- LONG( ADDR(.bss));
- LONG( SIZEOF(.bss));
- LONG( ADDR(.bss_RAM2));
- LONG( SIZEOF(.bss_RAM2));
- LONG( ADDR(.bss_RAM3));
- LONG( SIZEOF(.bss_RAM3));
- LONG( ADDR(.bss_RAM4));
- LONG( SIZEOF(.bss_RAM4));
- LONG( ADDR(.bss_RAM5));
- LONG( SIZEOF(.bss_RAM5));
- __bss_section_table_end = .;
- __section_table_end = . ;
- /* End of Global Section Table */
-
- *(.after_vectors*)
-
- } > SPIFI
-
- .text : ALIGN(4)
- {
- *(.text*)
- *(.rodata .rodata.* .constdata .constdata.*)
- . = ALIGN(4);
- } > SPIFI
- /*
- * for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
- */
- .ARM.extab : ALIGN(4)
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > SPIFI
-
- __exidx_start = .;
-
- .ARM.exidx : ALIGN(4)
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > SPIFI
- __exidx_end = .;
-
- _etext = .;
-
- /* DATA section for RamLoc72 */
-
- .data_RAM2 : ALIGN(4)
- {
- FILL(0xff)
- PROVIDE(__start_data_RAM2 = .) ;
- *(.ramfunc.$RAM2)
- *(.ramfunc.$RamLoc72)
- *(.data.$RAM2)
- *(.data.$RamLoc72)
- *(.data.$RAM2.*)
- *(.data.$RamLoc72.*)
- . = ALIGN(4) ;
- PROVIDE(__end_data_RAM2 = .) ;
- } > RamLoc72 AT>SPIFI
- /* DATA section for RamAHB32 */
-
- .data_RAM3 : ALIGN(4)
- {
- FILL(0xff)
- PROVIDE(__start_data_RAM3 = .) ;
- *(.ramfunc.$RAM3)
- *(.ramfunc.$RamAHB32)
- *(.data.$RAM3)
- *(.data.$RamAHB32)
- *(.data.$RAM3.*)
- *(.data.$RamAHB32.*)
- . = ALIGN(4) ;
- PROVIDE(__end_data_RAM3 = .) ;
- } > RamAHB32 AT>SPIFI
- /* DATA section for RamAHB16 */
-
- .data_RAM4 : ALIGN(4)
- {
- FILL(0xff)
- PROVIDE(__start_data_RAM4 = .) ;
- *(.ramfunc.$RAM4)
- *(.ramfunc.$RamAHB16)
- *(.data.$RAM4)
- *(.data.$RamAHB16)
- *(.data.$RAM4.*)
- *(.data.$RamAHB16.*)
- . = ALIGN(4) ;
- PROVIDE(__end_data_RAM4 = .) ;
- } > RamAHB16 AT>SPIFI
- /* DATA section for RamAHB_ETB16 */
-
- .data_RAM5 : ALIGN(4)
- {
- FILL(0xff)
- PROVIDE(__start_data_RAM5 = .) ;
- *(.ramfunc.$RAM5)
- *(.ramfunc.$RamAHB_ETB16)
- *(.data.$RAM5)
- *(.data.$RamAHB_ETB16)
- *(.data.$RAM5.*)
- *(.data.$RamAHB_ETB16.*)
- . = ALIGN(4) ;
- PROVIDE(__end_data_RAM5 = .) ;
- } > RamAHB_ETB16 AT>SPIFI
- /* MAIN DATA SECTION */
- .uninit_RESERVED (NOLOAD) :
- {
- . = ALIGN(4) ;
- KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
- _end_uninit_RESERVED = .;
- } > RamLoc128
-
- /* Main DATA section (RamLoc128) */
- .data : ALIGN(4)
- {
- FILL(0xff)
- _data = . ;
- *(vtable)
- *(.ramfunc*)
- *(.data*)
- . = ALIGN(4) ;
- _edata = . ;
- } > RamLoc128 AT>SPIFI
-
- /* BSS section for RamLoc72 */
- .bss_RAM2 :
- {
- . = ALIGN(4) ;
- PROVIDE(__start_bss_RAM2 = .) ;
- *(.bss.$RAM2)
- *(.bss.$RamLoc72)
- *(.bss.$RAM2.*)
- *(.bss.$RamLoc72.*)
- . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
- PROVIDE(__end_bss_RAM2 = .) ;
- } > RamLoc72
-
- /* BSS section for RamAHB32 */
- .bss_RAM3 :
- {
- . = ALIGN(4) ;
- PROVIDE(__start_bss_RAM3 = .) ;
- *(.bss.$RAM3)
- *(.bss.$RamAHB32)
- *(.bss.$RAM3.*)
- *(.bss.$RamAHB32.*)
- . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
- PROVIDE(__end_bss_RAM3 = .) ;
- } > RamAHB32
-
- /* BSS section for RamAHB16 */
- .bss_RAM4 :
- {
- . = ALIGN(4) ;
- PROVIDE(__start_bss_RAM4 = .) ;
- *(.bss.$RAM4)
- *(.bss.$RamAHB16)
- *(.bss.$RAM4.*)
- *(.bss.$RamAHB16.*)
- . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
- PROVIDE(__end_bss_RAM4 = .) ;
- } > RamAHB16
-
- /* BSS section for RamAHB_ETB16 */
- .bss_RAM5 :
- {
- . = ALIGN(4) ;
- PROVIDE(__start_bss_RAM5 = .) ;
- *(.bss.$RAM5)
- *(.bss.$RamAHB_ETB16)
- *(.bss.$RAM5.*)
- *(.bss.$RamAHB_ETB16.*)
- . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
- PROVIDE(__end_bss_RAM5 = .) ;
- } > RamAHB_ETB16
-
- /* MAIN BSS SECTION */
- .bss :
- {
- . = ALIGN(4) ;
- _bss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4) ;
- _ebss = .;
- PROVIDE(end = .);
- } > RamLoc128
-
- /* NOINIT section for RamLoc72 */
- .noinit_RAM2 (NOLOAD) :
- {
- . = ALIGN(4) ;
- *(.noinit.$RAM2)
- *(.noinit.$RamLoc72)
- *(.noinit.$RAM2.*)
- *(.noinit.$RamLoc72.*)
- . = ALIGN(4) ;
- } > RamLoc72
-
- /* NOINIT section for RamAHB32 */
- .noinit_RAM3 (NOLOAD) :
- {
- . = ALIGN(4) ;
- *(.noinit.$RAM3)
- *(.noinit.$RamAHB32)
- *(.noinit.$RAM3.*)
- *(.noinit.$RamAHB32.*)
- . = ALIGN(4) ;
- } > RamAHB32
-
- /* NOINIT section for RamAHB16 */
- .noinit_RAM4 (NOLOAD) :
- {
- . = ALIGN(4) ;
- *(.noinit.$RAM4)
- *(.noinit.$RamAHB16)
- *(.noinit.$RAM4.*)
- *(.noinit.$RamAHB16.*)
- . = ALIGN(4) ;
- } > RamAHB16
-
- /* NOINIT section for RamAHB_ETB16 */
- .noinit_RAM5 (NOLOAD) :
- {
- . = ALIGN(4) ;
- *(.noinit.$RAM5)
- *(.noinit.$RamAHB_ETB16)
- *(.noinit.$RAM5.*)
- *(.noinit.$RamAHB_ETB16.*)
- . = ALIGN(4) ;
- } > RamAHB_ETB16
-
- /* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD):
- {
- . = ALIGN(4) ;
- _noinit = .;
- *(.noinit*)
- . = ALIGN(4) ;
- _end_noinit = .;
- } > RamLoc128
- PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
- PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0);
-
- /* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
- + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
- + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
- + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
- ) );
-
- /* Provide basic symbols giving location and size of main text
- * block, including initial values of RW data sections. Note that
- * these will need extending to give a complete picture with
- * complex images (e.g multiple Flash banks).
- */
- _image_start = LOADADDR(.text);
- _image_end = LOADADDR(.data) + SIZEOF(.data);
- _image_size = _image_end - _image_start;
-}
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 99d9ac6dd..2c4620b97 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -19,7 +19,7 @@ else ()
set(JLINK_DEVICE ${MCU_VARIANT}_xxaa)
endif ()
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
@@ -84,9 +84,7 @@ function(add_board_target BOARD_TARGET)
# linker file
"LINKER:--script=${LD_FILE_GNU}"
-L${NRFX_DIR}/mdk
- # nanolib
- --specs=nosys.specs
- --specs=nano.specs
+ --specs=nosys.specs --specs=nano.specs
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 4b53b9a4f..29802dc37 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -12,10 +12,20 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_NRF5X \
-DCONFIG_GPIO_AS_PINRESET
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+#CFLAGS += -nostdlib
+#CFLAGS += -D__START=main
-LDFLAGS += -L$(TOP)/${NRFX_DIR}/mdk
+# suppress warning caused by vendor mcu driver
+CFLAGS += \
+ -Wno-error=undef \
+ -Wno-error=unused-parameter \
+ -Wno-error=cast-align \
+ -Wno-error=cast-qual \
+ -Wno-error=redundant-decls
+
+LDFLAGS += \
+ -specs=nosys.specs -specs=nano.specs \
+ -L$(TOP)/${NRFX_DIR}/mdk
SRC_C += \
src/portable/nordic/nrf5x/dcd_nrf5x.c \
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index aa8f00e70..161ff9041 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -13,6 +13,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=redundant-decls
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index bf7610a7b..081764fd3 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -13,6 +13,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=redundant-decls
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/nuc125_flash.ld
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 46f53420c..2466b3a31 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -14,6 +14,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=redundant-decls
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index b1f9245a6..b54895b58 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -9,6 +9,8 @@ CFLAGS += \
-DCFG_EXAMPLE_VIDEO_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_NUC120
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index 3e48d3998..f3b389354 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -12,6 +12,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=redundant-decls
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/nuc505_flashtoram.ld
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 11bc7c668..426e1ca8f 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -11,7 +11,7 @@ set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
#set(FREERTOS_PORT A_CUSTOM_PORT CACHE INTERNAL "")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "")
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 9afb38e06..4447e8499 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -31,6 +31,8 @@ else
$(info "Using PORT 0 FullSpeed")
endif
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/renesas/rusb2/dcd_rusb2.c \
src/portable/renesas/rusb2/hcd_rusb2.c \
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index 3044167b9..02ea0dfa4 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -16,6 +16,8 @@ CFLAGS += \
# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=redundant-decls
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/renesas/rusb2/dcd_rusb2.c \
src/portable/renesas/rusb2/hcd_rusb2.c \
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index 43a60a122..38430f017 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -18,6 +18,8 @@ CFLAGS += -Wno-error=redundant-decls
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
index 07186934a..44aad6ecb 100644
--- a/hw/bsp/samd21/family.cmake
+++ b/hw/bsp/samd21/family.cmake
@@ -7,7 +7,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS SAMD21 CACHE INTERNAL "")
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 79c63812d..3302aade5 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -16,6 +16,8 @@ CFLAGS += -Wno-error=redundant-decls
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
${SDK_DIR}/gcc/gcc/startup_samd21.c \
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake
index fa9586066..7591f3b1b 100644
--- a/hw/bsp/samd51/family.cmake
+++ b/hw/bsp/samd51/family.cmake
@@ -7,7 +7,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS SAMD51 CACHE INTERNAL "")
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 9a6c67e1a..94ca68705 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -12,6 +12,8 @@ CFLAGS += \
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
hw/mcu/microchip/samd51/gcc/gcc/startup_samd51.c \
diff --git a/hw/bsp/same5x/family.mk b/hw/bsp/same5x/family.mk
index 691863f11..b2bf0d359 100644
--- a/hw/bsp/same5x/family.mk
+++ b/hw/bsp/same5x/family.mk
@@ -13,6 +13,8 @@ CFLAGS += \
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
$(SDK_DIR)/gcc/gcc/startup_$(MCU).c \
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index ad5af2020..281a947f3 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -1,4 +1,5 @@
DEPS_SUBMODULES += hw/mcu/microchip
+ASF_DIR = hw/mcu/microchip/same70
CFLAGS += \
-mthumb \
@@ -16,7 +17,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
-ASF_DIR = hw/mcu/microchip/same70
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 769d03e21..3edc128a5 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -1,4 +1,5 @@
DEPS_SUBMODULES += hw/mcu/microchip
+ASF_DIR = hw/mcu/microchip/same70
CFLAGS += \
-mthumb \
@@ -16,7 +17,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
-ASF_DIR = hw/mcu/microchip/same70
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index ed0d59772..a9328be11 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -1,4 +1,5 @@
DEPS_SUBMODULES += hw/mcu/microchip
+ASF_DIR = hw/mcu/microchip/samg55
CFLAGS += \
-flto \
@@ -17,7 +18,7 @@ CFLAGS += -Wno-error=undef -Wno-error=null-dereference -Wno-error=redundant-decl
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
-ASF_DIR = hw/mcu/microchip/samg55
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/samg55j19_flash.ld
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index 0acb0ed14..59dbc9a25 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -16,6 +16,8 @@ CFLAGS += -Wno-error=redundant-decls
# SAM driver is flooded with -Wcast-qual which slow down complication significantly
CFLAGS_SKIP += -Wcast-qual
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index f9c1dd4db..a04bc19d8 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -19,6 +19,8 @@ SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(she
DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
DEPS_SUBMODULES += lib/CMSIS_5
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# All source paths should be relative to the top level.
LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index 78d7f6a66..15fa0ff20 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -38,6 +38,8 @@ CFLAGS += \
# lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
CFLAGS += -Wno-error=shadow -Wno-error=redundant-decls
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
SRC_C += src/portable/sony/cxd56/dcd_cxd56.c
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
index e0fc705f8..89c93c47a 100644
--- a/hw/bsp/stm32f0/family.cmake
+++ b/hw/bsp/stm32f0/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m0 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32F0 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 129a3b73a..537df4d7b 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -23,6 +23,8 @@ CFLAGS_GCC += \
# suppress warning caused by vendor mcu driver
CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-align
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# ------------------------
# All source paths should be relative to the top level.
# ------------------------
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
index 53af35862..6657c85ce 100644
--- a/hw/bsp/stm32f1/family.cmake
+++ b/hw/bsp/stm32f1/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32F1 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index c9321c3cb..90a984bfe 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -18,6 +18,8 @@ CFLAGS_GCC += \
-flto \
-nostdlib -nostartfiles \
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# ------------------------
# All source paths should be relative to the top level.
# ------------------------
@@ -40,6 +42,5 @@ INC += \
SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
-# flash target ROM bootloader
-flash-dfu-util: $(BUILD)/$(PROJECT).bin
- dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
+# flash target ROM bootloader: flash-dfu-util
+DFU_UTIL_OPTION = -a 0 --dfuse-address 0x08000000
diff --git a/hw/bsp/stm32f2/family.mk b/hw/bsp/stm32f2/family.mk
index ce50b16ad..c6ef1ec1d 100644
--- a/hw/bsp/stm32f2/family.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -21,6 +21,8 @@ CFLAGS_GCC += \
# mcu driver cause following warnings
CFLAGS_GCC += -Wno-error=sign-compare
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/synopsys/dwc2/dcd_dwc2.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/stm32f3/family.mk b/hw/bsp/stm32f3/family.mk
index a740e9012..be8271d96 100644
--- a/hw/bsp/stm32f3/family.mk
+++ b/hw/bsp/stm32f3/family.mk
@@ -19,6 +19,8 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake
index cad504bac..71ec33c6e 100644
--- a/hw/bsp/stm32f4/family.cmake
+++ b/hw/bsp/stm32f4/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32F4 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 0f4c792ab..ecbbff417 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -25,6 +25,8 @@ CFLAGS_GCC += \
# suppress warning caused by vendor mcu driver
CFLAGS_GCC += -Wno-error=cast-align
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# -----------------
# Sources & Include
# -----------------
diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake
index 48dd9c7ca..5b3bdf17e 100644
--- a/hw/bsp/stm32f7/family.cmake
+++ b/hw/bsp/stm32f7/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32F7 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 7f37a7e40..1cdf23c6b 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -35,6 +35,8 @@ CFLAGS_GCC += \
# mcu driver cause following warnings
CFLAGS_GCC += -Wno-error=cast-align
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# -----------------
# Sources & Include
# -----------------
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index cf52a6324..0a9779022 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index 6b199f21a..fb382b56a 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -21,6 +21,8 @@ CFLAGS_GCC += \
# suppress warning caused by vendor mcu driver
CFLAGS_GCC += -Wno-error=cast-align
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# -----------------
# Sources & Include
# -----------------
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index eee6bd9ed..15a834a00 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 2efe91449..4b0c6922d 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -22,6 +22,8 @@ CFLAGS_GCC += \
# suppress warning caused by vendor mcu driver
CFLAGS_GCC += -Wno-error=cast-align
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# -----------------
# Sources & Include
# -----------------
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index c08857a50..6174dfda3 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32H7 CACHE INTERNAL "")
@@ -66,9 +66,7 @@ function(add_board_target BOARD_TARGET)
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
-nostartfiles
- # nanolib
- --specs=nosys.specs
- --specs=nano.specs
+ --specs=nosys.specs --specs=nano.specs
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index a1ff26d0b..0777bb9c2 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -35,6 +35,8 @@ CFLAGS_GCC += \
# suppress warning caused by vendor mcu driver
CFLAGS_GCC += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=unused-parameter
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# -----------------
# Sources & Include
# -----------------
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
index 43f567b50..a811e1823 100644
--- a/hw/bsp/stm32l0/family.mk
+++ b/hw/bsp/stm32l0/family.mk
@@ -24,6 +24,8 @@ CFLAGS += \
-Wno-error=cast-align \
-Wno-error=maybe-uninitialized
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
index 87f87004b..9b06a64d4 100644
--- a/hw/bsp/stm32l4/family.cmake
+++ b/hw/bsp/stm32l4/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32L4 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index c16040887..956f82263 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -21,6 +21,8 @@ CFLAGS_GCC += \
# suppress warning caused by vendor mcu driver
CFLAGS_GCC += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
# -----------------
# Sources & Include
# -----------------
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index 2e4ed7d50..cde1df5ca 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -16,7 +16,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS STM32U5 CACHE INTERNAL "")
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index c3e66c5a5..2144ef37b 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -15,6 +15,8 @@ CFLAGS += \
# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=undef -Wno-error=unused-parameter
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/synopsys/dwc2/dcd_dwc2.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
index bc3afcaff..287b58ce5 100644
--- a/hw/bsp/stm32wb/family.mk
+++ b/hw/bsp/stm32wb/family.mk
@@ -16,6 +16,8 @@ CFLAGS += \
# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=cast-align -Wno-unused-parameter
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
SRC_C += \
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
index 608c530bb..49e39f6a0 100644
--- a/hw/bsp/tm4c123/family.mk
+++ b/hw/bsp/tm4c123/family.mk
@@ -1,4 +1,5 @@
DEPS_SUBMODULES += hw/mcu/ti
+MCU_DIR=hw/mcu/ti/tm4c123xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4
@@ -12,7 +13,7 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-MCU_DIR=hw/mcu/ti/tm4c123xx/
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.
LD_FILE = $(BOARD_PATH)/tm4c123.ld
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1797f0bc4..6fab190ea 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -388,6 +388,10 @@
#elif TU_CHECK_MCU(OPT_MCU_CH32V307)
#define TUP_DCD_ENDPOINT_MAX 16
#define TUP_RHPORT_HIGHSPEED 1
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32F20X)
+ #define TUP_DCD_ENDPOINT_MAX 16
+ #define TUP_RHPORT_HIGHSPEED 1
#endif
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 76e77c25d..a07d39828 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -24,11 +24,11 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_OSAL_NONE_H_
-#define _TUSB_OSAL_NONE_H_
+#ifndef TUSB_OSAL_NONE_H_
+#define TUSB_OSAL_NONE_H_
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
//--------------------------------------------------------------------+
@@ -43,39 +43,34 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec);
//--------------------------------------------------------------------+
// Binary Semaphore API
//--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
volatile uint16_t count;
-}osal_semaphore_def_t;
+} osal_semaphore_def_t;
typedef osal_semaphore_def_t* osal_semaphore_t;
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
semdef->count = 0;
return semdef;
}
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
(void) in_isr;
sem_hdl->count++;
return true;
}
// TODO blocking for now
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
(void) msec;
- while (sem_hdl->count == 0) { }
+ while (sem_hdl->count == 0) {}
sem_hdl->count--;
return true;
}
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
sem_hdl->count = 0;
}
@@ -90,19 +85,16 @@ typedef osal_semaphore_t osal_mutex_t;
// Note: multiple cores MCUs usually do provide IPC API for mutex
// or we can use std atomic function
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
mdef->count = 1;
return mdef;
}
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) {
return osal_semaphore_wait(mutex_hdl, msec);
}
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
return osal_semaphore_post(mutex_hdl, false);
}
@@ -119,11 +111,10 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
//--------------------------------------------------------------------+
#include "common/tusb_fifo.h"
-typedef struct
-{
- void (*interrupt_set)(bool);
+typedef struct {
+ void (* interrupt_set)(bool);
tu_fifo_t ff;
-}osal_queue_def_t;
+} osal_queue_def_t;
typedef osal_queue_def_t* osal_queue_t;
@@ -136,27 +127,23 @@ typedef osal_queue_def_t* osal_queue_t;
}
// lock queue by disable USB interrupt
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) {
// disable dcd/hcd interrupt
qhdl->interrupt_set(false);
}
// unlock queue
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) {
// enable dcd/hcd interrupt
qhdl->interrupt_set(true);
}
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
tu_fifo_clear(&qdef->ff);
return (osal_queue_t) qdef;
}
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
(void) msec; // not used, always behave as msec = 0
_osal_q_lock(qhdl);
@@ -166,8 +153,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
return success;
}
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) {
if (!in_isr) {
_osal_q_lock(qhdl);
}
@@ -179,19 +165,17 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
}
TU_ASSERT(success);
-
return success;
}
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
// Skip queue lock/unlock since this function is primarily called
// with interrupt disabled before going into low power mode
return tu_fifo_empty(&qhdl->ff);
}
#ifdef __cplusplus
- }
+}
#endif
-#endif /* _TUSB_OSAL_NONE_H_ */
+#endif
diff --git a/src/portable/wch/ch32v307/ch32_usbhs_reg.h b/src/portable/wch/ch32_usbhs_reg.h
similarity index 98%
rename from src/portable/wch/ch32v307/ch32_usbhs_reg.h
rename to src/portable/wch/ch32_usbhs_reg.h
index 5a2c1fbc9..9b956231f 100644
--- a/src/portable/wch/ch32v307/ch32_usbhs_reg.h
+++ b/src/portable/wch/ch32_usbhs_reg.h
@@ -1,7 +1,11 @@
#ifndef _USB_CH32_USBHS_REG_H
#define _USB_CH32_USBHS_REG_H
+#if (CFG_TUSB_MCU == OPT_MCU_CH32V307)
#include
+#elif (CFG_TUSB_MCU == OPT_MCU_CH32F20X)
+#include
+#endif
/******************* GLOBAL ******************/
diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c
similarity index 98%
rename from src/portable/wch/ch32v307/dcd_usbhs.c
rename to src/portable/wch/dcd_ch32_usbhs.c
index 3ad011cff..1f1c0b876 100644
--- a/src/portable/wch/ch32v307/dcd_usbhs.c
+++ b/src/portable/wch/dcd_ch32_usbhs.c
@@ -26,11 +26,11 @@
#include "tusb_option.h"
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307)
+#if CFG_TUD_ENABLED && ((CFG_TUSB_MCU == OPT_MCU_CH32V307) || (CFG_TUSB_MCU == OPT_MCU_CH32F20X))
#include "device/dcd.h"
#include "ch32_usbhs_reg.h"
-#include "core_riscv.h"
+
// Max number of bi-directional endpoints including EP0
#define EP_MAX 16
@@ -73,7 +73,7 @@ void dcd_init(uint8_t rhport) {
#if TUD_OPT_HIGH_SPEED
USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
#else
- #error OPT_MODE_FULL_SPEED not currently supported on CH32V307
+ #error OPT_MODE_FULL_SPEED not currently supported on CH32
USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index aedc02dbc..cf774a41c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -169,6 +169,7 @@
// WCH
#define OPT_MCU_CH32V307 2200 ///< WCH CH32V307
+#define OPT_MCU_CH32F20X 2210 ///< WCH CH32F20x
// NXP LPC MCX
diff --git a/tools/build_family.py b/tools/build_make.py
similarity index 97%
rename from tools/build_family.py
rename to tools/build_make.py
index fb90e0edb..f79a452e4 100644
--- a/tools/build_family.py
+++ b/tools/build_make.py
@@ -34,6 +34,7 @@ def build_family(example, family, make_option):
# sum all element of same index (column sum)
return list(map(sum, list(zip(*result))))
+
if __name__ == '__main__':
# IAR CC
if make_iar_option not in sys.argv:
@@ -42,7 +43,7 @@ if __name__ == '__main__':
# If examples are not specified in arguments, build all
all_examples = []
for d in os.scandir("examples"):
- if d.is_dir() and 'cmake' not in d.name:
+ if d.is_dir() and 'cmake' not in d.name and 'build_system' not in d.name:
for entry in os.scandir(d.path):
if entry.is_dir() and 'cmake' not in entry.name:
all_examples.append(d.name + '/' + entry.name)
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 6850cacb1..a993d696e 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -164,6 +164,9 @@ deps_optional = {
'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git',
'17761f5cf9dbbf2dcf665b7c04934188add20082',
'ch32v307'],
+ 'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git',
+ '77c4095087e5ed2c548ec9058e655d0b8757663b',
+ 'ch32f20x'],
'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
'20285262657d1b482d132d20d755c8c330d55c1f',
'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index 4919fe7b4..c3683c3d7 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -164,8 +164,8 @@
$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c
-
- $TUSB_DIR$/src/portable/wch/ch32v307/dcd_usbhs.c
+
+ $TUSB_DIR$/src/portable/wch/dcd_ch32_usbhs.c
$TUSB_DIR$/src/typec/usbc.c