clean up SPI code
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ad7754d488
commit
21a2567d1d
61
lib/vfd.c
61
lib/vfd.c
@ -350,7 +350,6 @@ void vfd_matrix(uint8_t nb, char c)
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/* shift out the VFD data */
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void vfd_shift(void)
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{
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// prepare SPI data
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for (uint8_t i=0; i<LENGTH(vfd_data) && (uint8_t)(i*2+1)<LENGTH(vfd_spi); i++) {
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vfd_spi[i*2] = vfd_data[i];
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@ -358,29 +357,8 @@ void vfd_shift(void)
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}
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vfd_spi_i = 0;
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spi_enable(VFD_SPI); // enable SPI (the tx empty interrupt will trigger)
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//while (true) {
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//spi_send(VFD_SPI, vfd_spi[vfd_spi_i++]); // send first data (also enables latch)
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//}
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/*
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gpio_clear(VFD_PORT, VFD_NLE); // do not latch data
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gpio_set(VFD_PORT, VFD_CLK); // clock is idle high
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for (uint8_t i=0; i<sizeof(vfd_data)/sizeof(vfd_data[0]); i++) {
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for (uint8_t b=0; b<32; b++) {
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gpio_clear(VFD_PORT, VFD_CLK); // change data on low
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if (vfd_data[i]&(1<<b)) { // shift the value
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gpio_set(VFD_PORT, VFD_DIN);
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} else {
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gpio_clear(VFD_PORT, VFD_DIN);
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}
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gpio_set(VFD_PORT, VFD_CLK); // signal need to be valid on high edge
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}
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}
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gpio_set(VFD_PORT, VFD_NLE); // latch data
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gpio_clear(VFD_PORT, VFD_NLE); // stop latching data
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*/
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// enable SPI (the tx empty interrupt will trigger)
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spi_enable(VFD_SPI);
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}
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/* transmit every digit and matrix */
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@ -456,15 +434,11 @@ void vfd_off(void)
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void vfd_setup(void)
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{
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rcc_periph_clock_enable(VFD_PORT_RCC); // enable clock for VFD GPIO
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gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, VFD_STR); // set VFD pin to 'output push-pull'
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gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, VFD_NLE); // set VFD pin to alternative function push-pull
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//gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, VFD_DIN);
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//gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, VFD_CLK);
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gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, VFD_STR); // set VFD pin to output push-pull
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gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, VFD_NLE); // set VFD pin to output push-pull
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gpio_set(VFD_PORT, VFD_STR); // disable HV output
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gpio_clear(VFD_PORT, VFD_NLE); // do not output latched data
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//gpio_set(VFD_PORT, VFD_CLK); // clock is idle high
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rcc_periph_clock_enable(VFD_SPI_RCC); // enable SPI clock
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gpio_set_mode(VFD_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, VFD_CLK); // set VFD pin to alternative function push-pull
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@ -479,20 +453,21 @@ void vfd_setup(void)
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* - send 16 bits at a time
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* - send least significant bit first (that's how I coded the data)
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*/
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spi_init_master(VFD_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_LSBFIRST);
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spi_init_master(VFD_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_LSBFIRST);
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//spi_set_bidirectional_transmit_only_mode(VFD_SPI); // only use MOSI to transmit
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//spi_set_unidirectional_mode(VFD_SPI); // MISO is unused
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//spi_disable_software_slave_management(VFD_SPI); // use hardware NSS
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spi_set_unidirectional_mode(VFD_SPI); // MISO is unused
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/* set NSS high to enable transmission
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* the NSS in STM32 can not be used as hardware slave select
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* RM0008 reference manual 25.3.1 is misleading
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* when hardware NSS is used and output is enabled NSS never goes up after transmission, even if SPI is disabled
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* when software NSS is used, NSS can not be set high again, even when writing to the register
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* the slave select must be done manually using GPIO */
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spi_enable_software_slave_management(VFD_SPI);
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//spi_enable_ss_output(VFD_SPI); // allow slave select
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spi_set_nss_high(VFD_SPI); // set NSS high
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spi_enable_tx_buffer_empty_interrupt(VFD_SPI); // enable TX empty interrupt
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nvic_enable_irq(VFD_SPI_IRQ); // enable SPI interrupt
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//spi_enable(VFD_SPI);
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//SPI_CR1(VFD_SPI) &= ~SPI_CR1_SSM;
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//SPI_CR2(VFD_SPI) |= SPI_CR2_SSOE;
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vfd_clear(); // initialize values
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}
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@ -507,13 +482,7 @@ void spi2_isr(void)
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gpio_clear(VFD_PORT, VFD_NLE); // slave select to latch data
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spi_send(VFD_SPI, vfd_spi[vfd_spi_i++]); // send next data
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} else { // all data transmitted
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while (SPI_SR(VFD_SPI) & SPI_SR_BSY); // wait until transmission is complete (not sure it's a good idea in an isr)
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gpio_set(VFD_PORT, VFD_NLE); // output latched data
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//spi_set_nss_high(VFD_SPI); // set NSS high
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spi_clean_disable(VFD_SPI); // disable latch to output data
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//spi_set_nss_high(VFD_SPI); // set NSS high
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gpio_set(GPIOA, GPIO1); // toggle LED
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//gpio_set(VFD_PORT, VFD_NLE); // do not output latched data
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spi_clean_disable(VFD_SPI); // wait for transmission to complete
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}
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}
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}
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@ -37,8 +37,8 @@
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/* latch enable pin
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* store the shifted data on low
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* output the parallel data on high
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* use the SPI NSS (PA4) */
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#define VFD_NLE GPIO_SPI1_NSS
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* use GPIO (PA4) (NSS does not work as SS) */
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#define VFD_NLE GPIO4
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/* clock signal
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* drive using SPI SCK (PA5) */
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#define VFD_CLK GPIO_SPI1_SCK
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