diff --git a/.gitmodules b/.gitmodules index ad85278b..9afa0d19 100644 --- a/.gitmodules +++ b/.gitmodules @@ -16,3 +16,6 @@ [submodule "hw/mcu/sony/cxd56/spresense-exported-sdk"] path = hw/mcu/sony/cxd56/spresense-exported-sdk url = https://github.com/sonydevworld/spresense-exported-sdk.git +[submodule "hw/mcu/ti"] + path = hw/mcu/ti + url = https://github.com/hathach/ti_driver.git diff --git a/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject b/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject index d07cc68f..f25307dd 100644 --- a/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject +++ b/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject @@ -19,7 +19,7 @@ arm_target_interface_type="SWD" build_treat_warnings_as_errors="Yes" c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;CFG_TUSB_MCU=OPT_MCU_LPC13XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss3")));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))" - c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc;$(rootDir)/src" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc13xx/lpc_chip_13xx/inc;$(rootDir)/src" debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml" debug_target_connection="J-Link" gcc_enable_all_warnings="Yes" diff --git a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c index ce093ed2..f7fc16ec 100644 --- a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c +++ b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c @@ -58,8 +58,6 @@ static const PINMUX_GRP_T pinmuxing[] = {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX }; - -#if 1 /* Setup system clocking */ static void SystemSetupClocking(void) { @@ -114,13 +112,11 @@ static void SystemSetupClocking(void) /* Wait for PLL to lock */ while (!Chip_Clock_IsUSBPLLLocked()) {} } -#endif // Invoked by startup code void SystemInit(void) { SystemSetupClocking(); -// Chip_SystemInit(); Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1); /* Enable IOCON clock */ diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk index 4e0c7039..0f9be1b5 100644 --- a/hw/bsp/lpcxpresso1347/board.mk +++ b/hw/bsp/lpcxpresso1347/board.mk @@ -7,7 +7,7 @@ CFLAGS += \ -D__USE_LPCOPEN \ -DCFG_EXAMPLE_MSC_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \ - -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \ + -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' # startup.c and lpc_types.h cause following errors diff --git a/hw/bsp/lpcxpresso1549/board.mk b/hw/bsp/lpcxpresso1549/board.mk new file mode 100644 index 00000000..929c63a8 --- /dev/null +++ b/hw/bsp/lpcxpresso1549/board.mk @@ -0,0 +1,45 @@ +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m3 \ + -nostdlib \ + -DCORE_M3 \ + -D__USE_LPCOPEN \ + -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_TUSB_MCU=OPT_MCU_LPC15XX \ + -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' + +# mcu driver cause following warnings +CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable + +MCU_DIR = hw/mcu/nxp/lpc_driver/lpc15xx/lpc_chip_15xx + +# All source paths should be relative to the top level. +LD_FILE = hw/bsp/$(BOARD)/lpc1549.ld + +SRC_C += \ + $(MCU_DIR)/../gcc/cr_startup_lpc15xx.c \ + $(MCU_DIR)/src/chip_15xx.c \ + $(MCU_DIR)/src/clock_15xx.c \ + $(MCU_DIR)/src/gpio_15xx.c \ + $(MCU_DIR)/src/iocon_15xx.c \ + $(MCU_DIR)/src/swm_15xx.c \ + $(MCU_DIR)/src/sysctl_15xx.c \ + $(MCU_DIR)/src/sysinit_15xx.c + +INC += \ + $(TOP)/$(MCU_DIR)/inc + +# For TinyUSB port source +VENDOR = nxp +CHIP_FAMILY = lpc_ip3511 + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM3 + +# For flash-jlink target +JLINK_DEVICE = LPC1549 +JLINK_IF = swd + +# flash using jlink +flash: flash-jlink diff --git a/hw/bsp/lpcxpresso1549/lpc1549.ld b/hw/bsp/lpcxpresso1549/lpc1549.ld new file mode 100644 index 00000000..6dd12ade --- /dev/null +++ b/hw/bsp/lpcxpresso1549/lpc1549.ld @@ -0,0 +1,246 @@ +/* + * GENERATED FILE - DO NOT EDIT + * Copyright (c) 2008-2013 Code Red Technologies Ltd, + * Copyright 2015, 2018-2019 NXP + * (c) NXP Semiconductors 2013-2019 + * Generated linker script file for LPC1549 + * Created from linkscript.ldt by FMCreateLinkLibraries + * Using Freemarker v2.3.23 + * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Oct 3, 2019 2:55:18 PM + */ + + +MEMORY +{ + /* Define each memory region */ + MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */ + Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */ + Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */ + Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */ +} + + /* Define a symbol for the top of each memory region */ + __base_MFlash256 = 0x0 ; /* MFlash256 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */ + __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */ + __base_Ram0_16 = 0x2000000 ; /* Ram0_16 */ + __base_RAM = 0x2000000 ; /* RAM */ + __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */ + __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */ + __base_Ram1_16 = 0x2004000 ; /* Ram1_16 */ + __base_RAM2 = 0x2004000 ; /* RAM2 */ + __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */ + __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */ + __base_Ram2_4 = 0x2008000 ; /* Ram2_4 */ + __base_RAM3 = 0x2008000 ; /* RAM3 */ + __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */ + __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */ + +ENTRY(ResetISR) + +SECTIONS +{ + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + __vectors_start__ = ABSOLUTE(.) ; + KEEP(*(.isr_vector)) + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)); + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)); + LONG( SIZEOF(.data_RAM2)); + LONG(LOADADDR(.data_RAM3)); + LONG( ADDR(.data_RAM3)); + LONG( SIZEOF(.data_RAM3)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + LONG( ADDR(.bss_RAM3)); + LONG( SIZEOF(.bss_RAM3)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + *(.after_vectors*) + + } > MFlash256 + + .text : ALIGN(4) + { + *(.text*) + *(.rodata .rodata.* .constdata .constdata.*) + . = ALIGN(4); + } > MFlash256 + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > MFlash256 + + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > MFlash256 + __exidx_end = .; + + _etext = .; + + /* DATA section for Ram1_16 */ + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM2 = .) ; + *(.ramfunc.$RAM2) + *(.ramfunc.$Ram1_16) + *(.data.$RAM2) + *(.data.$Ram1_16) + *(.data.$RAM2.*) + *(.data.$Ram1_16.*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM2 = .) ; + } > Ram1_16 AT>MFlash256 + /* DATA section for Ram2_4 */ + + .data_RAM3 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM3 = .) ; + *(.ramfunc.$RAM3) + *(.ramfunc.$Ram2_4) + *(.data.$RAM3) + *(.data.$Ram2_4) + *(.data.$RAM3.*) + *(.data.$Ram2_4.*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM3 = .) ; + } > Ram2_4 AT>MFlash256 + /* MAIN DATA SECTION */ + .uninit_RESERVED (NOLOAD) : + { + . = ALIGN(4) ; + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4) ; + _end_uninit_RESERVED = .; + } > Ram0_16 + + /* Main DATA section (Ram0_16) */ + .data : ALIGN(4) + { + FILL(0xff) + _data = . ; + *(vtable) + *(.ramfunc*) + *(.data*) + . = ALIGN(4) ; + _edata = . ; + } > Ram0_16 AT>MFlash256 + + /* BSS section for Ram1_16 */ + .bss_RAM2 : + { + . = ALIGN(4) ; + PROVIDE(__start_bss_RAM2 = .) ; + *(.bss.$RAM2) + *(.bss.$Ram1_16) + *(.bss.$RAM2.*) + *(.bss.$Ram1_16.*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM2 = .) ; + } > Ram1_16 + + /* BSS section for Ram2_4 */ + .bss_RAM3 : + { + . = ALIGN(4) ; + PROVIDE(__start_bss_RAM3 = .) ; + *(.bss.$RAM3) + *(.bss.$Ram2_4) + *(.bss.$RAM3.*) + *(.bss.$Ram2_4.*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM3 = .) ; + } > Ram2_4 + + /* MAIN BSS SECTION */ + .bss : + { + . = ALIGN(4) ; + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + } > Ram0_16 + + /* NOINIT section for Ram1_16 */ + .noinit_RAM2 (NOLOAD) : + { + . = ALIGN(4) ; + *(.noinit.$RAM2) + *(.noinit.$Ram1_16) + *(.noinit.$RAM2.*) + *(.noinit.$Ram1_16.*) + . = ALIGN(4) ; + } > Ram1_16 + + /* NOINIT section for Ram2_4 */ + .noinit_RAM3 (NOLOAD) : + { + . = ALIGN(4) ; + *(.noinit.$RAM3) + *(.noinit.$Ram2_4) + *(.noinit.$RAM3.*) + *(.noinit.$Ram2_4.*) + . = ALIGN(4) ; + } > Ram2_4 + + /* DEFAULT NOINIT SECTION */ + .noinit (NOLOAD): + { + . = ALIGN(4) ; + _noinit = .; + *(.noinit*) + . = ALIGN(4) ; + _end_noinit = .; + } > Ram0_16 + PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); + PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0); + + /* ## Create checksum value (used in startup) ## */ + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ + ) ); + + /* Provide basic symbols giving location and size of main text + * block, including initial values of RW data sections. Note that + * these will need extending to give a complete picture with + * complex images (e.g multiple Flash banks). + */ + _image_start = LOADADDR(.text); + _image_end = LOADADDR(.data) + SIZEOF(.data); + _image_size = _image_end - _image_start; +} \ No newline at end of file diff --git a/hw/bsp/lpcxpresso1549/lpcxpresso1549.c b/hw/bsp/lpcxpresso1549/lpcxpresso1549.c new file mode 100644 index 00000000..e10e2402 --- /dev/null +++ b/hw/bsp/lpcxpresso1549/lpcxpresso1549.c @@ -0,0 +1,126 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "chip.h" +#include "../board.h" + +#define LED_PORT 0 +#define LED_PIN 25 + +// Wake Switch +#define BUTTON_PORT 0 +#define BUTTON_PIN 17 + +/* System oscillator rate and RTC oscillator rate */ +const uint32_t OscRateIn = 12000000; +const uint32_t RTCOscRateIn = 32768; + +/* Pin muxing table, only items that need changing from their default pin + state are in this table. */ +static const PINMUX_GRP_T pinmuxing[] = +{ + {1, 11, (IOCON_MODE_PULLDOWN | IOCON_DIGMODE_EN)}, /* PIO1_11-ISP_1 (VBUS) */ +}; + +// Invoked by startup code +void SystemInit(void) +{ + Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON); + Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); + Chip_SYSCTL_PeriphReset(RESET_IOCON); + + // Pin Mux + Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); + + Chip_SetupXtalClocking(); +} + +void board_init(void) +{ + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + Chip_GPIO_Init(LPC_GPIO); + + // LED + Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN); + + // Button + Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN); + + // USB: Setup PLL clock, and power + Chip_SWM_MovablePortPinAssign(SWM_USB_VBUS_I, 1, 11); + Chip_USB_Init(); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +void board_led_write(bool state) +{ + Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state); +} + +uint32_t board_button_read(void) +{ + // active low + return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1; +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + (void) buf; + (void) len; + return 0; +} diff --git a/hw/bsp/stm32f103bluepill/STM32F103XB_FLASH.ld b/hw/bsp/stm32f103bluepill/STM32F103XB_FLASH.ld new file mode 100644 index 00000000..4be9df61 --- /dev/null +++ b/hw/bsp/stm32f103bluepill/STM32F103XB_FLASH.ld @@ -0,0 +1,167 @@ +/* +***************************************************************************** +** +** File : STM32F103XB_FLASH.ld +** +** Abstract : Linker script for STM32F103xB Device with +** 128KByte FLASH, 20KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20004FFF; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32f103bluepill/board.mk b/hw/bsp/stm32f103bluepill/board.mk index 4758edf1..26ad07b7 100644 --- a/hw/bsp/stm32f103bluepill/board.mk +++ b/hw/bsp/stm32f103bluepill/board.mk @@ -15,7 +15,7 @@ ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F1xx_HAL_Driver ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F1xx # All source paths should be relative to the top level. -LD_FILE = $(ST_CMSIS)/Source/Templates/gcc/linker/STM32F103XB_FLASH.ld +LD_FILE = hw/bsp/$(BOARD)/STM32F103XB_FLASH.ld SRC_C += \ $(ST_CMSIS)/Source/Templates/system_stm32f1xx.c \ diff --git a/hw/bsp/stm32l476disco/stm32l476disco.c b/hw/bsp/stm32l476disco/stm32l476disco.c index ab8f1322..8e01814c 100644 --- a/hw/bsp/stm32l476disco/stm32l476disco.c +++ b/hw/bsp/stm32l476disco/stm32l476disco.c @@ -28,6 +28,7 @@ #include "stm32l4xx.h" #include "stm32l4xx_hal_conf.h" +#include "stm32l4xx_hal.h" #define LED_PORT GPIOB #define LED_PIN GPIO_PIN_2 @@ -117,8 +118,6 @@ void board_init(void) SystemClock_Config(); - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_1);//RCC_MCO1SOURCE_SYSCLK - /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); @@ -165,20 +164,12 @@ void board_init(void) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /* This for ID line */ - GPIO_InitStruct.Pin = GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /* Enable USB FS Clock */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); } //--------------------------------------------------------------------+ -// Board porting API +// board porting API //--------------------------------------------------------------------+ void board_led_write(bool state) diff --git a/hw/mcu/nxp/lpc_driver b/hw/mcu/nxp/lpc_driver index 7d2ca412..fa206508 160000 --- a/hw/mcu/nxp/lpc_driver +++ b/hw/mcu/nxp/lpc_driver @@ -1 +1 @@ -Subproject commit 7d2ca4123ec4fe04c6ea0aa2662d7a6aebc0c4f7 +Subproject commit fa206508e9ea289ceeb9c35442dd8002002f9316 diff --git a/hw/mcu/ti b/hw/mcu/ti new file mode 160000 index 00000000..14fd86b9 --- /dev/null +++ b/hw/mcu/ti @@ -0,0 +1 @@ +Subproject commit 14fd86b9a69d7fef42d1045ef88fd8bcabe1be49 diff --git a/src/device/dcd.h b/src/device/dcd.h index 168eb181..bef062fb 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -42,7 +42,7 @@ typedef enum DCD_EVENT_BUS_RESET = 1, DCD_EVENT_UNPLUGGED, DCD_EVENT_SOF, - DCD_EVENT_SUSPEND, + DCD_EVENT_SUSPEND, // TODO LPM Sleep L1 support DCD_EVENT_RESUME, DCD_EVENT_SETUP_RECEIVED, diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 160eefb2..5b2bd83e 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -28,9 +28,11 @@ /* Since 2012 starting with LPC11uxx, NXP start to use common USB Device Controller with code name LPC IP3511 * for almost their new MCUs. Currently supported and tested families are - * - LPC11Uxx - * - LPC13xx - * - LPC51Uxx + * - LPC11U68, LPC11U37 + * - LPC1347 + * - LPC51U68 + * - LPC54114 + * - LPC55s69 * * For similar controller of other families, this file may require some minimal changes to work with. * Previous MCUs such as LPC17xx, LPC40xx, LPC18xx, LPC43xx have their own driver implementation. @@ -38,20 +40,23 @@ #if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \ CFG_TUSB_MCU == OPT_MCU_LPC13XX || \ + CFG_TUSB_MCU == OPT_MCU_LPC15XX || \ CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \ CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ CFG_TUSB_MCU == OPT_MCU_LPC55XX) -#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX - // LPC11Uxx and LPC13xx use lpcopen +#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX + // LPC 11Uxx, 13xx, 15xx use lpcopen #include "chip.h" #define DCD_REGS LPC_USB #define DCD_IRQHandler USB_IRQHandler + #elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ CFG_TUSB_MCU == OPT_MCU_LPC55XX // TODO 55xx has dual usb controllers #include "fsl_device_registers.h" #define DCD_REGS USB0 #define DCD_IRQHandler USB0_IRQHandler + #endif #include "device/dcd.h" @@ -61,6 +66,9 @@ //--------------------------------------------------------------------+ // Number of endpoints +// - 11 13 15 51 54 has 5x2 endpoints +// - 18/43 usb0 & 55s usb1 (HS) has 6x2 endpoints +// - 18/43 usb1 & 55s usb0 (FS) has 4x2 endpoints #define EP_COUNT 10 // only SRAM1 & USB RAM can be used for transfer. @@ -166,7 +174,7 @@ void dcd_init(uint8_t rhport) DCD_REGS->INTSTAT = DCD_REGS->INTSTAT; // clear all pending interrupt DCD_REGS->INTEN = INT_DEVICE_STATUS_MASK; DCD_REGS->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK | - CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK; + CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK; NVIC_ClearPendingIRQ(USB0_IRQn); } @@ -270,7 +278,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes); - return true; + return true; } //--------------------------------------------------------------------+ @@ -329,7 +337,7 @@ static void process_xfer_isr(uint32_t int_status) void DCD_IRQHandler(void) { - uint32_t const dev_cmd_stat = DCD_REGS->DEVCMDSTAT; + uint32_t const cmd_stat = DCD_REGS->DEVCMDSTAT; uint32_t int_status = DCD_REGS->INTSTAT & DCD_REGS->INTEN; DCD_REGS->INTSTAT = int_status; // Acknowledge handled interrupt @@ -340,16 +348,16 @@ void DCD_IRQHandler(void) if ( int_status & INT_DEVICE_STATUS_MASK ) { DCD_REGS->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK; - if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset + if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset { bus_reset(); dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); } - if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK) + if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK) { // device disconnect - if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK) + if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK) { // debouncing as this can be set when device is powering dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); @@ -357,12 +365,12 @@ void DCD_IRQHandler(void) } // TODO support suspend & resume - if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK) + if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK) { - if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) + if (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) { // suspend signal, bus idle for more than 3ms // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. - if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK) + if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK) { dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } @@ -376,7 +384,7 @@ void DCD_IRQHandler(void) } // Setup Receive - if ( tu_bit_test(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) ) + if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) ) { // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0; diff --git a/src/tusb_option.h b/src/tusb_option.h index 28664c73..6178b2cf 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -38,7 +38,8 @@ // LPC #define OPT_MCU_LPC11UXX 1 ///< NXP LPC11Uxx -#define OPT_MCU_LPC13XX 3 ///< NXP LPC13xx +#define OPT_MCU_LPC13XX 2 ///< NXP LPC13xx +#define OPT_MCU_LPC15XX 3 ///< NXP LPC15xx #define OPT_MCU_LPC175X_6X 4 ///< NXP LPC175x, LPC176x #define OPT_MCU_LPC177X_8X 5 ///< NXP LPC177x, LPC178x #define OPT_MCU_LPC18XX 6 ///< NXP LPC18xx