diff --git a/demos/bsp/boards/board.h b/demos/bsp/boards/board.h
index 52fac569..e058fcb2 100644
--- a/demos/bsp/boards/board.h
+++ b/demos/bsp/boards/board.h
@@ -118,9 +118,10 @@
//--------------------------------------------------------------------+
// Init board peripherals : Clock, UART, LEDs, Buttons
void board_init(void);
+
void board_leds(uint32_t on_mask, uint32_t off_mask);
+
uint32_t board_uart_send(uint8_t *buffer, uint32_t length);
-uint32_t board_uart_recv(uint8_t *buffer, uint32_t length);
uint8_t board_uart_getchar(void);
extern volatile uint32_t system_ticks;
diff --git a/demos/bsp/boards/embedded_artists/ea4357/emac.c b/demos/bsp/boards/embedded_artists/ea4357/emac.c
index c337548d..d7b6ae78 100644
--- a/demos/bsp/boards/embedded_artists/ea4357/emac.c
+++ b/demos/bsp/boards/embedded_artists/ea4357/emac.c
@@ -15,6 +15,10 @@
***** *****
******************************************************************/
+#include "../../board.h"
+
+#if BOARD == BOARD_EA4357
+
#include "EMAC.h"
//#include "tcpip.h"
#include "lpc43xx.h"
@@ -472,3 +476,5 @@ void CopyToFrame_EMAC(void *Source, unsigned int Size)
TxDescIndex = 0;
}
+#endif
+
diff --git a/demos/bsp/boards/embedded_artists/ea4357/nand.c b/demos/bsp/boards/embedded_artists/ea4357/nand.c
index ddacf6c2..62b2aea8 100644
--- a/demos/bsp/boards/embedded_artists/ea4357/nand.c
+++ b/demos/bsp/boards/embedded_artists/ea4357/nand.c
@@ -20,6 +20,9 @@
/******************************************************************************
* Includes
*****************************************************************************/
+#include "../../board.h"
+
+#if BOARD == BOARD_EA4357
#include "lpc_types.h"
#include "lpc43xx_scu.h"
@@ -383,7 +386,7 @@ uint32_t nand_isBlockValid(uint32_t block)
*
* Params:
* block - block number to read from
- * page - page withín block to read from
+ * page - page with�n block to read from
* pageBuf - data is copied to this buffer. The size must be at least
* pageSize.
*
@@ -540,4 +543,4 @@ uint32_t nand_eraseBlock(uint32_t block)
return ((nandStatus() & 0x01) != 0x01);
}
-
+#endif
diff --git a/demos/bsp/boards/embedded_artists/ea4357/sdram.c b/demos/bsp/boards/embedded_artists/ea4357/sdram.c
index a049cd01..92d8cd13 100644
--- a/demos/bsp/boards/embedded_artists/ea4357/sdram.c
+++ b/demos/bsp/boards/embedded_artists/ea4357/sdram.c
@@ -21,6 +21,9 @@
/******************************************************************************
* Includes
*****************************************************************************/
+#include "../../board.h"
+
+#if BOARD == BOARD_EA4357
#include "lpc43xx.h"
#include "lpc_types.h"
@@ -265,3 +268,5 @@ uint32_t sdram_test( void )
}
return 0x1;
}
+
+#endif
diff --git a/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c b/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c
index 39f08c8b..f08ae8b8 100644
--- a/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c
+++ b/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c
@@ -107,10 +107,11 @@ uint32_t board_uart_send(uint8_t *buffer, uint32_t length)
return UART_Send(BOARD_UART_PORT, buffer, length, BLOCKING);
}
-uint32_t board_uart_recv(uint8_t *buffer, uint32_t length)
+uint8_t board_uart_getchar(void)
{
- return UART_Receive(BOARD_UART_PORT, buffer, length, BLOCKING);
+ return UART_ReceiveByte(BOARD_UART_PORT);
}
+
#endif
#endif
diff --git a/demos/bsp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_libcfg_default.c b/demos/bsp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_libcfg_default.c
deleted file mode 100644
index f0f15fff..00000000
--- a/demos/bsp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_libcfg_default.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/**********************************************************************
-* $Id$ lpc17xx_libcfg_default.c 2010-05-21
-*//**
-* @file lpc17xx_libcfg_default.c
-* @brief Library configuration source file (default), used to build
-* library without examples
-* @version 2.0
-* @date 21. May. 2010
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2010, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers. This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Library group ----------------------------------------------------------- */
-/** @addtogroup LIBCFG_DEFAULT
- * @{
- */
-
-/* Includes ------------------------------------------------------------------- */
-#include "lpc17xx_libcfg_default.h"
-
-/* Public Functions ----------------------------------------------------------- */
-/** @addtogroup LIBCFG_DEFAULT_Public_Functions
- * @{
- */
-
-#ifndef __BUILD_WITH_EXAMPLE__
-
-#ifdef DEBUG
-/*******************************************************************************
-* @brief Reports the name of the source file and the source line number
-* where the CHECK_PARAM error has occurred.
-* @param[in] file Pointer to the source file name
-* @param[in] line assert_param error line source number
-* @return None
-*******************************************************************************/
-void check_failed(uint8_t *file, uint32_t line)
-{
- /* User can add his own implementation to report the file name and line number,
- ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
- /* Infinite loop */
- while(1);
-}
-#endif /* DEBUG */
-
-#endif /* __BUILD_WITH_EXAMPLE__ */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */
diff --git a/demos/device/device_os_none/tusb_config.h b/demos/device/device_os_none/tusb_config.h
index 4bf886b5..71a14acd 100644
--- a/demos/device/device_os_none/tusb_config.h
+++ b/demos/device/device_os_none/tusb_config.h
@@ -73,6 +73,8 @@
#define TUSB_CFG_HOST_HID_MOUSE 0
#define TUSB_CFG_HOST_HID_GENERIC 0
#define TUSB_CFG_HOST_MSC 0
+#define TUSB_CFG_HOST_CDC 0
+#define TUSB_CFG_HOST_CDC_RNDIS 0
//--------------------------------------------------------------------+
// DEVICE CONFIGURATION
@@ -96,8 +98,9 @@
//--------------------------------------------------------------------+
#define TUSB_CFG_DEBUG 3
-#define TUSB_CFG_OS TUSB_OS_NONE // defined using eclipse build
+//#define TUSB_CFG_OS TUSB_OS_NONE // defined using eclipse build
//#define TUSB_CFG_OS_TASK_PRIO
+
#define TUSB_CFG_OS_TICKS_PER_SECOND 1000
#ifdef __CODE_RED // make use of code red's support for ram region macros
@@ -112,10 +115,19 @@
#endif
#define TUSB_CFG_ATTR_USBRAM __attribute__ ((section(TUSB_RAM_SECTION)))
+
#elif defined __CC_ARM // Compiled with Keil armcc
+
#define TUSB_CFG_ATTR_USBRAM
+
+#elif __ICCARM__ // compiled with IAR
+
+ #define TUSB_CFG_ATTR_USBRAM @ ".ahb_sram1"
+
#else
+
#error compiler not specified
+
#endif
diff --git a/demos/host/host_os_none/.cproject b/demos/host/host_os_none/.cproject
index cda33db1..3bc0c150 100644
--- a/demos/host/host_os_none/.cproject
+++ b/demos/host/host_os_none/.cproject
@@ -461,6 +461,102 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -468,86 +564,73 @@
<?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="60000"/>
-<infoList vendor="NXP"><info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC4357</name>
-<family>LPC43xx</family>
+<Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"><chip><name>LPC1769</name>
+<family>LPC17xx</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/>
-<memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/>
<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/>
-<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/>
-<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/>
-<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/>
-<peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/>
-<peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/>
-<peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/>
-<peripheralInstance derived_from="SCT" determined="infoFile" id="SCT" location="0x40000000"/>
-<peripheralInstance derived_from="GPDMA" determined="infoFile" id="GPDMA" location="0x40002000"/>
-<peripheralInstance derived_from="SPIFI" determined="infoFile" id="SPIFI" location="0x40003000"/>
-<peripheralInstance derived_from="SDMMC" determined="infoFile" id="SDMMC" location="0x40004000"/>
-<peripheralInstance derived_from="EMC" determined="infoFile" id="EMC" location="0x40005000"/>
-<peripheralInstance derived_from="USB0" determined="infoFile" id="USB0" location="0x40006000"/>
-<peripheralInstance derived_from="USB1" determined="infoFile" id="USB1" location="0x40007000"/>
-<peripheralInstance derived_from="LCD" determined="infoFile" id="LCD" location="0x40008000"/>
-<peripheralInstance derived_from="EEPROM" determined="infoFile" id="EEPROM" location="0x4000e000"/>
-<peripheralInstance derived_from="ETHERNET" determined="infoFile" id="ETHERNET" location="0x40010000"/>
-<peripheralInstance derived_from="ATIMER" determined="infoFile" id="ATIMER" location="0x40040000"/>
-<peripheralInstance derived_from="REGFILE" determined="infoFile" id="REGFILE" location="0x40041000"/>
-<peripheralInstance derived_from="PMC" determined="infoFile" id="PMC" location="0x40042000"/>
-<peripheralInstance derived_from="CREG" determined="infoFile" id="CREG" location="0x40043000"/>
-<peripheralInstance derived_from="EVENTROUTER" determined="infoFile" id="EVENTROUTER" location="0x40044000"/>
-<peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40046000"/>
-<peripheralInstance derived_from="CGU" determined="infoFile" id="CGU" location="0x40050000"/>
-<peripheralInstance derived_from="CCU1" determined="infoFile" id="CCU1" location="0x40051000"/>
-<peripheralInstance derived_from="CCU2" determined="infoFile" id="CCU2" location="0x40052000"/>
-<peripheralInstance derived_from="RGU" determined="infoFile" id="RGU" location="0x40053000"/>
-<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40080000"/>
-<peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40081000"/>
-<peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x400c1000"/>
-<peripheralInstance derived_from="USART3" determined="infoFile" id="USART3" location="0x400c2000"/>
-<peripheralInstance derived_from="UART1" determined="infoFile" id="UART1" location="0x40082000"/>
-<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40083000"/>
-<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x400c5000"/>
-<peripheralInstance derived_from="TIMER0" determined="infoFile" id="TIMER0" location="0x40084000"/>
-<peripheralInstance derived_from="TIMER1" determined="infoFile" id="TIMER1" location="0x40085000"/>
-<peripheralInstance derived_from="TIMER2" determined="infoFile" id="TIMER2" location="0x400c3000"/>
-<peripheralInstance derived_from="TIMER3" determined="infoFile" id="TIMER3" location="0x400c4000"/>
-<peripheralInstance derived_from="SCU" determined="infoFile" id="SCU" location="0x40086000"/>
-<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x40087000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x40088000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40089000"/>
-<peripheralInstance derived_from="MCPWM" determined="infoFile" id="MCPWM" location="0x400a0000"/>
-<peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x400a1000"/>
-<peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x400e0000"/>
-<peripheralInstance derived_from="I2S0" determined="infoFile" id="I2S0" location="0x400a2000"/>
-<peripheralInstance derived_from="I2S1" determined="infoFile" id="I2S1" location="0x400a3000"/>
-<peripheralInstance derived_from="C-CAN1" determined="infoFile" id="C-CAN1" location="0x400a4000"/>
-<peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x400c0000"/>
-<peripheralInstance derived_from="QEI" determined="infoFile" id="QEI" location="0x400c6000"/>
-<peripheralInstance derived_from="GIMA" determined="infoFile" id="GIMA" location="0x400c7000"/>
-<peripheralInstance derived_from="DAC" determined="infoFile" id="DAC" location="0x400e1000"/>
-<peripheralInstance derived_from="C-CAN0" determined="infoFile" id="C-CAN0" location="0x400e2000"/>
-<peripheralInstance derived_from="ADC0" determined="infoFile" id="ADC0" location="0x400e3000"/>
-<peripheralInstance derived_from="ADC1" determined="infoFile" id="ADC1" location="0x400e4000"/>
-<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x400f4000"/>
-<peripheralInstance derived_from="SPI" determined="infoFile" id="SPI" location="0x40100000"/>
-<peripheralInstance derived_from="SGPIO" determined="infoFile" id="SGPIO" location="0x40101000"/>
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
+<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
+<peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&0x1" id="TIMER0" location="0x40004000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&0x1" id="TIMER1" location="0x40008000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&0x1" id="TIMER2" location="0x40090000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&0x1" id="TIMER3" location="0x40094000"/>
+<peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&0x1" id="RIT" location="0x400B0000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO0" location="0x2009C000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO1" location="0x2009C020"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO2" location="0x2009C040"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO3" location="0x2009C060"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO4" location="0x2009C080"/>
+<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&0x08000000" id="I2S" location="0x400A8000"/>
+<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/>
+<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&0x2=2" id="DAC" location="0x4008C000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&0x1" id="UART0" location="0x4000C000"/>
+<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&0x1" id="UART1" location="0x40010000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&0x1" id="UART2" location="0x40098000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&0x1" id="UART3" location="0x4009C000"/>
+<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&0x1" id="SPI" location="0x40020000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&0x1" id="SSP0" location="0x40088000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&0x1" id="SSP1" location="0x40030000"/>
+<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&0x1" id="ADC" location="0x40034000"/>
+<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&0x12" id="USBINTSTAT" location="0x400fc1c0"/>
+<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/>
+<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&0x12=0x12" id="USBDEV" location="0x5000C200"/>
+<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&0x1" id="PWM" location="0x40018000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&0x1" id="I2C0" location="0x4001C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&0x1" id="I2C1" location="0x4005C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&0x1" id="I2C2" location="0x400A0000"/>
+<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&0x1" id="DMA" location="0x50004000"/>
+<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&0x1" id="ENET" location="0x50000000"/>
+<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/>
+<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/>
+<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&0x1" id="QEI" location="0x400bc000"/>
+<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&0x11=0x11" id="USBHOST" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&0x1" id="RTC" location="0x40024000"/>
+<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/>
+<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/>
+<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/>
+<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/>
+<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANAFR" location="0x4003C000"/>
+<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANCEN" location="0x40040000"/>
+<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&0x1" id="CANCON1" location="0x40044000"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&0x1" id="CANCON2" location="0x40048000"/>
+<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&0x1" id="MCPWM" location="0x400B8000"/>
+<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/>
</chip>
-<processor><name gcc_name="cortex-m4">Cortex-M4</name>
+<processor><name gcc_name="cortex-m3">Cortex-M3</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig>
diff --git a/demos/host/src/tusb_config.h b/demos/host/src/tusb_config.h
index 3239c35a..fc1399ca 100644
--- a/demos/host/src/tusb_config.h
+++ b/demos/host/src/tusb_config.h
@@ -36,12 +36,6 @@
*/
/**************************************************************************/
-/** \file
- * \brief TBD
- *
- * \note TBD
- */
-
/** \ingroup TBD
* \defgroup TBD
* \brief TBD
@@ -59,8 +53,9 @@
//--------------------------------------------------------------------+
// CONTROLLER CONFIGURATION
//--------------------------------------------------------------------+
+//#define TUSB_CFG_MCU will be passed from IDE for easy board/mcu switching
#define TUSB_CFG_CONTROLLER_0_MODE (TUSB_MODE_HOST)
-#define TUSB_CFG_CONTROLLER_1_MODE (TUSB_MODE_NONE)
+#define TUSB_CFG_CONTROLLER_1_MODE (TUSB_MODE_NONE) // TODO not yet tested
//--------------------------------------------------------------------+
// HOST CONFIGURATION
@@ -83,16 +78,19 @@
//--------------------------------------------------------------------+
// DEVICE CONFIGURATION
//--------------------------------------------------------------------+
+#define TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE 64 // TODO refractor remove
+#define TUSB_CFG_DEVICE_STRING_DESCRIPTOR_COUNT 4
//------------- CLASS -------------//
-//#define TUSB_CFG_DEVICE_CDC
-//#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
-//#define TUSB_CFG_DEVICE_HID_MOUSE 1
+#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
+#define TUSB_CFG_DEVICE_HID_MOUSE 0
+#define TUSB_CFG_DEVICE_HID_GENERIC 0
+#define TUSB_CFG_DEVICE_MSC 0
+#define TUSB_CFG_DEVICE_CDC 0
//--------------------------------------------------------------------+
// COMMON CONFIGURATION
//--------------------------------------------------------------------+
-
#define TUSB_CFG_DEBUG 3
//#define TUSB_CFG_OS TUSB_OS_NONE // defined using eclipse build
@@ -101,19 +99,31 @@
#define TUSB_CFG_OS_TICKS_PER_SECOND 1000
#ifdef __CODE_RED // make use of code red's support for ram region macros
+
#if (TUSB_CFG_MCU == MCU_LPC11UXX) || (TUSB_CFG_MCU == MCU_LPC13UXX)
#define TUSB_RAM_SECTION ".data.$RAM2"
#elif (TUSB_CFG_MCU == MCU_LPC43XX)
#define TUSB_RAM_SECTION ".data.$RAM3"
+ #elif (TUSB_CFG_MCU == MCU_LPC175X_6X)
+ #define TUSB_RAM_SECTION ".data.$RAM2"
+ #else
+ #error Please define USB RAM section
#endif
#define TUSB_CFG_ATTR_USBRAM __attribute__ ((section(TUSB_RAM_SECTION)))
+
#elif defined __CC_ARM // Compiled with Keil armcc
+
#define TUSB_CFG_ATTR_USBRAM
+
#elif __ICCARM__ // compiled with IAR
+
#define TUSB_CFG_ATTR_USBRAM @ ".ahb_sram1"
+
#else
+
#error compiler not specified
+
#endif