From a30dfa33244c3db1a3987dc9f75e4aae9b192d63 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Nov 2018 13:11:19 +0700 Subject: [PATCH] clean up --- .../metro_m4_express/board_metro_m4_express.c | 6 ++---- src/portable/microchip/samd51/dcd_samd51.c | 18 ++++-------------- 2 files changed, 6 insertions(+), 18 deletions(-) diff --git a/hw/bsp/metro_m4_express/board_metro_m4_express.c b/hw/bsp/metro_m4_express/board_metro_m4_express.c index ef851674..4e55a920 100644 --- a/hw/bsp/metro_m4_express/board_metro_m4_express.c +++ b/hw/bsp/metro_m4_express/board_metro_m4_express.c @@ -43,8 +43,6 @@ #include "hal/include/hal_init.h" #include "hpl/gclk/hpl_gclk_base.h" #include "hpl_mclk_config.h" -#include "peripheral_clk_config.h" - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION @@ -60,7 +58,7 @@ void board_init(void) { // Clock init ( follow hpl_init.c ) - // hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, 0); _osc32kctrl_init_sources(); _oscctrl_init_sources(); @@ -84,7 +82,7 @@ void board_init(void) /* USB Clock init * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock * for low speed and full speed operation. */ - hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, CONF_GCLK_USB_SRC | GCLK_PCHCTRL_CHEN); + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); hri_mclk_set_AHBMASK_USB_bit(MCLK); hri_mclk_set_APBBMASK_USB_bit(MCLK); diff --git a/src/portable/microchip/samd51/dcd_samd51.c b/src/portable/microchip/samd51/dcd_samd51.c index 97121046..023a706e 100644 --- a/src/portable/microchip/samd51/dcd_samd51.c +++ b/src/portable/microchip/samd51/dcd_samd51.c @@ -57,9 +57,7 @@ enum }; static UsbDeviceDescBank sram_registers[8][2]; -static ATTR_ALIGNED(4) uint8_t setup_packet[8]; - -volatile uint32_t setup_count = 0; +static ATTR_ALIGNED(4) uint8_t _setup_packet[8]; // Setup the control endpoint 0. static void bus_reset(void) { @@ -74,8 +72,7 @@ static void bus_reset(void) { ep->EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1 | USB_DEVICE_EPINTENSET_RXSTP; // Prepare for setup packet - dcd_edpt_xfer(0, 0, setup_packet, sizeof(setup_packet)); - setup_count = 0; + dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet)); } @@ -119,7 +116,7 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num) } /*------------------------------------------------------------------*/ -/* DCD Endpoint +/* DCD Endpoint port *------------------------------------------------------------------*/ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) @@ -252,12 +249,8 @@ static bool maybe_handle_setup_packet(void) { { USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; - // uint8_t* buf = (uint8_t*) sram_registers[0][0].ADDR.reg; - // - // if (buf[6] == 0x12) asm("bkpt"); // This copies the data elsewhere so we can reuse the buffer. dcd_event_setup_received(0, (uint8_t*) sram_registers[0][0].ADDR.reg, true); - setup_count += 1; return true; } return false; @@ -299,9 +292,6 @@ void USB_1_Handler(void) { } void transfer_complete(uint8_t direction) { - // uint8_t* buf = (uint8_t*) sram_registers[0][0].ADDR.reg; - // - // if (buf[6] == 0x12 || setup_count == 2) asm("bkpt"); uint32_t epints = USB->DEVICE.EPINTSMRY.reg; for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) { if ((epints & (1 << epnum)) == 0) { @@ -324,7 +314,7 @@ void transfer_complete(uint8_t direction) { // just finished status stage (total size = 0), prepare for next setup packet if (epnum == 0 && total_transfer_size == 0) { - dcd_edpt_xfer(0, 0, setup_packet, sizeof(setup_packet)); + dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet)); } if (direction == TUSB_DIR_IN) {