From 959311532ed69376a6a5845ca5a2066264b9a4e7 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 6 Mar 2013 14:55:02 +0700 Subject: [PATCH] refractor - rename some field in ehci_qhd/qtd_t - code test for open pipe --- tests/test/host/ehci/test_ehci_init.c | 2 +- tests/test/host/ehci/test_ehci_pipe.c | 34 ++++++++++++---------- tests/test/host/ehci/test_ehci_structure.c | 8 ++--- tinyusb/host/ehci/ehci.c | 6 ++-- tinyusb/host/ehci/ehci.h | 8 ++--- 5 files changed, 30 insertions(+), 28 deletions(-) diff --git a/tests/test/host/ehci/test_ehci_init.c b/tests/test/host/ehci/test_ehci_init.c index 546853d4..323e89f1 100644 --- a/tests/test/host/ehci/test_ehci_init.c +++ b/tests/test/host/ehci/test_ehci_init.c @@ -146,7 +146,7 @@ void test_hcd_init_period_list(void) TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, framelist[list_idx].type); } - TEST_ASSERT(period_head->smask) + TEST_ASSERT(period_head->interrupt_smask) TEST_ASSERT_TRUE(period_head->next.terminate); TEST_ASSERT(period_head->qtd_overlay.halted); } diff --git a/tests/test/host/ehci/test_ehci_pipe.c b/tests/test/host/ehci/test_ehci_pipe.c index 0805a013..1526d60e 100644 --- a/tests/test/host/ehci/test_ehci_pipe.c +++ b/tests/test/host/ehci/test_ehci_pipe.c @@ -101,11 +101,15 @@ void tearDown(void) { } -void verify_open_qhd(ehci_qhd_t *p_qhd) +void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_packet_size) { TEST_ASSERT_EQUAL(dev_addr, p_qhd->device_address); TEST_ASSERT_FALSE(p_qhd->inactive_next_xact); - TEST_ASSERT_EQUAL(0, p_qhd->nak_count_reload); // TODO NAK Reload disable + TEST_ASSERT_EQUAL(endpoint_addr & 0x0F, p_qhd->endpoint_number); + TEST_ASSERT_EQUAL(usbh_device_info_pool[dev_addr].speed, p_qhd->endpoint_speed); + TEST_ASSERT_EQUAL(max_packet_size, p_qhd->max_package_size); + TEST_ASSERT_EQUAL(0, p_qhd->nak_count_reload); // TDD NAK Reload disable + TEST_ASSERT_EQUAL(hub_addr, p_qhd->hub_address); TEST_ASSERT_EQUAL(hub_port, p_qhd->hub_port); TEST_ASSERT_EQUAL(1, p_qhd->mult); @@ -124,13 +128,11 @@ void verify_open_qhd(ehci_qhd_t *p_qhd) //--------------------------------------------------------------------+ void verify_control_open_qhd(ehci_qhd_t *p_qhd) { - verify_open_qhd(p_qhd); + verify_open_qhd(p_qhd, 0, control_max_packet_size); - TEST_ASSERT_EQUAL(control_max_packet_size, p_qhd->max_package_size); - TEST_ASSERT_EQUAL(0, p_qhd->endpoint_number); TEST_ASSERT_EQUAL(1, p_qhd->data_toggle_control); - TEST_ASSERT_EQUAL(0, p_qhd->smask); - TEST_ASSERT_EQUAL(0, p_qhd->cmask); + TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask); + TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask); } void test_control_open_addr0_qhd_data(void) @@ -139,6 +141,7 @@ void test_control_open_addr0_qhd_data(void) ehci_qhd_t * const p_qhd = async_head; + //------------- Code Under Test -------------// hcd_pipe_control_open(dev_addr, control_max_packet_size); verify_control_open_qhd(p_qhd); @@ -149,6 +152,7 @@ void test_control_open_qhd_data(void) { ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].control.qhd; + //------------- Code Under TEST -------------// hcd_pipe_control_open(dev_addr, control_max_packet_size); verify_control_open_qhd(p_qhd); @@ -166,9 +170,9 @@ void test_control_open_highspeed(void) usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_HIGH; + //------------- Code Under TEST -------------// hcd_pipe_control_open(dev_addr, control_max_packet_size); - TEST_ASSERT_EQUAL(TUSB_SPEED_HIGH, p_qhd->endpoint_speed); TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint); } @@ -178,9 +182,9 @@ void test_control_open_non_highspeed(void) usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL; + //------------- Code Under TEST -------------// hcd_pipe_control_open(dev_addr, control_max_packet_size); - TEST_ASSERT_EQUAL(TUSB_SPEED_FULL, p_qhd->endpoint_speed); TEST_ASSERT_TRUE(p_qhd->non_hs_control_endpoint); } @@ -189,18 +193,15 @@ void test_control_open_non_highspeed(void) //--------------------------------------------------------------------+ void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint) { - verify_open_qhd(p_qhd); + verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize); TEST_ASSERT_FALSE(p_qhd->head_list_flag); - TEST_ASSERT_EQUAL(desc_endpoint->wMaxPacketSize, p_qhd->max_package_size); - TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x0F, p_qhd->endpoint_number); TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control); - TEST_ASSERT_EQUAL(0, p_qhd->smask); - TEST_ASSERT_EQUAL(0, p_qhd->cmask); + TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask); + TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask); TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint); - TEST_ASSERT_EQUAL(usbh_device_info_pool[dev_addr].speed, p_qhd->endpoint_speed); - // TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TEST highspeed bulk/control OUT + // TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control); @@ -216,6 +217,7 @@ void test_open_bulk_qhd_data(void) pipe_handle_t pipe_hdl; tusb_descriptor_endpoint_t const * desc_endpoint = &desc_ept_bulk_in; + //------------- Code Under TEST -------------// pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint); p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ]; diff --git a/tests/test/host/ehci/test_ehci_structure.c b/tests/test/host/ehci/test_ehci_structure.c index 8908c49a..811a042b 100644 --- a/tests/test/host/ehci/test_ehci_structure.c +++ b/tests/test/host/ehci/test_ehci_structure.c @@ -152,8 +152,8 @@ void test_qhd_structure(void) TEST_ASSERT_EQUAL( 28, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 1, nak_count_reload) ); //------------- Word 2 -------------// - TEST_ASSERT_EQUAL( 0, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, smask) ); - TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, cmask) ); + TEST_ASSERT_EQUAL( 0, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, interrupt_smask) ); + TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, non_hs_cmask) ); TEST_ASSERT_EQUAL( 16, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_address) ); TEST_ASSERT_EQUAL( 23, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_port) ); TEST_ASSERT_EQUAL( 30, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, mult) ); @@ -191,8 +191,8 @@ void test_sitd_structure(void) TEST_ASSERT_EQUAL( 31, BITFIELD_OFFSET_OF_UINT32(ehci_sitd_t, 1, direction) ); //------------- Word 2 -------------// - TEST_ASSERT_EQUAL( 4*2, offsetof(ehci_sitd_t, smask)); - TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, cmask)); + TEST_ASSERT_EQUAL( 4*2, offsetof(ehci_sitd_t, interrupt_smask)); + TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, non_hs_cmask)); //------------- Word 3 -------------// TEST_ASSERT_EQUAL( 1, BITFIELD_OFFSET_OF_UINT32(ehci_sitd_t, 3, split_state) ); diff --git a/tinyusb/host/ehci/ehci.c b/tinyusb/host/ehci/ehci.c index d592567e..2cc43774 100644 --- a/tinyusb/host/ehci/ehci.c +++ b/tinyusb/host/ehci/ehci.c @@ -177,7 +177,7 @@ tusb_error_t hcd_controller_init(uint8_t hostid) framelist[i].type = EHCI_QUEUE_ELEMENT_QHD; } - period_head->smask = 1; // queue head in period list must have smask non-zero + period_head->interrupt_smask = 1; // queue head in period list must have smask non-zero period_head->next.terminate = 1; period_head->qtd_overlay.halted = 1; // dummy node, always inactive @@ -354,8 +354,8 @@ static void queue_head_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_pa p_qhd->non_hs_control_endpoint = ((TUSB_XFER_CONTROL == xfer_type) && (usbh_device_info_pool[dev_addr].speed != TUSB_SPEED_HIGH) ) ? 1 : 0; p_qhd->nak_count_reload = 0; - p_qhd->smask = 0; - p_qhd->cmask = 0; + p_qhd->interrupt_smask = 0; + p_qhd->non_hs_cmask = 0; p_qhd->hub_address = usbh_device_info_pool[dev_addr].hub_addr; p_qhd->hub_port = usbh_device_info_pool[dev_addr].hub_port; p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet diff --git a/tinyusb/host/ehci/ehci.h b/tinyusb/host/ehci/ehci.h index 6a0f3988..2c666f71 100644 --- a/tinyusb/host/ehci/ehci.h +++ b/tinyusb/host/ehci/ehci.h @@ -179,8 +179,8 @@ typedef struct { // End of Word 1 /// Word 2 : Endpoint Capabilities - uint32_t smask : 8 ; ///< This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint - uint32_t cmask : 8 ; ///< This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction + uint32_t interrupt_smask : 8 ; ///< This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint + uint32_t non_hs_cmask : 8 ; ///< This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction uint32_t hub_address : 7 ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. See Section 4.12. uint32_t hub_port : 7 ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addrbelow), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. See Section 4.12. uint32_t mult : 2 ; ///< This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. 00b=Reserved 01b,10b,11b= 1 (2, 3) Transaction for this endpoint/micro frame @@ -254,8 +254,8 @@ typedef struct { // End of Word 1 /// Word 2: Micro-frame Schedule Control - uint8_t smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions - uint8_t cmask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. + uint8_t interrupt_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions + uint8_t non_hs_cmask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. uint16_t reserved ; ///< reserved // End of Word 2