diff --git a/demos/bsp/boards/board.h b/demos/bsp/boards/board.h
index edc681a0..6f9d256c 100644
--- a/demos/bsp/boards/board.h
+++ b/demos/bsp/boards/board.h
@@ -36,12 +36,6 @@
*/
/**************************************************************************/
-/** \file
- * \brief TBD
- *
- * \note TBD
- */
-
/**
* \defgroup Group_Board Boards
* \brief TBD
diff --git a/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c b/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c
index 65778e50..8edc22e8 100644
--- a/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c
+++ b/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.c
@@ -50,6 +50,11 @@ void board_init(void)
// Leds Init
GPIO_SetDir(CFG_LED_PORT, BIT_(CFG_LED_PIN), 1);
+
+ // lpcxpresso base board USB device : if base board J14 is inserted at 1-2, 1k5 resistor is controlled by P0_21 (active low)
+ GPIO_SetDir(0, BIT_(21), 1);
+ GPIO_ClearValue(0, BIT_(21));
+
#if CFG_UART_ENABLE
//------------- UART init -------------//
@@ -70,7 +75,6 @@ void board_init(void)
UART_CFG_Type UARTConfigStruct;
UART_ConfigStructInit(&UARTConfigStruct);
UARTConfigStruct.Baud_rate = CFG_UART_BAUDRATE;
- UARTConfigStruct.Clock_Speed = 0;
UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
diff --git a/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.h b/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.h
index cfb01c3e..05168d80 100644
--- a/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.h
+++ b/demos/bsp/boards/lpcxpresso/board_lpcxpresso1769.h
@@ -47,6 +47,9 @@
#define _TUSB_BOARD_LPCXPRESSO1769_H_
#include "LPC17xx.h"
+
+#include "lpc175x_6x/LPC17xx_DriverLib/include/lpc17xx_clkpwr.h"
+#include "lpc175x_6x/LPC17xx_DriverLib/include/lpc17xx_pinsel.h"
#include "lpc175x_6x/LPC17xx_DriverLib/include/lpc17xx_gpio.h"
#include "lpc175x_6x/LPC17xx_DriverLib/include/lpc17xx_uart.h"
@@ -57,7 +60,7 @@
#define CFG_LED_PORT (0)
#define CFG_LED_PIN (22)
-#define CFG_PRINTF_TARGET PRINTF_TARGET_SEMIHOST
+#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
#ifdef __cplusplus
}
diff --git a/demos/device/device_os_none/.cproject b/demos/device/device_os_none/.cproject
index 2214898d..657f36b8 100644
--- a/demos/device/device_os_none/.cproject
+++ b/demos/device/device_os_none/.cproject
@@ -30,7 +30,7 @@
-
+
-
+
@@ -62,7 +62,7 @@
-
+
@@ -119,7 +119,7 @@
-
+
-
+
@@ -151,7 +151,7 @@
-
+
@@ -208,7 +208,7 @@
-
+
-
+
@@ -243,7 +243,7 @@
-
+
@@ -302,7 +302,7 @@
-
+
-
+
@@ -334,7 +334,7 @@
-
+
@@ -354,7 +354,7 @@
-
+
@@ -371,82 +371,73 @@
<?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="1"/>
-<infoList vendor="NXP"><info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC4357</name>
-<family>LPC43xx</family>
+<Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"><chip><name>LPC1769</name>
+<family>LPC17xx</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/>
-<memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/>
<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/>
-<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/>
-<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/>
-<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
-<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
-<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
-<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
-<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/>
-<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/>
-<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/>
-<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/>
-<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/>
-<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/>
-<peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/>
-<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/>
-<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/>
-<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/>
-<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/>
-<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/>
-<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/>
-<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/>
-<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/>
-<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/>
-<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/>
-<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/>
-<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/>
-<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/>
-<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/>
-<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/>
-<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/>
-<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/>
-<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/>
-<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/>
-<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/>
-<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/>
-<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/>
-<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/>
-<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/>
-<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/>
-<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/>
-<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/>
-<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/>
-<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/>
-<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/>
-<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/>
-<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/>
-<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/>
-<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/>
-<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/>
-<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/>
-<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/>
-<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/>
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
+<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
+<peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&0x1" id="TIMER0" location="0x40004000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&0x1" id="TIMER1" location="0x40008000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&0x1" id="TIMER2" location="0x40090000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&0x1" id="TIMER3" location="0x40094000"/>
+<peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&0x1" id="RIT" location="0x400B0000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO0" location="0x2009C000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO1" location="0x2009C020"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO2" location="0x2009C040"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO3" location="0x2009C060"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO4" location="0x2009C080"/>
+<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&0x08000000" id="I2S" location="0x400A8000"/>
+<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/>
+<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&0x2=2" id="DAC" location="0x4008C000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&0x1" id="UART0" location="0x4000C000"/>
+<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&0x1" id="UART1" location="0x40010000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&0x1" id="UART2" location="0x40098000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&0x1" id="UART3" location="0x4009C000"/>
+<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&0x1" id="SPI" location="0x40020000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&0x1" id="SSP0" location="0x40088000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&0x1" id="SSP1" location="0x40030000"/>
+<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&0x1" id="ADC" location="0x40034000"/>
+<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&0x12" id="USBINTSTAT" location="0x400fc1c0"/>
+<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/>
+<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&0x12=0x12" id="USBDEV" location="0x5000C200"/>
+<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&0x1" id="PWM" location="0x40018000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&0x1" id="I2C0" location="0x4001C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&0x1" id="I2C1" location="0x4005C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&0x1" id="I2C2" location="0x400A0000"/>
+<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&0x1" id="DMA" location="0x50004000"/>
+<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&0x1" id="ENET" location="0x50000000"/>
+<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/>
+<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/>
+<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&0x1" id="QEI" location="0x400bc000"/>
+<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&0x11=0x11" id="USBHOST" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&0x1" id="RTC" location="0x40024000"/>
+<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/>
+<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/>
+<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/>
+<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/>
+<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANAFR" location="0x4003C000"/>
+<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANCEN" location="0x40040000"/>
+<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&0x1" id="CANCON1" location="0x40044000"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&0x1" id="CANCON2" location="0x40048000"/>
+<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&0x1" id="MCPWM" location="0x400B8000"/>
+<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/>
</chip>
-<processor><name gcc_name="cortex-m4">Cortex-M4</name>
+<processor><name gcc_name="cortex-m3">Cortex-M3</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig>
diff --git a/demos/device/device_os_none/tusb_config.h b/demos/device/device_os_none/tusb_config.h
index 1ee286cd..b7f7425c 100644
--- a/demos/device/device_os_none/tusb_config.h
+++ b/demos/device/device_os_none/tusb_config.h
@@ -82,7 +82,7 @@
//------------- CLASS -------------//
#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
-#define TUSB_CFG_DEVICE_HID_MOUSE 1
+#define TUSB_CFG_DEVICE_HID_MOUSE 0
#define TUSB_CFG_DEVICE_HID_GENERIC 0
#define TUSB_CFG_DEVICE_MSC 0
#define TUSB_CFG_DEVICE_CDC 1
diff --git a/tinyusb/device/dcd.h b/tinyusb/device/dcd.h
index 3de63094..d02108fa 100644
--- a/tinyusb/device/dcd.h
+++ b/tinyusb/device/dcd.h
@@ -84,10 +84,6 @@ void dcd_controller_set_configuration(uint8_t coreid);
tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length);
void dcd_pipe_control_stall(uint8_t coreid);
-//tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length);
-//tusb_error_t dcd_pipe_control_read(uint8_t coreid, void * buffer, uint16_t length);
-//void dcd_pipe_control_write_zero_length(uint8_t coreid);
-
endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code) ATTR_WARN_UNUSED_RESULT;
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes) ATTR_WARN_UNUSED_RESULT; // only queue, not transferring yet
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes, bool int_on_complete) ATTR_WARN_UNUSED_RESULT;
diff --git a/tinyusb/device/dcd_lpc175x_6x.c b/tinyusb/device/dcd_lpc175x_6x.c
index b9be0bc5..a2910fc2 100644
--- a/tinyusb/device/dcd_lpc175x_6x.c
+++ b/tinyusb/device/dcd_lpc175x_6x.c
@@ -52,12 +52,14 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-STATIC_ dcd_dma_descriptor_t* dcd_udca[32] ATTR_ALIGNED(128) TUSB_CFG_ATTR_USBRAM;
+STATIC_ ATTR_ALIGNED(128) dcd_dma_descriptor_t* dcd_udca[32] TUSB_CFG_ATTR_USBRAM;
STATIC_ dcd_dma_descriptor_t dcd_dd[DCD_MAX_DD];
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
+static void bus_reset(void);
+
static inline void endpoint_set_max_packet_size(uint8_t endpoint_idx, uint16_t max_packet_size) ATTR_ALWAYS_INLINE;
static inline void endpoint_set_max_packet_size(uint8_t endpoint_idx, uint16_t max_packet_size)
{
@@ -75,8 +77,8 @@ static inline void endpoint_set_max_packet_size(uint8_t endpoint_idx, uint16_t m
}
-static inline void sie_commamd_code (uint8_t phase, uint8_t code_data) ATTR_ALWAYS_INLINE;
-static inline void sie_commamd_code (uint8_t phase, uint8_t code_data)
+static inline void sie_cmd_code (sie_cmdphase_t phase, uint8_t code_data) ATTR_ALWAYS_INLINE;
+static inline void sie_cmd_code (sie_cmdphase_t phase, uint8_t code_data)
{
LPC_USB->USBDevIntClr = (DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK);
LPC_USB->USBCmdCode = (phase << 8) | (code_data << 16);
@@ -88,26 +90,29 @@ static inline void sie_commamd_code (uint8_t phase, uint8_t code_data)
LPC_USB->USBDevIntClr = wait_flag;
}
-static inline void sie_command_write (uint8_t cmd_code, uint8_t data_len, uint8_t data) ATTR_ALWAYS_INLINE;
-static inline void sie_command_write (uint8_t cmd_code, uint8_t data_len, uint8_t data)
+static inline void sie_write (uint8_t cmd_code, uint8_t data_len, uint8_t data) ATTR_ALWAYS_INLINE;
+static inline void sie_write (uint8_t cmd_code, uint8_t data_len, uint8_t data)
{
- sie_commamd_code(SIE_CMDPHASE_COMMAND, cmd_code);
+ sie_cmd_code(SIE_CMDPHASE_COMMAND, cmd_code);
if (data_len)
{
- sie_commamd_code(SIE_CMDPHASE_WRITE, data);
+ sie_cmd_code(SIE_CMDPHASE_WRITE, data);
}
}
-static inline uint32_t sie_command_read (uint8_t cmd_code, uint8_t data_len) ATTR_ALWAYS_INLINE;
-static inline uint32_t sie_command_read (uint8_t cmd_code, uint8_t data_len)
+static inline uint32_t sie_read (uint8_t cmd_code, uint8_t data_len) ATTR_ALWAYS_INLINE;
+static inline uint32_t sie_read (uint8_t cmd_code, uint8_t data_len)
{
// TODO multiple read
- sie_commamd_code(SIE_CMDPHASE_COMMAND , cmd_code);
- sie_commamd_code(SIE_CMDPHASE_READ , cmd_code);
+ sie_cmd_code(SIE_CMDPHASE_COMMAND , cmd_code);
+ sie_cmd_code(SIE_CMDPHASE_READ , cmd_code);
return LPC_USB->USBCmdData;
}
+static tusb_error_t pipe_control_write(void const * buffer, uint16_t length);
+static tusb_error_t pipe_control_read(void * buffer, uint16_t length);
+
//--------------------------------------------------------------------+
// IMPLEMENTATION
//--------------------------------------------------------------------+
@@ -119,20 +124,23 @@ void endpoint_control_isr(uint8_t coreid)
//------------- control OUT -------------//
if (endpoint_int_status & BIT_(0))
{
- uint32_t const endpoint_status = sie_command_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1);
+ uint32_t const endpoint_status = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1);
if (endpoint_status & SIE_ENDPOINT_STATUS_SETUP_RECEIVED_MASK)
{
- (void) sie_command_read(SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT+0, 1); // clear setup bit
+ tusb_control_request_t control_request;
- dcd_pipe_control_read(0, &usbd_devices[0].setup_packet, 8);
- usbd_isr(0, TUSB_EVENT_SETUP_RECEIVED);
+ (void) sie_read(SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT+0, 1); // clear setup bit, can be omitted ???
+
+ pipe_control_read(&control_request, 8);
+
+ usbd_setup_received_isr(0, &control_request);
}else
{
// Current not support any out control with data yet
-// dcd_pipe_control_read(0,..
+// pipe_control_read(0,..
}
- sie_command_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
- sie_command_write(SIE_CMDCODE_BUFFER_CLEAR , 0, 0);
+ sie_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
+ sie_write(SIE_CMDCODE_BUFFER_CLEAR , 0, 0);
}
//------------- control IN -------------//
@@ -152,10 +160,11 @@ void dcd_isr(uint8_t coreid)
//------------- usb bus event -------------//
if (device_int_status & DEV_INT_DEVICE_STATUS_MASK)
{
- uint32_t const dev_status_reg = sie_command_read(SIE_CMDCODE_DEVICE_STATUS, 1);
+ uint32_t const dev_status_reg = sie_read(SIE_CMDCODE_DEVICE_STATUS, 1);
if (dev_status_reg & SIE_DEV_STATUS_RESET_MASK)
{
- usbd_isr(coreid, TUSB_EVENT_BUS_RESET);
+ bus_reset();
+ usbd_bus_reset(coreid);
}
// TODO invoke some callbacks
@@ -173,7 +182,7 @@ void dcd_isr(uint8_t coreid)
if (device_int_status & DEV_INT_ERROR_MASK)
{
- uint32_t error_status = sie_command_read(SIE_CMDCODE_READ_ERROR_STATUS, 1);
+ uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS, 1);
(void) error_status;
// ASSERT(false, (void) 0);
}
@@ -183,21 +192,14 @@ void dcd_isr(uint8_t coreid)
//--------------------------------------------------------------------+
// USBD-DCD API
//--------------------------------------------------------------------+
-tusb_error_t dcd_init(void)
+static void bus_reset(void)
{
- //------------- user manual 11.13 usb device controller initialization -------------// LPC_USB->USBEpInd = 0;
- // step 6 : set up control endpoint
- endpoint_set_max_packet_size(0, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
- endpoint_set_max_packet_size(1, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
-
- // step 7 : slave mode set up
+ // step 7 : slave mode set up
+ LPC_USB->USBEpIntClr = 0xFFFFFFFF; // clear all pending interrupt
+ LPC_USB->USBDevIntClr = 0xFFFFFFFF; // clear all pending interrupt
LPC_USB->USBEpIntEn = (uint32_t) BIN8(11); // control endpoint cannot use DMA, non-control all use DMA
+ LPC_USB->USBEpIntPri = 0; // same priority for all endpoint
- LPC_USB->USBDevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
- LPC_USB->USBDevIntClr = 0xFFFFFFFF; // clear all pending interrupt
-
- LPC_USB->USBEpIntClr = 0xFFFFFFFF; // clear all pending interrupt
- LPC_USB->USBEpIntPri = 0; // same priority for all endpoint
// step 8 : DMA set up
LPC_USB->USBEpDMADis = 0xFFFFFFFF; // firstly disable all dma
@@ -205,6 +207,18 @@ tusb_error_t dcd_init(void)
LPC_USB->USBEoTIntClr = 0xFFFFFFFF;
LPC_USB->USBNDDRIntClr = 0xFFFFFFFF;
LPC_USB->USBSysErrIntClr = 0xFFFFFFFF;
+}
+
+tusb_error_t dcd_init(void)
+{
+ //------------- user manual 11.13 usb device controller initialization -------------// LPC_USB->USBEpInd = 0;
+ // step 6 : set up control endpoint
+ endpoint_set_max_packet_size(0, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
+ endpoint_set_max_packet_size(1, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
+
+ bus_reset();
+
+ LPC_USB->USBDevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
for (uint8_t index = 0; index < DCD_MAX_DD; index++)
{
@@ -214,26 +228,27 @@ tusb_error_t dcd_init(void)
LPC_USB->USBDMAIntEn = (DMA_INT_END_OF_XFER_MASK | DMA_INT_NEW_DD_REQUEST_MASK | DMA_INT_ERROR_MASK );
// clear all stall on control endpoint IN & OUT if any
- sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS , 1, 0);
- sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + 1, 1, 0);
+ sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS , 1, 0);
+ sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + 1, 1, 0);
+
+ sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1); // connect
return TUSB_ERROR_NONE;
}
void dcd_controller_connect(uint8_t coreid)
{
- sie_command_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
+ sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
}
void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr)
{
- sie_command_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
+ sie_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
}
-void dcd_controller_set_configuration(uint8_t coreid, uint8_t config_num)
+void dcd_controller_set_configuration(uint8_t coreid)
{
- (void) config_num; // supress compiler's warnings
- sie_command_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
+ sie_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
}
//--------------------------------------------------------------------+
@@ -245,10 +260,8 @@ static inline uint16_t length_unit_byte2dword(uint16_t length_in_bytes)
return (length_in_bytes + 3) / 4; // length_in_dword
}
-tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length)
+static tusb_error_t pipe_control_write(void const * buffer, uint16_t length)
{
- (void) coreid; // suppress compiler warning
-
ASSERT( length !=0 || buffer == NULL, TUSB_ERROR_INVALID_PARA);
LPC_USB->USBCtrl = SLAVE_CONTROL_WRITE_ENABLE_MASK; // logical endpoint = 0
@@ -262,16 +275,16 @@ tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_
LPC_USB->USBCtrl = 0;
- sie_command_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0); // select control IN endpoint
- sie_command_write(SIE_CMDCODE_BUFFER_VALIDATE , 0, 0);
+ sie_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0); // select control IN endpoint
+ sie_write(SIE_CMDCODE_BUFFER_VALIDATE , 0, 0);
return TUSB_ERROR_NONE;
}
-tusb_error_t dcd_pipe_control_read(uint8_t coreid, void * buffer, uint16_t length)
+static tusb_error_t pipe_control_read(void * buffer, uint16_t length)
{
LPC_USB->USBCtrl = SLAVE_CONTROL_READ_ENABLE_MASK; // logical endpoint = 0
- while ((LPC_USB->USBRxPLen & SLAVE_RXPLEN_PACKET_READY_MASK) == 0) {}
+ while ((LPC_USB->USBRxPLen & SLAVE_RXPLEN_PACKET_READY_MASK) == 0) {} // TODO blocking, should have timeout
uint16_t actual_length = min16_of(length, (uint16_t) (LPC_USB->USBRxPLen & SLAVE_RXPLEN_PACKET_LENGTH_MASK) );
uint32_t *p_read_data = (uint32_t*) buffer;
@@ -280,25 +293,49 @@ tusb_error_t dcd_pipe_control_read(uint8_t coreid, void * buffer, uint16_t lengt
*p_read_data = LPC_USB->USBRxData;
p_read_data++; // increase by 4 ( sizeof(uint32_t) )
}
- LPC_USB->USBCtrl = 0;
+ LPC_USB->USBCtrl = 0; // TODO not needed ?
return TUSB_ERROR_NONE;
}
-// TODO inline function
-void dcd_pipe_control_write_zero_length(uint8_t coreid)
-{
- dcd_pipe_control_write(coreid, NULL, 0);
-}
-
static inline uint8_t endpoint_address_to_physical_index(uint8_t ep_address) ATTR_ALWAYS_INLINE ATTR_CONST;
static inline uint8_t endpoint_address_to_physical_index(uint8_t ep_address)
{
return (ep_address << 1) + (ep_address & 0x80 ? 1 : 0 );
}
-tusb_error_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc)
+//--------------------------------------------------------------------+
+// CONTROL PIPE API
+//--------------------------------------------------------------------+
+void dcd_pipe_control_stall(uint8_t coreid)
{
+ ASSERT(false, VOID_RETURN);
+}
+
+tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length)
+{
+ (void) coreid;
+
+ if ( dir )
+ {
+ ASSERT_STATUS ( pipe_control_write(p_buffer, length) );
+ }else
+ {
+ ASSERT_STATUS ( pipe_control_read(p_buffer, length) );
+ }
+
+ return TUSB_ERROR_NONE;
+}
+
+//--------------------------------------------------------------------+
+// BULK/INTERRUPT/ISO PIPE API
+//--------------------------------------------------------------------+
+endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code)
+{
+ (void) coreid;
+
+ return (endpoint_handle_t) { 0 };
+
uint8_t phy_ep = endpoint_address_to_physical_index( p_endpoint_desc->bEndpointAddress );
//------------- Realize Endpoint with Max Packet Size -------------//
@@ -312,11 +349,25 @@ tusb_error_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_
LPC_USB->USBEpDMAEn = BIT_(phy_ep);
- sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+phy_ep, 1, 0); // clear all endpoint status
+ sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+phy_ep, 1, 0); // clear all endpoint status
+
+}
+
+bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl)
+{
+ ASSERT(false, false);
+}
+
+tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
+{
+ return TUSB_ERROR_FAILED;
+}
+
+tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes, bool int_on_complete)
+{
+ ASSERT_STATUS(TUSB_ERROR_FAILED);
return TUSB_ERROR_NONE;
}
-//tusb_error_t dcd_pipe_xfer()
-
#endif
diff --git a/tinyusb/device/dcd_lpc175x_6x.h b/tinyusb/device/dcd_lpc175x_6x.h
index f906915c..33ff7b62 100644
--- a/tinyusb/device/dcd_lpc175x_6x.h
+++ b/tinyusb/device/dcd_lpc175x_6x.h
@@ -144,11 +144,11 @@ enum {
};
//------------- SIE Command Code -------------//
-enum {
+typedef enum {
SIE_CMDPHASE_WRITE = 1,
SIE_CMDPHASE_READ = 2,
SIE_CMDPHASE_COMMAND = 5
-};
+} sie_cmdphase_t;
enum {
// device commands
diff --git a/tinyusb/device/dcd_lpc43xx.c b/tinyusb/device/dcd_lpc43xx.c
index 1d400d2a..fe55273c 100644
--- a/tinyusb/device/dcd_lpc43xx.c
+++ b/tinyusb/device/dcd_lpc43xx.c
@@ -339,7 +339,7 @@ static inline uint8_t qtd_find_free(uint8_t coreid)
//--------------------------------------------------------------------+
void dcd_pipe_control_stall(uint8_t coreid)
{
- LPC_USB[coreid]->ENDPTCTRL0 |= (ENDPTCTRL_MASK_STALL << 16); // stall Control IN
+ LPC_USB[coreid]->ENDPTCTRL0 |= (ENDPTCTRL_MASK_STALL << 16); // stall Control IN TODO stall control OUT as well
}
// control transfer does not need to use qtd find function
diff --git a/tinyusb/device/dcd_lpc_11uxx_13uxx.c b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
index dac52d40..8a92183b 100644
--- a/tinyusb/device/dcd_lpc_11uxx_13uxx.c
+++ b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
@@ -310,18 +310,6 @@ tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void *
//--------------------------------------------------------------------+
// PIPE HELPER
//--------------------------------------------------------------------+
-//static inline uint8_t edpt_pos2phy(uint8_t pos) ATTR_CONST ATTR_ALWAYS_INLINE;
-//static inline uint8_t edpt_pos2phy(uint8_t pos)
-//{ // 0-5 --> OUT, 16-21 IN
-// return (pos < DCD_QHD_MAX/2) ? (2*pos) : (2*(pos-16)+1);
-//}
-
-//static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
-//static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint)
-//{
-// return physical_endpoint/2 + ( (physical_endpoint%2) ? 16 : 0);
-//}
-
static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
{
diff --git a/tinyusb/device/usbd.c b/tinyusb/device/usbd.c
index 69e89b68..5850d0e2 100644
--- a/tinyusb/device/usbd.c
+++ b/tinyusb/device/usbd.c
@@ -50,7 +50,7 @@
#include "usbd_dcd.h"
// Some MCUs cannot transfer more than 64 bytes each queue, thus require special task-alike treatment
-#if MCU == MCU_LPC11UXX
+#if MCU == MCU_LPC11UXX || MCU == MCU_LPC175X_6X
#define USBD_CONTROL_ONE_PACKET_EACH_XFER // for each Transfer, cannot queue more than packet size
enum {
USBD_COTNROL_MAX_LENGTH_EACH_XFER = 64
@@ -184,7 +184,7 @@ tusb_error_t usbd_body_subtask(void)
if ( TUSB_ERROR_NONE == error )
{
- dcd_pipe_control_xfer(coreid, control_request.bmRequestType_bit.direction, p_buffer, length); // zero length
+ dcd_pipe_control_xfer(coreid, control_request.bmRequestType_bit.direction, p_buffer, length);
}
}
else if ( TUSB_REQUEST_SET_ADDRESS == control_request.bRequest )
diff --git a/tinyusb/device/usbd.h b/tinyusb/device/usbd.h
index 2f3201d9..e8e10e98 100644
--- a/tinyusb/device/usbd.h
+++ b/tinyusb/device/usbd.h
@@ -90,7 +90,7 @@ bool tusbd_is_configured(uint8_t coreid) ATTR_WARN_UNUSED_RESULT;
#ifdef _TINY_USB_SOURCE_FILE_
tusb_error_t usbd_init(void);
-
+OSAL_TASK_FUNCTION (usbd_task) (void* p_task_para);
#endif
#ifdef __cplusplus
diff --git a/tinyusb/hal/hal_lpc175x_6x.c b/tinyusb/hal/hal_lpc175x_6x.c
index 3f1b2a35..aca4bd42 100644
--- a/tinyusb/hal/hal_lpc175x_6x.c
+++ b/tinyusb/hal/hal_lpc175x_6x.c
@@ -46,10 +46,6 @@
#include "common/common.h"
#include "hal.h"
-enum {
- PCONP_PCUSB = 31
-};
-
//--------------------------------------------------------------------+
// IMPLEMENTATION
//--------------------------------------------------------------------+
@@ -66,7 +62,7 @@ tusb_error_t hal_init(void)
// LPC_PINCON->PINSEL3 &= ~(3<<6); TODO HOST
// LPC_PINCON->PINSEL3 |= (2<<6);
- LPC_SC->PCONP |= BIT_(PCONP_PCUSB); /* USB PCLK -> enable USB Per.*/
+ LPC_SC->PCONP |= CLKPWR_PCONP_PCUSB; /* USB PCLK -> enable USB Per.*/
// DEVICE mode
LPC_USB->USBClkCtrl = 0x12; /* Dev, PortSel, AHB clock enable */
diff --git a/tinyusb/hal/hal_lpc175x_6x.h b/tinyusb/hal/hal_lpc175x_6x.h
index 4f3224ce..013bdcb3 100644
--- a/tinyusb/hal/hal_lpc175x_6x.h
+++ b/tinyusb/hal/hal_lpc175x_6x.h
@@ -47,6 +47,7 @@
#define _TUSB_HAL_LPC175X_6X_H_
#include "LPC17xx.h"
+#include "lpc17xx_clkpwr.h"
#ifdef __cplusplus
extern "C" {