From dccb3b1a4675b2ece3d860f5903eed70930b7478 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 22 Jun 2021 00:20:08 +0900
Subject: [PATCH 1/5] change stdio channel to SCI5 from SCI0. change ports
 settings for LED and button. add PLL setting for 240MHz based on HOCO into
 HardwareSetup().

---
 .../rx63n/boards/rx65n_cloud_kit/r5f565ne.ld  |  38 ++--
 .../boards/rx65n_cloud_kit/rx65n_cloud_kit.c  | 188 ++++++++++--------
 2 files changed, 130 insertions(+), 96 deletions(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
index 8d4806f0..a02f0c02 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
@@ -1,16 +1,21 @@
+__USTACK_SIZE = 0x00000200;
+__ISTACK_SIZE = 0x00000200;
+
 MEMORY
 {
-	RAM : ORIGIN = 0x0, LENGTH = 262144
-	RAM2 : ORIGIN = 0x00800000, LENGTH = 393216
-	ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
-	OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
+	RAM  : ORIGIN = 0x4,        LENGTH = 0x3fffc
+	RAM2 : ORIGIN = 0x00800000, LENGTH = 0x60000
+	OFS  : ORIGIN = 0xFE7F5D00, LENGTH = 128
+	ROM  : ORIGIN = 0xFFE00000, LENGTH = 0x200000
 }
 SECTIONS
 {
 	.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
 	{
+		"_exvectors_start" = .;
 		KEEP(*(.exvectors))
-	} > ROM
+		"_exvectors_end" = .;
+	} >ROM
 	.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
 	{
 		KEEP(*(.fvectors))
@@ -20,6 +25,7 @@ SECTIONS
 		*(.text)
 		*(.text.*)
 		*(P)
+		KEEP(*(.text.*_isr))
 		etext = .;
 	} > ROM
 	.rvectors ALIGN(4):
@@ -89,15 +95,7 @@ SECTIONS
 		. = ALIGN(2);
 		_mdata = .;
 	} > ROM
-	.ustack 0x200: AT(0x200)
-	{
-		_ustack = .;
-	} > RAM
-	.istack 0x100: AT(0x100)
-	{
-		_istack = .;
-	} > RAM
-	.data 0x204: AT(_mdata)
+	.data : AT(_mdata)
 	{
 		_data = .;
 		*(.data)
@@ -123,6 +121,18 @@ SECTIONS
 		_ebss = .;
 		_end = .;
 	} > RAM
+	.ustack :
+	{
+		. = ALIGN(8);
+		. = . + __USTACK_SIZE;
+		PROVIDE(_ustack = .);
+	} > RAM
+	.istack :
+	{
+		. = ALIGN(8);
+		. = . + __ISTACK_SIZE;
+		PROVIDE(_istack = .);
+	} > RAM
 	.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
 	{
 		KEEP(*(.ofs1))
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
index 0853763c..e3f1483f 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -30,17 +30,17 @@
 
 #define IRQ_PRIORITY_CMT0     5
 #define IRQ_PRIORITY_USBI0    6
-#define IRQ_PRIORITY_SCI0     5
+#define IRQ_PRIORITY_SCI5     5
 
 #define SYSTEM_PRCR_PRC1      (1<<1)
 #define SYSTEM_PRCR_PRKEY     (0xA5u<<8)
 
-#define CMT_PCLK              48000000
+#define CMT_PCLK              60000000
 #define CMT_CMCR_CKS_DIV_128  2
 #define CMT_CMCR_CMIE         (1<<6)
 #define MPC_PFS_ISEL          (1<<6)
 
-#define SCI_PCLK              48000000
+#define SCI_PCLK              60000000
 #define SCI_SSR_FER           (1<<4)
 #define SCI_SSR_ORER          (1<<5)
 
@@ -49,83 +49,103 @@
 #define SCI_SCR_TE            (1u<<5)
 #define SCI_SCR_RIE           (1u<<6)
 #define SCI_SCR_TIE           (1u<<7)
+#define INT_Excep_SCI5_TEI5   INT_Excep_ICU_GROUPBL0
+
+#define IRQ_USB0_USBI0        62
+#define IEN_USB0_USBI0        IEN_PERIB_INTB185
+#define VECT_USB0_USBI0       VECT_PERIB_INTB185
+#define IR_USB0_USBI0         IR_PERIB_INTB185
+#define IER_USB0_USBI0        IER_PERIB_INTB185
+#define IPR_USB0_USBI0        IPR_PERIB_INTB185
+#define INT_Excep_USB0_USBI0  INT_Excep_PERIB_INTB185
 
 void HardwareSetup(void)
 {
-/*
- BSC.CS0MOD.WORD = 0x1234;
- BSC.CS7CNT.WORD = 0x5678;
+  FLASH.ROMCIV.WORD = 1;
+  while (FLASH.ROMCIV.WORD) ;
+  FLASH.ROMCE.WORD = 1;
+  while (!FLASH.ROMCE.WORD) ;
 
- SCI0.SCR.BIT.TE  = 0;
- SCI0.SCR.BIT.RE  = 0;
- SCI0.SCR.BIT.TE  = 1;
- SCI2.SSR.BIT.PER = 0;
+  SYSTEM.PRCR.WORD = 0xA503u;
+  if (!SYSTEM.RSTSR1.BYTE) {
+    RTC.RCR4.BYTE = 0;
+    RTC.RCR3.BYTE = 12;
+    while (12 != RTC.RCR3.BYTE) ;
+  }
+  SYSTEM.SOSCCR.BYTE = 1;
 
- TMR0.TCR.BYTE = 0x12;
- TMR1.TCR.BYTE = 0x12;
- TMR2.TCR.BYTE = 0x12;
+  if (SYSTEM.HOCOCR.BYTE) {
+    SYSTEM.HOCOCR.BYTE = 0;
+    while (!SYSTEM.OSCOVFSR.BIT.HCOVF) ;
+  }
+  SYSTEM.PLLCR.WORD  = 0x1D10u; /* HOCO x 15 */
+  SYSTEM.PLLCR2.BYTE = 0;
+  while (!SYSTEM.OSCOVFSR.BIT.PLOVF) ;
 
- P0.DDR.BYTE = 0x12;
- P1.DDR.BYTE = 0x12;
-*/
+  SYSTEM.SCKCR.LONG  = 0x21C11222u;
+  SYSTEM.SCKCR2.WORD = 0x0041u;
+  SYSTEM.ROMWT.BYTE  = 0x02u;
+  while (0x02u != SYSTEM.ROMWT.BYTE) ;
+  SYSTEM.SCKCR3.WORD = 0x400u;
+  SYSTEM.PRCR.WORD   = 0xA500u;
 }
 
 //--------------------------------------------------------------------+
-// SCI0 handling
+// SCI handling
 //--------------------------------------------------------------------+
 typedef struct {
   uint8_t *buf;
   uint32_t cnt;
 } sci_buf_t;
-static volatile sci_buf_t sci0_buf[2];
+static volatile sci_buf_t sci_buf[2];
 
-void INT_Excep_SCI0_TXI0(void)
+void INT_Excep_SCI5_TXI5(void)
 {
-  uint8_t *buf = sci0_buf[0].buf;
-  uint32_t cnt = sci0_buf[0].cnt;
+  uint8_t *buf = sci_buf[0].buf;
+  uint32_t cnt = sci_buf[0].cnt;
   
   if (!buf || !cnt) {
-    SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+    SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
     return;
   }
-  SCI0.TDR = *buf;
+  SCI5.TDR = *buf;
   if (--cnt) {
     ++buf;
   } else {
     buf = NULL;
-    SCI0.SCR.BIT.TIE  = 0;
-    SCI0.SCR.BIT.TEIE = 1;
+    SCI5.SCR.BIT.TIE  = 0;
+    SCI5.SCR.BIT.TEIE = 1;
   }
-  sci0_buf[0].buf = buf;
-  sci0_buf[0].cnt = cnt;
+  sci_buf[0].buf = buf;
+  sci_buf[0].cnt = cnt;
 }
 
-void INT_Excep_SCI0_TEI0(void)
+void INT_Excep_SCI5_TEI5(void)
 {
-  SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+  SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
 }
 
-void INT_Excep_SCI0_RXI0(void)
+void INT_Excep_SCI5_RXI5(void)
 {
-  uint8_t *buf = sci0_buf[1].buf;
-  uint32_t cnt = sci0_buf[1].cnt;
+  uint8_t *buf = sci_buf[1].buf;
+  uint32_t cnt = sci_buf[1].cnt;
 
   if (!buf || !cnt ||
-      (SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
-    sci0_buf[1].buf = NULL;
-    SCI0.SSR.BYTE   = 0;
-    SCI0.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+      (SCI5.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
+    sci_buf[1].buf = NULL;
+    SCI5.SSR.BYTE   = 0;
+    SCI5.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
     return;
   }
-  *buf = SCI0.RDR;
+  *buf = SCI5.RDR;
   if (--cnt) {
     ++buf;
   } else {
     buf = NULL;
-    SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+    SCI5.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
   }
-  sci0_buf[1].buf = buf;
-  sci0_buf[1].cnt = cnt;
+  sci_buf[1].buf = buf;
+  sci_buf[1].cnt = cnt;
 }
 
 //--------------------------------------------------------------------+
@@ -156,43 +176,47 @@ void board_init(void)
   /* Unlock MPC registers */
   MPC.PWPR.BIT.B0WI  = 0;
   MPC.PWPR.BIT.PFSWE = 1;
-  /* LED PA0 */
-  PORTA.PMR.BIT.B0  = 0U;
-  PORTA.PODR.BIT.B0 = 0U;
-  PORTA.PDR.BIT.B0  = 1U;
-  /* UART TXD0 => P20, RXD0 => P21 */
-  PORT2.PMR.BIT.B0 = 1U;
-  PORT2.PCR.BIT.B0 = 1U;
-  MPC.P20PFS.BYTE  = 0b01010;
-  PORT2.PMR.BIT.B1 = 1U;
-  MPC.P21PFS.BYTE  = 0b01010;
-  /* USB VBUS -> P16 DPUPE -> P14 */
-  PORT1.PMR.BIT.B4 = 1U;
+  // SW PB1
+  PORTB.PMR.BIT.B1 = 0U;
+  PORTB.PDR.BIT.B1 = 0U;
+  // LED PD6
+  PORTD.PODR.BIT.B6 = 1U;
+  PORTD.ODR1.BIT.B4 = 1U;
+  PORTD.PMR.BIT.B6  = 0U;
+  PORTD.PDR.BIT.B6  = 1U;
+  /* UART TXD5 => PA4, RXD5 => PA3 */
+  PORTA.PMR.BIT.B4 = 1U;
+  PORTA.PCR.BIT.B4 = 1U;
+  MPC.PA4PFS.BYTE  = 0b01010;
+  PORTA.PMR.BIT.B3 = 1U;
+  MPC.PA5PFS.BYTE  = 0b01010;
+  /* USB VBUS -> P16 */
   PORT1.PMR.BIT.B6 = 1U;
-  MPC.P14PFS.BYTE  = 0b10001;
   MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
-//  MPC.PFUSB0.BIT.PUPHZS = 1;
   /* Lock MPC registers */
   MPC.PWPR.BIT.PFSWE = 0;
   MPC.PWPR.BIT.B0WI  = 1;
 
-//  IR(USB0, USBI0)  = 0;
-//  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
-
-  /* Enable SCI0 */
+  /* Enable SCI5 */
   SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(SCI0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
-//  IR(SCI0,  RXI0)  = 0;
-//  IR(SCI0,  TXI0)  = 0;
-//  IR(SCI0,  TEI0)  = 0;
-//  IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
-//  IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
-//  IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
-//  IEN(SCI0, RXI0) = 1;
-//  IEN(SCI0, TXI0) = 1;
-//  IEN(SCI0, TEI0) = 1;
+  MSTP(SCI5) = 0;
+  SYSTEM.PRCR.WORD  = SYSTEM_PRCR_PRKEY;
+  SCI5.BRR = ((SCI_PCLK * 1.0) / (32.0 * 115200.0)) - 1;
+  IR(SCI5,  RXI5)   = 0;
+  IR(SCI5,  TXI5)   = 0;
+  IS(SCI5,  TEI5)   = 0;
+  IR(ICU, GROUPBL0) = 0;
+  IPR(SCI5, RXI5)   = IRQ_PRIORITY_SCI5;
+  IPR(SCI5, TXI5)   = IRQ_PRIORITY_SCI5;
+  IPR(ICU,GROUPBL0) = IRQ_PRIORITY_SCI5;
+  IEN(SCI5, RXI5)   = 1;
+  IEN(SCI5, TXI5)   = 1;
+  IEN(ICU,GROUPBL0) = 1;
+  EN(SCI5, TEI5)    = 1;
+
+  /* setup USBI0 interrupt. Group B edge */
+  IR(USB0, USBI0)  = 0;
+  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
 }
 
 //--------------------------------------------------------------------+
@@ -201,29 +225,29 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  PORTA.PODR.BIT.B0 = state ? 1 : 0;
+  PORTD.PODR.BIT.B6 = state ? 0 : 1;
 }
 
 uint32_t board_button_read(void)
 {
-  return 0;
+  return PORTB.PIDR.BIT.B1 ? 0 : 1;
 }
 
 int board_uart_read(uint8_t* buf, int len)
 {
-  sci0_buf[1].buf = buf;
-  sci0_buf[1].cnt = len;
-  SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
-  while (SCI0.SCR.BIT.RE) ;
-  return len - sci0_buf[1].cnt;
+  sci_buf[1].buf = buf;
+  sci_buf[1].cnt = len;
+  SCI5.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
+  while (SCI5.SCR.BIT.RE) ;
+  return len - sci_buf[1].cnt;
 }
 
 int board_uart_write(void const *buf, int len)
 {
-  sci0_buf[0].buf = (uint8_t*)buf;
-  sci0_buf[0].cnt = len;
-  SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
-  while (SCI0.SCR.BIT.TE) ;
+  sci_buf[0].buf = (uint8_t*)buf;
+  sci_buf[0].cnt = len;
+  SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
+  while (SCI5.SCR.BIT.TE) ;
   return len;
 }
 
@@ -239,5 +263,5 @@ uint32_t board_millis(void)
   return system_ticks;
 }
 #else
-uint32_t SystemCoreClock = 96000000;
+uint32_t SystemCoreClock = 120000000;
 #endif

From 60fedaa050b68201f03682bec3a5b16f4abc739e Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 26 Jun 2021 21:13:35 +0900
Subject: [PATCH 2/5] fix baudrate setting

---
 .../boards/rx65n_cloud_kit/rx65n_cloud_kit.c  | 32 ++++++++++---------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
index e3f1483f..7ebcfead 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -198,21 +198,23 @@ void board_init(void)
   MPC.PWPR.BIT.B0WI  = 1;
 
   /* Enable SCI5 */
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(SCI5) = 0;
-  SYSTEM.PRCR.WORD  = SYSTEM_PRCR_PRKEY;
-  SCI5.BRR = ((SCI_PCLK * 1.0) / (32.0 * 115200.0)) - 1;
-  IR(SCI5,  RXI5)   = 0;
-  IR(SCI5,  TXI5)   = 0;
-  IS(SCI5,  TEI5)   = 0;
-  IR(ICU, GROUPBL0) = 0;
-  IPR(SCI5, RXI5)   = IRQ_PRIORITY_SCI5;
-  IPR(SCI5, TXI5)   = IRQ_PRIORITY_SCI5;
-  IPR(ICU,GROUPBL0) = IRQ_PRIORITY_SCI5;
-  IEN(SCI5, RXI5)   = 1;
-  IEN(SCI5, TXI5)   = 1;
-  IEN(ICU,GROUPBL0) = 1;
-  EN(SCI5, TEI5)    = 1;
+  SYSTEM.PRCR.WORD   = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(SCI5)         = 0;
+  SYSTEM.PRCR.WORD   = SYSTEM_PRCR_PRKEY;
+  SCI5.SEMR.BIT.ABCS = 1;
+  SCI5.SEMR.BIT.BGDM = 1;
+  SCI5.BRR           = (SCI_PCLK / (8 * 115200)) - 1;
+  IR(SCI5,  RXI5)    = 0;
+  IR(SCI5,  TXI5)    = 0;
+  IS(SCI5,  TEI5)    = 0;
+  IR(ICU, GROUPBL0)  = 0;
+  IPR(SCI5, RXI5)    = IRQ_PRIORITY_SCI5;
+  IPR(SCI5, TXI5)    = IRQ_PRIORITY_SCI5;
+  IPR(ICU,GROUPBL0)  = IRQ_PRIORITY_SCI5;
+  IEN(SCI5, RXI5)    = 1;
+  IEN(SCI5, TXI5)    = 1;
+  IEN(ICU,GROUPBL0)  = 1;
+  EN(SCI5, TEI5)     = 1;
 
   /* setup USBI0 interrupt. Group B edge */
   IR(USB0, USBI0)  = 0;

From 511b2d47d1be37bfa1d6f35ddee80393ec93d39c Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 26 Jun 2021 22:42:27 +0900
Subject: [PATCH 3/5] add handling for software configurable interrupts.

---
 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk          |  5 ++++-
 hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c | 11 ++++++-----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
index 87cbd74a..a4f19b07 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -1,7 +1,10 @@
 CFLAGS += \
   -mcpu=rx64m \
   -misa=v2 \
-  -DCFG_TUSB_MCU=OPT_MCU_RX65X
+  -DCFG_TUSB_MCU=OPT_MCU_RX65X \
+  -DIR_USB0_USBI0=IR_PERIB_INTB185 \
+  -DIER_USB0_USBI0=IER_PERIB_INTB185 \
+  -DIEN_USB0_USBI0=IEN_PERIB_INTB185
 
 RX_NEWLIB ?= 1
 
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
index 7ebcfead..895b82e2 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -52,10 +52,7 @@
 #define INT_Excep_SCI5_TEI5   INT_Excep_ICU_GROUPBL0
 
 #define IRQ_USB0_USBI0        62
-#define IEN_USB0_USBI0        IEN_PERIB_INTB185
-#define VECT_USB0_USBI0       VECT_PERIB_INTB185
-#define IR_USB0_USBI0         IR_PERIB_INTB185
-#define IER_USB0_USBI0        IER_PERIB_INTB185
+#define SLIBR_USBI0           SLIBR185
 #define IPR_USB0_USBI0        IPR_PERIB_INTB185
 #define INT_Excep_USB0_USBI0  INT_Excep_PERIB_INTB185
 
@@ -158,6 +155,10 @@ void INT_Excep_USB0_USBI0(void)
 
 void board_init(void)
 {
+  /* setup software configurable interrupts */
+  ICU.SLIBR_USBI0.BYTE = IRQ_USB0_USBI0;
+  ICU.SLIPRCR.BYTE     = 1;
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   /* Enable CMT0 */
   SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
@@ -216,7 +217,7 @@ void board_init(void)
   IEN(ICU,GROUPBL0)  = 1;
   EN(SCI5, TEI5)     = 1;
 
-  /* setup USBI0 interrupt. Group B edge */
+  /* setup USBI0 interrupt. */
   IR(USB0, USBI0)  = 0;
   IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
 }

From 393a9120ac0725ba525aa09fcf8e24fd32735391 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 26 Jun 2021 23:09:18 +0900
Subject: [PATCH 4/5] add the entry for RX65N

---
 src/portable/renesas/usba/dcd_usba.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 06ea1a3f..de3e0e31 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -26,8 +26,8 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X )
-
+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                                 CFG_TUSB_MCU == OPT_MCU_RX65X)
 #include "device/dcd.h"
 #include "iodefine.h"
 

From 239ecadeca9312af8c0777b9e41fbd25187f45be Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 27 Jun 2021 23:39:50 +0900
Subject: [PATCH 5/5] add options for e2l

---
 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
index a4f19b07..34a4b2cb 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -52,4 +52,4 @@ PYOCD_TARGET =
 
 # flash using rfp-cli
 flash: $(BUILD)/$(PROJECT).mot
-	rfp-cli -device rx65x -tool e2l -auto $^
+	rfp-cli -device rx65x -tool e2l -if fine -fo id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auto $^