From 3ba72b53d88a5eb08004c9c3c4edf7101066eb3f Mon Sep 17 00:00:00 2001
From: zhangslice <1304224508@qq.com>
Date: Wed, 2 Jun 2021 09:46:48 +0800
Subject: [PATCH 01/14] Add MM32 SDK and USB driver
Signed-off-by: zhangslice <1304224508@qq.com>
---
.../CMSIS/IAR_Core/arm_common_tables.h | 121 +
.../CMSIS/IAR_Core/arm_const_structs.h | 66 +
.../mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h | 7122 +++++++++++++++++
.../mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h | 796 ++
.../mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h | 1735 ++++
.../mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h | 231 +
.../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h | 1900 +++++
.../mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h | 1813 +++++
.../mm32f327x/CMSIS/IAR_Core/core_armv8mml.h | 2821 +++++++
.../mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h | 850 ++
.../mm32f327x/CMSIS/IAR_Core/core_cm0plus.h | 975 +++
.../mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h | 1813 +++++
.../mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h | 1880 +++++
.../mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h | 2821 +++++++
.../mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h | 2061 +++++
.../mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h | 2592 ++++++
.../mm32f327x/CMSIS/IAR_Core/core_sc000.h | 976 +++
.../mm32f327x/CMSIS/IAR_Core/core_sc300.h | 1851 +++++
.../mm32f327x/CMSIS/IAR_Core/tz_context.h | 69 +
.../CMSIS/KEIL_Core/arm_common_tables.h | 121 +
.../CMSIS/KEIL_Core/arm_const_structs.h | 66 +
.../mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h | 7122 +++++++++++++++++
.../mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h | 796 ++
.../CMSIS/KEIL_Core/cmsis_armclang.h | 1735 ++++
.../CMSIS/KEIL_Core/cmsis_compiler.h | 231 +
.../mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h | 1900 +++++
.../mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h | 1813 +++++
.../mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h | 2821 +++++++
.../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h | 850 ++
.../mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h | 975 +++
.../mm32f327x/CMSIS/KEIL_Core/core_cm23.h | 1813 +++++
.../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h | 1880 +++++
.../mm32f327x/CMSIS/KEIL_Core/core_cm33.h | 2821 +++++++
.../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h | 2061 +++++
.../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h | 2592 ++++++
.../mm32f327x/CMSIS/KEIL_Core/core_sc000.h | 976 +++
.../mm32f327x/CMSIS/KEIL_Core/core_sc300.h | 1851 +++++
.../mm32f327x/CMSIS/KEIL_Core/tz_context.h | 69 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h | 33 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h | 341 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h | 130 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h | 340 +
.../MM32F327x/HAL_Lib/Inc/hal_comp.h | 228 +
.../MM32F327x/HAL_Lib/Inc/hal_conf.h | 62 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h | 84 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h | 46 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h | 166 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h | 72 +
.../MM32F327x/HAL_Lib/Inc/hal_device.h | 41 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h | 306 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h | 729 ++
.../MM32F327x/HAL_Lib/Inc/hal_eth_conf.h | 68 +
.../MM32F327x/HAL_Lib/Inc/hal_exti.h | 181 +
.../MM32F327x/HAL_Lib/Inc/hal_flash.h | 230 +
.../MM32F327x/HAL_Lib/Inc/hal_fsmc.h | 147 +
.../MM32F327x/HAL_Lib/Inc/hal_gpio.h | 198 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h | 255 +
.../MM32F327x/HAL_Lib/Inc/hal_iwdg.h | 130 +
.../MM32F327x/HAL_Lib/Inc/hal_misc.h | 128 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h | 156 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h | 329 +
.../MM32F327x/HAL_Lib/Inc/hal_redefine.h | 102 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h | 114 +
.../MM32F327x/HAL_Lib/Inc/hal_sdio.h | 503 ++
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h | 351 +
.../MM32F327x/HAL_Lib/Inc/hal_syscfg.h | 83 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h | 755 ++
.../MM32F327x/HAL_Lib/Inc/hal_uart.h | 211 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h | 71 +
.../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h | 89 +
.../MM32F327x/HAL_Lib/Inc/hal_wwdg.h | 90 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c | 563 ++
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c | 231 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c | 696 ++
.../MM32F327x/HAL_Lib/Src/hal_comp.c | 226 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c | 108 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c | 43 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c | 184 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c | 53 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c | 319 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c | 836 ++
.../MM32F327x/HAL_Lib/Src/hal_exti.c | 222 +
.../MM32F327x/HAL_Lib/Src/hal_flash.c | 548 ++
.../MM32F327x/HAL_Lib/Src/hal_fsmc.c | 124 +
.../MM32F327x/HAL_Lib/Src/hal_gpio.c | 344 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c | 526 ++
.../MM32F327x/HAL_Lib/Src/hal_iwdg.c | 208 +
.../MM32F327x/HAL_Lib/Src/hal_misc.c | 147 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c | 215 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c | 995 +++
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c | 234 +
.../MM32F327x/HAL_Lib/Src/hal_sdio.c | 527 ++
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c | 648 ++
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c | 1875 +++++
.../MM32F327x/HAL_Lib/Src/hal_uart.c | 502 ++
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c | 55 +
.../mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c | 131 +
.../MM32F327x/HAL_Lib/Src/hal_wwdg.c | 147 +
.../mm32f327x/MM32F327x/Include/mm32_device.h | 23 +
.../mm32f327x/MM32F327x/Include/mm32_reg.h | 71 +
.../MM32F327x/Include/mm32_reg_redefine_v1.h | 1175 +++
.../mm32f327x/MM32F327x/Include/reg_adc.h | 953 +++
.../mm32f327x/MM32F327x/Include/reg_bkp.h | 147 +
.../mm32f327x/MM32F327x/Include/reg_can.h | 532 ++
.../mm32f327x/MM32F327x/Include/reg_common.h | 643 ++
.../mm32f327x/MM32F327x/Include/reg_comp.h | 228 +
.../mm32f327x/MM32F327x/Include/reg_crc.h | 102 +
.../mm32f327x/MM32F327x/Include/reg_crs.h | 152 +
.../mm32f327x/MM32F327x/Include/reg_dac.h | 247 +
.../mm32f327x/MM32F327x/Include/reg_dbg.h | 113 +
.../mm32f327x/MM32F327x/Include/reg_dma.h | 325 +
.../mm32f327x/MM32F327x/Include/reg_eth.h | 730 ++
.../mm32f327x/MM32F327x/Include/reg_exti.h | 544 ++
.../mm32f327x/MM32F327x/Include/reg_flash.h | 290 +
.../mm32f327x/MM32F327x/Include/reg_fsmc.h | 194 +
.../mm32f327x/MM32F327x/Include/reg_gpio.h | 706 ++
.../mm32f327x/MM32F327x/Include/reg_i2c.h | 635 ++
.../mm32f327x/MM32F327x/Include/reg_iwdg.h | 125 +
.../mm32f327x/MM32F327x/Include/reg_pwm.h | 72 +
.../mm32f327x/MM32F327x/Include/reg_pwr.h | 219 +
.../mm32f327x/MM32F327x/Include/reg_rcc.h | 654 ++
.../mm32f327x/MM32F327x/Include/reg_rtc.h | 203 +
.../mm32f327x/MM32F327x/Include/reg_sdio.h | 391 +
.../mm32f327x/MM32F327x/Include/reg_spi.h | 359 +
.../mm32f327x/MM32F327x/Include/reg_syscfg.h | 299 +
.../mm32f327x/MM32F327x/Include/reg_tim.h | 681 ++
.../mm32f327x/MM32F327x/Include/reg_uart.h | 362 +
.../MM32F327x/Include/reg_usb_otg_fs.h | 923 +++
.../mm32f327x/MM32F327x/Include/reg_wwdg.h | 133 +
.../mm32/mm32f327x/MM32F327x/Include/types.h | 105 +
.../GCC_StartAsm/startup_mm32m3ux_u_gcc.S | 440 +
.../MM32F327x/Source/system_mm32f327x.c | 866 ++
src/portable/mm32/dcd_mm32f327x_otg.c | 462 ++
133 files changed, 96566 insertions(+)
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
create mode 100644 src/portable/mm32/dcd_mm32f327x_otg.c
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
new file mode 100644
index 00000000..dfea7460
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
new file mode 100644
index 00000000..84ffe8b8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
new file mode 100644
index 00000000..9d678052
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
@@ -0,0 +1,7122 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib
folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file arm_math.h
which is placed in the Include
folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h
for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM
folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+ * on ARMv8M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32()
, arm_mat_init_q31()
+ * and arm_mat_init_q15()
for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows
specifies the number of rows, nColumns
+ * specifies the number of columns, and pData
points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS
.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+#include "core_cm7.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+#include "core_armv8mbl.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+#include "core_armv8mml.h"
+#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+#define ARM_MATH_DSP
+#endif
+#else
+#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+#define __SIMD32_TYPE __unaligned int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+{
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+{
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+{
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+{
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+{
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+}
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+ q31_t data);
+
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+ q31_t data)
+{
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while ((data & mask) == 0) {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+}
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t* dst,
+ q31_t* pRecipTable)
+{
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0) {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++) {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+}
+
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t* dst,
+ q15_t* pRecipTable)
+{
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0) {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++) {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+{
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++) {
+ posMax = posMax * 2;
+ }
+
+ if (x > 0) {
+ posMax = (posMax - 1);
+
+ if (x > posMax) {
+ x = posMax;
+ }
+ }
+ else {
+ negMin = -posMax;
+
+ if (x < negMin) {
+ x = negMin;
+ }
+ }
+ return (x);
+}
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+{
+ /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+{
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+{
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+{
+ /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+{
+ /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+{
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+}
+
+/*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+{
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+}
+
+#if 0
+/*
+ * @brief C custom defined PKHBT for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+ uint32_t x,
+ uint32_t y,
+ uint32_t leftshift)
+{
+ return ( ((x ) & 0x0000FFFFUL) |
+ ((y << leftshift) & 0xFFFF0000UL) );
+}
+
+/*
+ * @brief C custom defined PKHTB for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+ uint32_t x,
+ uint32_t y,
+ uint32_t rightshift)
+{
+ return ( ((x ) & 0xFFFF0000UL) |
+ ((y >> rightshift) & 0x0000FFFFUL) );
+}
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q7(
+ const arm_fir_instance_q7* S,
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+void arm_fir_init_q7(
+ arm_fir_instance_q7* S,
+ uint16_t numTaps,
+ q7_t* pCoeffs,
+ q7_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q15(
+ const arm_fir_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps
is not a supported value.
+ */
+arm_status arm_fir_init_q15(
+ arm_fir_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q31(
+ const arm_fir_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void arm_fir_init_q31(
+ arm_fir_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_f32(
+ const arm_fir_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void arm_fir_init_f32(
+ arm_fir_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q15;
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_casd_df1_inst_f32;
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15* S,
+ uint8_t numStages,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31* S,
+ uint8_t numStages,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ int8_t postShift);
+
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32* S,
+ uint8_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_f64;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_q31;
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst,
+ q15_t* pScratch);
+
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32* pSrc,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15* pSrc,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31* pSrc,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst,
+ q15_t* pState);
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst,
+ q15_t* pState);
+
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32* pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15* pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31* pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31* S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t* pData);
+
+
+/**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15* S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t* pData);
+
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32* S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t* pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_f32(
+ arm_pid_instance_f32* S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+void arm_pid_reset_f32(
+ arm_pid_instance_f32* S);
+
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q31(
+ arm_pid_instance_q31* S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+void arm_pid_reset_q31(
+ arm_pid_instance_q31* S);
+
+
+/**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q15(
+ arm_pid_instance_q15* S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+void arm_pid_reset_q15(
+ arm_pid_instance_q15* S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t* pYData; /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15* S,
+ q15_t* pSrc);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t* pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15* S,
+ q15_t* pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t* pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31* S,
+ q31_t* pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t* pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31* S,
+ q31_t* pSrc);
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t* pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32* S,
+ float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t* pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32* S,
+ float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t* pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15* S,
+ q15_t* p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t* pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31* S,
+ q31_t* p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t* pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32* S,
+ float32_t* p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15* S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+ const arm_rfft_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31* S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+ const arm_rfft_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32* S,
+ arm_cfft_radix4_instance_f32* S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32* S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32* S,
+ float32_t* p, float32_t* pOut,
+ uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t* pTwiddle; /**< points to the twiddle factor table. */
+ float32_t* pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal
is not a supported transform length.
+ */
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32* S,
+ arm_rfft_instance_f32* S_RFFT,
+ arm_cfft_radix4_instance_f32* S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_f32(
+ const arm_dct4_instance_f32* S,
+ float32_t* pState,
+ float32_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t* pTwiddle; /**< points to the twiddle factor table. */
+ q31_t* pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31* S,
+ arm_rfft_instance_q31* S_RFFT,
+ arm_cfft_radix4_instance_q31* S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_q31(
+ const arm_dct4_instance_q31* S,
+ q31_t* pState,
+ q31_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t* pTwiddle; /**< points to the twiddle factor table. */
+ q15_t* pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15* S,
+ arm_rfft_instance_q15* S_RFFT,
+ arm_cfft_radix4_instance_q15* S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_q15(
+ const arm_dct4_instance_q15* S,
+ q15_t* pState,
+ q15_t* pInlineBuffer);
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_f32(
+ float32_t* pSrc,
+ float32_t scale,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q7(
+ q7_t* pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q15(
+ q15_t* pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q31(
+ q31_t* pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q7(
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ uint32_t blockSize,
+ float32_t* result);
+
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ uint32_t blockSize,
+ q31_t* result);
+
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ uint32_t blockSize,
+ q63_t* result);
+
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ uint32_t blockSize,
+ q63_t* result);
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q7(
+ q7_t* pSrc,
+ int8_t shiftBits,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q15(
+ q15_t* pSrc,
+ int8_t shiftBits,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q31(
+ q31_t* pSrc,
+ int8_t shiftBits,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_f32(
+ float32_t* pSrc,
+ float32_t offset,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q7(
+ q7_t* pSrc,
+ q7_t offset,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q15(
+ q15_t* pSrc,
+ q15_t offset,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q31(
+ q31_t* pSrc,
+ q31_t offset,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q7(
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q7(
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_f32(
+ float32_t value,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q7(
+ q7_t value,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q15(
+ q15_t value,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q31(
+ q31_t value,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void arm_conv_f32(
+ float32_t* pSrcA,
+ uint32_t srcALen,
+ float32_t* pSrcB,
+ uint32_t srcBLen,
+ float32_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void arm_conv_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_fast_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+*/
+void arm_conv_opt_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_f32(
+ float32_t* pSrcA,
+ uint32_t srcALen,
+ float32_t* pSrcB,
+ uint32_t srcBLen,
+ float32_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32* S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15* S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31* S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15* S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31* S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32* S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31* S,
+ uint8_t numStages,
+ q31_t* pCoeffs,
+ q63_t* pState,
+ uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_stereo_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f64;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64* S,
+ float64_t* pSrc,
+ float64_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32* S,
+ uint8_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32* S,
+ uint8_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64* S,
+ uint8_t numStages,
+ float64_t* pCoeffs,
+ float64_t* pState);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15* S,
+ uint16_t numStages,
+ q15_t* pCoeffs,
+ q15_t* pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31* S,
+ uint16_t numStages,
+ q31_t* pCoeffs,
+ q31_t* pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32* S,
+ uint16_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32* S,
+ uint16_t numStages,
+ float32_t* pkCoeffs,
+ float32_t* pvCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31* S,
+ uint16_t numStages,
+ q31_t* pkCoeffs,
+ q31_t* pvCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15* S,
+ uint16_t numStages,
+ q15_t* pkCoeffs,
+ q15_t* pvCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_f32(
+ const arm_lms_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pRef,
+ float32_t* pOut,
+ float32_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_init_f32(
+ arm_lms_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_init_q15(
+ arm_lms_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_q15(
+ const arm_lms_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pRef,
+ q15_t* pOut,
+ q15_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+} arm_lms_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_q31(
+ const arm_lms_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pRef,
+ q31_t* pOut,
+ q31_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_init_q31(
+ arm_lms_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pRef,
+ float32_t* pOut,
+ float32_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t* recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pRef,
+ q31_t* pOut,
+ q31_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t* recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pRef,
+ q15_t* pOut,
+ q15_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_f32(
+ float32_t* pSrcA,
+ uint32_t srcALen,
+ float32_t* pSrcB,
+ uint32_t srcBLen,
+ float32_t* pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+void arm_correlate_opt_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ float32_t* pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ q31_t* pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ q15_t* pScratchIn,
+ q31_t* pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7* S,
+ q7_t* pSrc,
+ q7_t* pDst,
+ q7_t* pScratchIn,
+ q31_t* pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7* S,
+ uint16_t numTaps,
+ q7_t* pCoeffs,
+ q7_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t* pSinVal,
+ float32_t* pCosVal);
+
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t* pSinVal,
+ q31_t* pCosVal);
+
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S
points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32* S,
+ float32_t in)
+{
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+}
+
+/**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31* S,
+ q31_t in)
+{
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+
+/**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15* S,
+ q15_t in)
+{
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE* vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32* src,
+ arm_matrix_instance_f32* dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64* src,
+ arm_matrix_instance_f64* dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic
to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha
and Ibeta
.
+ * When Ialpha
is superposed with Ia
as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0
, in this condition Ialpha
and Ibeta
+ * can be calculated using only Ia
and Ib
.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia
and Ib
are the instantaneous stator phases and
+ * pIalpha
and pIbeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t* pIalpha,
+ float32_t* pIbeta)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+}
+
+
+/**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t* pIalpha,
+ q31_t* pIbeta)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_q7_to_q31(
+ q7_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa
and pIb
are the instantaneous stator phases and
+ * Ialpha
and Ibeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Clarke transform
+* @param[in] Ialpha input two-phase orthogonal vector axis alpha
+* @param[in] Ibeta input two-phase orthogonal vector axis beta
+* @param[out] pIa points to output three-phase coordinate a
+* @param[out] pIb points to output three-phase coordinate b
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t* pIa,
+ float32_t* pIb)
+{
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+}
+
+
+/**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t* pIa,
+ q31_t* pIb)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_q7_to_q15(
+ q7_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha
and the Ibeta
currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha
and Ibeta
are the stator vector components,
+ * pId
and pIq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t* pId,
+ float32_t* pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+}
+
+
+/**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t* pId,
+ q31_t* pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q7_to_float(
+ q7_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha
and pIbeta
are the stator vector components,
+ * Id
and Iq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Park transform
+* @param[in] Id input coordinate of rotor reference frame d
+* @param[in] Iq input coordinate of rotor reference frame q
+* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+* @param[in] sinVal sine value of rotation angle theta
+* @param[in] cosVal cosine value of rotation angle theta
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t* pIalpha,
+ float32_t* pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+}
+
+
+/**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t* pIalpha,
+ q31_t* pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_float(
+ q31_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S
points to an instance of the Linear Interpolate function data structure.
+ * x
is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32* S,
+ float32_t x)
+{
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t* pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0) {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues) {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+}
+
+
+/**
+*
+* @brief Process function for the Q31 Linear Interpolation Function.
+* @param[in] pYData pointer to Q31 Linear Interpolation table
+* @param[in] x input sample to process
+* @param[in] nValues number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t* pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0) {
+ return (pYData[0]);
+ }
+ else {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t* pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0) {
+ return (pYData[0]);
+ }
+ else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t* pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0) {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1)) {
+ return (pYData[nValues - 1]);
+ }
+ else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+}
+
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+float32_t arm_sin_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q31_t arm_sin_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q15_t arm_sin_q15(
+ q15_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+float32_t arm_cos_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q31_t arm_cos_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q15_t arm_cos_q15(
+ q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1
is the current estimate,
+ * x0
is the previous estimate, and
+ * f'(x0)
is the derivative of f()
evaluated at x0
.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t* pOut)
+{
+ if (in >= 0.0f) {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t* pOut);
+
+
+/**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t* pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t* circBuffer,
+ int32_t L,
+ uint16_t* writeOffset,
+ int32_t bufferInc,
+ const int32_t* src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t* circBuffer,
+ int32_t L,
+ int32_t* readOffset,
+ int32_t bufferInc,
+ int32_t* dst,
+ int32_t* dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t*) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q15 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t* circBuffer,
+ int32_t L,
+ uint16_t* writeOffset,
+ int32_t bufferInc,
+ const q15_t* src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t* circBuffer,
+ int32_t L,
+ int32_t* readOffset,
+ int32_t bufferInc,
+ q15_t* dst,
+ q15_t* dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t*) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t* circBuffer,
+ int32_t L,
+ uint16_t* writeOffset,
+ int32_t bufferInc,
+ const q7_t* src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t* circBuffer,
+ int32_t L,
+ int32_t* readOffset,
+ int32_t bufferInc,
+ q7_t* dst,
+ q7_t* dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t*) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q63_t* pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q63_t* pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q7_t* pResult);
+
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ uint32_t numSamples,
+ q31_t* realResult,
+ q31_t* imagResult);
+
+
+/**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ uint32_t numSamples,
+ q63_t* realResult,
+ q63_t* imagResult);
+
+
+/**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ uint32_t numSamples,
+ float32_t* realResult,
+ float32_t* imagResult);
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_q15(
+ q15_t* pSrcCmplx,
+ q15_t* pSrcReal,
+ q15_t* pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_q31(
+ q31_t* pSrcCmplx,
+ q31_t* pSrcReal,
+ q31_t* pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_f32(
+ float32_t* pSrcCmplx,
+ float32_t* pSrcReal,
+ float32_t* pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q7_t* result,
+ uint32_t* index);
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q7_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q31(
+ float32_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q15(
+ float32_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q7(
+ float32_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_q15(
+ q31_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_q7(
+ q31_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_float(
+ q15_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_q31(
+ q15_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_q7(
+ q15_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y)
is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows
specifies the number of rows in the table;
+ * numCols
specifies the number of columns in the table;
+ * and pData
points to an array of size numRows*numCols
values.
+ * The data table pTable
is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols]
where x and y are integers.
+ *
+ * \par
+ * Let (x, y)
specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+/**
+*
+* @brief Floating-point bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate.
+* @param[in] Y interpolation coordinate.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32* S,
+ float32_t X,
+ float32_t Y)
+{
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t* pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+}
+
+
+/**
+*
+* @brief Q31 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31* S,
+ q31_t X,
+ q31_t Y)
+{
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t* pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+}
+
+
+/**
+* @brief Q15 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15* S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t* pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+}
+
+
+/**
+* @brief Q7 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7* S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t* pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+#else
+#define LOW_OPTIMIZATION_EXIT
+#endif
+
+/* Enter low optimization region - place directly above function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+#define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define LOW_OPTIMIZATION_EXIT
+
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+#else
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
new file mode 100644
index 00000000..4617b128
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
@@ -0,0 +1,796 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version V5.0.1
+ * @date 03. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+#define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+#define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+#define __ARM_ARCH_7EM__ 1
+#endif
+
+/* __ARM_ARCH_8M_BASE__ not applicable */
+/* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static __inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT __packed struct
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+#define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXB(value, ptr) __strex(value, ptr)
+#else
+#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#else
+#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXW(value, ptr) __strex(value, ptr)
+#else
+#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
new file mode 100644
index 00000000..6b21a5be
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
@@ -0,0 +1,1735 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version V5.0.1
+ * @date 02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static __inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wpacked"
+struct __attribute__((packed)) T_UINT32 {
+ uint32_t v;
+};
+#pragma clang diagnostic pop
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+ ({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
new file mode 100644
index 00000000..89cd6902
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
@@ -0,0 +1,231 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.1
+ * @date 30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * ARM Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+
+#include
+
+#ifndef __NO_RETURN
+#define __NO_RETURN __noreturn
+#endif
+#ifndef __USED
+#define __USED __root
+#endif
+#ifndef __WEAK
+#define __WEAK __weak
+#endif
+#ifndef __UNALIGNED_UINT32
+__packed struct T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef __PACKED
+#define __PACKED __packed
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT __packed struct
+#endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+#include
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+struct __attribute__((packed)) T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed))
+#endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+struct __packed__ T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __align(x)
+#endif
+#ifndef __PACKED
+#define __PACKED __packed__
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __packed__
+#endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+#include
+
+#ifndef __ASM
+#define __ASM _asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+// NO RETURN is automatically detected hence no warning here
+#define __NO_RETURN
+#endif
+#ifndef __USED
+#warning No compiler specific solution for __USED. __USED is ignored.
+#define __USED
+#endif
+#ifndef __WEAK
+#define __WEAK __weak
+#endif
+#ifndef __UNALIGNED_UINT32
+@packed struct T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef __PACKED
+#define __PACKED @packed
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT @packed struct
+#endif
+
+
+#else
+#error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
new file mode 100644
index 00000000..919f26d1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
@@ -0,0 +1,1900 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.1
+ * @date 02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+struct __attribute__((packed)) T_UINT32 {
+ uint32_t v;
+};
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+// __ASM volatile ("nop");
+//}
+#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+// __ASM volatile ("wfi");
+//}
+#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+// __ASM volatile ("wfe");
+//}
+#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+// __ASM volatile ("sev");
+//}
+#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF"::: "memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF"::: "memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF"::: "memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+ ({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+ ({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
new file mode 100644
index 00000000..4e65d1d9
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+/* CMSIS cmGrebe definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MBL_REV
+#define __ARMv8MBL_REV 0x0000U
+#warning "__ARMv8MBL_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT 0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT 0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
new file mode 100644
index 00000000..273c3849
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+/* CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MML_REV
+#define __ARMv8MML_REV 0x0000U
+#warning "__ARMv8MML_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT 0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
new file mode 100644
index 00000000..d06d984b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
@@ -0,0 +1,850 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV 0x0000U
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
new file mode 100644
index 00000000..ebc43f3a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
@@ -0,0 +1,975 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV 0x0000U
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
new file mode 100644
index 00000000..513635a5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+/* CMSIS cmGrebe definitions */
+#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM23_REV
+#define __CM23_REV 0x0000U
+#warning "__CM23_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT 0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT 0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
new file mode 100644
index 00000000..8cbf329b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
@@ -0,0 +1,1880 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV 0x0200U
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
new file mode 100644
index 00000000..00de7795
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM33_REV
+#define __CM33_REV 0x0000U
+#warning "__CM33_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT 0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
new file mode 100644
index 00000000..f4c8011f
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
@@ -0,0 +1,2061 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM4_REV
+#define __CM4_REV 0x0000U
+#warning "__CM4_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
new file mode 100644
index 00000000..c09acc82
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
@@ -0,0 +1,2592 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM7_REV
+#define __CM7_REV 0x0000U
+#warning "__CM7_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT 0U
+#warning "__ICACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT 0U
+#warning "__DCACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DTCM_PRESENT
+#define __DTCM_PRESENT 0U
+#warning "__DTCM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ register uint32_t ccsidr;
+ register uint32_t sets;
+ register uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
new file mode 100644
index 00000000..ed106336
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV 0x0000U
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
new file mode 100644
index 00000000..a1b17e1c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
@@ -0,0 +1,1851 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC300_REV
+#define __SC300_REV 0x0000U
+#warning "__SC300_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
new file mode 100644
index 00000000..cd6d8ab0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date: 21. September 2016
+ * $Revision: V1.0
+ *
+ * Project: TrustZone for ARMv8-M
+ * Title: Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ * Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
new file mode 100644
index 00000000..dfea7460
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
new file mode 100644
index 00000000..84ffe8b8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
new file mode 100644
index 00000000..9d678052
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
@@ -0,0 +1,7122 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib
folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file arm_math.h
which is placed in the Include
folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h
for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM
folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+ * on ARMv8M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32()
, arm_mat_init_q31()
+ * and arm_mat_init_q15()
for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows
specifies the number of rows, nColumns
+ * specifies the number of columns, and pData
points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS
.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+#include "core_cm7.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+#include "core_armv8mbl.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+#include "core_armv8mml.h"
+#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+#define ARM_MATH_DSP
+#endif
+#else
+#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+#define __SIMD32_TYPE __unaligned int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+{
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+{
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+{
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+{
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+{
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+}
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+ q31_t data);
+
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+ q31_t data)
+{
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while ((data & mask) == 0) {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+}
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t* dst,
+ q31_t* pRecipTable)
+{
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0) {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++) {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+}
+
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t* dst,
+ q15_t* pRecipTable)
+{
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0) {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++) {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+{
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++) {
+ posMax = posMax * 2;
+ }
+
+ if (x > 0) {
+ posMax = (posMax - 1);
+
+ if (x > posMax) {
+ x = posMax;
+ }
+ }
+ else {
+ negMin = -posMax;
+
+ if (x < negMin) {
+ x = negMin;
+ }
+ }
+ return (x);
+}
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+{
+ /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+{
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+{
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+{
+ /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+{
+ /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+{
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+}
+
+/*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+{
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+}
+
+#if 0
+/*
+ * @brief C custom defined PKHBT for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+ uint32_t x,
+ uint32_t y,
+ uint32_t leftshift)
+{
+ return ( ((x ) & 0x0000FFFFUL) |
+ ((y << leftshift) & 0xFFFF0000UL) );
+}
+
+/*
+ * @brief C custom defined PKHTB for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+ uint32_t x,
+ uint32_t y,
+ uint32_t rightshift)
+{
+ return ( ((x ) & 0xFFFF0000UL) |
+ ((y >> rightshift) & 0x0000FFFFUL) );
+}
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q7(
+ const arm_fir_instance_q7* S,
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+void arm_fir_init_q7(
+ arm_fir_instance_q7* S,
+ uint16_t numTaps,
+ q7_t* pCoeffs,
+ q7_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q15(
+ const arm_fir_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps
is not a supported value.
+ */
+arm_status arm_fir_init_q15(
+ arm_fir_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q31(
+ const arm_fir_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void arm_fir_init_q31(
+ arm_fir_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_f32(
+ const arm_fir_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void arm_fir_init_f32(
+ arm_fir_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q15;
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_casd_df1_inst_f32;
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15* S,
+ uint8_t numStages,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31* S,
+ uint8_t numStages,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ int8_t postShift);
+
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32* S,
+ uint8_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_f64;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t* pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_q31;
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst,
+ q15_t* pScratch);
+
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32* pSrc,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15* pSrc,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31* pSrc,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst,
+ q15_t* pState);
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst,
+ q15_t* pState);
+
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32* pSrcA,
+ const arm_matrix_instance_f32* pSrcB,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15* pSrcA,
+ const arm_matrix_instance_q15* pSrcB,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31* pSrcA,
+ const arm_matrix_instance_q31* pSrcB,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32* pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15* pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31* pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31* S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t* pData);
+
+
+/**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15* S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t* pData);
+
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32* S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t* pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_f32(
+ arm_pid_instance_f32* S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+void arm_pid_reset_f32(
+ arm_pid_instance_f32* S);
+
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q31(
+ arm_pid_instance_q31* S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+void arm_pid_reset_q31(
+ arm_pid_instance_q31* S);
+
+
+/**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q15(
+ arm_pid_instance_q15* S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+void arm_pid_reset_q15(
+ arm_pid_instance_q15* S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t* pYData; /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t* pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15* S,
+ q15_t* pSrc);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t* pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15* S,
+ q15_t* pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t* pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31* S,
+ q31_t* pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t* pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31* S,
+ q31_t* pSrc);
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t* pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32* S,
+ float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t* pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32* S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32* S,
+ float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t* pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15* S,
+ q15_t* p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t* pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31* S,
+ q31_t* p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t* pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t* pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32* S,
+ float32_t* p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15* S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+ const arm_rfft_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31* S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+ const arm_rfft_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32* S,
+ arm_cfft_radix4_instance_f32* S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32* S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32* S,
+ float32_t* p, float32_t* pOut,
+ uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t* pTwiddle; /**< points to the twiddle factor table. */
+ float32_t* pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal
is not a supported transform length.
+ */
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32* S,
+ arm_rfft_instance_f32* S_RFFT,
+ arm_cfft_radix4_instance_f32* S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_f32(
+ const arm_dct4_instance_f32* S,
+ float32_t* pState,
+ float32_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t* pTwiddle; /**< points to the twiddle factor table. */
+ q31_t* pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31* S,
+ arm_rfft_instance_q31* S_RFFT,
+ arm_cfft_radix4_instance_q31* S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_q31(
+ const arm_dct4_instance_q31* S,
+ q31_t* pState,
+ q31_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t* pTwiddle; /**< points to the twiddle factor table. */
+ q15_t* pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15* S,
+ arm_rfft_instance_q15* S_RFFT,
+ arm_cfft_radix4_instance_q15* S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_q15(
+ const arm_dct4_instance_q15* S,
+ q15_t* pState,
+ q15_t* pInlineBuffer);
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_f32(
+ float32_t* pSrc,
+ float32_t scale,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q7(
+ q7_t* pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q15(
+ q15_t* pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q31(
+ q31_t* pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q7(
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ uint32_t blockSize,
+ float32_t* result);
+
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q7(
+ q7_t* pSrcA,
+ q7_t* pSrcB,
+ uint32_t blockSize,
+ q31_t* result);
+
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ uint32_t blockSize,
+ q63_t* result);
+
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ uint32_t blockSize,
+ q63_t* result);
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q7(
+ q7_t* pSrc,
+ int8_t shiftBits,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q15(
+ q15_t* pSrc,
+ int8_t shiftBits,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q31(
+ q31_t* pSrc,
+ int8_t shiftBits,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_f32(
+ float32_t* pSrc,
+ float32_t offset,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q7(
+ q7_t* pSrc,
+ q7_t offset,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q15(
+ q15_t* pSrc,
+ q15_t offset,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q31(
+ q31_t* pSrc,
+ q31_t offset,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q7(
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q7(
+ q7_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_f32(
+ float32_t value,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q7(
+ q7_t value,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q15(
+ q15_t value,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q31(
+ q31_t value,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void arm_conv_f32(
+ float32_t* pSrcA,
+ uint32_t srcALen,
+ float32_t* pSrcB,
+ uint32_t srcBLen,
+ float32_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void arm_conv_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_fast_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+*/
+void arm_conv_opt_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_f32(
+ float32_t* pSrcA,
+ uint32_t srcALen,
+ float32_t* pSrcB,
+ uint32_t srcBLen,
+ float32_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32* S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15* S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31* S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15* S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31* S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32* S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31* S,
+ uint8_t numStages,
+ q31_t* pCoeffs,
+ q63_t* pState,
+ uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_stereo_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f64;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64* S,
+ float64_t* pSrc,
+ float64_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32* S,
+ uint8_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32* S,
+ uint8_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64* S,
+ uint8_t numStages,
+ float64_t* pCoeffs,
+ float64_t* pState);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15* S,
+ uint16_t numStages,
+ q15_t* pCoeffs,
+ q15_t* pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31* S,
+ uint16_t numStages,
+ q31_t* pCoeffs,
+ q31_t* pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32* S,
+ uint16_t numStages,
+ float32_t* pCoeffs,
+ float32_t* pState);
+
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32* S,
+ uint16_t numStages,
+ float32_t* pkCoeffs,
+ float32_t* pvCoeffs,
+ float32_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31* S,
+ uint16_t numStages,
+ q31_t* pkCoeffs,
+ q31_t* pvCoeffs,
+ q31_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15* S,
+ uint16_t numStages,
+ q15_t* pkCoeffs,
+ q15_t* pvCoeffs,
+ q15_t* pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_f32(
+ const arm_lms_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pRef,
+ float32_t* pOut,
+ float32_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_init_f32(
+ arm_lms_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_init_q15(
+ arm_lms_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_q15(
+ const arm_lms_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pRef,
+ q15_t* pOut,
+ q15_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+} arm_lms_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_q31(
+ const arm_lms_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pRef,
+ q31_t* pOut,
+ q31_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_init_q31(
+ arm_lms_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pRef,
+ float32_t* pOut,
+ float32_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t* recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pRef,
+ q31_t* pOut,
+ q31_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t* recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pRef,
+ q15_t* pOut,
+ q15_t* pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_f32(
+ float32_t* pSrcA,
+ uint32_t srcALen,
+ float32_t* pSrcB,
+ uint32_t srcBLen,
+ float32_t* pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ q15_t* pSrcA,
+ uint32_t srcALen,
+ q15_t* pSrcB,
+ uint32_t srcBLen,
+ q15_t* pDst,
+ q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ q31_t* pSrcA,
+ uint32_t srcALen,
+ q31_t* pSrcB,
+ uint32_t srcBLen,
+ q31_t* pDst);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+void arm_correlate_opt_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst,
+ q15_t* pScratch1,
+ q15_t* pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q7(
+ q7_t* pSrcA,
+ uint32_t srcALen,
+ q7_t* pSrcB,
+ uint32_t srcBLen,
+ q7_t* pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32* S,
+ float32_t* pSrc,
+ float32_t* pDst,
+ float32_t* pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32* S,
+ uint16_t numTaps,
+ float32_t* pCoeffs,
+ float32_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31* S,
+ q31_t* pSrc,
+ q31_t* pDst,
+ q31_t* pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31* S,
+ uint16_t numTaps,
+ q31_t* pCoeffs,
+ q31_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15* S,
+ q15_t* pSrc,
+ q15_t* pDst,
+ q15_t* pScratchIn,
+ q31_t* pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15* S,
+ uint16_t numTaps,
+ q15_t* pCoeffs,
+ q15_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7* S,
+ q7_t* pSrc,
+ q7_t* pDst,
+ q7_t* pScratchIn,
+ q31_t* pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7* S,
+ uint16_t numTaps,
+ q7_t* pCoeffs,
+ q7_t* pState,
+ int32_t* pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t* pSinVal,
+ float32_t* pCosVal);
+
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t* pSinVal,
+ q31_t* pCosVal);
+
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S
points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32* S,
+ float32_t in)
+{
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+}
+
+/**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31* S,
+ q31_t in)
+{
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+
+/**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15* S,
+ q15_t in)
+{
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE* vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32* src,
+ arm_matrix_instance_f32* dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64* src,
+ arm_matrix_instance_f64* dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic
to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha
and Ibeta
.
+ * When Ialpha
is superposed with Ia
as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0
, in this condition Ialpha
and Ibeta
+ * can be calculated using only Ia
and Ib
.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia
and Ib
are the instantaneous stator phases and
+ * pIalpha
and pIbeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t* pIalpha,
+ float32_t* pIbeta)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+}
+
+
+/**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t* pIalpha,
+ q31_t* pIbeta)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_q7_to_q31(
+ q7_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa
and pIb
are the instantaneous stator phases and
+ * Ialpha
and Ibeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Clarke transform
+* @param[in] Ialpha input two-phase orthogonal vector axis alpha
+* @param[in] Ibeta input two-phase orthogonal vector axis beta
+* @param[out] pIa points to output three-phase coordinate a
+* @param[out] pIb points to output three-phase coordinate b
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t* pIa,
+ float32_t* pIb)
+{
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+}
+
+
+/**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t* pIa,
+ q31_t* pIb)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_q7_to_q15(
+ q7_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha
and the Ibeta
currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha
and Ibeta
are the stator vector components,
+ * pId
and pIq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t* pId,
+ float32_t* pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+}
+
+
+/**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t* pId,
+ q31_t* pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q7_to_float(
+ q7_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha
and pIbeta
are the stator vector components,
+ * Id
and Iq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Park transform
+* @param[in] Id input coordinate of rotor reference frame d
+* @param[in] Iq input coordinate of rotor reference frame q
+* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+* @param[in] sinVal sine value of rotation angle theta
+* @param[in] cosVal cosine value of rotation angle theta
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t* pIalpha,
+ float32_t* pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+}
+
+
+/**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t* pIalpha,
+ q31_t* pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_float(
+ q31_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S
points to an instance of the Linear Interpolate function data structure.
+ * x
is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32* S,
+ float32_t x)
+{
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t* pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0) {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues) {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+}
+
+
+/**
+*
+* @brief Process function for the Q31 Linear Interpolation Function.
+* @param[in] pYData pointer to Q31 Linear Interpolation table
+* @param[in] x input sample to process
+* @param[in] nValues number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t* pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0) {
+ return (pYData[0]);
+ }
+ else {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t* pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0) {
+ return (pYData[0]);
+ }
+ else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t* pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0) {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1)) {
+ return (pYData[nValues - 1]);
+ }
+ else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+}
+
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+float32_t arm_sin_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q31_t arm_sin_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q15_t arm_sin_q15(
+ q15_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+float32_t arm_cos_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q31_t arm_cos_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q15_t arm_cos_q15(
+ q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1
is the current estimate,
+ * x0
is the previous estimate, and
+ * f'(x0)
is the derivative of f()
evaluated at x0
.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t* pOut)
+{
+ if (in >= 0.0f) {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t* pOut);
+
+
+/**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t* pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t* circBuffer,
+ int32_t L,
+ uint16_t* writeOffset,
+ int32_t bufferInc,
+ const int32_t* src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t* circBuffer,
+ int32_t L,
+ int32_t* readOffset,
+ int32_t bufferInc,
+ int32_t* dst,
+ int32_t* dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t*) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q15 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t* circBuffer,
+ int32_t L,
+ uint16_t* writeOffset,
+ int32_t bufferInc,
+ const q15_t* src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t* circBuffer,
+ int32_t L,
+ int32_t* readOffset,
+ int32_t bufferInc,
+ q15_t* dst,
+ q15_t* dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t*) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t* circBuffer,
+ int32_t L,
+ uint16_t* writeOffset,
+ int32_t bufferInc,
+ const q7_t* src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t* circBuffer,
+ int32_t L,
+ int32_t* readOffset,
+ int32_t bufferInc,
+ q7_t* dst,
+ q7_t* dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t*) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q63_t* pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q63_t* pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q7_t* pResult);
+
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult);
+
+
+/**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_f32(
+ float32_t* pSrc,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q31(
+ q31_t* pSrc,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q15(
+ q15_t* pSrc,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ uint32_t numSamples,
+ q31_t* realResult,
+ q31_t* imagResult);
+
+
+/**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ uint32_t numSamples,
+ q63_t* realResult,
+ q63_t* imagResult);
+
+
+/**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ uint32_t numSamples,
+ float32_t* realResult,
+ float32_t* imagResult);
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_q15(
+ q15_t* pSrcCmplx,
+ q15_t* pSrcReal,
+ q15_t* pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_q31(
+ q31_t* pSrcCmplx,
+ q31_t* pSrcReal,
+ q31_t* pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_f32(
+ float32_t* pSrcCmplx,
+ float32_t* pSrcReal,
+ float32_t* pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q7_t* result,
+ uint32_t* index);
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q7(
+ q7_t* pSrc,
+ uint32_t blockSize,
+ q7_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q15(
+ q15_t* pSrc,
+ uint32_t blockSize,
+ q15_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q31(
+ q31_t* pSrc,
+ uint32_t blockSize,
+ q31_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_f32(
+ float32_t* pSrc,
+ uint32_t blockSize,
+ float32_t* pResult,
+ uint32_t* pIndex);
+
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q15(
+ q15_t* pSrcA,
+ q15_t* pSrcB,
+ q15_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q31(
+ q31_t* pSrcA,
+ q31_t* pSrcB,
+ q31_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_f32(
+ float32_t* pSrcA,
+ float32_t* pSrcB,
+ float32_t* pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q31(
+ float32_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q15(
+ float32_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q7(
+ float32_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_q15(
+ q31_t* pSrc,
+ q15_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_q7(
+ q31_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_float(
+ q15_t* pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_q31(
+ q15_t* pSrc,
+ q31_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_q7(
+ q15_t* pSrc,
+ q7_t* pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y)
is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows
specifies the number of rows in the table;
+ * numCols
specifies the number of columns in the table;
+ * and pData
points to an array of size numRows*numCols
values.
+ * The data table pTable
is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols]
where x and y are integers.
+ *
+ * \par
+ * Let (x, y)
specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+/**
+*
+* @brief Floating-point bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate.
+* @param[in] Y interpolation coordinate.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32* S,
+ float32_t X,
+ float32_t Y)
+{
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t* pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+}
+
+
+/**
+*
+* @brief Q31 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31* S,
+ q31_t X,
+ q31_t Y)
+{
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t* pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+}
+
+
+/**
+* @brief Q15 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15* S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t* pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+}
+
+
+/**
+* @brief Q7 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7* S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t* pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+#else
+#define LOW_OPTIMIZATION_EXIT
+#endif
+
+/* Enter low optimization region - place directly above function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+#define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define LOW_OPTIMIZATION_EXIT
+
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+#else
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
new file mode 100644
index 00000000..4617b128
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
@@ -0,0 +1,796 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version V5.0.1
+ * @date 03. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+#define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+#define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+#define __ARM_ARCH_7EM__ 1
+#endif
+
+/* __ARM_ARCH_8M_BASE__ not applicable */
+/* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static __inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT __packed struct
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+#define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXB(value, ptr) __strex(value, ptr)
+#else
+#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#else
+#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXW(value, ptr) __strex(value, ptr)
+#else
+#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
new file mode 100644
index 00000000..6b21a5be
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
@@ -0,0 +1,1735 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version V5.0.1
+ * @date 02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static __inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wpacked"
+struct __attribute__((packed)) T_UINT32 {
+ uint32_t v;
+};
+#pragma clang diagnostic pop
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+ ({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
new file mode 100644
index 00000000..89cd6902
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
@@ -0,0 +1,231 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.1
+ * @date 30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * ARM Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+
+#include
+
+#ifndef __NO_RETURN
+#define __NO_RETURN __noreturn
+#endif
+#ifndef __USED
+#define __USED __root
+#endif
+#ifndef __WEAK
+#define __WEAK __weak
+#endif
+#ifndef __UNALIGNED_UINT32
+__packed struct T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef __PACKED
+#define __PACKED __packed
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT __packed struct
+#endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+#include
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+struct __attribute__((packed)) T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed))
+#endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+struct __packed__ T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __align(x)
+#endif
+#ifndef __PACKED
+#define __PACKED __packed__
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __packed__
+#endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+#include
+
+#ifndef __ASM
+#define __ASM _asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+// NO RETURN is automatically detected hence no warning here
+#define __NO_RETURN
+#endif
+#ifndef __USED
+#warning No compiler specific solution for __USED. __USED is ignored.
+#define __USED
+#endif
+#ifndef __WEAK
+#define __WEAK __weak
+#endif
+#ifndef __UNALIGNED_UINT32
+@packed struct T_UINT32 {
+ uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef __PACKED
+#define __PACKED @packed
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT @packed struct
+#endif
+
+
+#else
+#error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
new file mode 100644
index 00000000..919f26d1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
@@ -0,0 +1,1900 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.1
+ * @date 02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __UNALIGNED_UINT32
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+struct __attribute__((packed)) T_UINT32 {
+ uint32_t v;
+};
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+// __ASM volatile ("nop");
+//}
+#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+// __ASM volatile ("wfi");
+//}
+#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+// __ASM volatile ("wfe");
+//}
+#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+// __ASM volatile ("sev");
+//}
+#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF"::: "memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF"::: "memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF"::: "memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+ ({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+ ({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+ ({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
new file mode 100644
index 00000000..4e65d1d9
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+/* CMSIS cmGrebe definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MBL_REV
+#define __ARMv8MBL_REV 0x0000U
+#warning "__ARMv8MBL_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT 0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT 0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
new file mode 100644
index 00000000..273c3849
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+/* CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MML_REV
+#define __ARMv8MML_REV 0x0000U
+#warning "__ARMv8MML_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT 0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
new file mode 100644
index 00000000..d06d984b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
@@ -0,0 +1,850 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV 0x0000U
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
new file mode 100644
index 00000000..ebc43f3a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
@@ -0,0 +1,975 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV 0x0000U
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
new file mode 100644
index 00000000..513635a5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+/* CMSIS cmGrebe definitions */
+#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM23_REV
+#define __CM23_REV 0x0000U
+#warning "__CM23_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT 0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT 0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+ uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
new file mode 100644
index 00000000..8cbf329b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
@@ -0,0 +1,1880 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV 0x0200U
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
new file mode 100644
index 00000000..00de7795
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM33_REV
+#define __CM33_REV 0x0000U
+#warning "__CM33_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT 0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT 0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
new file mode 100644
index 00000000..f4c8011f
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
@@ -0,0 +1,2061 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM4_REV
+#define __CM4_REV 0x0000U
+#warning "__CM4_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
new file mode 100644
index 00000000..c09acc82
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
@@ -0,0 +1,2592 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED 1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED 0U
+#endif
+#else
+#define __FPU_USED 0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM7_REV
+#define __CM7_REV 0x0000U
+#warning "__CM7_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT 0U
+#warning "__ICACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT 0U
+#warning "__DCACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DTCM_PRESENT
+#define __DTCM_PRESENT 0U
+#warning "__DTCM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+ return 1U; /* Single precision FPU */
+ }
+ else {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ register uint32_t ccsidr;
+ register uint32_t sets;
+ register uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+#if defined ( __CC_ARM )
+ __schedule_barrier();
+#endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+#endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
new file mode 100644
index 00000000..ed106336
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV 0x0000U
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
new file mode 100644
index 00000000..a1b17e1c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
@@ -0,0 +1,1851 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.1
+ * @date 25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC300_REV
+#define __SC300_REV 0x0000U
+#warning "__SC300_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */
+ uint32_t T: 1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+ uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+#define NVIC_GetActive __NVIC_GetActive
+#define NVIC_SetPriority __NVIC_SetPriority
+#define NVIC_GetPriority __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0) {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0) {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t* vectors = (uint32_t*)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ }
+ else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
new file mode 100644
index 00000000..cd6d8ab0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date: 21. September 2016
+ * $Revision: V1.0
+ *
+ * Project: TrustZone for ARMv8-M
+ * Title: Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ * Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
new file mode 100644
index 00000000..c7707893
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
@@ -0,0 +1,33 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file: dtype.h
+/// @author AE TEAM
+/// @brief Define the data types to be used in the project, including the function
+/// library and application code. Use the data types defined in this file.
+////////////////////////////////////////////////////////////////////////////////
+#ifndef __DTYPE_H
+#define __DTYPE_H //This is done to avoid including the header file repeatedly in the same file
+
+
+//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers
+#ifndef __I
+#define __I volatile const //only read
+#endif
+#ifndef __O
+#define __O volatile //only write
+#endif
+#ifndef __IO
+#define __IO volatile //read write
+#endif
+
+//Common data type definitions
+
+typedef unsigned char int8u; //haven't symbol8 bit integer variable
+typedef signed char int8s; //have symbol8 bit integer variable
+typedef unsigned short int16u; //haven't symbol16 bit integer variable
+typedef signed short int16s; //have symbol16 bit integer variable
+typedef unsigned int int32u; //haven't symbol32 bit integer variable
+typedef signed int int32s; //have symbol32 bit integer variable
+typedef float fp32; //Single-precision floating-point number (32-bit length)
+typedef double fp64; //Double-precision floating-point number (64-bit length)
+
+#endif //__DTYPE_H
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
new file mode 100644
index 00000000..dc0aa3d6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
@@ -0,0 +1,341 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_adc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_ADC_H
+#define __HAL_ADC_H
+
+// Files includes
+#include "types.h"
+#include "reg_adc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_HAL
+/// @brief ADC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Channels
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_Channel_0 = 0x00, ///< ADC Channel 0
+ ADC_Channel_1 = 0x01, ///< ADC Channel 1
+ ADC_Channel_2 = 0x02, ///< ADC Channel 2
+ ADC_Channel_3 = 0x03, ///< ADC Channel 3
+ ADC_Channel_4 = 0x04, ///< ADC Channel 4
+ ADC_Channel_5 = 0x05, ///< ADC Channel 5
+ ADC_Channel_6 = 0x06, ///< ADC Channel 6
+ ADC_Channel_7 = 0x07, ///< ADC Channel 7
+
+ ADC_Channel_8 = 0x08, ///< ADC Channel 8
+ ADC_Channel_9 = 0x09, ///< ADC Channel 9
+ ADC_Channel_10 = 0x0A, ///< ADC Channel 10
+ ADC_Channel_11 = 0x0B, ///< ADC Channel 11
+ ADC_Channel_12 = 0x0C, ///< ADC Channel 12
+ ADC_Channel_13 = 0x0D, ///< ADC Channel 13
+ ADC_Channel_14 = 0x0E, ///< ADC Channel 14
+ ADC_Channel_15 = 0x0F, ///< ADC Channel 15
+ ADC_Channel_TempSensor = 0x0E, ///< Temperature sensor channel(ADC1)
+ ADC_Channel_VoltReference = 0x0F, ///< Internal reference voltage channel(ADC1)
+ ADC_Channel_Vrefint = 0x0F, ///< Internal reference voltage channel(ADC1)
+
+} ADCCHANNEL_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Sampling_Times
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_Samctl_1_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 1.5t
+ ADC_Samctl_2_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 2.5t
+ ADC_Samctl_3_5 = ADC_SMPR1_SAMCTL0_3_5, ///< ADC sample time select 3.5t
+ ADC_Samctl_4_5 = ADC_SMPR1_SAMCTL0_4_5, ///< ADC sample time select 4.5t
+ ADC_Samctl_5_5 = ADC_SMPR1_SAMCTL0_5_5, ///< ADC sample time select 5.5t
+ ADC_Samctl_6_5 = ADC_SMPR1_SAMCTL0_6_5, ///< ADC sample time select 6.5t
+ ADC_Samctl_7_5 = ADC_SMPR1_SAMCTL0_7_5, ///< ADC sample time select 7.5t
+ ADC_Samctl_8_5 = ADC_SMPR1_SAMCTL0_8_5, ///< ADC sample time select 7.5t
+ ADC_Samctl_13_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 13.5t
+ ADC_Samctl_14_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 14.5t
+ ADC_Samctl_28_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 28.5t
+ ADC_Samctl_29_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 29.5t
+ ADC_Samctl_41_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 41.5t
+ ADC_Samctl_42_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 42.5t
+ ADC_Samctl_55_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 55.5t
+ ADC_Samctl_56_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 56.5t
+ ADC_Samctl_71_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 71.5t
+ ADC_Samctl_72_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 72.5t
+ ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t
+ ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5 ///< ADC sample time select 240.5t
+} ADCSAM_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Resolution
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12, ///< ADC resolution select 12bit
+ ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11, ///< ADC resolution select 11bit
+ ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10, ///< ADC resolution select 10bit
+ ADC_Resolution_9b = ADC_CFGR_RSLTCTL_9, ///< ADC resolution select 9bit
+ ADC_Resolution_8b = ADC_CFGR_RSLTCTL_8 ///< ADC resolution select 8bit
+} ADCRSL_TypeDef;
+/// @brief ADC_Prescare
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_PCLK2_PRESCARE_3 = ADC_CFGR_PRE_3, ///< ADC preclk 3
+ ADC_PCLK2_PRESCARE_5 = ADC_CFGR_PRE_5, ///< ADC preclk 5
+ ADC_PCLK2_PRESCARE_7 = ADC_CFGR_PRE_7, ///< ADC preclk 7
+ ADC_PCLK2_PRESCARE_9 = ADC_CFGR_PRE_9, ///< ADC preclk 9
+ ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11, ///< ADC preclk 11
+ ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13, ///< ADC preclk 13
+ ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15, ///< ADC preclk 15
+ ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17, ///< ADC preclk 17
+
+ ADC_PCLK2_PRESCARE_2 = ADC_CFGR_PRE_2, ///< ADC preclk 2
+ ADC_PCLK2_PRESCARE_4 = ADC_CFGR_PRE_4, ///< ADC preclk 4
+ ADC_PCLK2_PRESCARE_6 = ADC_CFGR_PRE_6, ///< ADC preclk 6
+ ADC_PCLK2_PRESCARE_8 = ADC_CFGR_PRE_8, ///< ADC preclk 8
+ ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10, ///< ADC preclk 10
+ ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12, ///< ADC preclk 12
+ ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14, ///< ADC preclk 14
+ ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16 ///< ADC preclk 16
+} ADCPRE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Conversion_Mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_Mode_Imm = ADC_CR_IMM, ///< ADC single convert mode
+ ADC_Mode_Scan = ADC_CR_SCAN, ///< ADC single period convert mode
+ ADC_Mode_Continue = ADC_CR_CONTINUE ///< ADC continue scan convert mode
+} ADCMODE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC1_ExternalTrigConv_T1_CC1 = ADC_CR_T1_CC1,
+ ADC1_ExternalTrigConv_T1_CC2 = ADC_CR_T1_CC2,
+ ADC1_ExternalTrigConv_T1_CC3 = ADC_CR_T1_CC3,
+ ADC1_ExternalTrigConv_T2_CC2 = ADC_CR_T2_CC2,
+ ADC1_ExternalTrigConv_T3_TRIG = ADC_CR_T3_TRIG,
+ ADC1_ExternalTrigConv_T3_CC1 = ADC_CR_T3_CC1,
+ ADC1_ExternalTrigConv_EXTI_11 = ADC_CR_EXTI_11,
+ ADC1_ExternalTrigConv_T1_CC4_CC5 = ADC_CR_T1_CC4_CC5,
+ ADC1_ExternalTrigConv_T1_TRIG = ADC_CR_T1_TRIG,
+ ADC1_ExternalTrigConv_T8_CC4 = ADC_CR_T8_CC4,
+ ADC1_ExternalTrigConv_T8_CC4_CC5 = ADC_CR_T8_CC4_CC5,
+ ADC1_ExternalTrigConv_T2_CC1 = ADC_CR_T2_CC1,
+ ADC1_ExternalTrigConv_T3_CC4 = ADC_CR_T3_CC4,
+ ADC1_ExternalTrigConv_T2_TRIG = ADC_CR_T2_TRIG,
+ ADC1_ExternalTrigConv_T8_CC5 = ADC_CR_T8_CC5,
+ ADC1_ExternalTrigConv_EXTI_15 = ADC_CR_EXTI_15,
+ ADC1_ExternalTrigConv_T1_CC4 = ADC_CR_TIM1_CC4,
+ ADC1_ExternalTrigConv_T1_CC5 = ADC_CR_TIM1_CC5
+} EXTERTRIG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Data_Align
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_DataAlign_Right = ADC_CR_RIGHT, ///< ADC data left align
+ ADC_DataAlign_Left = ADC_CR_LEFT ///< ADC data right align
+} ADCDATAALI_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Flags_Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_IT_EOC = 1, ///< ADC conversion flag
+ ADC_FLAG_EOC = 1,
+ ADC_IT_AWD = 2, ///< ADC window comparator flag
+ ADC_FLAG_AWD = 2
+} ADCFLAG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Trig_Edge
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_ADC_Trig_Edge_Dual = ADC_CR_TRG_EDGE_DUAL, ///< ADC trig edge dual mode down and up
+ ADC_ADC_Trig_Edge_Down = ADC_CR_TRG_EDGE_DOWN, ///< ADC trig edge single mode down
+ ADC_ADC_Trig_Edge_Up = ADC_CR_TRG_EDGE_UP, ///< ADC trig edge single mode up
+ ADC_ADC_Trig_Edge_Mask = ADC_CR_TRG_EDGE_MASK ///< ADC trig edge is mask, not allowed
+} ADCTRIGEDGE_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Scan_Direct
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_Scan_Direct_Up = ADC_CR_SCANDIR, ///< ADC scan from low channel to high channel
+ ADC_Scan_Direct_Down = 0 ///< ADC scan from High channel to low channel
+} ADCSCANDIRECT_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Trig_Shift
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_ADC_Trig_Shift_0 = ADC_CR_TRGSHIFT_0, ///< ADC trig shift bit is 0
+ ADC_ADC_Trig_Shift_4 = ADC_CR_TRGSHIFT_4, ///< ADC trig shift bit is 4
+ ADC_ADC_Trig_Shift_16 = ADC_CR_TRGSHIFT_16, ///< ADC trig shift bit is 16
+ ADC_ADC_Trig_Shift_32 = ADC_CR_TRGSHIFT_32, ///< ADC trig shift bit is 32
+ ADC_ADC_Trig_Shift_64 = ADC_CR_TRGSHIFT_64, ///< ADC trig shift bit is 64
+ ADC_ADC_Trig_Shift_128 = ADC_CR_TRGSHIFT_128, ///< ADC trig shift bit is 128
+ ADC_ADC_Trig_Shift_256 = ADC_CR_TRGSHIFT_256, ///< ADC trig shift bit is 256
+ ADC_ADC_Trig_Shift_512 = ADC_CR_TRGSHIFT_512, ///< ADC trig shift bit is 512
+} ADCTRIGSHIFT_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_Inject_Seqen_Len1 = 0, ///< ADC Injected Seqence length is 1
+ ADC_Inject_Seqen_Len2 = 1, ///< ADC Injected Seqence length is 2
+ ADC_Inject_Seqen_Len3 = 2, ///< ADC Injected Seqence length is 3
+ ADC_Inject_Seqen_Len4 = 3, ///< ADC Injected Seqence length is 4
+} ADC_INJ_SEQ_LEN_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC_InjectedChannel_1 = 0x00,
+ ADC_InjectedChannel_2 = 0x04,
+ ADC_InjectedChannel_3 = 0x08,
+ ADC_InjectedChannel_4 = 0x0c,
+} ADC_INJ_SEQ_Channel_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ ADC1_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
+ ADC1_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
+ ADC1_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
+ ADC1_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1
+ ADC1_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4
+ ADC1_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
+ ADC1_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
+ ADC1_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
+
+ ADC2_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
+ ADC2_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
+ ADC2_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
+ ADC2_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1
+ ADC2_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4
+ ADC2_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
+ ADC2_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
+
+ ADC2_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
+ ADC3_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
+ ADC3_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
+ ADC3_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
+ ADC3_InjectExtTrigSrc_T4_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM4 CC1
+ ADC3_InjectExtTrigSrc_T5_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM5 CC4
+ ADC3_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
+ ADC3_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
+ ADC3_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
+} EXTER_INJ_TRIG_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u32 ADC_Resolution; ///< Convert data resolution
+ u32 ADC_PRESCARE; ///< Clock prescaler
+ u32 ADC_Mode; ///< ADC conversion mode
+ FunctionalState ADC_ContinuousConvMode; ///< Useless just for compatibility
+ u32 ADC_ExternalTrigConv; ///< External trigger source selection
+ u32 ADC_DataAlign; ///< Data alignmentn
+} ADC_InitTypeDef;
+
+/// @}
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_Exported_Variables
+/// @{
+#ifdef _HAL_ADC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_Exported_Functions
+/// @{
+void ADC_DeInit(ADC_TypeDef* adc);
+void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct);
+void ADC_StructInit(ADC_InitTypeDef* init_struct);
+void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source);
+#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
+void ADC_TempSensorVrefintCmd(FunctionalState state);
+void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
+void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
+
+u16 ADC_GetConversionValue(ADC_TypeDef* adc);
+
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
+ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
+void ADC_TempSensorCmd(FunctionalState state);
+void ADC_VrefintCmd(FunctionalState state);
+void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state);
+void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel);
+void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num);
+void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource);
+void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length);
+void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr);
+u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc);
+void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value);
+u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
new file mode 100644
index 00000000..26a93d4a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
@@ -0,0 +1,130 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_bkp.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_BKP_H
+#define __HAL_BKP_H
+
+// Files includes
+#include "types.h"
+#include "reg_bkp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_HAL
+/// @brief BKP HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_Exported_Types
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Data_Backup_Register
+/// @anchor Data_Backup_Register
+
+typedef enum {
+ BKP_DR1 = 0x0010,
+ BKP_DR2 = 0x0014,
+ BKP_DR3 = 0x0018,
+ BKP_DR4 = 0x001C,
+ BKP_DR5 = 0x0020,
+ BKP_DR6 = 0x0024,
+ BKP_DR7 = 0x0028,
+ BKP_DR8 = 0x002C,
+ BKP_DR9 = 0x0030,
+ BKP_DR10 = 0x0034,
+ BKP_DR11 = 0x0038,
+ BKP_DR12 = 0x003C,
+ BKP_DR13 = 0x0040,
+ BKP_DR14 = 0x0044,
+ BKP_DR15 = 0x0048,
+ BKP_DR16 = 0x004C,
+ BKP_DR17 = 0x0050,
+ BKP_DR18 = 0x0054,
+ BKP_DR19 = 0x0058,
+ BKP_DR20 = 0x005C
+} BKPDR_Typedef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Tamper_Pin_active_level
+/// @anchor Tamper_Pin_active_level
+typedef enum {
+ BKP_TamperPinLevel_High, ///< Tamper pin active on high level
+ BKP_TamperPinLevel_Low = BKP_CR_TPAL, ///< Tamper pin active on low level
+} BKPTPAL_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_output_source_to_output_on_the_Tamper_pin
+/// @anchor RTC_output_source_to_output_on_the_Tamper_pin
+typedef enum {
+ BKP_RTCOutputSource_None = 0x0000, ///< No RTC output on the Tamper pin
+ BKP_RTCOutputSource_CalibClock = 0x0080, ///< Output the RTC clock with frequency divided by 64 on the Tamper pin
+ BKP_RTCOutputSource_Alarm = 0x0100, ///< Output the RTC Alarm pulse signal on the Tamper pin
+ BKP_RTCOutputSource_Second = 0x0300 ///< Output the RTC Second pulse signal on the Tamper pin
+} BKPRTCOUTPUTSRC_Typedef;
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_Exported_Variables
+/// @{
+#ifdef _HAL_BKP_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_Exported_Functions
+/// @{
+
+void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data);
+u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr);
+
+void BKP_DeInit(void);
+void BKP_ClearFlag(void);
+void BKP_ClearITPendingBit(void);
+void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level);
+void BKP_TamperPinCmd(FunctionalState state);
+void BKP_ITConfig(FunctionalState state);
+void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source);
+void BKP_SetRTCCalibrationValue(u8 calibration_value);
+
+ITStatus BKP_GetITStatus(void);
+FlagStatus BKP_GetFlagStatus(void);
+void exBKP_Init(void);
+void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data);
+u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_BKP_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
new file mode 100644
index 00000000..b7e1d4b4
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
@@ -0,0 +1,340 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_can.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CAN_H
+#define __HAL_CAN_H
+
+// Files includes
+#include "types.h"
+#include "reg_can.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_HAL
+/// @brief CAN HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Types
+/// @{
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Initialization
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CANINITFAILED = 0x00000000, ///< CAN initialization failed
+ CANINITOK = 0x00000001 ///< CAN initialization ok
+} emCAN_INIT_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_sleep_constants
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CANSLEEPFAILED = 0x00000000, ///< CAN did not enter the sleep mode
+ CANSLEEPOK = 0x00000001 ///< CAN entered the sleep mode
+} emCAN_SLEEP_conts_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_wake_up_constants
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CANWAKEUPFAILED = 0x00000000, ///< CAN did not leave the sleep mode
+ CANWAKEUPOK = 0x00000001 ///< CAN leaved the sleep mode
+} emCAN_WAKE_conts_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CAN_BASICMode = 0x00000000,
+ CAN_PELIMode = 0x00000080,
+ CAN_WorkMode = 0x00000080,
+ CAN_ResetMode = 0x00000001,
+ CAN_ListenOnlyMode = 0x00000002,
+ CAN_SeftTestMode = 0x00000004,
+ CAN_FilterMode_Singal = 0x00000008,
+ CAN_FilterMode_Double = 0x000000f7,
+ CAN_SleepMode = 0x00000010
+} emCAN_CAN_Mode_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BASIC_CAN_interrupt
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CAN_IT_RIE = CAN_CR_RIE, ///< Overflow interrupt enable
+ CAN_IT_TIE = CAN_CR_TIE, ///< Transmit interrupt enable
+ CAN_IT_EIE = CAN_CR_EIE, ///< Error interrupt enable
+ CAN_IT_OIE = CAN_CR_OIE ///< Receive interrupt enable
+} emCAN_BASIC_IntEn_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PELI_CAN_interrupt
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CAN_IT_RI = CAN_IR_RI, ///< Overflow interrupt enable
+ CAN_IT_TI = CAN_IR_TI, ///< Transmit interrupt enable
+ CAN_IT_EI = CAN_IR_EI, ///< Error interrupt enable
+ CAN_IT_DOI = CAN_IR_DOI, ///< Receive interrupt enable
+ CAN_IT_WUI = 0x00001010, ///< Receive interrupt enable
+ CAN_IT_EPI = CAN_IR_EPI, ///< Receive interrupt enable
+ CAN_IT_ALI = CAN_IR_ALI, ///< Receive interrupt enable
+ CAN_IT_BEI = CAN_IR_BEI, ///< Receive interrupt enable
+ CAN_IT_ALL = 0xFFFF ///< Receive interrupt enable
+
+} emCAN_PELI_IntEn_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Status
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CAN_STATUS_RBS = CAN_SR_RBS,
+ CAN_STATUS_DOS = CAN_SR_DOS,
+ CAN_STATUS_TBS = CAN_SR_TBS,
+ CAN_STATUS_TCS = CAN_SR_TCS,
+ CAN_STATUS_RS = CAN_SR_RS,
+ CAN_STATUS_TS = CAN_SR_TS,
+ CAN_STATUS_ES = CAN_SR_ES,
+ CAN_STATUS_BS = CAN_SR_BS
+} emCAN_Status_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Command_register
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CAN_TR = CAN_CMR_TR, ///< Transmission request
+ CAN_AT = CAN_CMR_AT,
+ CAN_RRB = CAN_CMR_RRB,
+ CAN_CDO = CAN_CMR_CDO
+} emCAN_Command_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Peli transmit frame definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DataFrame = 0, ///< Data Frame
+ RemoteFrame = !DataFrame
+} TransFrame;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Basic init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 SJW;
+ u8 BRP;
+ FlagStatus SAM;
+ u8 TESG2;
+ u8 TESG1;
+ FunctionalState GTS;
+ u8 CDCLK;
+ u8 CLOSE_OPEN_CLK;
+ u8 RXINTEN;
+ u8 CBP;
+} CAN_Basic_InitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Peli init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 SJW;
+ u8 BRP;
+ FlagStatus SAM;
+ u8 TESG2;
+ u8 TESG1;
+ FunctionalState LOM;
+ FunctionalState STM;
+ FunctionalState SM;
+ FunctionalState SRR;
+ u32 EWLR;
+} CAN_Peli_InitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Basic filter init structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ u8 CAN_FilterId; ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF.
+ u8 CAN_FilterMaskId; ///< Specifies the filter mask number or identification number, This parameter can be a value between
+ ///< 0x00 and 0xFF.
+} CAN_Basic_FilterInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Peli filter init structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ u8 AFM;
+ u8 CAN_FilterId0; ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF
+ u8 CAN_FilterId1;
+ u8 CAN_FilterId2;
+ u8 CAN_FilterId3;
+ u8 CAN_FilterMaskId0; ///< Specifies the filter mask number or identification number, This parameter can be a value between
+ ///< 0x00 and 0xFF
+ u8 CAN_FilterMaskId1;
+ u8 CAN_FilterMaskId2;
+ u8 CAN_FilterMaskId3;
+} CAN_Peli_FilterInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Basic Tx message structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ u8 IDH; ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF.
+ u8 IDL; ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7.
+ u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame.
+ u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
+ u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
+} CanBasicTxMsg;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Basic Rx message structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ u16 ID; ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.
+ u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame
+ u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8
+ u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to 0xFF.
+} CanBasicRxMsg;
+
+///////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Peli_Tx message structure definition
+///////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ u8 IDLL; ///< Specifies the extended identifier.
+ ///< This parameter can be a value between 0 to 0xFF.
+ u8 IDLH;
+ u8 IDHL;
+ u8 IDHH;
+ u8 FF; ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref
+ ///< CAN_identifier_type
+ u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref
+ ///< TransFrame.
+ u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
+ u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
+} CanPeliTxMsg;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Rx message structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u32 ID; ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.
+ u8 FF; ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref
+ ///< CAN_identifier_type.
+ u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame.
+ u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8.
+ u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to0xFF.
+} CanPeliRxMsg;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup parasmeter_of_CAN_transmission_register
+/// @{
+#define CANTXFAILED (0x00U) ///< CAN transmission failed
+#define CANTXOK (0x01U) ///< CAN transmission succeeded
+#define CANTXPENDING (0x02U) ///< CAN transmission pending
+#define CAN_NO_MB (0x04U) ///< CAN cell did not provide an empty mailbox
+/// @}
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Variables
+/// @{
+#ifdef _HAL_CAN_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Functions
+/// @{
+
+// Basic and Peli Work all need function ---------------------------------------
+
+void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode);
+void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state);
+void CAN_ClearDataOverflow(CAN_TypeDef* can);
+void CAN_ClearITPendingBit(CAN_TypeDef* can);
+
+// Basic Work function ---------------------------------------------------------
+void CAN_DeInit(CAN_TypeDef* can);
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct);
+void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct);
+void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state);
+void CAN_CancelTransmit(CAN_TypeDef* can);
+void CAN_FIFORelease(CAN_TypeDef* can);
+void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message);
+
+u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message);
+u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct);
+u8 CAN_Sleep(CAN_TypeDef* can);
+u8 CAN_WakeUp(CAN_TypeDef* can);
+
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag);
+ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it);
+
+// Peli Work function ----------------------------------------------------------
+void CAN_Peli_SleepMode_Cmd(FunctionalState state);
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct);
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct);
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
+void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message);
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message);
+void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message);
+void CAN_Peli_ITConfig(u32 it, FunctionalState state);
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud);
+
+u32 CAN_Peli_GetRxFIFOInfo(void);
+u8 CAN_Peli_GetLastErrorCode(void);
+u8 CAN_Peli_GetReceiveErrorCounter(void);
+u8 CAN_Peli_GetLSBTransmitErrorCounter(void);
+
+ITStatus CAN_Peli_GetITStatus(u32 it);
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
new file mode 100644
index 00000000..617318d5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
@@ -0,0 +1,228 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_comp.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_COMP_H
+#define __HAL_COMP_H
+
+
+// Files includes
+#include "reg_common.h"
+#include "reg_comp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_HAL
+/// @brief COMP HAL modules
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_InvertingInput
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_InvertingInput_IO0 = COMP_CSR_INM_0, ///< INM0 as COMP inverting input
+ COMP_InvertingInput_IO1 = COMP_CSR_INM_1, ///< INM1 as COMP inverting input
+ COMP_InvertingInput_IO2 = COMP_CSR_INM_2, ///< INM2 as COMP inverting input
+ COMP_InvertingInput_CRV = COMP_CSR_INM_3, ///< INM3 as COMP inverting input
+ COMP_InvertingInput_IO3 = COMP_CSR_INM_3, ///< INM3 as COMP inverting input
+} EM_COMP_InvertingInput;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_NonInvertingInput
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_NonInvertingInput_IO0 = COMP_CSR_INP_INP0, ///< INP0 as COMP non-inverting input
+ COMP_NonInvertingInput_IO1 = COMP_CSR_INP_INP1, ///< INP1 as COMP non-inverting input
+ COMP_NonInvertingInput_IO2 = COMP_CSR_INP_INP2, ///< INP2 as COMP non-inverting input
+ COMP_NonInvertingInput_IO3 = COMP_CSR_INP_INP3, ///< INP3 as COMP non-inverting input
+} EM_COMP_NonInvertingInput;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_Output
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_Output_None = 0x00000000, ///< No output
+ COMP_Output_TIM1BKIN = COMP_CSR_OUT_TIM1_BRAKE, ///< Timer1 brake input
+ COMP_Output_TIM1OCREFCLR = COMP_CSR_OUT_TIM1_OCREFCLR, ///< Timer1 ocrefclear input
+ COMP_Output_TIM1IC1 = COMP_CSR_OUT_TIM1_CAPTURE1, ///< Timer1 input capture 1
+ COMP_Output_TIM2IC4 = COMP_CSR_OUT_TIM2_CAPTURE4, ///< Timer2 input capture 4
+ COMP_Output_TIM2OCREFCLR = COMP_CSR_OUT_TIM2_OCREFCLR, ///< Timer2 ocrefclear input
+ COMP_Output_TIM3IC1 = COMP_CSR_OUT_TIM3_CAPTURE1, ///< Timer3 input capture 1
+ COMP_Output_TIM3OCREFCLR = COMP_CSR_OUT_TIM3_OCREFCLR ///< Timer3 ocrefclear input
+} EM_COMP_Output;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_OutputPoloarity
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_NonInverted = 0x00000000, ///< COMP non-inverting output
+ COMP_OutputPol_NonInverted = 0x00000000,
+ COMP_Inverted = 0x00008000, ///< COMP inverting output
+ COMP_OutputPol_Inverted = 0x00008000
+} EM_COMP_OutputPol;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_Hysteresis
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_Hysteresis_No = COMP_CSR_HYST_0, ///< Hysteresis Voltage: 0mV
+ COMP_Hysteresis_Low = COMP_CSR_HYST_15, ///< Hysteresis Voltage: 15mV
+ COMP_Hysteresis_Medium = COMP_CSR_HYST_30, ///< Hysteresis Voltage: 30mV
+ COMP_Hysteresis_High = COMP_CSR_HYST_90 ///< Hysteresis Voltage: 90mV
+} EM_COMP_Hysteresis;
+typedef enum {
+ COMP_Filter_0_Period = COMP_CSR_OFLT_0, ///< filter is ((u32)0x00000000)
+ COMP_Filter_2_Period = COMP_CSR_OFLT_1, ///< filter is ((u32)0x00040000)
+ COMP_Filter_4_Period = COMP_CSR_OFLT_2, ///< filter is ((u32)0x00080000)
+ COMP_Filter_8_Period = COMP_CSR_OFLT_3, ///< filter is ((u32)0x000C0000)
+ COMP_Filter_16_Period = COMP_CSR_OFLT_4, ///< filter is ((u32)0x00100000)
+ COMP_Filter_32_Period = COMP_CSR_OFLT_5, ///< filter is ((u32)0x00140000)
+ COMP_Filter_64_Period = COMP_CSR_OFLT_6, ///< filter is ((u32)0x00180000)
+ COMP_Filter_128_Period = COMP_CSR_OFLT_7, ///< filter is ((u32)0x001C0000)
+} EM_COMP_FILT;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_Mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_Mode_HighSpeed = COMP_CSR_MODE_HIGHRATE, ///< Comparator high rate mode
+ COMP_Mode_MediumSpeed = COMP_CSR_MODE_MEDIUMRATE, ///< Comparator medium rate mode
+ COMP_Mode_LowPower = COMP_CSR_MODE_LOWPOWER, ///< Comparator low power mode
+ COMP_Mode_UltraLowPower = COMP_CSR_MODE_LOWESTPOWER ///< Comparator lowest power mode
+} EM_COMP_Mode;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_OutputLevel
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP_OutputLevel_High = COMP_CSR_OUT, ///< High output
+ COMP_OutputLevel_Low = 0x00000000 ///< Low output
+} EM_COMP_OutputLevel;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ union {
+ u32 COMP_InvertingInput;
+ u32 Invert; ///< Selects the inverting input of the comparator.
+ };
+ union {
+ u32 COMP_NonInvertingInput;
+ u32 NonInvert; ///< Selects the non inverting input of the comparator.
+ };
+ union {
+ u32 COMP_Output;
+ u32 Output; ///< Selects the output redirection of the comparator.
+ u32 BlankingSrce; ///< Selects the output blanking source of the comparator.
+ };
+ union {
+ u32 COMP_OutputPol;
+ u32 OutputPol; ///< Selects the output polarity of the comparator.
+ };
+ union {
+ u32 COMP_Hysteresis;
+ u32 Hysteresis; ///< Selects the hysteresis voltage of the comparator.
+ };
+ union {
+ u32 COMP_Mode;
+ u32 Mode; ///< Selects the operating mode of the comparator and allows
+ };
+ union {
+ u32 COMP_Filter;
+ u32 OFLT; ///< to adjust the speed/consumption.
+ };
+} COMP_InitTypeDef;
+
+
+
+typedef struct {
+
+ FunctionalState COMP_Poll_En; ///< Selects the inverting input of the comparator.
+
+ u32 COMP_Poll_Ch; ///< Selects the non inverting input of the comparator.
+ u32 COMP_Poll_Fixn; ///< Selects the output redirection of the comparator.
+ u32 COMP_Poll_Period; ///< Selects the output polarity of the comparator.
+ u32 COMP_Poll_Pout; ///< Selects the hysteresis voltage of the comparator.
+
+} COMP_POLL_InitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_Exported_Constants
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ COMP1 = (0x00000C), ///< Select comparator 1
+ COMP2 = (0x000010), ///< Select comparator 2
+} COMP_Selection_TypeDef;
+
+#define COMP_BlankingSrce_None ((u32)0x00000000)
+#define COMP_CSR_CLEAR_MASK ((u32)0x00000003)
+
+#define COMP_CSR_COMPSW1 ((u32)0x00000002)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+///@defgroup COMP_Exported_Variables
+/// @{
+#ifdef _HAL_COMP_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_Exported_Functions
+/// @{
+
+
+void COMP_DeInit(COMP_Selection_TypeDef selection);
+void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct);
+void COMP_StructInit(COMP_InitTypeDef* init_struct);
+void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state);
+void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state);
+void COMP_LockConfig(COMP_Selection_TypeDef selection);
+
+u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection);
+
+void COMP_SetCrv(u8 crv_select, u8 crv_level);
+#define SET_COMP_CRV COMP_SetCrv
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_COMP_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
new file mode 100644
index 00000000..758c7a61
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
@@ -0,0 +1,62 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_conf.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CONF_H
+#define __HAL_CONF_H
+// Files includes
+#include "mm32_device.h"
+
+#include "hal_adc.h"
+#include "hal_bkp.h"
+#include "hal_can.h"
+#include "hal_comp.h"
+#include "hal_crc.h"
+#include "hal_crs.h"
+#include "hal_dac.h"
+#include "hal_dbg.h"
+#include "hal_dma.h"
+#include "hal_exti.h"
+#include "hal_flash.h"
+#include "hal_gpio.h"
+#include "hal_i2c.h"
+#include "hal_iwdg.h"
+#include "hal_misc.h"
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_rtc.h"
+#include "hal_spi.h"
+#include "hal_syscfg.h"
+#include "hal_tim.h"
+#include "hal_uart.h"
+#include "hal_uid.h"
+#include "hal_wwdg.h"
+#include "hal_redefine.h"
+#include "hal_eth.h"
+#include "hal_eth_conf.h"
+#include "hal_fsmc.h"
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_CONF_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
new file mode 100644
index 00000000..f5f3d605
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
@@ -0,0 +1,84 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_crc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CRC_H
+#define __HAL_CRC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_crc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_HAL
+/// @brief CRC HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Types
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Variables
+/// @{
+#ifdef _HAL_CRC_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Functions
+/// @{
+void CRC_ResetDR(void);
+void CRC_SetIDRegister(u8 id_value);
+
+u32 CRC_CalcCRC(u32 data);
+u32 CRC_CalcBlockCRC(u32* buffer, u32 length);
+u32 CRC_GetCRC(void);
+
+u8 CRC_GetIDRegister(void);
+
+/// @}
+
+/// @}
+
+/// @}
+
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_CRC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
new file mode 100644
index 00000000..d3c2a6cc
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
@@ -0,0 +1,46 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_crs.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CRS_H
+#define __HAL_CRS_H
+
+
+// Files includes
+#include "types.h"
+#include "reg_crs.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRS_HAL
+/// @brief CRS HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Types
+/// @{
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
new file mode 100644
index 00000000..e538b20b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
@@ -0,0 +1,166 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_dac.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DAC_H
+#define __HAL_DAC_H
+
+// Files includes
+#include "types.h"
+#include "reg_dac.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_HAL
+/// @brief DAC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Trigger_Selection
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DAC_Trigger_None = 0x00000000,
+ DAC_Trigger_T1_TRIG = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1),
+ DAC_Trigger_T3_TRIG = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1),
+ DAC_Trigger_T2_TRIG = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1),
+ DAC_Trigger_T4_TRIG = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1),
+ DAC_Trigger_Ext_IT9 = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1),
+ DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE)
+} emDACTRIG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Wave_Generation
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DAC_WaveGeneration_None = DAC_CR_WAVE1_NONE,
+ DAC_WaveGeneration_Noise = DAC_CR_WAVE1_NOISE,
+ DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE
+} emDACWAVE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Mask_Amplitude
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DAC_TriangleAmplitude_1 = DAC_CR_MAMP1_1,
+ DAC_TriangleAmplitude_3 = DAC_CR_MAMP1_3,
+ DAC_TriangleAmplitude_7 = DAC_CR_MAMP1_7,
+ DAC_TriangleAmplitude_15 = DAC_CR_MAMP1_15,
+ DAC_TriangleAmplitude_31 = DAC_CR_MAMP1_31,
+ DAC_TriangleAmplitude_63 = DAC_CR_MAMP1_63,
+ DAC_TriangleAmplitude_127 = DAC_CR_MAMP1_127,
+ DAC_TriangleAmplitude_255 = DAC_CR_MAMP1_255,
+ DAC_TriangleAmplitude_511 = DAC_CR_MAMP1_511,
+ DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023,
+ DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047,
+ DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095
+} emDACAMP_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief channel
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DAC_Channel_1, ///< DAC channel 1
+ DAC_Channel_2 = (u32)0x00000010 ///< DAC Channel 2
+} emDACCH_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Data_Alignement
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DAC_Align_12b_R = ((u32)0x00000000),
+ DAC_Align_12b_L = ((u32)0x00000004),
+ DAC_Align_8b_R = ((u32)0x00000008)
+} emDACALIGN_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Output_Buffer
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DAC_OutputBuffer_Enable = 0x00000000, ///< DAC output buffer enable
+ DAC_OutputBuffer_Disable = DAC_CR_BOFF1 ///< DAC output buffer disable
+} emDACBOFF_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ emDACTRIG_TypeDef DAC_Trigger;
+ emDACWAVE_TypeDef DAC_WaveGeneration;
+ emDACAMP_TypeDef DAC_LFSRUnmask_TriangleAmplitude;
+ emDACBOFF_TypeDef DAC_OutputBuffer;
+} DAC_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Constants
+/// @{
+#define DHR12R1_Offset ((u32)0x00000008)
+#define DHR12R2_Offset ((u32)0x00000014)
+#define DHR12RD_Offset ((u32)0x00000020)
+#define DOR_Offset ((u32)0x0000002C)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Variables
+/// @{
+#ifdef _HAL_DAC_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Functions
+/// @{
+void DAC_DeInit(void);
+void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct);
+void DAC_StructInit(DAC_InitTypeDef* init_struct);
+void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state);
+void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state);
+void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state);
+void DAC_DualSoftwareTriggerCmd(FunctionalState state);
+void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state);
+void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data);
+void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data);
+void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1);
+
+u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_DAC_H
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
new file mode 100644
index 00000000..0e9b41d1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_dbg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DBG_H
+#define __HAL_DBG_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DBG_HAL
+/// @brief DBG HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DBG_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DIV_Exported_Variables
+/// @{
+#ifdef _HAL_DBG_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DBG_Exported_Functions
+/// @{
+void DBGMCU_Configure(u32 periph, FunctionalState state);
+
+/// @}
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_DBG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
new file mode 100644
index 00000000..ff213370
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
@@ -0,0 +1,41 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_device.h
+/// @author AE team
+/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
+/// microcontroller devices
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DEVICE_H
+#define __HAL_DEVICE_H
+
+
+
+
+
+#include "mm32_device.h"
+
+
+#endif // __HAL_device_H
+
+/// @}
+
+
+/// @}
+
+/// @}
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
new file mode 100644
index 00000000..892e750b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
@@ -0,0 +1,306 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_dma.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DMA_H
+#define __HAL_DMA_H
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_dma.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_HAL
+/// @brief DMA HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA data transfer direction Enumerate definition
+/// @anchor DMA_data_transfer_direction
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_DIR_PeripheralSRC = 0U,
+ DMA_DIR_PeripheralDST = DMA_CCR_DIR // 0x00000010U
+} DMA_data_transfer_direction_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA peripheral incremented mode Enumerate definition
+/// @anchor DMA_peripheral_incremented_mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_PeripheralInc_Disable = 0U,
+ DMA_PeripheralInc_Enable = DMA_CCR_PINC // 0x00000040U
+} DMA_peripheral_incremented_mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA memory incremented mode Enumerate definition
+/// @anchor DMA_memory_incremented_mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_MemoryInc_Disable = 0U,
+ DMA_MemoryInc_Enable = DMA_CCR_MINC // 0x00000080U
+} DMA_memory_incremented_mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA peripheral data size Enumerate definition
+/// @anchor DMA_peripheral_data_size
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_PeripheralDataSize_Byte = 0U,
+ DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD,
+ DMA_PeripheralDataSize_Word = DMA_CCR_PSIZE_WORD
+} DMA_peripheral_data_size_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA memory data size Enumerate definition
+/// @anchor DMA_memory_data_size
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_MemoryDataSize_Byte = 0U,
+ DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD, // 0x00000400U
+ DMA_MemoryDataSize_Word = DMA_CCR_MSIZE_WORD // 0x00000800U
+} DMA_memory_data_size_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA circular normal mode Enumerate definition
+/// @anchor DMA_circular_normal_mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_Mode_Normal = 0U,
+ DMA_Mode_Circular = DMA_CCR_CIRC // 0x00000020U
+} DMA_circular_normal_mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA priority level Enumerate definition
+/// @anchor DMA_priority_level
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_Priority_Low = 0U,
+ DMA_Priority_Medium = DMA_CCR_PL_Medium, // 0x00001000U
+ DMA_Priority_High = DMA_CCR_PL_High, // 0x00002000U
+ DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh // 0x00003000U
+} DMA_priority_level_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA memory to memory Enumerate definition
+/// @anchor DMA_memory_to_memory
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_M2M_Disable = 0U,
+ DMA_M2M_Enable = DMA_CCR_M2M // 0x00004000U
+} DMA_memory_to_memory_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA auto reload Enumerate definition
+/// @anchor DMA_auto_reload
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_Auto_Reload_Disable = 0U, //
+ DMA_Auto_Reload_Enable = DMA_CCR_ARE
+} DMA_auto_reload_TypeDef;
+/// @brief DMA Interrupt Setting Enumerate definition
+/// @anchor DMA_auto_reload
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMA_IT_TC = DMA_CCR_TCIE, //(0x00000002UL),
+ DMA_IT_HT = DMA_CCR_HTIE, //(0x00000004UL),
+ DMA_IT_TE = DMA_CCR_TEIE, //(0x00000008UL),
+} DMA_Interrupt_EN_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA interrupts Enumerate definition
+/// @anchor DMA_Flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ DMAx_IT_GLy = (0x00000001UL),
+ DMAx_IT_TCy = (0x00000002UL),
+ DMAx_IT_HTy = (0x00000004UL),
+ DMAx_IT_TEy = (0x00000008UL),
+ DMA1_IT_GL1 = (0x00000001UL),
+ DMA1_IT_TC1 = (0x00000002UL),
+ DMA1_IT_HT1 = (0x00000004UL),
+ DMA1_IT_TE1 = (0x00000008UL),
+ DMA1_IT_GL2 = (0x00000010UL),
+ DMA1_IT_TC2 = (0x00000020UL),
+ DMA1_IT_HT2 = (0x00000040UL),
+ DMA1_IT_TE2 = (0x00000080UL),
+ DMA1_IT_GL3 = (0x00000100UL),
+ DMA1_IT_TC3 = (0x00000200UL),
+ DMA1_IT_HT3 = (0x00000400UL),
+ DMA1_IT_TE3 = (0x00000800UL),
+ DMA1_IT_GL4 = (0x00001000UL),
+ DMA1_IT_TC4 = (0x00002000UL),
+ DMA1_IT_HT4 = (0x00004000UL),
+ DMA1_IT_TE4 = (0x00008000UL),
+ DMA1_IT_GL5 = (0x00010000UL),
+ DMA1_IT_TC5 = (0x00020000UL),
+ DMA1_IT_HT5 = (0x00040000UL),
+ DMA1_IT_TE5 = (0x00080000UL),
+ DMA1_IT_GL6 = (0x00100000UL),
+ DMA1_IT_TC6 = (0x00200000UL),
+ DMA1_IT_HT6 = (0x00400000UL),
+ DMA1_IT_TE6 = (0x00800000UL),
+ DMA1_IT_GL7 = (0x01000000UL),
+ DMA1_IT_TC7 = (0x02000000UL),
+ DMA1_IT_HT7 = (0x04000000UL),
+ DMA1_IT_TE7 = (0x08000000UL),
+ DMA2_IT_GL1 = (0x10000001UL),
+ DMA2_IT_TC1 = (0x10000002UL),
+ DMA2_IT_HT1 = (0x10000004UL),
+ DMA2_IT_TE1 = (0x10000008UL),
+ DMA2_IT_GL2 = (0x10000010UL),
+ DMA2_IT_TC2 = (0x10000020UL),
+ DMA2_IT_HT2 = (0x10000040UL),
+ DMA2_IT_TE2 = (0x10000080UL),
+ DMA2_IT_GL3 = (0x10000100UL),
+ DMA2_IT_TC3 = (0x10000200UL),
+ DMA2_IT_HT3 = (0x10000400UL),
+ DMA2_IT_TE3 = (0x10000800UL),
+ DMA2_IT_GL4 = (0x10001000UL),
+ DMA2_IT_TC4 = (0x10002000UL),
+ DMA2_IT_HT4 = (0x10004000UL),
+ DMA2_IT_TE4 = (0x10008000UL),
+ DMA2_IT_GL5 = (0x10010000UL),
+ DMA2_IT_TC5 = (0x10020000UL),
+ DMA2_IT_HT5 = (0x10040000UL),
+ DMA2_IT_TE5 = (0x10080000UL),
+} DMA_Interrupts_TypeDef;
+typedef enum {
+ DMAx_FLAG_GLy = (0x00000001UL),
+ DMAx_FLAG_TCy = (0x00000002UL),
+ DMAx_FLAG_HTy = (0x00000004UL),
+ DMAx_FLAG_TEy = (0x00000008UL),
+ DMA1_FLAG_GL1 = (0x00000001UL),
+ DMA1_FLAG_TC1 = (0x00000002UL),
+ DMA1_FLAG_HT1 = (0x00000004UL),
+ DMA1_FLAG_TE1 = (0x00000008UL),
+ DMA1_FLAG_GL2 = (0x00000010UL),
+ DMA1_FLAG_TC2 = (0x00000020UL),
+ DMA1_FLAG_HT2 = (0x00000040UL),
+ DMA1_FLAG_TE2 = (0x00000080UL),
+ DMA1_FLAG_GL3 = (0x00000100UL),
+ DMA1_FLAG_TC3 = (0x00000200UL),
+ DMA1_FLAG_HT3 = (0x00000400UL),
+ DMA1_FLAG_TE3 = (0x00000800UL),
+ DMA1_FLAG_GL4 = (0x00001000UL),
+ DMA1_FLAG_TC4 = (0x00002000UL),
+ DMA1_FLAG_HT4 = (0x00004000UL),
+ DMA1_FLAG_TE4 = (0x00008000UL),
+ DMA1_FLAG_GL5 = (0x00010000UL),
+ DMA1_FLAG_TC5 = (0x00020000UL),
+ DMA1_FLAG_HT5 = (0x00040000UL),
+ DMA1_FLAG_TE5 = (0x00080000UL),
+ DMA1_FLAG_GL6 = (0x00100000UL),
+ DMA1_FLAG_TC6 = (0x00200000UL),
+ DMA1_FLAG_HT6 = (0x00400000UL),
+ DMA1_FLAG_TE6 = (0x00800000UL),
+ DMA1_FLAG_GL7 = (0x01000000UL),
+ DMA1_FLAG_TC7 = (0x02000000UL),
+ DMA1_FLAG_HT7 = (0x04000000UL),
+ DMA1_FLAG_TE7 = (0x08000000UL),
+ DMA2_FLAG_GL1 = (0x10000001UL),
+ DMA2_FLAG_TC1 = (0x10000002UL),
+ DMA2_FLAG_HT1 = (0x10000004UL),
+ DMA2_FLAG_TE1 = (0x10000008UL),
+ DMA2_FLAG_GL2 = (0x10000010UL),
+ DMA2_FLAG_TC2 = (0x10000020UL),
+ DMA2_FLAG_HT2 = (0x10000040UL),
+ DMA2_FLAG_TE2 = (0x10000080UL),
+ DMA2_FLAG_GL3 = (0x10000100UL),
+ DMA2_FLAG_TC3 = (0x10000200UL),
+ DMA2_FLAG_HT3 = (0x10000400UL),
+ DMA2_FLAG_TE3 = (0x10000800UL),
+ DMA2_FLAG_GL4 = (0x10001000UL),
+ DMA2_FLAG_TC4 = (0x10002000UL),
+ DMA2_FLAG_HT4 = (0x10004000UL),
+ DMA2_FLAG_TE4 = (0x10008000UL),
+ DMA2_FLAG_GL5 = (0x10010000UL),
+ DMA2_FLAG_TC5 = (0x10020000UL),
+ DMA2_FLAG_HT5 = (0x10040000UL),
+ DMA2_FLAG_TE5 = (0x10080000UL),
+} DMA_Flags_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u32 DMA_PeripheralBaseAddr; ///< the peripheral base address for DMA Channeln.
+ u32 DMA_MemoryBaseAddr; ///< the memory base address for DMA Channeln.
+ DMA_data_transfer_direction_TypeDef DMA_DIR; ///< the peripheral is the source or destination.
+ u32 DMA_BufferSize; ///< Specifies the buffer size, in data unit, of the Buffer size
+ DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc; ///< Specifies whether the Peripheral address increment or not
+ DMA_memory_incremented_mode_TypeDef DMA_MemoryInc; ///< Specifies whether the memory address register is increment or not
+ DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize; ///< Specifies the Peripheral data width.
+ DMA_memory_data_size_TypeDef DMA_MemoryDataSize; ///< Specifies the Memory data width.
+ DMA_circular_normal_mode_TypeDef DMA_Mode; ///< Specifies the operation mode of the DMA Channeln circular or normal mode.
+ DMA_priority_level_TypeDef DMA_Priority; ///< Specifies the software priority for the DMA priority level
+ DMA_memory_to_memory_TypeDef DMA_M2M; ///< Specifies if the DMA Channeln will be used in memory-to-memory transfer.
+ DMA_auto_reload_TypeDef DMA_Auto_reload; ///< Specifies if the DMA Channeln will auto reload the CNDTR register
+} DMA_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_Exported_Variables
+/// @{
+#ifdef _HAL_DMA_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_Exported_Functions
+/// @{
+
+void DMA_DeInit(DMA_Channel_TypeDef* channel);
+void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct);
+void DMA_StructInit(DMA_InitTypeDef* init_struct);
+void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state);
+void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state);
+void DMA_ClearFlag(DMA_Flags_TypeDef flag);
+void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length);
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel);
+FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag);
+ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it);
+
+void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr);
+void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len);
+void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr);
+
+/// @}
+
+/// @}
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_DMA_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
new file mode 100644
index 00000000..4000bbaa
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
@@ -0,0 +1,729 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file HAL_eth.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __HAL_ETH_H
+#define __HAL_ETH_H
+
+// Files includes
+#include "types.h"
+#include "mm32_device.h"
+#include "HAL_eth_conf.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_HAL
+/// @brief ETH HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_Exported_Types
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// ETH | Header | Extra | VLAN tag | Payload | CRC |
+// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 |
+#define ETH_MAX_PACKET_SIZE 1524
+#define ETH_HEADER 14 ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte
+#define ETH_EXTRA 2
+#define VLAN_TAG 4
+#define ETH_PAYLOAD_MIN 46
+#define ETH_PAYLOAD_MAX 1500
+#define JUMBO_FRAME_PAYLOAD 9000
+
+#ifndef ETH_RX_BUF_SIZE
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+#ifndef ETH_RX_BUF_NUM
+#define ETH_RX_BUF_NUM 4
+#endif
+
+#ifndef ETH_TX_BUF_SIZE
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+#ifndef ETH_TX_BUF_NUM
+#define ETH_TX_BUF_NUM 4
+#endif
+
+#define ETH_DMA_RDES_FL_Pos 16 ///< Ethernet DMA Received Frame Length Position
+
+#define ETH_WAKEUP_REGISTER_LENGTH 8 ///< ETHERNET Remote Wake-up frame register length
+
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 ///< ETHERNET Missed frames counter Shift
+
+#define ETH_DMA_TDES_COLLISION_COUNTSHIFT 3 ///< ETHERNET DMA Tx descriptors Collision Count Shift
+#define ETH_DMA_TDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift
+
+#define ETH_DMA_RDES_FRAME_LENGTHSHIFT 16 ///< ETHERNET DMA Rx descriptors Frame Length Shift
+#define ETH_DMA_RDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift
+
+///< ETHERNET errors
+#define ETH_ERROR ((u32)0)
+#define ETH_SUCCESS ((u32)1)
+
+
+#ifdef _HAL_ETH_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH Init Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 ETH_AutoNegotiation;
+ __IO u32 ETH_Watchdog;
+ __IO u32 ETH_Jabber;
+ __IO u32 ETH_InterFrameGap;
+ __IO u32 ETH_CarrierSense;
+ __IO u32 ETH_Speed;
+ __IO u32 ETH_ReceiveOwn;
+ __IO u32 ETH_LoopbackMode;
+ __IO u32 ETH_Mode;
+ __IO u32 ETH_ChecksumOffload;
+ __IO u32 ETH_RetryTransmission;
+ __IO u32 ETH_AutomaticPadCRCStrip;
+ __IO u32 ETH_BackOffLimit;
+ __IO u32 ETH_DeferralCheck;
+ __IO u32 ETH_ReceiveAll;
+ __IO u32 ETH_SourceAddrFilter;
+ __IO u32 ETH_PassControlFrames;
+ __IO u32 ETH_BroadcastFramesReception;
+ __IO u32 ETH_DestinationAddrFilter;
+ __IO u32 ETH_PromiscuousMode;
+ __IO u32 ETH_MulticastFramesFilter;
+ __IO u32 ETH_UnicastFramesFilter;
+ __IO u32 ETH_HashTableHigh;
+ __IO u32 ETH_HashTableLow;
+ __IO u32 ETH_PauseTime;
+ __IO u32 ETH_ZeroQuantaPause;
+ __IO u32 ETH_PauseLowThreshold;
+ __IO u32 ETH_UnicastPauseFrameDetect;
+ __IO u32 ETH_ReceiveFlowControl;
+ __IO u32 ETH_TransmitFlowControl;
+ __IO u32 ETH_VLANTagComparison;
+ __IO u32 ETH_VLANTagIdentifier;
+ __IO u32 ETH_DropTCPIPChecksumErrorFrame;
+ __IO u32 ETH_ReceiveStoreForward;
+ __IO u32 ETH_FlushReceivedFrame;
+ __IO u32 ETH_TransmitStoreForward;
+ __IO u32 ETH_TransmitThresholdControl;
+ __IO u32 ETH_ForwardErrorFrames;
+ __IO u32 ETH_ForwardUndersizedGoodFrames;
+ __IO u32 ETH_ReceiveThresholdControl;
+ __IO u32 ETH_SecondFrameOperate;
+ __IO u32 ETH_AddressAlignedBeats;
+ __IO u32 ETH_FixedBurst;
+ __IO u32 ETH_RxDMABurstLength;
+ __IO u32 ETH_TxDMABurstLength;
+ __IO u32 ETH_DescriptorSkipLength;
+ __IO u32 ETH_DMAArbitration;
+} ETH_InitTypeDef;
+
+typedef struct {
+ __IO u32 CS; ///< Control and Status
+ __IO u32 BL; ///< Buffer1, Buffer2 lengths
+ __IO u32 BUF1ADDR; ///< Buffer1 address pointer
+ __IO u32 BUF2NDADDR; ///< Buffer2 or next descriptor address pointer
+
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS ///< Enhanced ETHERNET DMA PTP Descriptors
+ __IO u32 ExtendedStatus; ///< Extended status for PTP receive descriptor
+ __IO u32 Reserved1; ///< Reserved
+ __IO u32 TimeStampLow; ///< Time Stamp Low value for transmit and receive
+ __IO u32 TimeStampHigh; ///< Time Stamp High value for transmit and receive
+#endif
+} ETH_DMADESCTypeDef;
+
+typedef struct {
+ __IO u32 len;
+ __IO u32 buf;
+ __IO ETH_DMADESCTypeDef* ptrDesc;
+} FrameTypeDef;
+
+typedef struct {
+ __IO ETH_DMADESCTypeDef* ptrFS_Rx_Desc; ///< First Segment Rx Desc
+ __IO ETH_DMADESCTypeDef* ptrLS_Rx_Desc; ///< Last Segment Rx Desc
+ __IO u32 cnt; ///< Segment count
+} ETH_DMA_Rx_Frame_infos;
+
+
+
+#define ETH_DMA_TDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine
+#define ETH_DMA_TDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
+#define ETH_DMA_TDES_JT ((u32)0x00004000) ///< Jabber Timeout
+#define ETH_DMA_TDES_FF ((u32)0x00002000) ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush
+#define ETH_DMA_TDES_LCA ((u32)0x00000800) ///< Loss of Carrier: carrier lost during transmission
+#define ETH_DMA_TDES_NC ((u32)0x00000400) ///< No Carrier: no carrier signal from the transceiver
+#define ETH_DMA_TDES_LCO ((u32)0x00000200) ///< Late Collision: transmission aborted due to collision
+#define ETH_DMA_TDES_EC ((u32)0x00000100) ///< Excessive Collision: transmission aborted after 16 collisions
+#define ETH_DMA_TDES_VF ((u32)0x00000080) ///< VLAN Frame
+#define ETH_DMA_TDES_CC ((u32)0x00000078) ///< Collision Count
+#define ETH_DMA_TDES_ED ((u32)0x00000004) ///< Excessive Deferral
+#define ETH_DMA_TDES_UF ((u32)0x00000002) ///< Underflow Error: late data arrival from the memory
+#define ETH_DMA_TDES_DB ((u32)0x00000001) ///< Deferred Bit
+
+#define ETH_DMA_TDES_IC ((u32)0x80000000) ///< Interrupt on Completion
+#define ETH_DMA_TDES_LS ((u32)0x40000000) ///< Last Segment
+#define ETH_DMA_TDES_FS ((u32)0x20000000) ///< First Segment
+#define ETH_DMA_TDES_DC ((u32)0x04000000) ///< Disable CRC
+#define ETH_DMA_TDES_TER ((u32)0x02000000) ///< Transmit end of ring
+#define ETH_DMA_TDES_TCH ((u32)0x01000000) ///< Second Address Chained
+#define ETH_DMA_TDES_DP ((u32)0x00800000) ///< Disable Padding
+#define ETH_DMA_TDES_TBS2 ((u32)0x003FF800) ///< Transmit Buffer 2 Size
+#define ETH_DMA_TDES_TBS1 ((u32)0x000007FF) ///< Transmit Buffer 1 Size
+
+#define ETH_DMA_TDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer
+
+#define ETH_DMA_TDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer
+
+#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
+#define ETH_DMA_PTP_TDES_TTSL ((u32)0xFFFFFFFF) ///< Transmit Time Stamp Low
+#define ETH_DMA_PTP_TDES_TTSH ((u32)0xFFFFFFFF) ///< Transmit Time Stamp High
+#endif
+
+#define ETH_DMA_RDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine
+#define ETH_DMA_RDES_AFM ((u32)0x40000000) ///< DA Filter Fail for the rx frame
+#define ETH_DMA_RDES_FL ((u32)0x3FFF0000) ///< Receive descriptor frame length
+#define ETH_DMA_RDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
+#define ETH_DMA_RDES_DE ((u32)0x00004000) ///< Descriptor error: no more descriptors for receive frame
+#define ETH_DMA_RDES_SAF ((u32)0x00002000) ///< SA Filter Fail for the received frame
+#define ETH_DMA_RDES_LE ((u32)0x00001000) ///< Frame size not matching with length field
+#define ETH_DMA_RDES_OE ((u32)0x00000800) ///< Overflow Error: Frame was damaged due to buffer overflow
+#define ETH_DMA_RDES_VLAN ((u32)0x00000400) ///< VLAN Tag: received frame is a VLAN frame
+#define ETH_DMA_RDES_FS ((u32)0x00000200) ///< First descriptor of the frame
+#define ETH_DMA_RDES_LS ((u32)0x00000100) ///< Last descriptor of the frame
+#define ETH_DMA_RDES_IPV4HCE ((u32)0x00000080) ///< IPC Checksum Error: Rx Ipv4 header checksum error
+#define ETH_DMA_RDES_LC ((u32)0x00000040) ///< Late collision occurred during reception
+#define ETH_DMA_RDES_FT ((u32)0x00000020) ///< Frame type - Ethernet, otherwise 802.3
+#define ETH_DMA_RDES_RWT ((u32)0x00000010) ///< Receive Watchdog Timeout: watchdog timer expired during reception
+#define ETH_DMA_RDES_RE ((u32)0x00000008) ///< Receive error: error reported by MII interface
+#define ETH_DMA_RDES_DBE ((u32)0x00000004) ///< Dribble bit error: frame contains non int multiple of 8 bits
+#define ETH_DMA_RDES_CE ((u32)0x00000002) ///< CRC error
+#define ETH_DMA_RDES_MAMPCE ((u32)0x00000001) ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+
+#define ETH_DMA_RDES_DIC ((u32)0x80000000) ///< Disable Interrupt on Completion
+#define ETH_DMA_RDES_RER ((u32)0x02000000) ///< Receive End of Ring
+#define ETH_DMA_RDES_RCH ((u32)0x01000000) ///< Second Address Chained
+#define ETH_DMA_RDES_RBS2 ((u32)0x003FF800) ///< Receive Buffer2 Size
+#define ETH_DMA_RDES_RBS1 ((u32)0x000007FF) ///< Receive Buffer1 Size
+
+#define ETH_DMA_RDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer
+
+#define ETH_DMA_RDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer
+
+
+#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
+#define ETH_DMA_PTP_RDES_PTPV ((u32)0x00002000) ///< PTP Version
+#define ETH_DMA_PTP_RDES_PTPFT ((u32)0x00001000) ///< PTP Frame Type
+#define ETH_DMA_PTP_RDES_PTPMT ((u32)0x00000F00) ///< PTP Message Type
+#define ETH_DMA_PTP_RDES_PTPMT_Sync ((u32)0x00000100) ///< SYNC message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_FollowUp ((u32)0x00000200) ///< FollowUp message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_DelayReq ((u32)0x00000300) ///< DelayReq message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_DelayResp ((u32)0x00000400) ///< DelayResp message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce ((u32)0x00000500) ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock)
+#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag ((u32)0x00000600) ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)
+#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700) ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock)
+#define ETH_DMA_PTP_RDES_IPV6PR ((u32)0x00000080) ///< IPv6 Packet Received
+#define ETH_DMA_PTP_RDES_IPV4PR ((u32)0x00000040) ///< IPv4 Packet Received
+#define ETH_DMA_PTP_RDES_IPCB ((u32)0x00000020) ///< IP Checksum Bypassed
+#define ETH_DMA_PTP_RDES_IPPE ((u32)0x00000010) ///< IP Payload Error
+#define ETH_DMA_PTP_RDES_IPHE ((u32)0x00000008) ///< IP Header Error
+#define ETH_DMA_PTP_RDES_IPPT ((u32)0x00000007) ///< IP Payload Type
+#define ETH_DMA_PTP_RDES_IPPT_UDP ((u32)0x00000001) ///< UDP payload encapsulated in the IP datagram
+#define ETH_DMA_PTP_RDES_IPPT_TCP ((u32)0x00000002) ///< TCP payload encapsulated in the IP datagram
+#define ETH_DMA_PTP_RDES_IPPT_ICMP ((u32)0x00000003) ///< ICMP payload encapsulated in the IP datagram
+
+
+
+#define ETH_DMA_PTP_RDES_TTSL ((u32)0xFFFFFFFF) ///< Receive Time Stamp Low
+#define ETH_DMA_PTP_RDES_TTSH ((u32)0xFFFFFFFF) ///< Receive Time Stamp High
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+#define PHY_READ_TIMEOUT ((u32)0x0004FFFF)
+#define PHY_WRITE_TIMEOUT ((u32)0x0004FFFF)
+
+#define PHY_BCR 0 ///< Transceiver Basic Control Register
+#define PHY_BSR 1 ///< Transceiver Basic Status Register
+
+#define PHY_Reset ((u16)0x8000) ///< PHY Reset
+#define PHY_Loopback ((u16)0x4000) ///< Select loop-back mode
+#define PHY_FULLDUPLEX_100M ((u16)0x2100) ///< Set the full-duplex mode at 100 Mb/s
+#define PHY_HALFDUPLEX_100M ((u16)0x2000) ///< Set the half-duplex mode at 100 Mb/s
+#define PHY_FULLDUPLEX_10M ((u16)0x0100) ///< Set the full-duplex mode at 10 Mb/s
+#define PHY_HALFDUPLEX_10M ((u16)0x0000) ///< Set the half-duplex mode at 10 Mb/s
+#define PHY_AutoNegotiation ((u16)0x1000) ///< Enable auto-negotiation function
+#define PHY_Restart_AutoNegotiation ((u16)0x0200) ///< Restart auto-negotiation function
+#define PHY_Powerdown ((u16)0x0800) ///< Select the power down mode
+#define PHY_Isolate ((u16)0x0400) ///< Isolate PHY from MII
+
+#define PHY_AutoNego_Complete ((u16)0x0020) ///< Auto-Negotiation process completed
+#define PHY_Linked_Status ((u16)0x0004) ///< Valid link established
+#define PHY_Jabber_detection ((u16)0x0002) ///< Jabber condition detected
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_AutoNegotiation_Enable ((u32)0x00000001)
+#define ETH_AutoNegotiation_Disable ((u32)0x00000000)
+
+#define ETH_Watchdog_Enable ((u32)0x00000000)
+#define ETH_Watchdog_Disable ((u32)0x00800000)
+
+#define ETH_Jabber_Enable ((u32)0x00000000)
+#define ETH_Jabber_Disable ((u32)0x00400000)
+
+#define ETH_InterFrameGap_96Bit ((u32)0x00000000) ///< minimum IFG between frames during transmission is 96Bit
+#define ETH_InterFrameGap_88Bit ((u32)0x00020000) ///< minimum IFG between frames during transmission is 88Bit
+#define ETH_InterFrameGap_80Bit ((u32)0x00040000) ///< minimum IFG between frames during transmission is 80Bit
+#define ETH_InterFrameGap_72Bit ((u32)0x00060000) ///< minimum IFG between frames during transmission is 72Bit
+#define ETH_InterFrameGap_64Bit ((u32)0x00080000) ///< minimum IFG between frames during transmission is 64Bit
+#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) ///< minimum IFG between frames during transmission is 56Bit
+#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) ///< minimum IFG between frames during transmission is 48Bit
+#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) ///< minimum IFG between frames during transmission is 40Bit
+
+#define ETH_CarrierSense_Enable ((u32)0x00000000)
+#define ETH_CarrierSense_Disable ((u32)0x00010000)
+
+#define ETH_Speed_10M ((u32)0x00000000)
+#define ETH_Speed_100M ((u32)0x00004000)
+
+#define ETH_ReceiveOwn_Enable ((u32)0x00000000)
+#define ETH_ReceiveOwn_Disable ((u32)0x00002000)
+
+#define ETH_LoopbackMode_Enable ((u32)0x00001000)
+#define ETH_LoopbackMode_Disable ((u32)0x00000000)
+
+#define ETH_Mode_FullDuplex ((u32)0x00000800)
+#define ETH_Mode_HalfDuplex ((u32)0x00000000)
+
+#define ETH_ChecksumOffload_Enable ((u32)0x00000400)
+#define ETH_ChecksumOffload_Disable ((u32)0x00000000)
+
+#define ETH_RetryTransmission_Enable ((u32)0x00000000)
+#define ETH_RetryTransmission_Disable ((u32)0x00000200)
+
+#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)
+
+#define ETH_BackOffLimit_10 ((u32)0x00000000)
+#define ETH_BackOffLimit_8 ((u32)0x00000020)
+#define ETH_BackOffLimit_4 ((u32)0x00000040)
+#define ETH_BackOffLimit_1 ((u32)0x00000060)
+
+#define ETH_DeferralCheck_Enable ((u32)0x00000010)
+#define ETH_DeferralCheck_Disable ((u32)0x00000000)
+
+#define ETH_ReceiveAll_Enable ((u32)0x80000000)
+#define ETH_ReceiveAll_Disable ((u32)0x00000000)
+
+#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
+#define ETH_SourceAddrFilter_Disable ((u32)0x00000000)
+
+#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) ///< MAC filters all control frames from reaching the application
+#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) ///< MAC forwards all control frames to application even if they fail the Address Filter
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) ///< MAC forwards control frames that pass the Address Filter.
+
+#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)
+#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)
+
+#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)
+
+#define ETH_PromiscuousMode_Enable ((u32)0x00000001)
+#define ETH_PromiscuousMode_Disable ((u32)0x00000000)
+
+#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)
+#define ETH_MulticastFramesFilter_None ((u32)0x00000010)
+
+#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)
+
+#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)
+#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)
+
+#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) ///< Pause time minus 4 slot times
+#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) ///< Pause time minus 28 slot times
+#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) ///< Pause time minus 144 slot times
+#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) ///< Pause time minus 256 slot times
+
+#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
+
+#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)
+#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)
+
+#define ETH_TransmitFlowControl_Enable ((u32)0x00000002)
+#define ETH_TransmitFlowControl_Disable ((u32)0x00000000)
+
+#define ETH_VLANTagComparison_12Bit ((u32)0x00010000)
+#define ETH_VLANTagComparison_16Bit ((u32)0x00000000)
+
+#define ETH_MAC_FLAG_TST ((u32)0x00000200) ///< Time stamp trigger flag (on MAC)
+#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) ///< MMC transmit flag
+#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) ///< MMC receive flag
+#define ETH_MAC_FLAG_MMC ((u32)0x00000010) ///< MMC flag (on MAC)
+#define ETH_MAC_FLAG_PMT ((u32)0x00000008) ///< PMT flag (on MAC)
+
+#define ETH_MAC_IT_TST ((u32)0x00000200) ///< Time stamp trigger interrupt (on MAC)
+#define ETH_MAC_IT_MMCT ((u32)0x00000040) ///< MMC transmit interrupt
+#define ETH_MAC_IT_MMCR ((u32)0x00000020) ///< MMC receive interrupt
+#define ETH_MAC_IT_MMC ((u32)0x00000010) ///< MMC interrupt (on MAC)
+#define ETH_MAC_IT_PMT ((u32)0x00000008) ///< PMT interrupt (on MAC)
+
+#define ETH_MAC_Address0 ((u32)0x00000000)
+#define ETH_MAC_Address1 ((u32)0x00000008)
+#define ETH_MAC_Address2 ((u32)0x00000010)
+#define ETH_MAC_Address3 ((u32)0x00000018)
+
+#define ETH_MAC_AddressFilter_SA ((u32)0x00000000)
+#define ETH_MAC_AddressFilter_DA ((u32)0x00000008)
+
+#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) ///< Mask MAC Address high reg bits [15:8]
+#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) ///< Mask MAC Address high reg bits [7:0]
+#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) ///< Mask MAC Address low reg bits [31:24]
+#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) ///< Mask MAC Address low reg bits [23:16]
+#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) ///< Mask MAC Address low reg bits [15:8]
+#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) ///< Mask MAC Address low reg bits [70]
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMA_TDES_LastSegment ((u32)0x40000000) ///< Last Segment
+#define ETH_DMA_TDES_FirstSegment ((u32)0x20000000) ///< First Segment
+
+#define ETH_DMA_TDES_ChecksumByPass ((u32)0x00000000) ///< Checksum engine bypass
+#define ETH_DMA_TDES_ChecksumIPV4Header ((u32)0x00400000) ///< IPv4 header checksum insertion
+#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment ((u32)0x00800000) ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present
+#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull ((u32)0x00C00000) ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header
+
+#define ETH_DMA_RDES_Buffer1 ((u32)0x00000000) ///< DMA Rx Desc Buffer1
+#define ETH_DMA_RDES_Buffer2 ((u32)0x00000001) ///< DMA Rx Desc Buffer2
+
+#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)
+
+#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)
+#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)
+
+#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)
+#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)
+
+#define ETH_TransmitStoreForward_Enable ((u32)0x00200000)
+#define ETH_TransmitStoreForward_Disable ((u32)0x00000000)
+
+#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Transmit FIFO is 64 Bytes
+#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) ///< threshold level of the MTL Transmit FIFO is 128 Bytes
+#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) ///< threshold level of the MTL Transmit FIFO is 192 Bytes
+#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) ///< threshold level of the MTL Transmit FIFO is 256 Bytes
+#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) ///< threshold level of the MTL Transmit FIFO is 40 Bytes
+#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) ///< threshold level of the MTL Transmit FIFO is 32 Bytes
+#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) ///< threshold level of the MTL Transmit FIFO is 24 Bytes
+#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) ///< threshold level of the MTL Transmit FIFO is 16 Bytes
+
+#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)
+#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)
+
+#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)
+
+#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Receive FIFO is 64 Bytes
+#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) ///< threshold level of the MTL Receive FIFO is 32 Bytes
+#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) ///< threshold level of the MTL Receive FIFO is 96 Bytes
+#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) ///< threshold level of the MTL Receive FIFO is 128 Bytes
+
+#define ETH_SecondFrameOperate_Enable ((u32)0x00000004)
+#define ETH_SecondFrameOperate_Disable ((u32)0x00000000)
+
+#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)
+#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)
+
+#define ETH_FixedBurst_Enable ((u32)0x00010000)
+#define ETH_FixedBurst_Disable ((u32)0x00000000)
+
+#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 1
+#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 2
+#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4
+#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8
+#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16
+#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32
+#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4
+#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8
+#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16
+#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32
+#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 64
+#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 128
+
+#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
+#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
+#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
+#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
+#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
+#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
+#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
+#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
+#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
+#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
+#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
+#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
+
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)
+
+#define ETH_DMA_FLAG_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA)
+#define ETH_DMA_FLAG_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA)
+#define ETH_DMA_FLAG_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA)
+#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) ///< Error bits 0-Rx DMA, 1-Tx DMA
+#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) ///< Error bits 0-write trnsf, 1-read transfr
+#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) ///< Error bits 0-data buffer, 1-desc. access
+#define ETH_DMA_FLAG_NIS ((u32)0x00010000) ///< Normal interrupt summary flag
+#define ETH_DMA_FLAG_AIS ((u32)0x00008000) ///< Abnormal interrupt summary flag
+#define ETH_DMA_FLAG_ER ((u32)0x00004000) ///< Early receive flag
+#define ETH_DMA_FLAG_FBE ((u32)0x00002000) ///< Fatal bus error flag
+#define ETH_DMA_FLAG_ET ((u32)0x00000400) ///< Early transmit flag
+#define ETH_DMA_FLAG_RWT ((u32)0x00000200) ///< Receive watchdog timeout flag
+#define ETH_DMA_FLAG_RPS ((u32)0x00000100) ///< Receive process stopped flag
+#define ETH_DMA_FLAG_RBU ((u32)0x00000080) ///< Receive buffer unavailable flag
+#define ETH_DMA_FLAG_R ((u32)0x00000040) ///< Receive flag
+#define ETH_DMA_FLAG_TU ((u32)0x00000020) ///< Underflow flag
+#define ETH_DMA_FLAG_RO ((u32)0x00000010) ///< Overflow flag
+#define ETH_DMA_FLAG_TJT ((u32)0x00000008) ///< Transmit jabber timeout flag
+#define ETH_DMA_FLAG_TBU ((u32)0x00000004) ///< Transmit buffer unavailable flag
+#define ETH_DMA_FLAG_TPS ((u32)0x00000002) ///< Transmit process stopped flag
+#define ETH_DMA_FLAG_T ((u32)0x00000001) ///< Transmit flag
+
+#define ETH_DMA_IT_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA)
+#define ETH_DMA_IT_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA)
+#define ETH_DMA_IT_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA)
+#define ETH_DMA_IT_NIS ((u32)0x00010000) ///< Normal interrupt summary
+#define ETH_DMA_IT_AIS ((u32)0x00008000) ///< Abnormal interrupt summary
+#define ETH_DMA_IT_ER ((u32)0x00004000) ///< Early receive interrupt
+#define ETH_DMA_IT_FBE ((u32)0x00002000) ///< Fatal bus error interrupt
+#define ETH_DMA_IT_ET ((u32)0x00000400) ///< Early transmit interrupt
+#define ETH_DMA_IT_RWT ((u32)0x00000200) ///< Receive watchdog timeout interrupt
+#define ETH_DMA_IT_RPS ((u32)0x00000100) ///< Receive process stopped interrupt
+#define ETH_DMA_IT_RBU ((u32)0x00000080) ///< Receive buffer unavailable interrupt
+#define ETH_DMA_IT_R ((u32)0x00000040) ///< Receive interrupt
+#define ETH_DMA_IT_TU ((u32)0x00000020) ///< Underflow interrupt
+#define ETH_DMA_IT_RO ((u32)0x00000010) ///< Overflow interrupt
+#define ETH_DMA_IT_TJT ((u32)0x00000008) ///< Transmit jabber timeout interrupt
+#define ETH_DMA_IT_TBU ((u32)0x00000004) ///< Transmit buffer unavailable interrupt
+#define ETH_DMA_IT_TPS ((u32)0x00000002) ///< Transmit process stopped interrupt
+#define ETH_DMA_IT_T ((u32)0x00000001) ///< Transmit interrupt
+
+#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Tx Command issued
+#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) ///< Running - fetching the Tx descriptor
+#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) ///< Running - waiting for status
+#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) ///< Running - reading the data from host memory
+#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) ///< Suspended - Tx Descriptor unavailable
+#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) ///< Running - closing Rx descriptor
+
+#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Rx Command issued
+#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) ///< Running - fetching the Rx descriptor
+#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) ///< Running - waiting for packet
+#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) ///< Suspended - Rx Descriptor unavailable
+#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) ///< Running - closing descriptor
+#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) ///< Running - queuing the receive frame into host memory
+
+#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) ///< Overflow bit for FIFO overflow counter
+#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) ///< Overflow bit for missed frame counter
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) ///< Wake-Up Frame Filter Register Pointer Reset
+#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) ///< Wake-Up Frame Received
+#define ETH_PMT_FLAG_MPR ((u32)0x00000020) ///< Magic Packet Received
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMC_IT_TGF ((u32)0x00200000) ///< When Tx good frame counter reaches half the maximum value
+#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) ///< When Tx good multi col counter reaches half the maximum value
+#define ETH_MMC_IT_TGFSC ((u32)0x00004000) ///< When Tx good single col counter reaches half the maximum value
+
+#define ETH_MMC_IT_RGUF ((u32)0x10020000) ///< When Rx good unicast frames counter reaches half the maximum value
+#define ETH_MMC_IT_RFAE ((u32)0x10000040) ///< When Rx alignment error counter reaches half the maximum value
+#define ETH_MMC_IT_RFCE ((u32)0x10000020) ///< When Rx crc error counter reaches half the maximum value
+
+#define ETH_MMCCR ((u32)0x00000100) ///< MMC CR register
+#define ETH_MMCRIR ((u32)0x00000104) ///< MMC RIR register
+#define ETH_MMCTIR ((u32)0x00000108) ///< MMC TIR register
+#define ETH_MMCRIMR ((u32)0x0000010C) ///< MMC RIMR register
+#define ETH_MMCTIMR ((u32)0x00000110) ///< MMC TIMR register
+#define ETH_MMCTGFSCCR ((u32)0x0000014C) ///< MMC TGFSCCR register
+#define ETH_MMCTGFMSCCR ((u32)0x00000150) ///< MMC TGFMSCCR register
+#define ETH_MMCTGFCR ((u32)0x00000168) ///< MMC TGFCR register
+#define ETH_MMCRFCECR ((u32)0x00000194) ///< MMC RFCECR register
+#define ETH_MMCRFAECR ((u32)0x00000198) ///< MMC RFAECR register
+#define ETH_MMCRGUFCR ((u32)0x000001C4) ///< MMC RGUFCR register
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_PTP_FineUpdate ((u32)0x00000001) ///< Fine Update method
+#define ETH_PTP_CoarseUpdate ((u32)0x00000000) ///< Coarse Update method
+
+#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) ///< Addend Register Update
+#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) ///< Time Stamp Interrupt Trigger
+#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) ///< Time Stamp Update
+#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) ///< Time Stamp Initialize
+
+#define ETH_PTP_FLAG_TSTTR ((u32)0x10000002) ///< Time stamp target time reached
+#define ETH_PTP_FLAG_TSSO ((u32)0x10000001) ///< Time stamp seconds overflow
+
+#define ETH_PTP_PositiveTime ((u32)0x00000000) ///< Positive time value
+#define ETH_PTP_NegativeTime ((u32)0x80000000) ///< Negative time value
+
+#define ETH_PTPTSCR ((u32)0x00000700) ///< PTP TSCR register
+#define ETH_PTPSSIR ((u32)0x00000704) ///< PTP SSIR register
+#define ETH_PTPTSHR ((u32)0x00000708) ///< PTP TSHR register
+#define ETH_PTPTSLR ((u32)0x0000070C) ///< PTP TSLR register
+#define ETH_PTPTSHUR ((u32)0x00000710) ///< PTP TSHUR register
+#define ETH_PTPTSLUR ((u32)0x00000714) ///< PTP TSLUR register
+#define ETH_PTPTSAR ((u32)0x00000718) ///< PTP TSAR register
+#define ETH_PTPTTHR ((u32)0x0000071C) ///< PTP TTHR register
+#define ETH_PTPTTLR ((u32)0x00000720) ///< PTP TTLR register
+
+#define ETH_PTPTSSR ((u32)0x00000728) ///< PTP TSSR register
+
+#define ETH_PTP_OrdinaryClock ((u32)0x00000000) ///< Ordinary Clock
+#define ETH_PTP_BoundaryClock ((u32)0x00010000) ///< Boundary Clock
+#define ETH_PTP_EndToEndTransparentClock ((u32)0x00020000) ///< End To End Transparent Clock
+#define ETH_PTP_PeerToPeerTransparentClock ((u32)0x00030000) ///< Peer To Peer Transparent Clock
+
+#define ETH_PTP_SnapshotMasterMessage ((u32)0x00008000) ///< Time stamp snapshot for message relevant to master enable
+#define ETH_PTP_SnapshotEventMessage ((u32)0x00004000) ///< Time stamp snapshot for event message enable
+#define ETH_PTP_SnapshotIPV4Frames ((u32)0x00002000) ///< Time stamp snapshot for IPv4 frames enable
+#define ETH_PTP_SnapshotIPV6Frames ((u32)0x00001000) ///< Time stamp snapshot for IPv6 frames enable
+#define ETH_PTP_SnapshotPTPOverEthernetFrames ((u32)0x00000800) ///< Time stamp snapshot for PTP over ethernet frames enable
+#define ETH_PTP_SnapshotAllReceivedFrames ((u32)0x00000100) ///< Time stamp snapshot for all received frames enable
+
+#define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) ///< ETHERNET MAC address high offset
+#define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) ///< ETHERNET MAC address low offset
+
+#define MACMIIAR_CR_MASK ((u32)0xFFFFFFE3)
+
+#define MACCR_CLEAR_MASK ((u32)0xFF20810F)
+#define MACFCR_CLEAR_MASK ((u32)0x0000FF41)
+#define DMAOMR_CLEAR_MASK ((u32)0xF8DE3F23)
+
+
+
+GLOBAL __IO ETH_DMADESCTypeDef* DMATxDescToSet;
+GLOBAL __IO ETH_DMADESCTypeDef* DMARxDescToGet;
+
+GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
+GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos;
+GLOBAL __IO u32 Frame_Rx_index;
+
+#undef GLOBAL
+
+void ETH_DeInit(void);
+void ETH_StructInit(ETH_InitTypeDef* ptr);
+u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr);
+void ETH_Start(void);
+void ETH_Stop(void);
+void ETH_MACTransmissionCmd(FunctionalState sta);
+void ETH_MACReceptionCmd(FunctionalState sta);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);
+void ETH_BackPressureActivationCmd(FunctionalState sta);
+void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr);
+void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr);
+void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta);
+void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta);
+void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte);
+FrameTypeDef ETH_Get_Received_Frame(void);
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
+u32 ETH_Prepare_Transmit_Descriptors(u16 len);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
+u32 ETH_CheckFrameReceived(void);
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf);
+u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+FlagStatus ETH_GetDMAFlagStatus(u32 flag);
+void ETH_DMAClearFlag(u32 flag);
+void ETH_DMAITConfig(u32 it, FunctionalState sta);
+ITStatus ETH_GetDMAITStatus(u32 it);
+void ETH_DMAClearITPendingBit(u32 it);
+u32 ETH_GetTransmitProcessState(void);
+u32 ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState sta);
+void ETH_DMAReceptionCmd(FunctionalState sta);
+FlagStatus ETH_GetDMAOverflowStatus(u32 val);
+u32 ETH_GetRxOverflowMissedFrameCounter(void);
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
+u32 ETH_GetCurrentTxDescStartAddress(void);
+u32 ETH_GetCurrentRxDescStartAddress(void);
+u32 ETH_GetCurrentTxBufferAddress(void);
+u32 ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+void ETH_SetReceiveWatchdogTimer(u8 val);
+u16 ETH_ReadPHYRegister(u16 addr, u16 reg);
+u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val);
+u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta);
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(u32* buf);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta);
+FlagStatus ETH_GetPMTFlagStatus(u32 flag);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState sta);
+void ETH_MagicPacketDetectionCmd(FunctionalState sta);
+void ETH_PowerDownCmd(FunctionalState sta);
+void ETH_MMCCounterFullPreset(void);
+void ETH_MMCCounterHalfPreset(void);
+void ETH_MMCCounterFreezeCmd(FunctionalState sta);
+void ETH_MMCResetOnReadCmd(FunctionalState sta);
+void ETH_MMCCounterRolloverCmd(FunctionalState sta);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(u32 it, FunctionalState sta);
+ITStatus ETH_GetMMCITStatus(u32 it);
+u32 ETH_GetMMCRegister(u32 reg);
+
+/// @}
+
+/// @}
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_ETH_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
new file mode 100644
index 00000000..f00e17e6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
@@ -0,0 +1,68 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_eth_conf.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __HAL_ETH_CONF_H
+#define __HAL_ETH_CONF_H
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_HAL
+/// @brief ETH HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_Exported_Types
+/// @{
+
+
+// #define USE_ENHANCED_DMA_DESCRIPTORS
+// #define CUSTOM_DRIVER_BUFFERS_CONFIG
+#define DP83848
+
+#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#define ETH_RX_BUF_NUM 4
+#define ETH_TX_BUF_NUM 4
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+#if defined(DP83848)
+#define PHY_SR ((u16)0x10)
+#define PHY_SR_LINKSTATUS ((u16)0x0001)
+#define PHY_SPEED_STATUS ((u16)0x0002)
+#define PHY_DUPLEX_STATUS ((u16)0x0004)
+
+#define PHY_MICR ((u16)0x11)
+#define PHY_MICR_INT_EN ((u16)0x0002)
+#define PHY_MICR_INT_OE ((u16)0x0001)
+
+#define PHY_MISR ((u16)0x12)
+#define PHY_MISR_LINK_INT_EN ((u16)0x0020)
+#define PHY_LINK_STATUS ((u16)0x2000)
+#endif
+
+/// @}
+
+/// @}
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_ETH_CONF_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
new file mode 100644
index 00000000..a90daff9
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
@@ -0,0 +1,181 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_exti.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_EXTI_H
+#define __HAL_EXTI_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_exti.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_HAL
+/// @brief EXTI HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI mode enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ EXTI_Mode_Interrupt = 0x00, ///< EXTI interrupt mode
+ EXTI_Mode_Event = 0x04 ///< EXTI event mode
+} EXTIMode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Trigger enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ EXTI_Trigger_Rising = 0x08, ///< EXTI rising edge triggering
+ EXTI_Trigger_Falling = 0x0C, ///< EXTI falling edge triggering
+ EXTI_Trigger_Rising_Falling = 0x10 ///< EXTI rising and falling edge triggers
+} EXTITrigger_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u32 EXTI_Line; ///< Specifies the EXTI lines to be enabled or disabled.
+ ///< This parameter can be any combination of @ref EXTI_Lines
+ EXTIMode_TypeDef EXTI_Mode; ///< Specifies the mode for the EXTI lines.
+ ///< This parameter can be a value of @ref EXTIMode_TypeDef
+ EXTITrigger_TypeDef EXTI_Trigger; ///< Specifies the trigger signal active edge for the EXTI lines.
+ ///< This parameter can be a value of @ref EXTIMode_TypeDef
+ FunctionalState EXTI_LineCmd; ///< Specifies the new state of the selected EXTI lines.
+ ///< This parameter can be set either to ENABLE or DISABLE
+} EXTI_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Constants
+/// @{
+
+
+
+#define EXTI_LineNone ((u32)0x0000000) ///< No interrupt selected
+#define EXTI_Line0 ((u32)0x0000001) ///< External interrupt line 0
+#define EXTI_Line1 ((u32)0x0000002) ///< External interrupt line 1
+#define EXTI_Line2 ((u32)0x0000004) ///< External interrupt line 2
+#define EXTI_Line3 ((u32)0x0000008) ///< External interrupt line 3
+#define EXTI_Line4 ((u32)0x0000010) ///< External interrupt line 4
+#define EXTI_Line5 ((u32)0x0000020) ///< External interrupt line 5
+#define EXTI_Line6 ((u32)0x0000040) ///< External interrupt line 6
+#define EXTI_Line7 ((u32)0x0000080) ///< External interrupt line 7
+#define EXTI_Line8 ((u32)0x0000100) ///< External interrupt line 8
+#define EXTI_Line9 ((u32)0x0000200) ///< External interrupt line 9
+#define EXTI_Line10 ((u32)0x0000400) ///< External interrupt line 10
+#define EXTI_Line11 ((u32)0x0000800) ///< External interrupt line 11
+#define EXTI_Line12 ((u32)0x0001000) ///< External interrupt line 12
+#define EXTI_Line13 ((u32)0x0002000) ///< External interrupt line 13
+#define EXTI_Line14 ((u32)0x0004000) ///< External interrupt line 14
+#define EXTI_Line15 ((u32)0x0008000) ///< External interrupt line 15
+#define EXTI_Line16 ((u32)0x0010000) ///< External interrupt line 16 Connected to the PVD Output
+#define EXTI_Line17 ((u32)0x0020000) ///< External interrupt line 17 Connected to the RTC Alarm event
+#define EXTI_Line18 ((u32)0x0040000) ///< External interrupt line 18 Connected to the USB Wakeup from suspend event
+#define EXTI_Line19 ((u32)0x0080000) ///< External interrupt line 19
+#define EXTI_Line20 ((u32)0x0100000) ///< External interrupt line 20
+#define EXTI_Line21 ((u32)0x0200000) ///< External interrupt line 21
+#define EXTI_Line22 ((u32)0x0400000) ///< External interrupt line 22
+#define EXTI_Line23 ((u32)0x0800000) ///< External interrupt line 23
+#define EXTI_Line24 ((u32)0x1000000) ///< External interrupt line 24
+
+#define EXTI_PortSourceGPIOA (0x00U)
+#define EXTI_PortSourceGPIOB (0x01U)
+#define EXTI_PortSourceGPIOC (0x02U)
+#define EXTI_PortSourceGPIOD (0x03U)
+#define EXTI_PortSourceGPIOE (0x04U)
+#define EXTI_PortSourceGPIOF (0x05U)
+
+#define EXTI_PinSource0 (0x00U)
+#define EXTI_PinSource1 (0x01U)
+#define EXTI_PinSource2 (0x02U)
+#define EXTI_PinSource3 (0x03U)
+#define EXTI_PinSource4 (0x04U)
+#define EXTI_PinSource5 (0x05U)
+#define EXTI_PinSource6 (0x06U)
+#define EXTI_PinSource7 (0x07U)
+#define EXTI_PinSource8 (0x08U)
+#define EXTI_PinSource9 (0x09U)
+#define EXTI_PinSource10 (0x0AU)
+#define EXTI_PinSource11 (0x0BU)
+#define EXTI_PinSource12 (0x0CU)
+#define EXTI_PinSource13 (0x0DU)
+#define EXTI_PinSource14 (0x0EU)
+#define EXTI_PinSource15 (0x0FU)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Variables
+/// @{
+
+#ifdef _HAL_EXTI_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Functions
+/// @{
+
+FlagStatus EXTI_GetFlagStatus(u32 line);
+ITStatus EXTI_GetITStatus(u32 line);
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* init_struct);
+void EXTI_StructInit(EXTI_InitTypeDef* init_struct);
+void EXTI_GenerateSWInterrupt(u32 line);
+void EXTI_ClearFlag(u32 line);
+void EXTI_ClearITPendingBit(u32 line);
+void exEXTI_LineDisable(u32 line);
+u32 exEXTI_GetAllFlagStatus(void);
+
+
+void EXTI_MemoryRemapConfig(u32 memory_remap);
+void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_EXTI_H
+////////////////////////////////////////////////////////////////////////////////
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
new file mode 100644
index 00000000..ee313dee
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
@@ -0,0 +1,230 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_flash.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_FLASH_H
+#define __HAL_FLASH_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_flash.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_HAL
+/// @brief FLASH HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Status
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ FLASH_BUSY = 1, ///< FLASH busy status
+ FLASH_ERROR_PG, ///< FLASH programming error status
+ FLASH_ERROR_WRP, ///< FLASH write protection error status
+ FLASH_COMPLETE, ///< FLASH end of operation status
+ FLASH_TIMEOUT ///< FLASH Last operation timed out status
+} FLASH_Status;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Latency
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ FLASH_Latency_0 = FLASH_ACR_LATENCY_0, ///< FLASH Zero Latency cycle
+ FLASH_Latency_1 = FLASH_ACR_LATENCY_1, ///< FLASH One Latency cycle
+ FLASH_Latency_2 = FLASH_ACR_LATENCY_2, ///< FLASH Two Latency cycles
+ FLASH_Latency_3 = FLASH_ACR_LATENCY_3 ///< FLASH Three Latency cycles
+} FLASH_Latency_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Half_Cycle_Enable_Disable
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ FLASH_HalfCycleAccess_Enable = FLASH_ACR_HLFCYA, ///< FLASH Half Cycle Enable
+ FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA ///< FLASH Half Cycle Disable
+} FLASH_HalfCycleAccess_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Prefetch_Buffer_Enable_Disable
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ FLASH_PrefetchBuffer_Enable = FLASH_ACR_PRFTBE, ///< FLASH Prefetch Buffer Enable
+ FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE ///< FLASH Prefetch Buffer Disable
+} FLASH_PrefetchBuffer_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Option_Bytes_IWatchdog
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ OB_IWDG_SW = 0x0001, ///< Software IWDG selected
+ OB_IWDG_HW = 0x0000 ///< Hardware IWDG selected
+} OB_IWDG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Option_Bytes_nRST_STOP
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ OB_STOP_NoRST = 0x0002, ///< No reset generated when entering in STOP
+ OB_STOP_RST = 0x0000 ///< Reset generated when entering in STOP
+} OB_STOP_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Option_Bytes_nRST_STDBY
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ OB_STDBY_NoRST = 0x0004, ///< No reset generated when entering in STANDBY
+ OB_STDBY_RST = 0x0000 ///< Reset generated when entering in STANDBY
+} OB_STDBY_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_Interrupts
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ FLASH_IT_ERROR = FLASH_CR_ERRIE, ///< FPEC error interrupt source
+ FLASH_IT_EOP = FLASH_CR_EOPIE ///< End of FLASH Operation Interrupt source
+} FLASH_IT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_Flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ FLASH_FLAG_EOP = FLASH_SR_EOP, ///< FLASH End of Operation flag
+ FLASH_FLAG_PGERR = FLASH_SR_PGERR, ///< FLASH Program error flag
+ FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR, ///< FLASH Write protected error flag
+ FLASH_FLAG_BSY = FLASH_SR_BUSY, ///< FLASH Busy flag
+ FLASH_FLAG_OPTERR = FLASH_OBR_OPTERR ///< FLASH Option Byte error flag
+} FLASH_FLAG_TypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Constants
+/// @{
+
+
+#define RDP_Key ((u16)0x00A5)
+#define FLASH_KEY1 ((u32)0x45670123)
+#define FLASH_KEY2 ((u32)0xCDEF89AB)
+#define EraseTimeout ((u32)0x00000FFF)
+#define ProgramTimeout ((u32)0x0000000F)
+
+#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) ///< Write protection of page 0 to 3
+#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) ///< Write protection of page 4 to 7
+#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) ///< Write protection of page 8 to 11
+#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) ///< Write protection of page 12 to 15
+#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) ///< Write protection of page 16 to 19
+#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) ///< Write protection of page 20 to 23
+#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) ///< Write protection of page 24 to 27
+#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) ///< Write protection of page 28 to 31
+#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) ///< Write protection of page 32 to 35
+#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) ///< Write protection of page 36 to 39
+#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) ///< Write protection of page 40 to 43
+#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) ///< Write protection of page 44 to 47
+#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) ///< Write protection of page 48 to 51
+#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) ///< Write protection of page 52 to 55
+#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) ///< Write protection of page 56 to 59
+#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) ///< Write protection of page 60 to 63
+#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) ///< Write protection of page 64 to 67
+#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) ///< Write protection of page 68 to 71
+#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) ///< Write protection of page 72 to 75
+#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) ///< Write protection of page 76 to 79
+#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) ///< Write protection of page 80 to 83
+#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) ///< Write protection of page 84 to 87
+#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) ///< Write protection of page 88 to 91
+#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) ///< Write protection of page 92 to 95
+#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) ///< Write protection of page 96 to 99
+#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) ///< Write protection of page 100 to 103
+#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) ///< Write protection of page 104 to 107
+#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) ///< Write protection of page 108 to 111
+#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) ///< Write protection of page 112 to 115
+#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) ///< Write protection of page 115 to 119
+#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) ///< Write protection of page 120 to 123
+#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) ///< Write protection of page 124 to 127
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Variables
+/// @{
+
+#ifdef _HAL_FLASH_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Functions
+/// @{
+void FLASH_SetLatency(FLASH_Latency_TypeDef latency);
+void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access);
+void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+void FLASH_OPTB_Enable(void);
+void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state);
+void FLASH_ClearFlag(u16 flag);
+void exFLASH_EraseEE(u32 page_address);
+void exFLASH_ProgramEE(u16* buf, u32 address, u16 len);
+void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len);
+void* exFLASH_Locate(u32 page_address, u16 len);
+void* exFLASH_ReadEE(u32 page_address, u16 len);
+
+u8 exFLASH_FindEmpty(u16* ptr, u16 len);
+u32 FLASH_GetUserOptionByte(void);
+u32 FLASH_GetWriteProtectionOptionByte(void);
+
+FLASH_Status FLASH_ErasePage(u32 page_address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_EraseProtect(void);
+FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data);
+FLASH_Status FLASH_ProgramWord(u32 address, u32 data);
+FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data);
+FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data);
+FLASH_Status FLASH_ProgramProtect(u32 address, u16 data);
+FLASH_Status FLASH_EnableWriteProtection(u32 page);
+FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(u32 time_out);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState state);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+FlagStatus FLASH_GetFlagStatus(u16 flag);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_FLASH_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
new file mode 100644
index 00000000..dbfe3816
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_fsmc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_FSMC_H
+#define __HAL_FSMC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_fsmc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FSMC_HAL
+/// @brief FSMC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FSMC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_interrupts_define
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+// Timing parameter configuration register set selection register set0 register set1 register set2
+
+#define FSMC_TimingRegSelect_0 ((u32)0x00000000)
+#define FSMC_TimingRegSelect_1 ((u32)0x00000100)
+#define FSMC_TimingRegSelect_2 ((u32)0x00000200)
+
+// Capacity of external device
+#define FSMC_MemSize_None ((u32)0x00000000)
+#define FSMC_MemSize_64KB ((u32)0x00000001)
+#define FSMC_MemSize_128KB ((u32)0x00000002)
+#define FSMC_MemSize_256KB ((u32)0x00000002)
+#define FSMC_MemSize_512KB ((u32)0x00000004)
+#define FSMC_MemSize_1MB ((u32)0x00000005)
+#define FSMC_MemSize_2MB ((u32)0x00000006)
+#define FSMC_MemSize_4MB ((u32)0x00000007)
+#define FSMC_MemSize_8MB ((u32)0x00000008)
+#define FSMC_MemSize_16MB ((u32)0x00000009)
+#define FSMC_MemSize_32MB ((u32)0x0000000A)
+#define FSMC_MemSize_64MB ((u32)0x0000000B)
+#define FSMC_MemSize_128MB ((u32)0x0000000C)
+#define FSMC_MemSize_256MB ((u32)0x0000000D)
+#define FSMC_MemSize_512MB ((u32)0x0000000E)
+#define FSMC_MemSize_1GB ((u32)0x0000000F)
+#define FSMC_MemSize_2GB ((u32)0x00000010)
+#define FSMC_MemSize_4GB ((u32)0x00000011)
+
+
+// Memory data bus bit width setting
+typedef enum {
+ FSMC_DataWidth_16bits = (0x0000), //16bits
+ FSMC_DataWidth_32bits = (0x0001), //32bits
+ FSMC_DataWidth_64bits = (0x0002), //64bits
+ FSMC_DataWidth_128bits = (0x0003), //128bits
+ FSMC_DataWidth_8bits = (0x0004), //8bits
+} FSMC_NORSRAM_DataWidth_TypeDef;
+
+typedef enum {
+ FSMC_NORSRAM_BANK0 = 0,
+ FSMC_NORSRAM_BANK1 = 1,
+ FSMC_NORSRAM_BANK2 = 2,
+} FSMC_NORSRAM_BANK_TypeDef;
+
+typedef struct {
+ u32 FSMC_SMReadPipe; //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high
+
+ u32 FSMC_ReadyMode; //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations.
+ //0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT)
+ u32 FSMC_WritePeriod; //Write cycle
+
+ u32 FSMC_WriteHoldTime; //Address/data hold time during write operation
+
+ u32 FSMC_AddrSetTime; //Address establishment time
+
+ u32 FSMC_ReadPeriod; //Read cycle
+
+ FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth;
+
+} FSMC_NORSRAM_Bank_InitTypeDef;
+
+typedef struct {
+ u32 FSMC_Mode;
+ u32 FSMC_TimingRegSelect;
+ u32 FSMC_MemSize;
+ u32 FSMC_MemType;
+ u32 FSMC_AddrDataMode;
+} FSMC_InitTypeDef;
+
+
+#define FSMC_MemType_SDRAM ((u32)0x0<<5)
+#define FSMC_MemType_NorSRAM ((u32)0x1<<5)
+#define FSMC_MemType_FLASH ((u32)0x2<<5)
+#define FSMC_MemType_RESERVED ((u32)0x3<<5)
+//SYSCFG_CFGR1
+#define FSMC_Mode_6800 ((u32)0x40000000)
+#define FSMC_Mode_8080 ((u32)0x20000000)
+#define FSMC_Mode_NorFlash ((u32)0x00000000)
+
+#define FSMC_AddrDataMUX ((u32)0x00000000)
+#define FSMC_AddrDataDeMUX ((u32)0x10000000)
+
+
+
+
+void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct);
+void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct);
+void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct);
+void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank);
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_FSMC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
new file mode 100644
index 00000000..b28afd83
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
@@ -0,0 +1,198 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_gpio.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_GPIO_H
+#define __HAL_GPIO_H
+
+// Files includes
+#include "types.h"
+#include "reg_gpio.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_HAL
+/// @brief GPIO HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Output Maximum frequency selection
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ GPIO_Speed_50MHz = 1, ///< Maximum speed is 50MHz
+ GPIO_Speed_20MHz, ///< Maximum speed is 20MHz
+ GPIO_Speed_10MHz ///< Maximum speed is 10MHz
+} GPIOSpeed_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configuration Mode enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ GPIO_Mode_AIN = 0x00, ///< Analog input
+ GPIO_Mode_FLOATING = 0x04, ///< Floating input
+ GPIO_Mode_IPD = 0x28, ///< Pull down input
+ GPIO_Mode_IPU = 0x48, ///< Pull up input
+ GPIO_Mode_Out_OD = 0x14, ///< Universal open drain output
+ GPIO_Mode_Out_PP = 0x10, ///< Universal push-pull output
+ GPIO_Mode_AF_OD = 0x1C, ///< Multiplex open drain output
+ GPIO_Mode_AF_PP = 0x18 ///< Multiplexed push-pull output
+} GPIOMode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Bit_SET and Bit_RESET enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ Bit_RESET = 0, ///< bit reset
+ Bit_SET ///< bit set
+} BitAction;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u16 GPIO_Pin; ///< GPIO_Pin
+ GPIOSpeed_TypeDef GPIO_Speed; ///< GPIO_Speed
+ GPIOMode_TypeDef GPIO_Mode; ///< GPIO_Mode
+} GPIO_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Constants
+/// @{
+
+#define GPIO_Speed_2MHz GPIO_Speed_20MHz
+
+#define GPIO_Pin_0 (0x0001U) ///< Pin 0 selected
+#define GPIO_Pin_1 (0x0002U) ///< Pin 1 selected
+#define GPIO_Pin_2 (0x0004U) ///< Pin 2 selected
+#define GPIO_Pin_3 (0x0008U) ///< Pin 3 selected
+#define GPIO_Pin_4 (0x0010U) ///< Pin 4 selected
+#define GPIO_Pin_5 (0x0020U) ///< Pin 5 selected
+#define GPIO_Pin_6 (0x0040U) ///< Pin 6 selected
+#define GPIO_Pin_7 (0x0080U) ///< Pin 7 selected
+#define GPIO_Pin_8 (0x0100U) ///< Pin 8 selected
+#define GPIO_Pin_9 (0x0200U) ///< Pin 9 selected
+#define GPIO_Pin_10 (0x0400U) ///< Pin 10 selected
+#define GPIO_Pin_11 (0x0800U) ///< Pin 11 selected
+#define GPIO_Pin_12 (0x1000U) ///< Pin 12 selected
+#define GPIO_Pin_13 (0x2000U) ///< Pin 13 selected
+#define GPIO_Pin_14 (0x4000U) ///< Pin 14 selected
+#define GPIO_Pin_15 (0x8000U) ///< Pin 15 selected
+#define GPIO_Pin_All (0xFFFFU) ///< All pins selected
+
+
+#define GPIO_AF_0 (0x00U) ///< Alternative function 0
+#define GPIO_AF_1 (0x01U) ///< Alternative function 1
+#define GPIO_AF_2 (0x02U) ///< Alternative function 2
+#define GPIO_AF_3 (0x03U) ///< Alternative function 3
+#define GPIO_AF_4 (0x04U) ///< Alternative function 4
+#define GPIO_AF_5 (0x05U) ///< Alternative function 5
+#define GPIO_AF_6 (0x06U) ///< Alternative function 6
+#define GPIO_AF_7 (0x07U) ///< Alternative function 7
+#define GPIO_AF_8 (0x08U) ///< Alternative function 8
+#define GPIO_AF_9 (0x09U) ///< Alternative function 9
+#define GPIO_AF_10 (0x0AU) ///< Alternative function 10
+#define GPIO_AF_11 (0x0BU) ///< Alternative function 11
+#define GPIO_AF_12 (0x0CU) ///< Alternative function 12
+#define GPIO_AF_13 (0x0DU) ///< Alternative function 13
+#define GPIO_AF_14 (0x0EU) ///< Alternative function 14
+#define GPIO_AF_15 (0x0FU) ///< Alternative function 15
+#define GPIO_PortSourceGPIOA (0x00U)
+#define GPIO_PortSourceGPIOB (0x01U)
+#define GPIO_PortSourceGPIOC (0x02U)
+#define GPIO_PortSourceGPIOD (0x03U)
+
+#define GPIO_PinSource0 (0x00U)
+#define GPIO_PinSource1 (0x01U)
+#define GPIO_PinSource2 (0x02U)
+#define GPIO_PinSource3 (0x03U)
+#define GPIO_PinSource4 (0x04U)
+#define GPIO_PinSource5 (0x05U)
+#define GPIO_PinSource6 (0x06U)
+#define GPIO_PinSource7 (0x07U)
+#define GPIO_PinSource8 (0x08U)
+#define GPIO_PinSource9 (0x09U)
+#define GPIO_PinSource10 (0x0AU)
+#define GPIO_PinSource11 (0x0BU)
+#define GPIO_PinSource12 (0x0CU)
+#define GPIO_PinSource13 (0x0DU)
+#define GPIO_PinSource14 (0x0EU)
+#define GPIO_PinSource15 (0x0FU)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Variables
+/// @{
+
+#ifdef _HAL_GPIO_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Functions
+/// @{
+void GPIO_DeInit(GPIO_TypeDef* gpio);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct);
+void GPIO_StructInit(GPIO_InitTypeDef* init_struct);
+void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin);
+void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin);
+void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value);
+void GPIO_Write(GPIO_TypeDef* gpio, u16 value);
+void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state);
+void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin);
+bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin);
+bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin);
+
+u16 GPIO_ReadInputData(GPIO_TypeDef* gpio);
+u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio);
+
+
+void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function);
+
+void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_GPIO_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
new file mode 100644
index 00000000..42a9ab55
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
@@ -0,0 +1,255 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_i2c.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_I2C_H
+#define __HAL_I2C_H
+
+// Files includes
+#include "types.h"
+#include "reg_i2c.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_HAL
+/// @brief I2C HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DRV_Exported_Constants
+/// @{
+
+#define I2C_OWN_ADDRESS 0x20
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ union {
+ u16 Mode; ///< Specifies the I2C mode. This parameter can be a value of I2C_mode.
+ u16 I2C_Mode;
+ };
+ union {
+ u16 Speed; ///< Specifies the I2C speed. This parameter can be a value of I2C_speed.
+ u16 I2C_Speed;
+ };
+ union {
+ u16 OwnAddress; ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.
+ u16 I2C_OwnAddress;
+ };
+
+ union {
+ u32 ClockSpeed; ///< Specifies the clock speed.
+ u32 I2C_ClockSpeed;
+ };
+} I2C_InitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C DMA Direction
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RDMAE_SET = 1, // 1 - DMA read
+ TDMAE_SET // 2 - DMA transmit
+} I2C_DMA_Dir_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Transfer Direction
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ I2C_Direction_Transmitter, // I2C Transmitter
+ I2C_Direction_Receiver // I2C Receiver
+} I2C_Trans_Dir_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Acknowledged Address
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ I2C_AcknowledgedAddress_7bit = 0x4000, // 7-bit address
+ I2C_AcknowledgedAddress_10bit = 0xC000 // 10-bit address
+} I2C_ACKaddr_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Private_Defines
+/// @{
+#define INTR_MASK ((u16)0xC000)
+#define FLAG_Mask ((u32)0x00793FFF)
+#define IC_TAR_ENDUAL_Set ((u16)0x1000)
+#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_modes
+/// @{
+#define TX_EMPTY_CTRL I2C_CR_EMPINT
+#define IC_SLAVE_DISABLE I2C_CR_SLAVEDIS
+#define IC_RESTART_EN I2C_CR_REPEN
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_interrupts_definition
+/// @{
+#define I2C_IT_RX_UNDER ((u16)0x0001)
+#define I2C_IT_RX_OVER ((u16)0x0002)
+#define I2C_IT_RX_FULL ((u16)0x0004)
+#define I2C_IT_TX_OVER ((u16)0x0008)
+#define I2C_IT_TX_EMPTY ((u16)0x0010)
+#define I2C_IT_RD_REQ ((u16)0x0020)
+#define I2C_IT_TX_ABRT ((u16)0x0040)
+#define I2C_IT_RX_DONE ((u16)0x0080)
+#define I2C_IT_ACTIVITY ((u16)0x0100)
+#define I2C_IT_STOP_DET ((u16)0x0200)
+#define I2C_IT_START_DET ((u16)0x0400)
+#define I2C_IT_GEN_CALL ((u16)0x0800)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_flags_definition
+/// @{
+#define I2C_FLAG_RX_UNDER ((u16)0x0001)
+#define I2C_FLAG_RX_OVER ((u16)0x0002)
+#define I2C_FLAG_RX_FULL ((u16)0x0004)
+#define I2C_FLAG_TX_OVER ((u16)0x0008)
+#define I2C_FLAG_TX_EMPTY ((u16)0x0010)
+#define I2C_FLAG_RD_REQ ((u16)0x0020)
+#define I2C_FLAG_TX_ABRT ((u16)0x0040)
+#define I2C_FLAG_RX_DONE ((u16)0x0080)
+#define I2C_FLAG_ACTIVITY ((u16)0x0100)
+#define I2C_FLAG_STOP_DET ((u16)0x0200)
+#define I2C_FLAG_START_DET ((u16)0x0400)
+#define I2C_FLAG_GEN_CALL ((u16)0x0800)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Events
+/// @{
+#define I2C_EVENT_RX_UNDER ((u16)0x0001)
+#define I2C_EVENT_RX_OVER ((u16)0x0002)
+#define I2C_EVENT_RX_FULL ((u16)0x0004)
+#define I2C_EVENT_TX_OVER ((u16)0x0008)
+#define I2C_EVENT_TX_EMPTY ((u16)0x0010)
+#define I2C_EVENT_RD_REQ ((u16)0x0020)
+#define I2C_EVENT_TX_ABRT ((u16)0x0040)
+#define I2C_EVENT_RX_DONE ((u16)0x0080)
+#define I2C_EVENT_ACTIVITY ((u16)0x0100)
+#define I2C_EVENT_STOP_DET ((u16)0x0200)
+#define I2C_EVENT_START_DET ((u16)0x0400)
+#define I2C_EVENT_GEN_CALL ((u16)0x0800)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Statusflags_definition
+/// @{
+#define I2C_STATUS_FLAG_ACTIVITY ((u16)0x8001)
+#define I2C_STATUS_FLAG_TFNF ((u16)0x8002)
+#define I2C_STATUS_FLAG_TFE ((u16)0x8004)
+#define I2C_STATUS_FLAG_RFNE ((u16)0x8008)
+#define I2C_STATUS_FLAG_RFF ((u16)0x8010)
+#define I2C_STATUS_FLAG_M_ACTIVITY ((u16)0x8020)
+#define I2C_STATUS_FLAG_S_ACTIVITY ((u16)0x8040)
+/// @}
+
+
+
+#define IC_SLAVE_ENABLE (0x0000<<6)
+#define IC_7BITADDR_MASTER (0x0000<<4)
+#define IC_7BITADDR_SLAVE (0x0000<<3)
+#define I2C_Speed_STANDARD ((u16)0x0002)
+#define I2C_Speed_FAST ((u16)0x0004)
+#define I2C_Mode_MASTER ((u16)0x0001)
+#define I2C_Mode_SLAVE ((u16)0x0000)
+#define CMD_READ ((u16)0x0100)
+#define CMD_WRITE ((u16)0x0000)
+#define I2C_Mode_I2C ((u16)0x0000)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Variables
+/// @{
+#ifdef _HAL_I2C_C_
+
+#define GLOBAL
+
+static u8 I2C_CMD_DIR = 0;
+u16 I2C_DMA_DIR = 0;
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Functions
+/// @{
+void I2C_DeInit(I2C_TypeDef* i2c);
+void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct);
+void I2C_StructInit(I2C_InitTypeDef* init_struct);
+void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr);
+void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state);
+void I2C_SendData(I2C_TypeDef* i2c, u8 dat);
+void I2C_ReadCmd(I2C_TypeDef* i2c);
+void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir);
+void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag);
+void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it);
+
+u8 I2C_ReceiveData(I2C_TypeDef* i2c);
+u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg);
+u32 I2C_GetLastEvent(I2C_TypeDef* i2c);
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag);
+ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it);
+
+////////////////////////////////////////////////////////////////////////////////
+// Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr);
+void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_I2C_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
new file mode 100644
index 00000000..e0b86d7b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
@@ -0,0 +1,130 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_iwdg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_IWDG_H
+#define __HAL_IWDG_H
+
+// Files includes
+#include "types.h"
+#include "reg_iwdg.h"
+#include "reg_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_HAL
+/// @brief IWDG HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG prescaler
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ IWDG_Prescaler_4 = IWDG_PR_PRE_DIV4,
+ IWDG_Prescaler_8 = IWDG_PR_PRE_DIV8,
+ IWDG_Prescaler_16 = IWDG_PR_PRE_DIV16,
+ IWDG_Prescaler_32 = IWDG_PR_PRE_DIV32,
+ IWDG_Prescaler_64 = IWDG_PR_PRE_DIV64,
+ IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128,
+ IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256
+} IWDGPrescaler_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG flag
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ IWDG_FLAG_PVU = 0x0001, // IWDG prescaler value update flag
+ IWDG_FLAG_RVU = 0x0002 // IWDG counter reload value update flag
+} IWDGFlag_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Write access to IWDG_PR and IWDG_RLR registers
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ IWDG_WriteAccess_Enable = 0x5555, // Enable write
+ IWDG_WriteAccess_Disable = 0x0000 // Disable write
+} IWDGWriteAccess_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Key Reload
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ KR_KEY_Reload = 0xAAAA, // Reload value
+ KR_KEY_Enable = 0xCCCC // Start IWDG
+} IWDGKey_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Overflow Configration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ IWDG_Overflow_Reset = 0, //
+ IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL //
+} IWDGOverflowConfig_TypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_Exported_Variables
+/// @{
+#ifdef _HAL_IWDG_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_Exported_Functions
+/// @{
+FlagStatus IWDG_GetFlagStatus(u16 flag);
+
+void IWDG_WriteAccessCmd(u16 write_access);
+void IWDG_SetPrescaler(u8 prescaler);
+void IWDG_SetReload(u16 reload);
+u32 IWDG_GetReload(void);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+void PVU_CheckStatus(void);
+void RVU_CheckStatus(void);
+
+void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config);
+void IWDG_ClearITPendingBit(void);
+void IWDG_EnableIT(void);
+void IWDG_Reset(void);
+void IWDG_ClearIT(void);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_IWDG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
new file mode 100644
index 00000000..0b742996
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
@@ -0,0 +1,128 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_misc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_MISC_H
+#define __HAL_MISC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_HAL
+/// @brief NVIC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 NVIC_IRQChannel;
+ u8 NVIC_IRQChannelPreemptionPriority;
+ u8 NVIC_IRQChannelSubPriority;
+ FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC New Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 NVIC_IRQChannel;
+ u8 NVIC_IRQChannelPreemptionPriority; // Cortex-M0 not used
+ u8 NVIC_IRQChannelSubPriority;
+ FunctionalState NVIC_IRQChannelCmd;
+} exNVIC_Init_TypeDef;
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Constants
+/// @{
+
+#define NVIC_VectTab_RAM (0x20000000U)
+#define NVIC_VectTab_FLASH (0x08000000U)
+
+#define NVIC_LP_SEVONPEND (0x10U)
+#define NVIC_LP_SLEEPDEEP (0x04U)
+#define NVIC_LP_SLEEPONEXIT (0x02U)
+
+#define NVIC_PriorityGroup_0 (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority
+#define NVIC_PriorityGroup_1 (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority
+#define NVIC_PriorityGroup_2 (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority
+#define NVIC_PriorityGroup_3 (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority
+#define NVIC_PriorityGroup_4 (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority
+
+#define AIRCR_VECTKEY_MASK (0x05FA0000U)
+
+#define SysTick_CLKSource_HCLK_Div8 (0xFFFFFFFBU)
+
+
+#define SysTick_CLKSource_EXTCLK (0xFFFFFFFBU)
+#define SysTick_CLKSource_HCLK (0x00000004U)
+/// @}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Variables
+/// @{
+
+#ifdef _HAL_NVIC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Functions
+/// @{
+
+void NVIC_PriorityGroupConfig(u32 priority_group);
+void NVIC_SetVectorTable(u32 vect_tab, u32 offset);
+
+void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state);
+void NVIC_Init(NVIC_InitTypeDef* init_struct);
+
+void SysTick_CLKSourceConfig(u32 systick_clk_source);
+
+void exNVIC_Init(exNVIC_Init_TypeDef* init_struct);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_NVIC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
new file mode 100644
index 00000000..f7837ca8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
@@ -0,0 +1,156 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_pwr.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_PWR_H
+#define __HAL_PWR_H
+
+// Files includes
+#include "types.h"
+#include "reg_pwr.h"
+#include "reg_syscfg.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_HAL
+/// @brief PWR HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_Exported_Types
+/// @{
+
+typedef enum {
+ emWUP_Pin1 = 0,
+ emWUP_Pin2 = 1,
+ emWUP_Pin3,
+ emWUP_Pin4,
+ emWUP_Pin5,
+ emWUP_Pin6,
+} emWUP_Pin_Typedef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PVD_detection_level
+
+typedef enum {
+ emPVD_LEVEL0 = SYSCFG_PDETCSR_PLS_1V7,
+ emPVD_LEVEL1 = SYSCFG_PDETCSR_PLS_2V0,
+ emPVD_LEVEL2 = SYSCFG_PDETCSR_PLS_2V3,
+ emPVD_LEVEL3 = SYSCFG_PDETCSR_PLS_2V6,
+ emPVD_LEVEL4 = SYSCFG_PDETCSR_PLS_2V9,
+ emPVD_LEVEL5 = SYSCFG_PDETCSR_PLS_3V2,
+ emPVD_LEVEL6 = SYSCFG_PDETCSR_PLS_3V5,
+ emPVD_LEVEL7 = SYSCFG_PDETCSR_PLS_3V8,
+ emPVD_LEVEL8 = SYSCFG_PDETCSR_PLS_4V1,
+ emPVD_LEVEL9 = SYSCFG_PDETCSR_PLS_4V4,
+ emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7
+} emPVD_Level_Typedef;
+#define PWR_PVDLevel_1V7 SYSCFG_PDETCSR_PLS_1V7
+#define PWR_PVDLevel_2V0 SYSCFG_PDETCSR_PLS_2V0
+#define PWR_PVDLevel_2V3 SYSCFG_PDETCSR_PLS_2V3
+#define PWR_PVDLevel_2V6 SYSCFG_PDETCSR_PLS_2V6
+#define PWR_PVDLevel_2V9 SYSCFG_PDETCSR_PLS_2V9
+#define PWR_PVDLevel_3V2 SYSCFG_PDETCSR_PLS_3V2
+#define PWR_PVDLevel_3V5 SYSCFG_PDETCSR_PLS_3V5
+#define PWR_PVDLevel_3V8 SYSCFG_PDETCSR_PLS_3V8
+#define PWR_PVDLevel_4V1 SYSCFG_PDETCSR_PLS_4V1
+#define PWR_PVDLevel_4V4 SYSCFG_PDETCSR_PLS_4V4
+#define PWR_PVDLevel_4V7 SYSCFG_PDETCSR_PLS_4V7
+/// @brief Regulator_state_is_STOP_mode
+typedef enum {
+ PWR_Regulator_ON = 0x00000000,
+ PWR_Regulator_LowPower = 0x00000001
+
+} emPWR_Reg_Stop_mode_Typedef;
+
+/// @brief STOP_mode_entry
+typedef enum {
+ PWR_STOPEntry_WFI = 0x00000001,
+ PWR_STOPEntry_WFE = 0x00000002
+
+} emPWR_STOP_ModeEn_Typedef;
+
+/// @brief Low Power Mode
+typedef enum {
+ LP_STOP_MODE = 0,
+ LP_SLEEP_MODE = 1,
+ LP_STANDBY_MODE = 2
+} emPWR_LP_Mode_Typedef;
+
+/// @brief Wait_for_mode
+typedef enum {
+ LP_WFI,
+ LP_WFE
+} emPWR_Wait_Mode_Typedef;
+//typedef enum {
+// PWR_FLAG_WU = PWR_CSR_WUF,
+// PWR_FLAG_SB = PWR_CSR_SBF,
+
+// PWR_FLAG_PVDO = PWR_CSR_PVDO
+
+
+//} emPWR_PWR_Flag_Typedef;
+
+
+/// @}
+
+///////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_Exported_Variables
+/// @{
+
+#ifdef _HAL_PWR_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_Exported_Functions
+/// @{
+
+void PWR_DeInit(void);
+
+void PWR_BackupAccessCmd(FunctionalState state);
+
+void PWR_PVDCmd(FunctionalState state);
+void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level);
+void PWR_WakeUpPinCmd(FunctionalState state);
+void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry);
+void PWR_EnterSTANDBYMode(void);
+
+
+void PWR_ClearFlag(u32 flag);
+FlagStatus PWR_GetFlagStatus(u32 flag);
+FlagStatus PWR_GetPVDOFlagStatus(u32 flag);
+void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_PWR_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
new file mode 100644
index 00000000..deb916d4
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
@@ -0,0 +1,329 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_rcc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_RCC_H
+#define __HAL_RCC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "mm32_reg.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_HAL
+/// @brief RCC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Constants
+/// @{
+
+
+/// @}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Enumeration
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief HSE configuration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_HSE_OFF = 0, // HSE OFF
+ RCC_HSE_ON = RCC_CR_HSEON, // HSE ON
+ RCC_HSE_Bypass = RCC_CR_HSEBYP // HSE Bypass
+} RCCHSE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Used for flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ CR_REG_INDEX = 1, //
+ BDCR_REG_INDEX = 2, //
+ CSR_REG_INDEX = 3, //
+ RCC_FLAG_MASK = 0x1FU //
+} RCC_RegisterFlag_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Flag
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ // Flags in the CR register
+ RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)), ///< Internal High Speed clock ready flag
+ RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)), ///< External High Speed clock ready flag
+
+ RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)), ///< PLL clock ready flag
+
+ // Flags in the CSR register
+ RCC_FLAG_LSIRDY = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)), ///< Internal Low Speed oscillator Ready
+ RCC_FLAG_PINRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)), ///< PIN reset flag
+ RCC_FLAG_PORRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)), ///< POR/PDR reset flag
+ RCC_FLAG_SFTRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)), ///< Software Reset flag
+ RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watchdog reset flag
+ RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog reset flag
+
+ // Flags in the BDCR register
+ RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) ///< External Low Speed oscillator Ready
+} RCC_FLAG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief System clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_HSI = 0, // Set HSI as systemCLOCK
+ RCC_HSE = 1, // Set HSE as systemCLOCK
+ RCC_PLL = 2, // Set PLL as systemCLOCK
+ RCC_LSI = 3 // Set LSI as systemCLOCK
+} SYSCLK_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PLL entry clock source
+////////////////////////////////////////////////////////////////////////////////
+
+typedef enum {
+ RCC_HSI_Div4 = 0,
+ RCC_HSI_Div = 0,
+ RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC,
+ RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC),
+} RCC_PLLSource_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PLL multiplication factor
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_PLLMul_2 = 0x00000000U,
+ RCC_PLLMul_3 = 0x00040000U,
+ RCC_PLLMul_4 = 0x00080000U,
+ RCC_PLLMul_5 = 0x000C0000U,
+ RCC_PLLMul_6 = 0x00100000U,
+ RCC_PLLMul_7 = 0x00140000U,
+ RCC_PLLMul_8 = 0x00180000U,
+ RCC_PLLMul_9 = 0x001C0000U,
+ RCC_PLLMul_10 = 0x00200000U,
+ RCC_PLLMul_11 = 0x00240000U,
+ RCC_PLLMul_12 = 0x00280000U,
+ RCC_PLLMul_13 = 0x002C0000U,
+ RCC_PLLMul_14 = 0x00300000U,
+ RCC_PLLMul_15 = 0x00340000U,
+ RCC_PLLMul_16 = 0x00380000U
+} RCC_PLLMul_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief AHB clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_SYSCLK_Div1 = RCC_CFGR_HPRE_DIV1,
+ RCC_SYSCLK_Div2 = RCC_CFGR_HPRE_DIV2,
+ RCC_SYSCLK_Div4 = RCC_CFGR_HPRE_DIV4,
+ RCC_SYSCLK_Div8 = RCC_CFGR_HPRE_DIV8,
+ RCC_SYSCLK_Div16 = RCC_CFGR_HPRE_DIV16,
+ RCC_SYSCLK_Div64 = RCC_CFGR_HPRE_DIV64,
+ RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128,
+ RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256,
+ RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512
+} RCC_AHB_CLK_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief APB1 and APB2clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_HCLK_Div1 = RCC_CFGR_PPRE1_DIV1,
+ RCC_HCLK_Div2 = RCC_CFGR_PPRE1_DIV2,
+ RCC_HCLK_Div4 = RCC_CFGR_PPRE1_DIV4,
+ RCC_HCLK_Div8 = RCC_CFGR_PPRE1_DIV8,
+ RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16
+} RCC_APB1_APB2_CLK_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USB Device clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_USBCLKSource_PLLCLK_Div1 = 0,
+ RCC_USBCLKSource_PLLCLK_Div2 = 1,
+ RCC_USBCLKSource_PLLCLK_Div3 = 2,
+ RCC_USBCLKSource_PLLCLK_Div4 = 3
+} RCC_USBCLKSOURCE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_PCLK2_Div2 = (0x00000000),
+ RCC_PCLK2_Div4 = (0x00004000),
+ RCC_PCLK2_Div6 = (0x00008000),
+ RCC_PCLK2_Div8 = (0x0000C000)
+} RCC_ADCCLKSOURCE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief LSE configuration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_LSE_OFF = 0, // LSE OFF
+ RCC_LSE_ON = RCC_BDCR_LSEON, // LSE ON
+ RCC_LSE_Bypass = RCC_BDCR_LSEBYP // LSE Bypass
+} RCC_LSE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_RTCCLKSource_LSE = RCC_BDCR_RTCSEL_LSE,
+ RCC_RTCCLKSource_LSI = RCC_BDCR_RTCSEL_LSI,
+ RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE
+} RCC_RTCCLKSOURCE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clock source to output on MCO pin
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK,
+ RCC_MCO_LSI = RCC_CFGR_MCO_LSI,
+ RCC_MCO_LSE = RCC_CFGR_MCO_LSE,
+ RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK,
+ RCC_MCO_HSI = RCC_CFGR_MCO_HSI,
+ RCC_MCO_HSE = RCC_CFGR_MCO_HSE,
+ RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL
+} RCC_MCO_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Interrupt source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RCC_IT_LSIRDY = RCC_CIR_LSIRDYF,
+ RCC_IT_LSERDY = RCC_CIR_LSERDYF,
+ RCC_IT_HSIRDY = RCC_CIR_HSIRDYF,
+ RCC_IT_HSERDY = RCC_CIR_HSERDYF,
+ RCC_IT_PLLRDY = RCC_CIR_PLLRDYF,
+ RCC_IT_CSS = RCC_CIR_CSSF
+} RCC_IT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC clock frequency type definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u32 SYSCLK_Frequency; ///< returns SYSCLK clock frequency.
+ u32 HCLK_Frequency; ///< returns hclk clock frequency.
+ u32 PCLK1_Frequency; ///< returns PCLK1 clock frequency.
+ u32 PCLK2_Frequency; ///< returns PCLK2 clock frequency.
+ u32 ADCCLK_Frequency; ///< returns ADCCLK clock frequency.
+} RCC_ClocksTypeDef;
+/// @}
+
+/// @}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Variables
+/// @{
+#ifdef _HAL_RCC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Functions
+/// @{
+void RCC_DeInit(void);
+void RCC_HSEConfig(RCCHSE_TypeDef state);
+void RCC_HSICmd(FunctionalState state);
+void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src);
+void RCC_PLLDMDNConfig(u32 plldn, u32 plldm);
+void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul);
+void RCC_PLLCmd(FunctionalState state);
+void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk);
+void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk);
+void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk);
+void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src);
+void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2);
+void RCC_LSICmd(FunctionalState state);
+
+void RCC_RTCCLKCmd(FunctionalState state);
+void RCC_LSEConfig(RCC_LSE_TypeDef state);
+void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src);
+void RCC_BackupResetCmd(FunctionalState state);
+
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk);
+void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state);
+void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state);
+void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state);
+void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state);
+void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state);
+
+void RCC_ClockSecuritySystemCmd(FunctionalState state);
+void RCC_MCOConfig(RCC_MCO_TypeDef mco_src);
+void RCC_ClearFlag(void);
+void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state);
+void RCC_ClearITPendingBit(u8 it);
+
+u8 RCC_GetSYSCLKSource(void);
+u32 RCC_GetSysClockFreq(void);
+u32 RCC_GetHCLKFreq(void);
+
+u32 RCC_GetPCLK1Freq(void);
+u32 RCC_GetPCLK2Freq(void);
+FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag);
+ITStatus RCC_GetITStatus(RCC_IT_TypeDef it);
+
+////////////////////////////////////////////////////////////////////////////////
+// Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para);
+void exRCC_SystickDisable(void);
+void exRCC_SystickEnable(u32 sys_tick_period);
+void exRCC_APB1PeriphReset(u32 apb1_periph);
+void exRCC_APB2PeriphReset(u32 apb2_periph);
+void exRCC_BackupReset(void);
+void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state);
+void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state);
+/// @}
+
+/// @}
+
+/// @}
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_RCC_H
+////////////////////////////////////////////////////////////////////////////////
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
new file mode 100644
index 00000000..da5295c7
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
@@ -0,0 +1,102 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_redefine.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_REDEFINE_H
+#define __HAL_REDEFINE_H
+
+// Files includes
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup REDEFINE_HAL
+/// @brief REDEFINE HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Types
+/// @{
+///
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Constants
+/// @{
+//Lib redefine
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief HAL_lib Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define TIM_TRGOSource_Reset TIM_TRIGSource_Reset
+#define TIM_TRGOSource_Enable TIM_TRIGSource_Enable
+#define TIM_TRGOSource_Update TIM_TRIGSource_Update
+#define TIM_TRGOSource_OC1 TIM_TRIGSource_OC1
+#define TIM_TRGOSource_OC1Ref TIM_TRIGSource_OC1Ref
+#define TIM_TRGOSource_OC2Ref TIM_TRIGSource_OC2Ref
+#define TIM_TRGOSource_OC3Ref TIM_TRIGSource_OC3Ref
+#define TIM_TRGOSource_OC4Ref TIM_TRIGSource_OC4Ref
+///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
+///< The Counter Enable CEN is used as the trigger output (TRIG).
+///< The update event is used as the trigger output (TRIG).
+///< The trigger output sends a positive pulse when the CC1IF flag ///< is to be set, as soon as a capture or compare match occurs (TRIG).
+///< OC1REF signal is used as the trigger output (TRIG).
+///< OC2REF signal is used as the trigger output (TRIG).
+///< OC3REF signal is used as the trigger output (TRIG).
+///< OC4REF signal is used as the trigger output (TRIG).
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Variables
+/// @{
+#ifdef _HAL_REDEFINE_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Functions
+/// @{
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_REDEFINE_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
new file mode 100644
index 00000000..fcf48d56
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
@@ -0,0 +1,114 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_rtc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_RTC_H
+#define __HAL_RTC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_rtc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_HAL
+/// @brief RTC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_interrupts_define
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RTC_IT_OW = RTC_CR_OWIE, ///< Overflow interrupt
+ RTC_IT_ALR = RTC_CR_ALRIE, ///< Alarm interrupt
+ RTC_IT_SEC = RTC_CR_SECIE ///< Second interrupt
+} RTC_IT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_interrupts_flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ RTC_FLAG_RTOFF = RTC_CSR_RTOFF, ///< RTC Operation OFF flag
+ RTC_FLAG_RSF = RTC_CSR_RSF, ///< Registers Synchronized flag
+ RTC_FLAG_OW = RTC_CSR_OWF, ///< Overflow flag
+ RTC_FLAG_ALR = RTC_CSR_ALRF, ///< Alarm flag
+ RTC_FLAG_SEC = RTC_CSR_SECF ///< Second flag
+} RTC_FLAG_TypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Variables
+/// @{
+
+#ifdef _HAL_RTC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+GLOBAL bool accessRTC;
+
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Functions
+/// @{
+void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state);
+void RTC_ClearFlag(RTC_FLAG_TypeDef flag);
+void RTC_ClearITPendingBit(RTC_IT_TypeDef it);
+void RTC_EnterConfigMode(void);
+void RTC_SetCounter(u32 count);
+void RTC_SetPrescaler(u32 prescaler);
+void RTC_SetAlarm(u32 alarm);
+void RTC_ExitConfigMode(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+
+u32 RTC_GetCounter(void);
+u32 RTC_GetDivider(void);
+
+FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag);
+ITStatus RTC_GetITStatus(RTC_IT_TypeDef it);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_RTC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
new file mode 100644
index 00000000..199ccc4c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
@@ -0,0 +1,503 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_gpio.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_SDIO_H
+#define __HAL_SDIO_H
+
+// Files includes
+#include "mm32_reg.h"
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_HAL
+/// @brief GPIO HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Output Maximum frequency selection
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
+#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
+#define SDIO_FLAG_CMDREND ((u32)0x00000040)
+#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
+#define SDIO_FLAG_DATAEND ((u32)0x00000100)
+#define SDIO_FLAG_STBITERR ((u32)0x00000200)
+#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
+#define SDIO_FLAG_CMDACT ((u32)0x00000800)
+#define SDIO_FLAG_TXACT ((u32)0x00001000)
+#define SDIO_FLAG_RXACT ((u32)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
+#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
+#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
+#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
+#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
+
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function.
+#define SD_POLLING_MODE 0 /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
+#define SD_DMA_MODE 1 /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO Various error enumeration definitions
+////////////////////////////////////////////////////////////////////////////////
+
+typedef enum {
+ SD_CMD_CRC_FAIL = 1, ///< Command response received (but CRC check failed)
+ SD_DATA_CRC_FAIL, ///< Data bock sent/received (CRC check Failed)
+ SD_CMD_RSP_TIMEOUT, ///< Command response timeout
+ SD_DATA_TIMEOUT, ///< Data time out
+ SD_TX_UNDERRUN, ///< Transmit FIFO under-run
+ SD_RX_OVERRUN, ///< Receive FIFO over-run
+ SD_START_BIT_ERR, ///< Start bit not detected on all data signals in widE bus mode
+ SD_CMD_OUT_OF_RANGE, ///< CMD's argument was out of range.
+ SD_ADDR_MISALIGNED, ///< Misaligned address
+ SD_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
+ SD_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs.
+ SD_BAD_ERASE_PARAM, ///< An Invalid selection for erase groups
+ SD_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block
+ SD_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
+ SD_COM_CRC_FAILED, ///< CRC check of the previous command failed
+ SD_ILLEGAL_CMD, ///< Command is not legal for the card state
+ SD_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data
+ SD_CC_ERROR, ///< Internal card controller error
+ SD_GENERAL_UNKNOWN_ERROR, ///< General or Unknown error
+ SD_STREAM_READ_UNDERRUN, ///< The card could not sustain data transfer in stream read operation.
+ SD_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode
+ SD_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error
+ SD_WP_ERASE_SKIP, ///< only partial address space was erased
+ SD_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC
+ SD_ERASE_RESET, ///< Erase sequence was cleared before executing because an out of erase sequence command was received
+ SD_AKE_SEQ_ERROR, ///< Error in sequence of authentication.
+ SD_INVALID_VOLTRANGE, ///< SD invalid voltage range,
+ SD_ADDR_OUT_OF_RANGE, ///< SD addresses are out of range,
+ SD_SWITCH_ERROR, ///< SD switch error,
+ SD_SDIO_DISABLED, ///< SD SDIO disability,
+ SD_SDIO_FUNCTION_BUSY, ///< SD SDIO function busy,
+ SD_SDIO_FUNCTION_FAILED, ///< SD SDIO failed,
+ SD_SDIO_UNKNOWN_FUNCTION, ///< SDIO unknown function,
+ SD_INTERNAL_ERROR, ///< SD internal error,
+ SD_NOT_CONFIGURED, ///< SD is not configured,
+ SD_REQUEST_PENDING, ///< The SD request waits,
+ SD_REQUEST_NOT_APPLICABLE, ///< The SD requirement does not apply,
+ SD_INVALID_PARAMETER, ///< Invalid SD parameter,
+ SD_UNSUPPORTED_FEATURE, ///< Features not supported by SD,
+ SD_UNSUPPORTED_HW, ///< HW not supported by SD,
+ SD_ERROR, ///< SD error
+ SD_OK = 0 ///< SD OK
+} SD_Error;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SD card CSD register data
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 CSDStruct; ///< CSD structure
+ u8 SysSpecVersion; ///< System specification version
+ u8 Reserved1; ///< Reserved
+ u8 TAAC; ///< Data read access-time 1
+ u8 NSAC; ///< Data read access-time 2 in CLK cycles
+ u8 MaxBusClkFrec; ///< Max. bus clock frequency
+ u16 CardComdClasses; ///< Card command classes
+ u8 RdBlockLen; ///< Max. read data block length
+ u8 PartBlockRead; ///< Partial blocks for read allowed
+ u8 WrBlockMisalign; ///< Write block misalignment
+ u8 RdBlockMisalign; ///< Read block misalignment
+ u8 DSRImpl; ///< DSR implemented
+ u8 Reserved2; ///< Reserved
+ u32 DeviceSize; ///< Device Size
+ u8 MaxRdCurrentVDDMin; ///< Max. read current @ VDD min
+ u8 MaxRdCurrentVDDMax; ///< Max. read current @ VDD max
+ u8 MaxWrCurrentVDDMin; ///< Max. write current @ VDD min
+ u8 MaxWrCurrentVDDMax; ///< Max. write current @ VDD max
+ u8 DeviceSizeMul; ///< Device size multiplier
+ u8 EraseGrSize; ///< Erase group size
+ u8 EraseGrMul; ///< Erase group size multiplier
+ u8 WrProtectGrSize; ///< Write protect group size
+ u8 WrProtectGrEnable; ///< Write protect group enable
+ u8 ManDeflECC; ///< Manufacturer default ECC
+ u8 WrSpeedFact; ///< Write speed factor
+ u8 MaxWrBlockLen; ///< Max. write data block length
+ u8 WriteBlockPaPartial; ///< Partial blocks for write allowed
+ u8 Reserved3; ///< Reserded
+ u8 ContentProtectAppli; ///< Content protection application
+ u8 FileFormatGrouop; ///< File format group
+ u8 CopyFlag; ///< Copy flag (OTP)
+ u8 PermWrProtect; ///< Permanent write protection
+ u8 TempWrProtect; ///< Temporary write protection
+ u8 FileFormat; ///< File Format
+ u8 ECC; ///< ECC code
+ u8 CSD_CRC; ///< CSD CRC
+ u8 Reserved4; ///< always 1
+} SD_CSD;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SD card CID register data
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 ManufacturerID; ///< ManufacturerID
+ u16 OEM_AppliID; ///< OEM/Application ID
+ u32 ProdName1; ///< Product Name part1
+ u8 ProdName2; ///< Product Name part2
+ u8 ProdRev; ///< Product Revision
+ u32 ProdSN; ///< Product Serial Number
+ u8 Reserved1; ///< Reserved1
+ u16 ManufactDate; ///< Manufacturing Date
+ u8 CID_CRC; ///< CID CRC
+ u8 Reserved2; ///< always 1
+} SD_CID;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SD state
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SD_CARD_READY = ((u32)0x00000001),
+ SD_CARD_IDENTIFICATION = ((u32)0x00000002),
+ SD_CARD_STANDBY = ((u32)0x00000003),
+ SD_CARD_TRANSFER = ((u32)0x00000004),
+ SD_CARD_SENDING = ((u32)0x00000005),
+ SD_CARD_RECEIVING = ((u32)0x00000006),
+ SD_CARD_PROGRAMMING = ((u32)0x00000007),
+ SD_CARD_DISCONNECTED = ((u32)0x00000008),
+ SD_CARD_ERROR = ((u32)0x000000FF)
+} SDCardState;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SD message ,include CSD,CID data
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ SD_CSD SD_csd;
+ SD_CID SD_cid;
+ long long CardCapacity;
+ u32 CardBlockSize;
+ u16 RCA;
+ u8 CardType;
+} SD_CardInfo;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO init
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u8 SDIO_MDEN;
+ u8 SDIO_DATWT;
+ u8 SDIO_SelPTSM;
+ u8 SDIO_CLKSP;
+ u8 SDIO_OUTM;
+ u8 SDIO_SelSM;
+ u8 SDIO_OPMSel;
+} SDIO_InitTypeDef;
+
+typedef struct {
+ u32 SDIO_Argument; ///Specifies the SDIO command argument which is sent
+ ///to a card as part of a command message. If a command
+ ///contains an argument, it must be loaded into this register
+ ///before writing the command to the command register
+
+ u32 SDIO_CmdIndex; ///Specifies the SDIO command index. It must be lower than 0x40.
+
+ u32 SDIO_Response; ///Specifies the SDIO response type.
+ ///This parameter can be a value of @ref SDIO_Response_Type
+
+ u32 SDIO_Wait; ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ ///This parameter can be a value of @ref SDIO_Wait_Interrupt_State
+
+/// u32 SDIO_CPSM; ///Specifies whether SDIO Command path state machine (CPSM)
+ ///is enabled or disabled.
+ ///This parameter can be a value of @ref SDIO_CPSM_State
+} SDIO_CmdInitTypeDef;
+typedef struct {
+ u32 SDIO_DataTimeOut; // < Specifies the data timeout period in card bus clock periods.
+ //
+ u32 SDIO_DataLength; // < Specifies the number of data bytes to be transferred.
+ //
+ u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer.
+ // This parameter can be a value of @ref SDIO_Data_Block_Size
+ //
+ u32 SDIO_TransferDir; // < Specifies the data transfer direction, whether the transfer
+ // is a read or write.
+ // This parameter can be a value of @ref SDIO_Transfer_Direction
+ //
+// u32 SDIO_TransferMode; // < Specifies whether data transfer is in stream or block mode.
+// // This parameter can be a value of @ref SDIO_Transfer_Type
+// //
+// u32 SDIO_DPSM; // < Specifies whether SDIO Data path state machine (DPSM)
+// // is enabled or disabled.
+// // This parameter can be a value of @ref SDIO_DPSM_State
+} SDIO_DataInitTypeDef;
+
+
+
+extern SD_CardInfo SDCardInfo;
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SDIO Ö¸instruction set
+/// @{
+#define SD_CMD_GO_IDLE_STATE ((u8)0)
+#define SD_CMD_SEND_OP_COND ((u8)1)
+#define SD_CMD_ALL_SEND_CID ((u8)2)
+#define SD_CMD_SET_REL_ADDR ((u8)3)
+#define SD_CMD_SET_DSR ((u8)4)
+#define SD_CMD_SDIO_SEN_OP_COND ((u8)5)
+#define SD_CMD_HS_SWITCH ((u8)6)
+#define SD_CMD_SEL_DESEL_CARD ((u8)7)
+#define SD_CMD_HS_SEND_EXT_CSD ((u8)8)
+#define SD_CMD_SEND_CSD ((u8)9)
+#define SD_CMD_SEND_CID ((u8)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP ((u8)11)
+#define SD_CMD_STOP_TRANSMISSION ((u8)12)
+#define SD_CMD_SEND_STATUS ((u8)13)
+#define SD_CMD_HS_BUSTEST_READ ((u8)14)
+#define SD_CMD_GO_INACTIVE_STATE ((u8)15)
+#define SD_CMD_SET_BLOCKLEN ((u8)16)
+#define SD_CMD_READ_SINGLE_BLOCK ((u8)17)
+#define SD_CMD_READ_MULT_BLOCK ((u8)18)
+#define SD_CMD_HS_BUSTEST_WRITE ((u8)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((u8)20)
+#define SD_CMD_SET_BLOCK_COUNT ((u8)23)
+#define SD_CMD_WRITE_SINGLE_BLOCK ((u8)24)
+#define SD_CMD_WRITE_MULT_BLOCK ((u8)25)
+#define SD_CMD_PROG_CID ((u8)26)
+#define SD_CMD_PROG_CSD ((u8)27)
+#define SD_CMD_SET_WRITE_PROT ((u8)28)
+#define SD_CMD_CLR_WRITE_PROT ((u8)29)
+#define SD_CMD_SEND_WRITE_PROT ((u8)30)
+#define SD_CMD_SD_ERASE_GRP_START ((u8)32)
+#define SD_CMD_SD_ERASE_GRP_END ((u8)33)
+#define SD_CMD_ERASE_GRP_START ((u8)35)
+#define SD_CMD_ERASE_GRP_END ((u8)36)
+#define SD_CMD_ERASE ((u8)38)
+#define SD_CMD_FAST_IO ((u8)39)
+#define SD_CMD_GO_IRQ_STATE ((u8)40)
+#define SD_CMD_LOCK_UNLOCK ((u8)42)
+#define SD_CMD_APP_CMD ((u8)55)
+#define SD_CMD_GEN_CMD ((u8)56)
+#define SD_CMD_NO_CMD ((u8)64)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup Following commands are SD Card Specific commands.
+/// @{
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((u8)6)
+#define SD_CMD_SD_APP_STAUS ((u8)13)
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((u8)22)
+#define SD_CMD_SD_APP_OP_COND ((u8)41)
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((u8)42)
+#define SD_CMD_SD_APP_SEND_SCR ((u8)51)
+#define SD_CMD_SDIO_RW_DIRECT ((u8)52)
+#define SD_CMD_SDIO_RW_EXTENDED ((u8)53)
+
+#define SD_CMD_SD_APP_GET_MKB ((u8)43)
+#define SD_CMD_SD_APP_GET_MID ((u8)44)
+#define SD_CMD_SD_APP_SET_CER_RN1 ((u8)45)
+#define SD_CMD_SD_APP_GET_CER_RN2 ((u8)46)
+#define SD_CMD_SD_APP_SET_CER_RES2 ((u8)47)
+#define SD_CMD_SD_APP_GET_CER_RES1 ((u8)48)
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((u8)18)
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((u8)25)
+#define SD_CMD_SD_APP_SECURE_ERASE ((u8)38)
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((u8)49)
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((u8)48)
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SD support define.
+/// @{
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((u32)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((u32)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD ((u32)0x00000002)
+#define SDIO_MULTIMEDIA_CARD ((u32)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD ((u32)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((u32)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((u32)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD ((u32)0x00000007)
+/// @}
+
+#ifndef NULL
+#define NULL 0
+#endif
+#define SDIO_STATIC_FLAGS ((u32)0x000005FF)
+#define SDIO_CMD0TIMEOUT ((u32)0x00010000)
+#define SDIO_DATATIMEOUT ((u32)0xFFFFFFFF)
+#define SDIO_FIFO_Address ((u32)0x40018080)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup Mask for errors Card Status R1 (OCR Register)
+/// @{
+#define SD_OCR_ADDR_OUT_OF_RANGE ((u32)0x80000000)
+#define SD_OCR_ADDR_MISALIGNED ((u32)0x40000000)
+#define SD_OCR_BLOCK_LEN_ERR ((u32)0x20000000)
+#define SD_OCR_ERASE_SEQ_ERR ((u32)0x10000000)
+#define SD_OCR_BAD_ERASE_PARAM ((u32)0x08000000)
+#define SD_OCR_WRITE_PROT_VIOLATION ((u32)0x04000000)
+#define SD_OCR_LOCK_UNLOCK_FAILED ((u32)0x01000000)
+#define SD_OCR_COM_CRC_FAILED ((u32)0x00800000)
+#define SD_OCR_ILLEGAL_CMD ((u32)0x00400000)
+#define SD_OCR_CARD_ECC_FAILED ((u32)0x00200000)
+#define SD_OCR_CC_ERROR ((u32)0x00100000)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR ((u32)0x00080000)
+#define SD_OCR_STREAM_READ_UNDERRUN ((u32)0x00040000)
+#define SD_OCR_STREAM_WRITE_OVERRUN ((u32)0x00020000)
+#define SD_OCR_CID_CSD_OVERWRIETE ((u32)0x00010000)
+#define SD_OCR_WP_ERASE_SKIP ((u32)0x00008000)
+#define SD_OCR_CARD_ECC_DISABLED ((u32)0x00004000)
+#define SD_OCR_ERASE_RESET ((u32)0x00002000)
+#define SD_OCR_AKE_SEQ_ERROR ((u32)0x00000008)
+#define SD_OCR_ERRORBITS ((u32)0xFDFFE008)
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup Masks for R6 Response
+/// @{
+#define SD_R6_GENERAL_UNKNOWN_ERROR ((u32)0x00002000)
+#define SD_R6_ILLEGAL_CMD ((u32)0x00004000)
+#define SD_R6_COM_CRC_FAILED ((u32)0x00008000)
+/// @}
+#define SD_VOLTAGE_WINDOW_SD ((u32)0x80100000)
+#define SD_HIGH_CAPACITY ((u32)0x40000000)
+#define SD_STD_CAPACITY ((u32)0x00000000)
+#define SD_CHECK_PATTERN ((u32)0x000001AA)
+#define SD_VOLTAGE_WINDOW_MMC ((u32)0x80FF8000)
+
+#define SD_MAX_VOLT_TRIAL ((u32)0x0000FFFF)
+#define SD_ALLZERO ((u32)0x00000000)
+
+#define SD_WIDE_BUS_SUPPORT ((u32)0x00040000)
+#define SD_SINGLE_BUS_SUPPORT ((u32)0x00010000)
+#define SD_CARD_LOCKED ((u32)0x02000000)
+#define SD_CARD_PROGRAMMING ((u32)0x00000007)
+#define SD_CARD_RECEIVING ((u32)0x00000006)
+#define SD_DATATIMEOUT ((u32)0xFFFFFFFF)
+#define SD_0TO7BITS ((u32)0x000000FF)
+#define SD_8TO15BITS ((u32)0x0000FF00)
+#define SD_16TO23BITS ((u32)0x00FF0000)
+#define SD_24TO31BITS ((u32)0xFF000000)
+#define SD_MAX_DATA_LENGTH ((u32)0x01FFFFFF)
+
+#define SD_HALFFIFO ((u32)0x00000008)
+#define SD_HALFFIFOBYTES ((u32)0x00000020)
+
+#define SD_CCCC_LOCK_UNLOCK ((u32)0x00000080)
+#define SD_CCCC_WRITE_PROT ((u32)0x00000040)
+#define SD_CCCC_ERASE ((u32)0x00000020)
+
+
+#define SDIO_SEND_IF_COND ((u32)0x00000008)
+
+#define SDIO_Response_No ((u32)0x00)
+#define SDIO_Response_Short ((u32)0x01)
+#define SDIO_Response_Long ((u32)0x03)
+
+#define SDIO_DataBlockSize_1b ((u32)0x00000000)
+#define SDIO_DataBlockSize_2b ((u32)0x00000001)
+#define SDIO_DataBlockSize_4b ((u32)0x00000002)
+#define SDIO_DataBlockSize_8b ((u32)0x00000003)
+#define SDIO_DataBlockSize_16b ((u32)0x00000004)
+#define SDIO_DataBlockSize_32b ((u32)0x00000005)
+#define SDIO_DataBlockSize_64b ((u32)0x00000006)
+#define SDIO_DataBlockSize_128b ((u32)0x00000007)
+#define SDIO_DataBlockSize_256b ((u32)0x00000008)
+#define SDIO_DataBlockSize_512b ((u32)0x00000009)
+#define SDIO_DataBlockSize_1024b ((u32)0x0000000A)
+#define SDIO_DataBlockSize_2048b ((u32)0x0000000B)
+#define SDIO_DataBlockSize_4096b ((u32)0x0000000C)
+#define SDIO_DataBlockSize_8192b ((u32)0x0000000D)
+#define SDIO_DataBlockSize_16384b ((u32)0x0000000E)
+//Define the data block length when the block data transfer mode is selected:
+//0000: (0 decimal) lock length = 2^0 = 1 byte
+//0001: (1 decimal) lock length = 2^1 = 2 bytes
+//0010: (2 decimal) lock length = 2^2 = 4 bytes
+//0011: (3 decimal) lock length = 2^3 = 8 bytes
+//0100: (4 decimal) lock length = 2^4 = 16 bytes
+//0101: (5 decimal) lock length = 2^5 = 32 bytes
+//0110: (6 decimal) lock length = 2^6 = 64 bytes
+//0111: (7 decimal) lock length = 2^7 = 128 bytes
+//1000: (8 decimal) lock length = 2^8 = 256 bytes
+//1001: (9 decimal) lock length = 2^9 = 512 bytes
+//1010: (10 decimal) lock length = 2^10 = 1024 bytes
+//1011: (11 decimal) lock length = 2^11 = 2048 bytes
+//1100: (12 decimal) lock length = 2^12 = 4096 bytes
+//1101: (13 decimal) lock length = 2^13 = 8192 bytes
+//1110: (14 decimal) lock length = 2^14 = 16384 bytes
+//1111: (15 decimal) reserved
+
+
+#define SDIO_TransferDir_ToCard ((u32)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
+
+#define SDIO_Wait_No ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled
+#define SDIO_Wait_IT ((u32)0x00000100) //SDIO Wait Interrupt Request
+#define SDIO_Wait_Pend ((u32)0x00000200) // SDIO Wait End of transfer
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Functions
+/// @{
+void SDIO_DeInit(void);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockSet(u32 value);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state);
+void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state);
+void SDIO_Clock_Set(u8 clkdiv);
+void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg);
+SD_Error SD_PowerOFF(void);
+SD_Error CmdError(void);
+SD_Error CmdResp2Error(void);
+SD_Error CmdResp3Error(void);
+SD_Error CmdResp6Error(u8 cmd, u16* prca);
+SD_Error CmdResp7Error(void);
+SD_Error CmdResp1Error(u8 cmd);
+void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir);
+void SDIO_ClearITPendingBit(u32 SDIO_IT);
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
+u32 SDIO_GetTimeOutCounter(void);
+u32 SDIO_ReadData(void);
+void SDIO_WriteData(u32 tempbuff);
+void SDIO_DMACmd(FunctionalState state);
+/// @}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
new file mode 100644
index 00000000..db1a9aa3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
@@ -0,0 +1,351 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_spi.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_SPI_H
+#define __HAL_SPI_H
+
+// Files includes
+#include "types.h"
+#include "reg_spi.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_HAL
+/// @brief SPI HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI mode enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_Mode_Slave = 0x0000, ///< SPI slave mode
+ SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode
+} SPI_Mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI data size enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_DataSize_8b = 0x0000, ///< 8 bits valid data
+ SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data
+} SPI_DataSize_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI clock polarity enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state.
+ SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
+} SPI_CPOL_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI clock phase enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge.
+ SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge.
+} SPI_CPHA_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI nss control mode enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_NSS_Soft = 0x0000,
+ SPI_NSS_Hard = SPI_GCR_NSS
+} SPI_NSS_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI baud rate prescaler enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2
+ SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4
+ SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7
+ SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16
+ SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32
+ SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64
+ SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128
+ SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256
+} SPI_BaudRatePrescaler_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI first bit enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB
+ SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB
+} SPI_FirstBit_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI FIFO trigger level enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level
+ SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level
+} SPI_TLF_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI bit derection enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_Direction_Rx, ///< Receive enable
+ SPI_Direction_Tx, ///< Transmit enable
+ SPI_Disable_Rx, ///< Receive disable
+ SPI_Disable_Tx ///< Transmit disable
+} SPI_Direction_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI flag enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag
+ SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag
+ SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag
+ SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag
+} SPI_FLAG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI slave mode data edge adjust enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode
+ SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode
+} SPI_SlaveAdjust_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI data edge adjust enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode
+ SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode
+} SPI_DataEdgeAdjust_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI interruput enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt
+ SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt
+ SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut
+ SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt
+ SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt
+ SPI_IT_RX = 0x02, ///< Receive available data interrupt
+ SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt
+} SPI_IT_TypeDef;
+
+
+typedef enum {
+ I2S_Standard_Phillips = 0x0000,
+ I2S_Standard_MSB = 0x0010,
+ I2S_Standard_LSB = 0x0020,
+ I2S_Standard_PCMShort = 0x0030,
+ I2S_Standard_PCMLong = 0x00B0,
+} SPI_I2S_STANDARD_TypeDef;
+
+
+typedef enum {
+ I2S_DataFormat_16b = 0x0000,
+ I2S_DataFormat_16bextended = 0x0001,
+ I2S_DataFormat_24b = 0x0003,
+ I2S_DataFormat_32b = 0x0005,
+} SPI_I2S_DATAFORMAT_TypeDef;
+typedef enum {
+ I2S_AudioFreq_192k = (192000),
+ I2S_AudioFreq_96k = (96000),
+ I2S_AudioFreq_48k = (48000),
+ I2S_AudioFreq_44k = (44100),
+ I2S_AudioFreq_32k = (32000),
+ I2S_AudioFreq_24k = (24000),
+ I2S_AudioFreq_22k = (22050),
+ I2S_AudioFreq_16k = (16000),
+ I2S_AudioFreq_11k = (11025),
+ I2S_AudioFreq_12k = (12000),
+ I2S_AudioFreq_8k = (8000),
+ I2S_AudioFreq_4k = (4000),
+ I2S_AudioFreq_Default = (2),
+} SPI_I2S_AUDIO_FREQ_TypeDef;
+typedef enum {
+ I2S_Mode_SlaveTx = 0x0000,
+ I2S_Mode_SlaveRx = 0x0100,
+ I2S_Mode_MasterTx = 0x0200,
+ I2S_Mode_MasterRx = 0x0300,
+} SPI_I2S_TRANS_MODE_TypeDef;
+
+typedef enum {
+ I2S_MCLKOutput_Enable = 0x0800,
+ I2S_MCLKOutput_Disable = 0x0000,
+} SPI_I2S_MCLK_OUTPUT_TypeDef;
+
+typedef enum {
+ I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state.
+ I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
+} SPI_I2S_CPOL_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode
+ SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size
+ u8 SPI_DataWidth; ///< SPI data length
+ SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state
+ SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture
+ SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software
+ SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be
+ ///< used to configure the transmit and receive SCK clock
+ SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit
+ // u16 SPI_length;
+} SPI_InitTypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2S Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode.
+ SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication.
+ SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication.
+ SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not.
+ SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication.
+ SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock.
+} I2S_InitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Register_Mask
+/// @{
+
+#define GCR_Mask ((u32)0x0FFF)
+#define CCR_Mask ((u32)0x003F)
+#define BRR_Mask ((u32)0xFFFF)
+#define ECR_Mask ((u32)0x001F)
+
+/// @}
+
+
+// SPI_7bit_8bit data width
+#define SPI_DataWidth_1b ((u16)0x0001)
+#define SPI_DataWidth_2b ((u16)0x0002)
+#define SPI_DataWidth_3b ((u16)0x0003)
+#define SPI_DataWidth_4b ((u16)0x0004)
+#define SPI_DataWidth_5b ((u16)0x0005)
+#define SPI_DataWidth_6b ((u16)0x0006)
+#define SPI_DataWidth_7b ((u16)0x0007)
+#define SPI_DataWidth_8b ((u16)0x0008)
+#define SPI_DataWidth_9b ((u16)0x0009)
+#define SPI_DataWidth_10b ((u16)0x000a)
+#define SPI_DataWidth_11b ((u16)0x000b)
+#define SPI_DataWidth_12b ((u16)0x000c)
+#define SPI_DataWidth_13b ((u16)0x000d)
+#define SPI_DataWidth_14b ((u16)0x000e)
+#define SPI_DataWidth_15b ((u16)0x000f)
+#define SPI_DataWidth_16b ((u16)0x0010)
+#define SPI_DataWidth_17b ((u16)0x0011)
+#define SPI_DataWidth_18b ((u16)0x0012)
+#define SPI_DataWidth_19b ((u16)0x0013)
+#define SPI_DataWidth_20b ((u16)0x0014)
+#define SPI_DataWidth_21b ((u16)0x0015)
+#define SPI_DataWidth_22b ((u16)0x0016)
+#define SPI_DataWidth_23b ((u16)0x0017)
+#define SPI_DataWidth_24b ((u16)0x0018)
+#define SPI_DataWidth_25b ((u16)0x0019)
+#define SPI_DataWidth_26b ((u16)0x001a)
+#define SPI_DataWidth_27b ((u16)0x001b)
+#define SPI_DataWidth_28b ((u16)0x001c)
+#define SPI_DataWidth_29b ((u16)0x001d)
+#define SPI_DataWidth_30b ((u16)0x001e)
+#define SPI_DataWidth_31b ((u16)0x001f)
+#define SPI_DataWidth_32b ((u16)0x0000)
+
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Variables
+/// @{
+
+#ifdef _HAL_SPI_C_
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Functions
+/// @{
+
+void SPI_DeInit(SPI_TypeDef* spi);
+void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct);
+void SPI_StructInit(SPI_InitTypeDef* init_struct);
+void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state);
+void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state);
+void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
+void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state);
+void SPI_SendData(SPI_TypeDef* spi, u32 data);
+void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss);
+
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction);
+void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
+void SPI_RxBytes(SPI_TypeDef* spi, u16 number);
+void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value);
+
+bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size);
+void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize);
+u32 SPI_ReceiveData(SPI_TypeDef* spi);
+
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag);
+
+ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
+
+////////////////////////////////////////////////////////////////////////////////
+// Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state);
+void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state);
+void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
+void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
+void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value);
+void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state);
+void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_SPI_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
new file mode 100644
index 00000000..e034f962
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
@@ -0,0 +1,83 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_syscfg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_SYSCFG_H
+#define __HAL_SYSCFG_H
+
+// Files includes
+#include "types.h"
+#include "mm32_device.h"
+#include "hal_EXTI.H"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SYSCFG_HAL
+/// @brief SYSCFG HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SYSCFG_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SYSCFG mode enumeration
+////////////////////////////////////////////////////////////////////////////////
+// @defgroup SYSCFG_Memory_Remap_Config
+#define SYSCFG_MemoryRemap_Flash ((u8)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory ((u8)0x01)
+#define SYSCFG_MemoryRemap_SRAM ((u8)0x03)
+
+
+
+
+///
+/// @}
+///
+
+
+
+
+// Exported macro ------------------------------------------------------------
+// Exported functions -------------------------------------------------------
+
+// Function used to set the SYSCFG configuration to the default reset state
+#define SYSCFG_DeInit EXTI_DeInit
+#define SYSCFG_MemoryRemapConfig EXTI_MemoryRemapConfig
+#define SYSCFG_EXTILineConfig EXTI_LineConfig
+u32 SYSCFG_GetPendingIT(u32 ITSourceLine);
+void SYSCFG_BreakConfig(u32 SYSCFG_Break);
+FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag);
+void SYSCFG_ClearFlag(u32 SYSCFG_Flag);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_SYSCFG_H
+////////////////////////////////////////////////////////////////////////////////
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
new file mode 100644
index 00000000..4e57960d
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
@@ -0,0 +1,755 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_tim.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_TIM_H
+#define __HAL_TIM_H
+
+// Files includes
+#include "types.h"
+#include "reg_tim.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_HAL
+/// @brief TIM HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Channel
+/// @anchor TIM_Channel
+typedef enum {
+ TIM_Channel_1 = 0x0000, ///< TIM Channel 1
+ TIM_Channel_2 = 0x0004, ///< TIM Channel 2
+ TIM_Channel_3 = 0x0008, ///< TIM Channel 3
+ TIM_Channel_4 = 0x000C, ///< TIM Channel 4
+ TIM_Channel_5 = 0x0010 ///< TIM Channel 5
+} TIMCHx_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Counter_Mode
+/// @anchor TIM_Counter_Mode
+typedef enum {
+ TIM_CounterMode_Up = 0x0000, ///< TIM Up Counting Mode
+ TIM_CounterMode_Down = TIM_CR1_DIR, ///< TIM Down Counting Mode
+ TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1, ///< TIM Center Aligned Mode1
+ TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2, ///< TIM Center Aligned Mode2
+ TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3 ///< TIM Center Aligned Mode3
+} TIMCOUNTMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action
+/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action
+typedef enum {
+ TIM_OCMode_Timing = 0x0000, ///< Output compare mode: Timing
+ TIM_OCMode_Active = 0x0010, ///< Output compare mode: Active
+ TIM_OCMode_Inactive = 0x0020, ///< Output compare mode: Inactive
+ TIM_OCMode_Toggle = 0x0030, ///< Output compare mode: Toggle
+ TIM_OCMode_PWM1 = 0x0060, ///< Output compare mode: PWM1
+ TIM_OCMode_PWM2 = 0x0070, ///< Output compare mode: PWM2
+ TIM_ForcedAction_Active = 0x0050, ///< Force active level on OCnREF
+ TIM_ForcedAction_InActive = 0x0040 ///< Force inactive level on OCnREF
+} TIMOCMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Clock_Division_CKD
+/// @anchor TIM_Clock_Division_CKD
+typedef enum {
+ TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1, ///< TDTS = Tck_tim
+ TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2, ///< TDTS = 2 * Tck_tim
+ TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4 ///< TDTS = 4 * Tck_tim
+} TIMCKD_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Internal_Trigger_Selection
+/// @anchor TIM_Internal_Trigger_Selection
+typedef enum {
+ TIM_TS_ITR0 = TIM_SMCR_TS_ITR0, ///< Internal Trigger 0
+ TIM_TS_ITR1 = TIM_SMCR_TS_ITR1, ///< Internal Trigger 1
+ TIM_TS_ITR2 = TIM_SMCR_TS_ITR2, ///< Internal Trigger 2
+ TIM_TS_ITR3 = TIM_SMCR_TS_ITR3, ///< Internal Trigger 3
+ TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED, ///< TI1 Edge Detector
+ TIM_TS_TI1FP1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1
+ TIM_TS_TI2FP2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2
+ TIM_TS_ETRF = TIM_SMCR_TS_ETRF ///< TI1 Edge Detector
+} TIMTS_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Trigger_Output_Source
+/// @anchor TIM_Trigger_Output_Source
+typedef enum {
+ TIM_TRIGSource_Reset = TIM_CR2_MMS_RESET, ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
+ TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE, ///< The Counter Enable CEN is used as the trigger output (TRIG).
+ TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE, ///< The update event is used as the trigger output (TRIG).
+ TIM_TRIGSource_OC1 = TIM_CR2_MMS_OC1, ///< The trigger output sends a positive pulse when the CC1IF flag
+ ///< is to be set, as soon as a capture or compare match occurs (TRIG).
+ TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF, ///< OC1REF signal is used as the trigger output (TRIG).
+ TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF, ///< OC2REF signal is used as the trigger output (TRIG).
+ TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF, ///< OC3REF signal is used as the trigger output (TRIG).
+ TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF ///< OC4REF signal is used as the trigger output (TRIG).
+} TIMMMS_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Slave_Mode
+/// @anchor TIM_Slave_Mode
+typedef enum {
+ TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET, ///< Rising edge of the selected trigger signal (TRGI) re-initializes
+ ///< the counter and triggers an update of the registers.
+ TIM_SlaveMode_Gated = TIM_SMCR_SMS_GATED, ///< The counter clock is enabled when the trigger signal (TRGI) is high.
+ TIM_SlaveMode_Trigger = TIM_SMCR_SMS_TRIGGER, ///< The counter starts at a rising edge of the trigger TRGI.
+ TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1 ///< Rising edges of the selected trigger (TRGI) clock the counter.
+} TIMSMSMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Event_Source
+/// @anchor TIM_Event_Source
+typedef enum {
+ TIM_EventSource_Update = TIM_EGR_UG, ///< Timer update Event source
+ TIM_EventSource_CC1 = TIM_EGR_CC1G, ///< Timer Capture Compare 1 Event source
+ TIM_EventSource_CC2 = TIM_EGR_CC2G, ///< Timer Capture Compare 2 Event source
+ TIM_EventSource_CC3 = TIM_EGR_CC3G, ///< Timer Capture Compare 3 Event source
+ TIM_EventSource_CC4 = TIM_EGR_CC4G, ///< Timer Capture Compare 4 Event source
+ TIM_EventSource_COM = TIM_EGR_COMG, ///< Timer COM event source
+ TIM_EventSource_Trigger = TIM_EGR_TG, ///< Timer Trigger Event source
+ TIM_EventSource_Break = TIM_EGR_BG, ///< Timer Break event source
+ TIM_EventSource_CC5 = (s32)0x00010000, ///< Timer Capture Compare 5 Event source
+} TIMEGR_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_External_Trigger_Prescaler
+/// @anchor TIM_External_Trigger_Prescaler
+typedef enum {
+ TIM_ExtTRGPSC_OFF = TIM_SMCR_ETPS_OFF, ///< ETRP Prescaler OFF
+ TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2, ///< ETRP frequency divided by 2
+ TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4, ///< ETRP frequency divided by 4
+ TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8 ///< ETRP frequency divided by 8
+} TIMEXTTRGPSC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_TIx_External_Clock_Source
+/// @anchor TIM_TIx_External_Clock_Source
+typedef enum {
+ TIM_TIxExternalCLK1Source_TI1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1
+ TIM_TIxExternalCLK1Source_TI2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2
+ TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED ///< TI1 Edge Detector
+} TIM_TIEXTCLKSRC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Lock_level
+/// @anchor Lock_level
+typedef enum {
+ TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF, ///< No bit is write protected.
+ TIM_LOCKLevel_1 = TIM_BDTR_LOCK_1, ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
+ ///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
+ TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2, ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
+ ///< register, as s32 as the related channel is configured in output through the CCxS
+ ///< bits) as well as OSSR and OSSI bits can no longer be written.
+ TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3 ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers,
+ ///< as s32 as the related channel is configured in output through the CCxS bits)
+ ///< can no longer be written.
+} TIMLOCKLEVEL_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_One_Pulse_Mode
+/// @anchor TIM_One_Pulse_Mode
+typedef enum {
+ TIM_OPMode_Repetitive = 0, ///< Counter is not stopped at update event
+ TIM_OPMode_Single = TIM_CR1_OPM ///< Counter stops counting at the next update event (clearing the bit CEN)
+} TIMOPMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Polarity
+/// @anchor TIM_Output_Compare_Polarity
+typedef enum {
+ TIM_OCPolarity_High, ///< Output Compare active high
+ TIM_OCPolarity_Low = TIM_CCER_CC1P ///< Output Compare active low
+} TIMCCxP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_N_Polarity
+/// @anchor TIM_Output_Compare_N_Polarity
+typedef enum {
+ TIM_OCNPolarity_High, ///< Output Compare active high
+ TIM_OCNPolarity_Low = TIM_CCER_CC1NP ///< Output Compare active low
+} TIMCCxNP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_state
+/// @anchor TIM_Output_Compare_state
+typedef enum {
+ TIM_OutputState_Disable = 0, ///< Output Compare Disable
+ TIM_OutputState_Enable = TIM_CCER_CC1EN ///< Output Compare Enable
+} TIMOUTPUTSTATE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_N_state
+/// @anchor TIM_Output_Compare_N_state
+typedef enum {
+ TIM_OutputNState_Disable = 0, ///< Output Compare N Disable
+ TIM_OutputNState_Enable = TIM_CCER_CC1NEN ///< Output Compare N Enable
+} TIMOUTPUTNSTATE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Capture_Compare_state
+/// @anchor TIM_Capture_Compare_state
+typedef enum {
+ TIM_CCx_Disable = 0, ///< Capture/Compare Enable
+ TIM_CCx_Enable = TIM_CCER_CC1EN ///< Capture/Compare Enable
+} TIMCCxE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Capture_Compare_N_state
+/// @anchor TIM_Capture_Compare_N_state
+typedef enum {
+ TIM_CCxN_Disable = 0, ///< Capture/Compare N Enable
+ TIM_CCxN_Enable = TIM_CCER_CC1NEN ///< Capture/Compare N Enable
+} TIMCCxNE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Break_Input_enable_disable
+/// @anchor Break_Input_enable_disable
+typedef enum {
+ TIM_Break_Disable = 0, ///< Break inputs (BRK and CSS clock failure event) disabled
+ TIM_Break_Enable = TIM_BDTR_BKEN ///< Break inputs (BRK and CSS clock failure event) enabled
+} TIMBKE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Break_Polarity
+/// @anchor Break_Polarity
+typedef enum {
+ TIM_BreakPolarity_Low = 0, ///< Break input BRK is active low
+ TIM_BreakPolarity_High = TIM_BDTR_BKP ///< Break input BRK is active high
+} TIMBKP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_AOE_Bit_Set_Reset
+/// @anchor TIM_AOE_Bit_Set_Reset
+typedef enum {
+ TIM_AutomaticOutput_Disable = 0, ///< MOE can be set only by software.
+ TIM_AutomaticOutput_Enable = TIM_BDTR_AOEN ///< MOE can be set by software or automatically at the next
+ ///< update event (if the break input is not be active).
+} TIMAOE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DOE_Bit_Set_Reset
+/// @anchor TIM_DOE_Bit_Set_Reset
+typedef enum {
+ TIM_DirectOutput_Disable = 0, ///< Direct output disable, output waiting for dead time
+ TIM_DirectOutput_Enable = TIM_BDTR_DOEN ///< Direct output enable, no longer waiting for output after dead time
+} TIMDOE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OSSI_Off_State_Selection_for_Idle_mode_state
+/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state
+typedef enum {
+ TIM_OSSIState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
+ TIM_OSSIState_Enable = TIM_BDTR_OSSI ///< When inactive, OC/OCN outputs are forced first with their idle level
+ ///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1).
+} TIMOSSI_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OSSR_Off_State_Selection_for_Run_mode_state
+/// @anchor OSSR_Off_State_Selection_for_Run_mode_state
+typedef enum {
+ TIM_OSSRState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
+ TIM_OSSRState_Enable = TIM_BDTR_OSSR ///< When inactive, OC/OCN outputs are enabled with their inactive level
+ ///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1.
+} TIMOSSR_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Idle_State
+/// @anchor TIM_Output_Compare_Idle_State
+typedef enum {
+ TIM_OCIdleState_Reset = 0, ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
+ TIM_OCIdleState_Set = TIM_CR2_OIS1 ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
+} TIMOIS_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_N_Idle_State
+/// @anchor TIM_Output_Compare_N_Idle_State
+typedef enum {
+ TIM_OCNIdleState_Reset = 0, ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4)
+ TIM_OCNIdleState_Set = TIM_CR2_OIS1N ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4)
+} TIMOISN_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Input_Capture_Selection
+/// @anchor TIM_Input_Capture_Selection
+typedef enum {
+ TIM_ICSelection_DirectTI = TIM_CCMR1_CC1S_DIRECTTI,
+ TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI,
+ TIM_ICSelection_TRC = TIM_CCMR1_CC1S_TRC ///< TIM Input is selected to be connected to TRC.
+} TIMICSEL_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Input_Capture_Prescaler
+/// @anchor TIM_Input_Capture_Prescaler
+typedef enum {
+ TIM_ICPSC_DIV1 = 0x0000, ///< no prescaler
+ TIM_ICPSC_DIV2 = 0x0004, ///< capture is done once every 2 events
+ TIM_ICPSC_DIV4 = 0x0008, ///< capture is done once every 4 events
+ TIM_ICPSC_DIV8 = 0x000C ///< capture is done once every 8 events
+} TIMICPSC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Input_Capture_Polarity
+/// @anchor TIM_Input_Capture_Polarity
+typedef enum {
+ TIM_ICPolarity_Rising = 0, ///< IC Rising edge
+ TIM_ICPolarity_Falling = TIM_CCER_CC1P, ///< IC Falling edge
+ TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP
+} TIMICP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_External_Trigger_Polarity
+/// @anchor TIM_External_Trigger_Polarity
+typedef enum {
+ TIM_ExtTRGPolarity_NonInverted = 0, ///< Active high or rising edge active
+ TIM_ExtTRGPolarity_Inverted = TIM_SMCR_ETP ///< Active low or falling edge active
+} TIMETP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Prescaler_Reload_Mode
+/// @anchor TIM_Prescaler_Reload_Mode
+typedef enum {
+ TIM_PSCReloadMode_Update = 0, ///< The Prescaler is loaded at the update event
+ TIM_PSCReloadMode_Immediate = TIM_EGR_UG ///< The Prescaler is loaded immediately
+} TIMUG_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Encoder_Mode
+/// @anchor TIM_Encoder_Mode
+typedef enum {
+ TIM_EncoderMode_TI1 = TIM_SMCR_SMS_ENCODER1, ///< Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ TIM_EncoderMode_TI2 = TIM_SMCR_SMS_ENCODER2, ///< Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3 ///< Counter counts on both TI1FP1 and TI2FP2 edges depending
+ ///< on the level of the other input.
+} TIMSMSENCODER_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Update_Source
+/// @anchor TIM_Update_Source
+typedef enum {
+ TIM_UpdateSource_Global = 0, ///< Source of update is counter overflow/underflow.
+ TIM_UpdateSource_Regular = TIM_CR1_URS ///< Source of update is the counter overflow/underflow
+ ///< or the setting of UG bit, or an update generation
+ ///< through the slave mode controller.
+} TIMURS_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Preload_State
+/// @anchor TIM_Output_Compare_Preload_State
+typedef enum {
+ TIM_OCPreload_Disable = 0, ///< TIM output compare preload disable
+ TIM_OCPreload_Enable = TIM_CCMR1_OC1PEN ///< TIM output compare preload enable
+} TIMOCPE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Fast_State
+/// @anchor TIM_Output_Compare_Fast_State
+typedef enum {
+ TIM_OCFast_Disable = 0, ///< TIM output compare fast disable
+ TIM_OCFast_Enable = TIM_CCMR1_OC1FEN, ///< TIM output compare fast enable
+} TIMOCFE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Clear_State
+/// @anchor TIM_Output_Compare_Clear_State
+typedef enum {
+ TIM_OCClear_Disable = 0, ///< TIM Output clear disable
+ TIM_OCClear_Enable = TIM_CCMR1_OC1CEN ///< TIM Output clear enable
+} TIMOCCE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Master_Slave_Mode
+/// @anchor TIM_Master_Slave_Mode
+typedef enum {
+ TIM_MasterSlaveMode_Disable = 0, ///< No action
+ TIM_MasterSlaveMode_Enable = TIM_SMCR_MSM ///< synchronization between the current timer and its slaves (through TRIG)
+} TIMMSM_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_interrupt_sources
+/// @anchor TIM_Master_Slave_Mode
+typedef enum {
+ TIM_IT_Update = TIM_DIER_UI, ///< TIM update Interrupt source
+ TIM_IT_CC1 = TIM_DIER_CC1I, ///< TIM Capture Compare 1 Interrupt source
+ TIM_IT_CC2 = TIM_DIER_CC2I, ///< TIM Capture Compare 2 Interrupt source
+ TIM_IT_CC3 = TIM_DIER_CC3I, ///< TIM Capture Compare 3 Interrupt source
+ TIM_IT_CC4 = TIM_DIER_CC4I, ///< TIM Capture Compare 4 Interrupt source
+ TIM_IT_COM = TIM_DIER_COMI, ///< TIM Commutation Interrupt source
+ TIM_IT_Trigger = TIM_DIER_TI, ///< TIM Trigger Interrupt source
+ TIM_IT_Break = TIM_DIER_BI ///< TIM Break Interrupt source
+ , TIM_IT_CC5 = TIM_DIER_CC5I ///< TIM Capture Compare 5 Interrupt source
+} TIMIT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Flags
+/// @anchor TIM_Flags
+typedef enum {
+ TIM_FLAG_Update = TIM_SR_UI, ///< TIM update Flag
+ TIM_FLAG_CC1 = TIM_SR_CC1I, ///< TIM Capture Compare 1 Flag
+ TIM_FLAG_CC2 = TIM_SR_CC2I, ///< TIM Capture Compare 2 Flag
+ TIM_FLAG_CC3 = TIM_SR_CC3I, ///< TIM Capture Compare 3 Flag
+ TIM_FLAG_CC4 = TIM_SR_CC4I, ///< TIM Capture Compare 4 Flag
+ TIM_FLAG_COM = TIM_SR_COMI, ///< TIM Commutation Flag
+ TIM_FLAG_Trigger = TIM_SR_TI, ///< TIM Trigger Flag
+ TIM_FLAG_Break = TIM_SR_BI, ///< TIM Break Flag
+ TIM_FLAG_CC1OF = TIM_SR_CC1O, ///< TIM Capture Compare 1 overcapture Flag
+ TIM_FLAG_CC2OF = TIM_SR_CC2O, ///< TIM Capture Compare 2 overcapture Flag
+ TIM_FLAG_CC3OF = TIM_SR_CC3O, ///< TIM Capture Compare 3 overcapture Flag
+ TIM_FLAG_CC4OF = TIM_SR_CC4O ///< TIM Capture Compare 4 overcapture Flag
+ , TIM_FLAG_CC5 = TIM_SR_CC5I ///< TIM Capture Compare 5 Flag
+} TIMFLAG_Typedef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMA_sources
+/// @anchor TIM_DMA_sources
+typedef enum {
+ TIM_DMA_Update = TIM_DIER_UD, ///< TIM update Interrupt source
+ TIM_DMA_CC1 = TIM_DIER_CC1D, ///< TIM Capture Compare 1 DMA source
+ TIM_DMA_CC2 = TIM_DIER_CC2D, ///< TIM Capture Compare 2 DMA source
+ TIM_DMA_CC3 = TIM_DIER_CC3D, ///< TIM Capture Compare 3 DMA source
+ TIM_DMA_CC4 = TIM_DIER_CC4D, ///< TIM Capture Compare 4 DMA source
+ TIM_DMA_COM = TIM_DIER_COMD, ///< TIM Commutation DMA source
+ TIM_DMA_Trigger = TIM_DIER_TD ///< TIM Trigger DMA source
+} TIMDMASRC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMA_Base_address
+/// @anchor TIM_DMA_Base_address
+typedef enum {
+ TIM_DMABase_CR1 = 0x0000,
+ TIM_DMABase_CR2 = 0x0001,
+ TIM_DMABase_SMCR = 0x0002,
+ TIM_DMABase_DIER = 0x0003,
+ TIM_DMABase_SR = 0x0004,
+ TIM_DMABase_EGR = 0x0005,
+ TIM_DMABase_CCMR1 = 0x0006,
+ TIM_DMABase_CCMR2 = 0x0007,
+ TIM_DMABase_CCER = 0x0008,
+ TIM_DMABase_CNT = 0x0009,
+ TIM_DMABase_PSC = 0x000A,
+ TIM_DMABase_ARR = 0x000B,
+ TIM_DMABase_RCR = 0x000C,
+ TIM_DMABase_CCR1 = 0x000D,
+ TIM_DMABase_CCR2 = 0x000E,
+ TIM_DMABase_CCR3 = 0x000F,
+ TIM_DMABase_CCR4 = 0x0010,
+ TIM_DMABase_BDTR = 0x0011,
+ TIM_DMABase_DCR = 0x0012
+} TIMDMABASE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMA_Burst_Length
+/// @anchor TIM_DMA_Burst_Length
+typedef enum {
+ TIM_DMABurstLength_1Byte = 0x0000,
+ TIM_DMABurstLength_2Bytes = 0x0100,
+ TIM_DMABurstLength_3Bytes = 0x0200,
+ TIM_DMABurstLength_4Bytes = 0x0300,
+ TIM_DMABurstLength_5Bytes = 0x0400,
+ TIM_DMABurstLength_6Bytes = 0x0500,
+ TIM_DMABurstLength_7Bytes = 0x0600,
+ TIM_DMABurstLength_8Bytes = 0x0700,
+ TIM_DMABurstLength_9Bytes = 0x0800,
+ TIM_DMABurstLength_10Bytes = 0x0900,
+ TIM_DMABurstLength_11Bytes = 0x0A00,
+ TIM_DMABurstLength_12Bytes = 0x0B00,
+ TIM_DMABurstLength_13Bytes = 0x0C00,
+ TIM_DMABurstLength_14Bytes = 0x0D00,
+ TIM_DMABurstLength_15Bytes = 0x0E00,
+ TIM_DMABurstLength_16Bytes = 0x0F00,
+ TIM_DMABurstLength_17Bytes = 0x1000,
+ TIM_DMABurstLength_18Bytes = 0x1100
+} TIMDMABURSTLENGTH_Typedef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM Time Base Init structure definition
+/// @note This structure is used with all tim.
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ u16 TIM_Prescaler; ///< Specifies the prescaler value used to divide the TIM clock.
+ ///< This parameter can be a number between 0x0000 and 0xFFFF
+ TIMCOUNTMODE_Typedef TIM_CounterMode; ///< Specifies the counter mode.
+ ///< This parameter can be a value of @ref TIM_Counter_Mode
+ u32 TIM_Period; ///< Specifies the period value to be loaded into the active
+ ///< Auto-Reload Register at the next update event.
+ ///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF.
+ ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
+ TIMCKD_TypeDef TIM_ClockDivision; ///< Specifies the clock division.
+ ///< This parameter can be a value of @ref TIM_Clock_Division_CKD
+ u8 TIM_RepetitionCounter; ///< Specifies the repetition counter value. Each time the RCR downcounter
+ ///< reaches zero, an update event is generated and counting restarts
+ ///< from the RCR value (N).
+ ///< This means in PWM mode that (N+1) corresponds to:
+ ///< - the number of PWM periods in edge-aligned mode
+ ///< - the number of half PWM period in center-aligned mode
+ ///< This parameter must be a number between 0x00 and 0xFF.
+ ///< @note This parameter is valid only for TIM1 and TIM8.
+} TIM_TimeBaseInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM Output Compare Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ TIMOCMODE_Typedef TIM_OCMode; ///< Specifies the TIM mode.
+ ///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes
+ TIMOUTPUTSTATE_Typedef TIM_OutputState; ///< Specifies the TIM Output Compare state.
+ ///< This parameter can be a value of TIM_Output_Compare_state
+ TIMOUTPUTNSTATE_Typedef TIM_OutputNState; ///< Specifies the TIM complementary Output Compare state.
+ ///< This parameter can be a value of TIM_Output_Compare_N_state
+ ///< @note This parameter is valid only for TIM1 and TIM8.
+ u32 TIM_Pulse; ///< Specifies the pulse value to be loaded into the Capture Compare Register.
+ ///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF
+ ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
+ TIMCCxP_Typedef TIM_OCPolarity; ///< Specifies the output polarity.
+ ///< This parameter can be a value of @ref TIM_Output_Compare_Polarity
+ TIMCCxNP_Typedef TIM_OCNPolarity; ///< Specifies the complementary output polarity.
+ ///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ ///< @note This parameter is valid only for TIM1 and TIM8.
+ TIMOIS_Typedef TIM_OCIdleState; ///< Specifies the TIM Output Compare pin state during Idle state.
+ ///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ ///< @note This parameter is valid only for TIM1 and TIM8.
+ TIMOISN_Typedef TIM_OCNIdleState; ///< Specifies the TIM Output Compare pin state during Idle state.
+ ///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ ///< @note This parameter is valid only for TIM1 and TIM8.
+} TIM_OCInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM Input Capture Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ TIMCHx_Typedef TIM_Channel; ///< Specifies the TIM channel.
+ ///< This parameter can be a value of @ref TIM_Channel
+ TIMICP_Typedef TIM_ICPolarity; ///< Specifies the active edge of the input signal.
+ ///< This parameter can be a value of @ref TIM_Input_Capture_Polarity
+ TIMICSEL_Typedef TIM_ICSelection; ///< Specifies the input.
+ ///< This parameter can be a value of @ref TIM_Input_Capture_Selection
+ TIMICPSC_Typedef TIM_ICPrescaler; ///< Specifies the Input Capture Prescaler.
+ ///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler
+ u16 TIM_ICFilter; ///< Specifies the input capture filter.
+ ///< This parameter can be a number between 0x0 and 0xF
+} TIM_ICInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BDTR structure definition
+/// @note This structure is used only with TIM1 and TIM8.
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ TIMOSSR_Typedef TIM_OSSRState; ///< Specifies the Off-State selection used in Run mode.
+ ///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state
+ TIMOSSI_Typedef TIM_OSSIState; ///< Specifies the Off-State used in Idle state.
+ ///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state
+ TIMLOCKLEVEL_Typedef TIM_LOCKLevel; ///< Specifies the LOCK level parameters.
+ ///< This parameter can be a value of @ref Lock_level
+ u16 TIM_DeadTime; ///< Specifies the delay time between the switching-off and
+ ///< the switching-on of the outputs.
+ ///< This parameter can be a number between 0x00 and 0xFF
+ TIMBKE_Typedef TIM_Break; ///< Specifies whether the TIM Break input is enabled or not.
+ ///< This parameter can be a value of @ref Break_Input_enable_disable
+ TIMBKP_Typedef TIM_BreakPolarity; ///< Specifies the TIM Break Input pin polarity.
+ ///< This parameter can be a value of @ref Break_Polarity
+ TIMAOE_Typedef TIM_AutomaticOutput; ///< Specifies whether the TIM Automatic Output feature is enabled or not.
+ ///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset
+} TIM_BDTRInitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Exported_Variables
+/// @{
+#ifdef _HAL_TIM_C_
+#define GLOBAL
+
+static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+//================= TimeBase management ======================================
+void TIM_DeInit(TIM_TypeDef* tim);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct);
+void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct);
+void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode);
+void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode);
+void TIM_SetCounter(TIM_TypeDef* tim, u32 counter);
+void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload);
+void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state);
+void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source);
+void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state);
+void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode);
+void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div);
+void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state);
+
+u32 TIM_GetCounter(TIM_TypeDef* tim);
+u16 TIM_GetPrescaler(TIM_TypeDef* tim);
+
+//================= Advanced-control timers specific features ================
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct);
+void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state);
+
+//================= Output Compare management ================================
+void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct);
+void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode);
+void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare);
+void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare);
+void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare);
+void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare);
+void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state);
+void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en);
+void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en);
+void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state);
+
+//================= Input Capture management =================================
+void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct);
+void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
+void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
+void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+
+u32 TIM_GetCapture1(TIM_TypeDef* tim);
+u32 TIM_GetCapture2(TIM_TypeDef* tim);
+u32 TIM_GetCapture3(TIM_TypeDef* tim);
+u32 TIM_GetCapture4(TIM_TypeDef* tim);
+
+//================= Interrupts, DMA and flags management =====================
+void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef
+void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source);
+void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
+void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef
+void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length);
+void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state);
+void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
+ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it);
+
+//================= Clocks management ========================================
+void TIM_InternalClockConfig(TIM_TypeDef* tim);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
+
+//================= Synchronization management ===============================
+void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source);
+void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source);
+void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode);
+void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
+
+//================= Specific interface management ============================
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim,
+ TIMSMSENCODER_Typedef encoder_mode,
+ TIMICP_Typedef ic1_polarity,
+ TIMICP_Typedef iC2_polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state);
+
+//================= extend Channel IC management ==============================
+void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+
+#define exTIM_SetIC1Plority TIM_SetIC1Plority
+#define exTIM_SetIC2Plority TIM_SetIC2Plority
+#define exTIM_SetIC3Plority TIM_SetIC3Plority
+#define exTIM_SetIC4Plority TIM_SetIC4Plority
+//================= extend Channel 5 management ==============================
+
+void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare);
+void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+u32 TIM_GetCapture5(TIM_TypeDef* tim);
+
+#define exTIM_SetCompare5 TIM_SetCompare5
+#define exTIM_OC5Init TIM_OC5Init
+#define exTIM_OC5PreloadConfig TIM_OC5PreloadConfig
+#define exTIM_OC5PolarityConfig TIM_OC5PolarityConfig
+#define exTIM_OC5FastConfig TIM_OC5FastConfig
+#define exTIM_ClearOC5Ref TIM_ClearOC5Ref
+#define exTIM_GetCapture5 TIM_GetCapture5
+
+//============= extend Advanced-control timers specific features ==============
+void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state);
+#define exTIM_DirectOutput TIM_DirectOutput
+void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);
+void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_TIM_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
new file mode 100644
index 00000000..a46f234e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_uart.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_UART_H
+#define __HAL_UART_H
+
+// Files includes
+#include "reg_uart.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup UART_HAL
+/// @brief UART HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Types
+/// @{
+///
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Word Length Enumerate definition
+/// @anchor UART_Word_Length
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ UART_WordLength_5b = 0U,
+ UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos,
+ UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos,
+ UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos
+} UART_WordLength_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Stop Bits Enumerate definition
+/// @anchor UART_Stop_Bits
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ UART_StopBits_1 = 0U,
+ UART_StopBits_2 = UART_CCR_SPB,
+
+ UART_StopBits_0_5 = UART_CCR_SPB1,
+ UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0,
+} UART_Stop_Bits_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Parity Enumerate definition
+/// @anchor UART_Parity
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ UART_Parity_No = 0U,
+ UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL,
+ UART_Parity_Odd = UART_CCR_PEN
+} UART_Parity_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Hardware Flow Control Enumerate definition
+/// @anchor UART_Hardware_Flow_Control
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ UART_HWFlowControl_None = 0U,
+
+ // UART_HWFlowControl_RTS = UART_GCR_AUTOFLOW,
+ // UART_HWFlowControl_CTS = UART_GCR_AUTOFLOW,
+
+ UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW
+} UART_HW_FLOWCONTROL_TypeDef;
+
+typedef enum {
+ UART_WakeUp_IdleLine = 0U, //
+ UART_WakeUp_AddressMark = UART_CCR_WAKE
+} UART_WakeUp_TypeDef;
+
+typedef enum {
+ UART_9bit_Polarity_Low = 0U, //
+ UART_9bit_Polarity_High = UART_CCR_B8POL
+} UART_9bit_Polarity_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Auto BaudRate definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+ Data_F8 = 0,
+ Data_FE,
+ ABRMODE_FALLING_TO_RISINGEDGE1BIT,
+ ABRMODE_FALLING_TO_RISINGEDGE2BIT,
+ ABRMODE_FALLING_TO_RISINGEDGE4BIT,
+ ABRMODE_FALLING_TO_RISINGEDGE8BIT,
+ ABRMODE_FALLING_TO_FALLINGEDGE2BIT,
+ ABRMODE_FALLING_TO_FALLINGEDGE4BIT,
+ ABRMODE_FALLING_TO_FALLINGEDGE8BIT,
+ ABRMODE_STARTBIT,
+ ABRMODE_VALUE0X55,
+ ABRMODE_VALUE0x7F,
+ ABRMODE_VALUE0X80,
+ ABRMODE_VALUE0XF7,
+ ABRMODE_VALUE0XF8 = Data_F8,
+ ABRMODE_VALUE0XFE = Data_FE,
+ ABRMODE_VALUE0XFF,
+} UART_AutoBaud_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ union {
+ u32 BaudRate; ///< This member configures the UART communication baud rate.
+ u32 UART_BaudRate;
+ };
+ union {
+ UART_WordLength_TypeDef WordLength; ///< Specifies the number of data bits transmitted or received in a frame.
+ u16 UART_WordLength;
+ };
+ union {
+ UART_Stop_Bits_TypeDef StopBits; ///< Specifies the number of stop bits transmitted.
+ u16 UART_StopBits;
+ };
+ union {
+ UART_Parity_TypeDef Parity; ///< Specifies the parity mode.
+ u16 UART_Parity;
+ };
+ union {
+ u16 Mode; ///< Specifies wether the Receive or Transmit mode is
+ u16 UART_Mode;
+ };
+ union {
+ UART_HW_FLOWCONTROL_TypeDef HWFlowControl; ///< Specifies wether the hardware flow control mode is enabled or disabled.
+ u16 UART_HardwareFlowControl;
+ };
+} UART_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Variables
+/// @{
+#ifdef _HAL_UART_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Functions
+/// @{
+void UART_DeInit(UART_TypeDef* uart);
+void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct);
+void UART_StructInit(UART_InitTypeDef* init_struct);
+void UART_Cmd(UART_TypeDef* uart, FunctionalState state);
+void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state);
+void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state);
+void UART_SendData(UART_TypeDef* uart, u16 Data);
+void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it);
+
+u16 UART_ReceiveData(UART_TypeDef* uart);
+FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag);
+
+ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it);
+
+void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode);
+void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SetRXAddress(UART_TypeDef* uart, u8 address);
+void UART_SetRXMASK(UART_TypeDef* uart, u8 address);
+void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state);
+void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state);
+void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity);
+void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state);
+void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time);
+void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SendBreak(UART_TypeDef* uart);
+void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_UART_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
new file mode 100644
index 00000000..2dba789d
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
@@ -0,0 +1,71 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_uid.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_UID_H
+#define __HAL_UID_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UID_HAL
+/// @brief UID HAL modules
+/// @{
+
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup UID_Exported_Variables
+/// @{
+#ifdef _HAL_UID_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+
+
+#endif
+GLOBAL u8 device_id_data[12];
+
+#undef GLOBAL
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UID_Exported_Functions
+/// @{
+void GetChipUID(void);
+
+/// @}
+
+
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_UID_H
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
new file mode 100644
index 00000000..773af563
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
@@ -0,0 +1,89 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_ver.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_VER_H
+#define __HAL_VER_H
+
+// Files includes
+#include "reg_common.h"
+#include "reg_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup UART_HAL
+/// @brief UART HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Types
+/// @{
+///
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Word Length Enumerate definition
+/// @anchor UART_Word_Length
+////////////////////////////////////////////////////////////////////////////////
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Variables
+/// @{
+#ifdef _HAL_VER_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Functions
+/// @{
+
+u32 Get_MM32LibVersion(void);
+u32 Get_ChipsetREVID(void);
+u32 Get_ChipsetDEVID(void);
+u32 Get_ChipsetUIDw0(void);
+u32 Get_ChipsetUIDw1(void);
+u32 Get_ChipsetUIDw2(void);
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_VER_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
new file mode 100644
index 00000000..287ddd5c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
@@ -0,0 +1,90 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_wwdg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_WWDG_H
+#define __HAL_WWDG_H
+
+// Files includes
+#include "types.h"
+#include "reg_wwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_HAL
+/// @brief WWDG HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_Prescaler
+/// @anchor WWDG_Prescaler
+
+typedef enum {
+ WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1,
+ WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2,
+ WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4,
+ WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8
+} WWDG_Prescaler_Typedef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_Exported_Variables
+/// @{
+
+#ifdef _HAL_WWDG_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_Exported_Functions
+/// @{
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(u32 prescaler);
+void WWDG_SetWindowValue(u8 window_value);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(u8 count);
+u32 WWDG_GetCounter(void);
+void WWDG_Enable(u8 count);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_WWDG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
new file mode 100644
index 00000000..503e91a6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
@@ -0,0 +1,563 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_adc.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_ADC_C_
+
+// Files includes
+#include "hal_adc.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup ADC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup ADC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the adc peripheral registers to their default
+/// reset values.
+/// @param adc: select the ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_DeInit(ADC_TypeDef* adc)
+{
+
+ switch (*(vu32*)&adc) {
+
+ case ADC1_BASE:
+ exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1);
+ break;
+ case ADC2_BASE:
+ exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2);
+ break;
+ case ADC3_BASE:
+ exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the adc peripheral according to the specified parameters
+/// in the init_struct, Please use this function if you want to be
+/// compatible with older versions of the library.
+/// @param adc: select the ADC peripheral.
+/// @param init_struct: pointer to an ADC_InitTypeDef structure that contains
+/// the configuration information for the specified ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct)
+{
+ adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL);
+ adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution;
+
+ adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL);
+ adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct : pointer to an ADC_InitTypeDef structure which will be
+/// initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_StructInit(ADC_InitTypeDef* init_struct)
+{
+ init_struct->ADC_Resolution = ADC_Resolution_12b;
+ init_struct->ADC_PRESCARE = ADC_PCLK2_PRESCARE_2;
+ init_struct->ADC_Mode = ADC_CR_IMM; //ADC_Mode_Single;
+ init_struct->ADC_ContinuousConvMode = DISABLE; // useless
+ init_struct->ADC_ExternalTrigConv = ADC1_ExternalTrigConv_T1_CC1;
+ init_struct->ADC_DataAlign = ADC_DataAlign_Right;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified ADC peripheral.
+/// @param adc:select the ADC peripheral.
+/// @param state: new state of the adc peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified ADC DMA request.
+/// @param adc: select the ADC peripheral.
+/// @param state: New state of the selected ADC DMA transfer.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified ADC interrupts.
+/// @param adc: select the ADC peripheral.
+/// @param adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled.
+/// @param state: New state of the specified ADC interrupts.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state)
+{
+ if (adc_interrupt == ADC_IT_EOC)
+ (state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE);
+ else
+ (state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the selected ADC software start conversion .
+/// @param adc: select the ADC peripheral.
+/// @param state: New state of the selected ADC software start conversion.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the selected ADC Software start conversion Status.
+/// @param adc: select the ADC peripheral.
+/// @retval The new state of ADC software start conversion (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc)
+{
+ return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable the selected ADC channel and configure its sample time. Please
+/// use this function if you want to be compatible with older versions
+/// of the library.
+/// @param adc: select the ADC peripheral.
+/// @param channel: the ADC channel to configure.
+/// @param sample_time: the ADC Channel n Sample time to configure.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time) //ADCSAM_TypeDef
+{
+
+ u32 tempchan;
+ sample_time = sample_time & 0xF;
+ tempchan = channel;
+ if(tempchan > 8) {
+ tempchan = tempchan & 0xF;
+ tempchan = tempchan - 8;
+ adc->SMPR2 &= ~(0xF << tempchan);
+ adc->SMPR2 |= (sample_time << tempchan);
+ }
+ else {
+ adc->SMPR1 &= ~(0xF << tempchan);
+ adc->SMPR1 |= (sample_time << tempchan);
+ }
+ adc->ADCHS &= ~(1 << channel);
+ adc->ADCHS |= (1 << channel);
+
+ if (channel & ADC_CHSR_CHT)
+ ADC_TempSensorVrefintCmd(ENABLE);
+ else if (channel & ADC_CHSR_CHV)
+ ADC_TempSensorVrefintCmd(ENABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the adc conversion through external trigger.
+/// @param adc: select the ADC peripheral.
+/// @param state: New state of the selected ADC external trigger.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the adc external trigger for injected channels conversion.
+/// @param adc: select the ADC peripheral.
+/// @param adc_external_trig_source: Configuring the external trigger source
+/// for the ADC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source)
+{
+ adc->ADCR &= ~ADC_CR_TRGSEL;
+ adc->ADCR |= adc_external_trig_source;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the last adc conversion result data for regular channel.
+/// @param adc: select the ADC peripheral.
+/// @retval The data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetConversionValue(ADC_TypeDef* adc)
+{
+ return (u16)adc->ADDATA;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the last ADC conversion result data in dual mode.
+/// @param None
+/// @retval The Data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u32 ADC_GetDualModeConversionValue()
+{
+ return (*(vu32*)ADC1_BASE);
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the analog watchdog.
+/// @param adc: to select the ADC peripheral.
+/// @param state: New state of the selected ADC analog watchdog.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the high and low thresholds of the analog watchdog.
+/// @param adc: select the ADC peripheral.
+/// @param high_threshold: the ADC analog watchdog High threshold value.
+/// This parameter must be a 12bit value.
+/// @param low_threshold: the ADC analog watchdog Low threshold value.
+/// This parameter must be a 12bit value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold)
+{
+ u32 tempThreshold;
+ tempThreshold = high_threshold;
+ adc->ADCMPR = (tempThreshold << 16) | low_threshold;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the analog watchdog guarded single channel
+/// @param adc: select the ADC peripheral.
+/// @param channel: the ADC channel to configure for the analog watchdog.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
+{
+ adc->ADCR &= ~ADC_CR_CMPCH;
+ adc->ADCR |= (channel << ADC_CR_CMPCH_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the temperature sensor and Vrefint channel.
+/// @param state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_TempSensorVrefintCmd(FunctionalState state)
+{
+ (state) ? (ADC1->ADCFG |= (ADC_CFGR_TEN | ADC_CFGR_VEN))
+ : (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN));
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the temperature sensor .
+/// @param state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_TempSensorCmd(FunctionalState state)
+{
+ ADC_TempSensorVrefintCmd(state);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Vrefint channel.
+/// @param state: New state of the Vrefint channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_VrefintCmd(FunctionalState state)
+{
+ ADC_TempSensorVrefintCmd(state);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the temperature sensor and Vrefint channel.
+/// @param chs: temperature sensor bit & Vrefint bit.
+/// @param state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state)
+{
+ if (chs & ADC_CHSR_CHT) {
+ (state) ? (ADC1->ADCFG |= ADC_CFGR_TEN)
+ : (ADC1->ADCFG &= ~ADC_CFGR_TEN);
+ }
+ else if (chs & ADC_CHSR_CHV) {
+ (state) ? (ADC1->ADCFG |= ADC_CFGR_VEN)
+ : (ADC1->ADCFG &= ~ADC_CFGR_VEN);
+ }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified ADC flag is set or not.
+/// @param adc: select the ADC peripheral.
+/// @param adc_flag: specifies the flag to check.
+/// @retval The New state of adc_flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
+{
+ return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the adc's pending flags.
+/// @param adc: select the ADC peripheral.
+/// @param adc_flag: specifies the flag to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
+{
+ (adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified adc's interrupt has occurred or not.
+/// @param adc: select the ADC peripheral.
+/// @param adc_interrupt: specifies the ADC interrupt source to check.
+/// @retval The new state of adc_interrupt (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
+{
+ return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the adc's interrupt pending bits.
+/// @param adc: select the ADC peripheral.
+/// @param adc_interrupt: specifies the ADC interrupt pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
+{
+ (adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the adc any channels conversion rank and channel.
+/// @param adc: select the ADC peripheral.
+/// @param rank: rank can be 0x0~0xf for the convert sequence.
+/// @param adc_channel: Configuring the target channel to be converted.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel)
+{
+ rank = rank & 0xF;
+ if(rank < 8) {
+ adc->CHANY0 &= ~(0x0F << (4 * rank));
+ adc->CHANY0 |= (adc_channel << (4 * rank));
+ }
+ else {
+ adc->CHANY1 &= ~(0x0F << (4 * (rank - 8)));
+ adc->CHANY1 |= (adc_channel << (4 * (rank - 8)));
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the adc any channels conversion Max rank number
+/// @param adc: select the ADC peripheral.
+/// @param num: Configuring the max rank number for the ADC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num)
+{
+ if(num > 15) num = 15; //15 ? 16 need to be confirmed
+ adc->ANYCFG = num;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the ANY channel converter.
+/// @param state: enable or disable the ANY channel converter mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the selected ADC automatic injected group
+/// conversion after regular one.
+/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param state: new state of the selected ADC auto injected conversion
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the adc external trigger for injected channels conversion.
+/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion.
+
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource)
+{
+ u32 tmpreg = 0;
+ // Get the old register value
+ tmpreg = adc->ANYCR;
+ // Clear the old external event selection for injected group
+ tmpreg &= ADC_ANY_CR_JTRGSEL;
+ // Set the external event selection for injected group
+ tmpreg |= ADC_ExtInjTrigSource;
+ // Store the new register value
+ adc->ANYCR = tmpreg;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the adc injected channels conversion through
+/// external trigger
+/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param state: new state of the selected ADC external trigger start of
+/// injected conversion.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the selected ADC start of the injected
+/// channels conversion.
+/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param state: new state of the selected ADC software start injected conversion.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the selected ADC start of the injected
+/// channels conversion.
+/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param NewState: new state of the selected ADC software start injected conversion.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+ (state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST);
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable the selected ADC channel and configure its sample time. Please
+/// use this function if you want to be compatible with older versions
+/// of the library.
+/// @param adc: select the ADC peripheral.
+/// @param event: the ADC external event to configure.
+/// @param sample_time: the ADC Channel n Sample time to configure.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time)
+{
+ adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \
+ | ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN);
+ adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Injection channel length configuration.
+/// @param adc: select the ADC peripheral.
+/// @param Length: Injection channel length.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length)
+{
+ adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos);
+ adc->JSQR |= Length << ADC_JSQR_JL_Pos;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Injection channel configuration.
+/// @param adc : select the ADC peripheral.
+/// @param off_addr : Injection channel offset address.
+/// @param channel: The sampling channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel)
+{
+ adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5);
+ adc->JSQR |= (channel << (off_addr >> 2) * 5);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Injection channel converted value.
+/// @param adc : select the ADC peripheral.
+/// @param off_addr : Injection channel offset address.
+/// @retval value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr)
+{
+ u32 value;
+ value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr));
+
+ return (u16)value;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Injection current converted value.
+/// @param adc : select the ADC peripheral.
+/// @retval value. Returns the last adc conversion result data for injected channel.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc)
+{
+ return (u16)adc->JDATA;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Injection channel compensation configuration.
+/// @param adc : select the ADC peripheral.
+/// @param off_addr : Injection channel.
+/// @param value : compensation value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value)
+{
+ *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Get channel convertion result.
+/// @param adc : select the ADC peripheral.
+/// @param channel : Converted channel.
+/// @retval The Data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
+{
+ return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2)));
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
new file mode 100644
index 00000000..323971dd
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
@@ -0,0 +1,231 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_bkp.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_BKP_C_
+
+// Files includes
+#include "types.h"
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_bkp.h"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup BKP_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup BKP_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the BKP peripheral registers to their default reset
+/// values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_DeInit(void)
+{
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the Tamper Pin active level.
+/// @param tamper_pin_level: specifies the Tamper Pin active level.
+/// This parameter can be one of the following values:
+/// @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+/// @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level)
+{
+ BKP->CR = tamper_pin_level;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Tamper Pin activation.
+/// @param state: new state of the Tamper Pin activation.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_TamperPinCmd(FunctionalState state)
+{
+ (state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Tamper Pin Interrupt.
+/// @param state: new state of the Tamper Pin Interrupt.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ITConfig(FunctionalState state)
+{
+ (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select the RTC output source to output on the Tamper pin.
+/// @param rtc_output_source: specifies the RTC output source.
+/// This parameter can be one of the following values:
+/// @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+/// @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+/// divided by 64 on the Tamper pin.
+/// @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+/// the Tamper pin.
+/// @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+/// the Tamper pin.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source)
+{
+ MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets RTC Clock Calibration value.
+/// @param calibration_value: specifies the RTC Clock Calibration value.
+/// This parameter must be a number between 0 and 0x7F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_SetRTCCalibrationValue(u8 calibration_value)
+{
+ MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the Tamper Pin Event flag is set or not.
+/// @param None.
+/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus BKP_GetFlagStatus(void)
+{
+ return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears Tamper Pin Event pending flag.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ClearFlag(void)
+{
+ SET_BIT(BKP->CSR, BKP_CSR_CTE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the Tamper Pin Interrupt has occurred or not.
+/// @param None.
+/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus BKP_GetITStatus(void)
+{
+ return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears Tamper Pin Interrupt pending bit.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ClearITPendingBit(void)
+{
+ SET_BIT(BKP->CSR, BKP_CSR_CTI);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Writes user data to the specified data Backup Register.
+/// @param bkp_dr: specifies the data Backup Register.
+/// This parameter can be BKP_DRx where x:[1, 10]
+/// @param data: data to write
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data)
+{
+ *(vu16*)(BKP_BASE + bkp_dr) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads data from the specified data Backup Register.
+/// @param bkp_dr: specifies the data Backup Register.
+/// This parameter can be BKP_DRx where x:[1, 10]
+/// @retval data: The content of the specified data Backup Register
+////////////////////////////////////////////////////////////////////////////////
+u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr)
+{
+ return (*(vu16*)(BKP_BASE + bkp_dr));
+}
+////////////////////////////////////////////////////////////////////////////////
+// Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the BKP peripheral, enable access to the backup
+/// registers.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exBKP_Init(void)
+{
+ RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE);
+ //COMMON_EnableIpClock(emCLOCK_PWR);
+ RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE);
+ //COMMON_EnableIpClock(emCLOCK_BKP);
+
+ RCC->BDCR |= RCC_BDCR_DBP;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Writes user data to the specified data Backup Register immediately.
+/// @param bkp_dr: specifies the data Backup Register.
+/// This parameter can be BKP_DRx where x:[1, 10]
+/// @param data: data to write
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat)
+{
+ RCC->BDCR |= RCC_BDCR_DBP;
+ *(vu16*)(BKP_BASE + bkp_dr) = dat;
+ RCC->BDCR &= ~RCC_BDCR_DBP;
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads data from the specified data Backup Register immediately.
+/// @param bkp_dr: specifies the data Backup Register.
+/// This parameter can be BKP_DRx where x:[1, 10]
+/// @retval data: The content of the specified data Backup Register
+////////////////////////////////////////////////////////////////////////////////
+u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr)
+{
+ u16 dat;
+ RCC->BDCR |= RCC_BDCR_DBP;
+ dat = (*(vu16*)(BKP_BASE + bkp_dr));
+ RCC->BDCR &= ~RCC_BDCR_DBP;
+ return dat;
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
new file mode 100644
index 00000000..9dd85df2
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
@@ -0,0 +1,696 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_can.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define __HAL_CAN_C
+
+// Files includes
+#include "hal_can.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CAN_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CAN_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the CAN peripheral registers to their default reset
+/// values.
+/// @param can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_DeInit(CAN_TypeDef* can)
+{
+ exRCC_APB1PeriphReset(RCC_APB1ENR_CAN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the CAN peripheral according to the specified
+/// parameters in the CAN_InitStruct.
+/// @param can: select the CAN peripheral.
+/// @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+/// contains the configuration information for the CAN peripheral.
+/// @retval Constant indicates initialization succeed which will be
+/// CANINITFAILED or CANINITOK.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct)
+{
+ u8 InitStatus = CANINITFAILED;
+
+ can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP));
+ can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1));
+
+ if (init_struct->GTS == ENABLE) {
+ can->CMR |= (u32)CAN_SleepMode;
+ InitStatus = CANINITFAILED;
+ }
+ else {
+ can->CMR &= ~(u32)CAN_SleepMode;
+ InitStatus = CANINITOK;
+ }
+
+ (init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode);
+
+ can->CDR |=
+ ((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK);
+
+ return InitStatus;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the CAN_Basic reception filter according to the specified
+/// parameters in the basic_filter_init_struct.
+/// @param basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef
+/// structure that contains the configuration information.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct)
+{
+ // Filter Mode
+ CAN1->ACR = basic_filter_init_struct->CAN_FilterId;
+ CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct)
+{
+ // Reset CAN_Basic init structure parameters values
+
+ // initialize the BRP member(where can be set with (0..63))
+ init_struct->BRP = 0x0;
+ // initialize the SJW member(where can be set with (0..3))
+ init_struct->SJW = 0x0;
+ // Initialize the TESG1 member(where can be set with (0..15))
+ init_struct->TESG1 = 0x0;
+ // Initialize the TESG2 member(where can be set with(0..7))
+ init_struct->TESG2 = 0x0;
+ // Initialize the SAM member(where can be set (SET or RESET))
+ init_struct->SAM = RESET;
+ // Initialize the GTS member to Sleep Mode(where can be set (ENABLE or
+ // DISABLE))
+ init_struct->GTS = DISABLE;
+ // Initialize the external pin CLKOUT frequence
+ init_struct->CDCLK = 0x0;
+ // Initialize the external clk is open or close
+ init_struct->CLOSE_OPEN_CLK = 0x0;
+ // Initialize the TX1 pin work as rx interrupt output
+ init_struct->RXINTEN = 0x0;
+ // Initialize the CBP of CDR register
+ init_struct->CBP = 0x0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified CAN interrupts.
+/// @param can: select the CAN peripheral.
+/// @param it: specifies the CAN interrupt sources to be enabled or
+/// disabled.
+/// This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE,
+/// CAN_IT_RIE.
+/// @param state: new state of the CAN interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state)
+{
+ (state) ? (can->CR |= it) : (can->CR &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initiates and transmits a CAN frame message.
+/// @param can:select the CAN peripheral.
+/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+/// CAN data.
+/// @retval CANTXOK if the CAN driver transmits the message
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message)
+{
+ can->TXID0 = (basic_transmit_message->IDH);
+ can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC);
+ if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) {
+ can->TXDR0 = basic_transmit_message->Data[0];
+ can->TXDR1 = basic_transmit_message->Data[1];
+ can->TXDR2 = basic_transmit_message->Data[2];
+ can->TXDR3 = basic_transmit_message->Data[3];
+ can->TXDR4 = basic_transmit_message->Data[4];
+ can->TXDR5 = basic_transmit_message->Data[5];
+ can->TXDR6 = basic_transmit_message->Data[6];
+ can->TXDR7 = basic_transmit_message->Data[7];
+ }
+
+ can->CMR = CAN_CMR_TR;
+
+ return (can->SR & 0x01);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Cancels a transmit request.
+/// @param can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_CancelTransmit(CAN_TypeDef* can)
+{
+ // abort transmission
+ can->CMR = CAN_AT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Releases the specified receive FIFO.
+/// @param can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_FIFORelease(CAN_TypeDef* can)
+{
+ // Release FIFO
+ can->CMR |= (u32)CAN_RRB;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Receives a correct CAN frame.
+/// @param can: select the CAN peripheral.
+/// @param RxMessage: pointer to a structure receive frame which contains CAN
+/// Id,CAN DLC, CAN data and FMI number.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message)
+{
+ u16 tempid;
+
+ basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1;
+ basic_receive_message->DLC = (u8)((can->RXID1) & 0xf);
+ tempid = (u16)(((can->RXID1) & 0xe0) >> 5);
+ tempid |= (u16)(can->RXID0 << 3);
+ basic_receive_message->ID = tempid;
+ basic_receive_message->Data[0] = CAN1->RXDR0;
+ basic_receive_message->Data[1] = CAN1->RXDR1;
+ basic_receive_message->Data[2] = CAN1->RXDR2;
+ basic_receive_message->Data[3] = CAN1->RXDR3;
+ basic_receive_message->Data[4] = CAN1->RXDR4;
+ basic_receive_message->Data[5] = CAN1->RXDR5;
+ basic_receive_message->Data[6] = CAN1->RXDR6;
+ basic_receive_message->Data[7] = CAN1->RXDR7;
+ CAN_FIFORelease(can);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select the Sleep mode or not in Basic workmode
+/// @param state to go into the Sleep mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Sleep(CAN_TypeDef* can)
+{
+ can->CMR |= CAN_SleepMode;
+ // At this step, sleep mode status
+ return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Wakes the CAN up.
+/// @param can: where x can be 1 to select the CAN peripheral.
+/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_WakeUp(CAN_TypeDef* can)
+{
+ // Wake up request
+ can->CMR &= ~CAN_SleepMode;
+ return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified CAN flag is set or not.
+/// @param can: select the CAN peripheral.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg CAN_STATUS_RBS: Receive buffer status
+/// @arg CAN_STATUS_DOS: Data overflow status
+/// @arg CAN_STATUS_TBS: Transmit buffer status
+/// @arg CAN_STATUS_TCS: Transmit complete status
+/// @arg CAN_STATUS_RS: Receiving status
+/// @arg CAN_STATUS_TS: Transmiting status
+/// @arg CAN_STATUS_ES: Error status
+/// @arg CAN_STATUS_BS: bus status, close or open
+/// @retval The new state of CAN_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag)
+{
+ return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified CAN interrupt has occurred or not.
+/// @param can: where x can be 1 to select the CAN peripheral.
+/// @param it: specifies the CAN interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg CAN_IT_TI: Transmit Interrupt
+/// @arg CAN_IT_EI: ERROR Interrupt
+/// @arg CAN_IT_DOI: Data voerflow Interrupt
+/// @arg CAN_IT_WUI: Wakeup Interrupt
+/// @arg CAN_IT_ALL: use it can enble all Interrupt
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it)
+{
+ return (ITStatus)((can->IR & it) != it) ? RESET : SET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select the can work as peli mode or basic mode
+/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @param CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode)
+{
+ can->CDR |= mode;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select the Reset mode or not
+/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @param state to go into the Reset mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state)
+{
+ (state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clear the data overflow.
+/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ClearDataOverflow(CAN_TypeDef* can)
+{
+ can->CMR |= (u32)CAN_CDO;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the CAN's IT pending.
+/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ClearITPendingBit(CAN_TypeDef* can)
+{
+ u32 temp = 0;
+ temp = temp;
+ temp = can->IR; // read this register clear all interrupt
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select the Sleep mode or not in Peli workmode
+/// @param state to go into the Sleep mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_SleepMode_Cmd(FunctionalState state)
+{
+ (state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each CAN1_PELI_InitStruct member with its default value.
+/// @param init_struct : pointer to a CAN_Peli_InitTypeDef structure
+/// which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct)
+{
+ //--------------- Reset CAN_Peli init structure parameters values
+ //---------------
+ init_struct->BRP = 0x0; // initialize the BRP member(where can be set with (0..63))
+ init_struct->SJW = 0x0; // initialize the SJW member(where can be set with (0..3))
+ init_struct->TESG1 = 0x0; // Initialize the TESG1 member(where can be set with (0..15))
+ init_struct->TESG2 = 0x0; // Initialize the TESG2 member(where can be set with(0..7))
+ init_struct->SAM = RESET; // Initialize the SAM member(where can be set (SET or RESET))
+ init_struct->LOM = DISABLE; // Initialize the LOM member
+ init_struct->STM = DISABLE; // Initialize the STM member
+ init_struct->SM = DISABLE; // Initialize the SM member
+ init_struct->SRR = DISABLE;
+ init_struct->EWLR = 0x96;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the CAN_Peli peripheral according to the specified
+/// parameters in the init_struct.
+/// @param init_struct: pointer to a CAN_Peli_InitTypeDef structure that
+/// contains the configuration information for the CAN peripheral in the peli workmode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct)
+{
+ CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP);
+ CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1);
+ if (init_struct->LOM == ENABLE)
+ CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode;
+ else
+ CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode;
+ if (init_struct->STM == ENABLE)
+ CAN1_PELI->MOD |= (u32)CAN_SeftTestMode;
+ else
+ CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode;
+ if (init_struct->SM == ENABLE)
+ CAN1_PELI->MOD |= (u32)CAN_SleepMode;
+ else
+ CAN1_PELI->MOD &= ~(u32)CAN_SleepMode;
+ CAN1_PELI->EWLR = (u32)init_struct->EWLR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the CAN_Peli reception filter according to the specified
+/// parameters in the peli_filter_init_struct.
+/// @param peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef
+/// structure that contains the configuration information.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
+{
+ (peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal)
+ : (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double);
+
+ CAN1_PELI->FF = peli_filter_init_struct->CAN_FilterId0;
+ CAN1_PELI->ID0 = peli_filter_init_struct->CAN_FilterId1;
+ CAN1_PELI->ID1 = peli_filter_init_struct->CAN_FilterId2;
+ CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3;
+
+ CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0;
+ CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1;
+ CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2;
+ CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each peli_filter_init_struct member with its default value.
+/// @param peli_filter_init_struct: pointer to a CAN_InitTypeDef structure
+/// which ill be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
+{
+ peli_filter_init_struct->CAN_FilterId0 = 0;
+ peli_filter_init_struct->CAN_FilterId1 = 0;
+ peli_filter_init_struct->CAN_FilterId2 = 0;
+ peli_filter_init_struct->CAN_FilterId3 = 0;
+
+ peli_filter_init_struct->CAN_FilterMaskId0 = 0;
+ peli_filter_init_struct->CAN_FilterMaskId1 = 0;
+ peli_filter_init_struct->CAN_FilterMaskId2 = 0;
+ peli_filter_init_struct->CAN_FilterMaskId3 = 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initiates and transmits a CAN frame message.
+/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+/// CAN data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message)
+{
+ CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
+ if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
+ CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
+
+ CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
+ if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+ CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
+ CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
+ CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
+ CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
+ CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
+ CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
+ CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
+ CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
+ }
+ }
+ else {
+ CAN1_PELI->ID0 = peli_transmit_message->IDHH;
+ CAN1_PELI->ID1 = peli_transmit_message->IDHL;
+ CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
+ CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
+ if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+ CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
+ CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
+ CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
+ CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
+ CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
+ CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
+ CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
+ CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
+ }
+ }
+
+ (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initiates and transmits a CAN frame message.
+/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+/// CAN data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message)
+{
+ CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
+ if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
+ CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
+
+ CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
+ if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+ CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
+ CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
+ CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
+ CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
+ CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
+ CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
+ CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
+ CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
+ }
+ }
+ else {
+ CAN1_PELI->ID0 = peli_transmit_message->IDHH;
+ CAN1_PELI->ID1 = peli_transmit_message->IDHL;
+ CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
+ CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
+ if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+ CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
+ CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
+ CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
+ CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
+ CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
+ CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
+ CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
+ CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
+ }
+ }
+
+ (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Receives a correct CAN frame.
+/// @param RxMessage: pointer to a structure receive frame which contains CAN
+/// Id,CAN DLC, CAN data and FMI number.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message)
+{
+ u32 tempid;
+ peli_receive_message->FF = (CAN1_PELI->FF) >> 7;
+ peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1;
+ peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf;
+
+ if (((FunctionalState)peli_receive_message->FF) != ENABLE) {
+ tempid = (u32)(CAN1_PELI->ID1 >> 5);
+ tempid |= (u32)(CAN1_PELI->ID0 << 3);
+ peli_receive_message->ID = tempid;
+ peli_receive_message->Data[0] = CAN1_PELI->DATA0;
+ peli_receive_message->Data[1] = CAN1_PELI->DATA1;
+ peli_receive_message->Data[2] = CAN1_PELI->DATA2;
+ peli_receive_message->Data[3] = CAN1_PELI->DATA3;
+ peli_receive_message->Data[4] = CAN1_PELI->DATA4;
+ peli_receive_message->Data[5] = CAN1_PELI->DATA5;
+ peli_receive_message->Data[6] = CAN1_PELI->DATA6;
+ peli_receive_message->Data[7] = CAN1_PELI->DATA7;
+ }
+ else {
+ tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3);
+ tempid |= (u32)(CAN1_PELI->DATA0 << 5);
+ tempid |= (u32)(CAN1_PELI->ID1 << 13);
+ tempid |= (u32)(CAN1_PELI->ID0 << 21);
+ peli_receive_message->ID = tempid;
+ peli_receive_message->Data[0] = CAN1_PELI->DATA2;
+ peli_receive_message->Data[1] = CAN1_PELI->DATA3;
+ peli_receive_message->Data[2] = CAN1_PELI->DATA4;
+ peli_receive_message->Data[3] = CAN1_PELI->DATA5;
+ peli_receive_message->Data[4] = CAN1_PELI->DATA6;
+ peli_receive_message->Data[5] = CAN1_PELI->DATA7;
+ peli_receive_message->Data[6] = CAN1_PELI->DATA8;
+ peli_receive_message->Data[7] = CAN1_PELI->DATA9;
+ }
+ CAN_FIFORelease(CAN1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Get available current informatoin in receive FIFO only in Peli
+/// workmode.
+/// @retval The value in reg RMC
+////////////////////////////////////////////////////////////////////////////////
+u32 CAN_Peli_GetRxFIFOInfo(void)
+{
+ return CAN1_PELI->RMC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the CAN's last error code (LEC).
+/// @retval Error code:
+/// - CAN_ERRORCODE_NoErr: No Error
+/// - CAN_ERRORCODE_StuffErr: Stuff Error
+/// - CAN_ERRORCODE_FormErr: Form Error
+/// - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+/// - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+/// - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+/// - CAN_ERRORCODE_CRCErr: CRC Error
+/// - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetLastErrorCode(void)
+{
+ // Return the error code
+ return (u8)CAN1_PELI->ECC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the CAN Receive Error Counter (REC).
+/// @note In case of an error during reception, this counter is incremented
+/// by 1 or by 8 depending on the error condition as defined by the CAN
+/// standard. After every successful reception, the counter is
+/// decremented by 1 or reset to 120 if its value was higher than 128.
+/// When the counter value exceeds 127, the CAN controller enters the
+/// error passive state.
+/// @retval CAN Receive Error Counter.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetReceiveErrorCounter(void)
+{
+ // Return the Receive Error Counter
+ return (u8)(CAN1_PELI->RXERR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the LSB of the 9-bit can Transmit Error Counter(TEC).
+/// @retval LSB of the 8-bit CAN Transmit Error Counter.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetLSBTransmitErrorCounter(void)
+{
+ // Return the LSB of the 8-bit CAN Transmit Error Counter(TEC)
+ return (u8)(CAN1_PELI->TXERR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified CAN interrupts in peli workmode.
+/// @param it: specifies the CAN interrupt sources to be enabled or
+/// disabled.
+/// This parameter can be:
+/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg CAN_IT_TI: Transmit Interrupt
+/// @arg CAN_IT_EI: ERROR Interrupt
+/// @arg CAN_IT_DOI: Data voerflow Interrupt
+/// @arg CAN_IT_WUI: Wakeup Interrupt
+/// @arg CAN_IT_EPI(only Peli): passive error Interrupt
+/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt
+/// @arg CAN_IT_BEI(only Peli): bus error Interrupt
+/// @arg CAN_IT_ALL: use it can enble all Interrupt
+/// @param state: new state of the CAN interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_ITConfig(u32 it, FunctionalState state)
+{
+ (state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified CAN interrupt has occurred or not.
+/// @param it: specifies the CAN interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg CAN_IT_TI: Transmit Interrupt
+/// @arg CAN_IT_EI: ERROR Interrupt
+/// @arg CAN_IT_DOI: Data voerflow Interrupt
+/// @arg CAN_IT_WUI: Wakeup Interrupt
+/// @arg CAN_IT_EPI(only Peli): passive error Interrupt
+/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt
+/// @arg CAN_IT_BEI(only Peli): bus error Interrupt
+/// @arg CAN_IT_ALL: use it can enble all Interrupt
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus CAN_Peli_GetITStatus(u32 it)
+{
+ return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Config CAN_Peli_InitTypeDef baud parameter.
+/// @param CAN_Peli_InitTypeDef: CAN struct.
+/// @param src_clk: CAN module clock.
+/// @param baud: specified baud.
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud)
+{
+ u32 i, value = baud, record = 1;
+ u32 remain = 0, sumPrescaler = 0;
+ while ((baud == 0) || (src_clk == 0))
+ ;
+ sumPrescaler = src_clk / baud;
+ sumPrescaler = sumPrescaler / 2;
+ for (i = 25; i > 3; i--) {
+ remain = sumPrescaler - ((sumPrescaler / i) * i);
+ if (remain == 0) {
+ record = i;
+ break;
+ }
+ else {
+ if (remain < value) {
+ value = remain;
+ record = i;
+ }
+ }
+ }
+ init_struct->SJW = 0;
+ init_struct->BRP = (sumPrescaler / record) - 1;
+ init_struct->TESG2 = (record - 3) / 3;
+ init_struct->TESG1 = (record - 3) - init_struct->TESG2;
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
new file mode 100644
index 00000000..b5555826
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
@@ -0,0 +1,226 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_comp.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_COMP_C_
+
+// Files includes
+#include "hal_comp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup COMP_HAL
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup COMP_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes COMP peripheral registers to their default reset
+/// values.
+/// @param selection: the selected comparator.
+/// select the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_DeInit(COMP_Selection_TypeDef selection)
+{
+ *(vu32*)(COMP_BASE + selection) = 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the COMP peripheral according to the specified
+/// @param selection: the selected comparator.
+/// select the COMP peripheral.
+/// @param init_struct: pointer to an COMP_InitTypeDef structure that
+/// contains the configuration information for the specified COMP
+/// peripheral.
+/// - COMP_InvertingInput specifies the inverting input of COMP
+/// - COMP_NonInvertingInput specifies the non inverting input of COMP
+/// - COMP_Output connect COMP output to selected timer
+/// input (Input capture / Output Compare Reference Clear / Break
+/// Input)
+/// - COMP_BlankingSrce specifies the blanking source of COMP
+/// - COMP_OutputPol select output polarity
+/// - COMP_Hysteresis configures COMP hysteresis value
+/// - COMP_Mode configures COMP power mode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct)
+{
+ *(vu32*)(COMP_BASE + selection) = init_struct->Invert |
+ init_struct->NonInvert |
+ init_struct->Output |
+ init_struct->OutputPol |
+ init_struct->BlankingSrce |
+ init_struct->Hysteresis |
+ init_struct->Mode |
+ init_struct->OFLT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct: pointer to an COMP_InitTypeDef structure which will
+/// be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_StructInit(COMP_InitTypeDef* init_struct)
+{
+
+ init_struct->Invert = COMP_InvertingInput_IO1;
+ init_struct->NonInvert = COMP_NonInvertingInput_IO1;
+ init_struct->Output = COMP_Output_None;
+ init_struct->BlankingSrce = COMP_BlankingSrce_None;
+ init_struct->OutputPol = COMP_NonInverted;
+ init_struct->Hysteresis = COMP_Hysteresis_No;
+ init_struct->Mode = COMP_Mode_UltraLowPower;
+ init_struct->OFLT = COMP_Filter_4_Period; ///< to adjust the speed/consumption.
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable or disable the COMP peripheral.
+/// @param selection: the selected comparator.
+/// select the COMP peripheral.
+/// @param NewState: new state of the COMP peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// When enabled, the comparator compares the non inverting input with
+/// the inverting input and the comparison result is available on
+/// comparator output.
+/// When disabled, the comparator doesn't perform comparison and the
+/// output level is low.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state)
+{
+ (state) ? (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_EN) :
+ (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select CRV param.
+/// @param crv_select: Select source for CRV.
+/// @param crv_level: Set level for CRV.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_SetCrv(u8 crv_select, u8 crv_level)
+{
+ u32 temreg = 0;
+ temreg = COMP->CRV;
+ temreg &= ~COMP_CRV_MASK;
+ // Load config to CRV and enable
+ temreg |= crv_select | crv_level | (1 << 4);
+ COMP->CRV = temreg;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Close or Open the SW1 switch.
+/// @param selection: the selected comparator.
+/// select the COMP peripheral.
+/// @param state: new state of the COMP peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// When enabled, the comparator compares the non inverting input with
+/// the inverting input and the comparison result is available on
+/// comparator output.
+/// When disabled, the comparator doesn't perform comparison and the
+/// output level is low.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state)
+{
+ (state) ?
+ (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_COMPSW1) :
+ (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Return the output level (high or low) of the selected comparator.
+/// The output level depends on the selected polarity.
+/// If the polarity is not inverted:
+/// - Comparator output is low when the non-inverting input is at a
+/// lower voltage than the inverting input
+/// - Comparator output is high when the non-inverting input is at a
+/// higher voltage than the inverting input
+/// If the polarity is inverted:
+/// - Comparator output is high when the non-inverting input is at a
+/// lower voltage than the inverting input
+/// - Comparator output is low when the non-inverting input is at a
+/// higher voltage than the inverting input
+/// @param comp: the selected comparator.
+/// select the COMP peripheral.
+/// @retval The selected comparator output level: low or high.
+////////////////////////////////////////////////////////////////////////////////
+u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection)
+{
+ return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ?
+ COMP_OutputLevel_High :
+ COMP_OutputLevel_Low );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Lock the selected comparator (COMP1/COMP2) configuration.
+/// @param selection: the selected comparator.
+/// select the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_LockConfig(COMP_Selection_TypeDef selection)
+{
+ *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable or disable the COMP register.
+/// @param state: new state of the COMP peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_CrvCmd(FunctionalState state)
+{
+ (state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select comparator external reference voltage.
+/// @param selection: the selected external reference voltage.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_SwitchCrv(u32 crv)
+{
+ COMP->CRV |= crv;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Select comparator external reference voltage source.
+/// @param selection: the selected external reference voltage source.
+/// This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_CrvSrc(u32 src)
+{
+ COMP->CRV |= src;
+}
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
new file mode 100644
index 00000000..817698bf
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
@@ -0,0 +1,108 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_crc.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_CRC_C_
+
+// Files includes
+#include "hal_crc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Resets the CRC Data register (DR).
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CRC_ResetDR()
+{
+ CRC->CR = CRC_CR_RESET;
+}
+//#pragma optimize(0)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Computes the 32-bit CRC of a given data word(32-bit).
+/// @param Data: data word(32-bit) to compute its CRC
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_CalcCRC(u32 data)
+{
+ CRC->DR = data;
+ return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+/// @param buffer: pointer to the buffer containing the data to be computed
+/// @param length: length of the buffer to be computed
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_CalcBlockCRC(u32* buffer, u32 length)
+{
+ u32 i;
+ for (i = 0; i < length; i++) {
+ CRC->DR = buffer[i];
+ }
+ return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the current CRC value.
+/// @param None.
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_GetCRC(void)
+{
+ return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Stores a 8-bit data in the Independent Data(ID) register.
+/// @param id_value: 8-bit value to be stored in the ID register
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CRC_SetIDRegister(u8 id_value)
+{
+ CRC->IDR = id_value;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the 8-bit data stored in the Independent Data(ID) register
+/// @param None.
+/// @retval 8-bit value of the ID register
+////////////////////////////////////////////////////////////////////////////////
+u8 CRC_GetIDRegister()
+{
+ return (CRC->IDR);
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
new file mode 100644
index 00000000..10b26d35
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
@@ -0,0 +1,43 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_crs.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_CRS_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_crs.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRS_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRS_Exported_Functions
+/// @{
+
+/// @}
+
+/// @}
+
+/// @}
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
new file mode 100644
index 00000000..b3583f15
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
@@ -0,0 +1,184 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_dac.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_DAC_C_
+
+// Files includes
+#include "hal_dac.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DAC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DAC_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the DAC peripheral registers to their default reset values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DeInit(void)
+{
+ exRCC_APB1PeriphReset(RCC_APB1ENR_DAC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
+/// @param channel: the selected DAC channel.
+/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified
+/// DAC channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct)
+{
+ DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel);
+ DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) |
+ (u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer))
+ << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each DAC_InitStruct member with its default value.
+/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_StructInit(DAC_InitTypeDef* init_struct)
+{
+ init_struct->DAC_Trigger = DAC_Trigger_None;
+ init_struct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1;
+ init_struct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DAC channel.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the DAC channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+ (state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DAC channel DMA request.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the selected DAC channel DMA request.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+ (state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the selected DAC channel software trigger.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the selected DAC channel software trigger.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+ (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4)))
+ : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables simultaneously the two DAC channels software triggers.
+/// @param state: new state of the DAC channels software triggers.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DualSoftwareTriggerCmd(FunctionalState state)
+{
+ (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2))
+ : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the selected DAC channel wave generation.
+/// @param channel: the selected DAC channel.
+/// @param wave: Specifies the wave type to enable or disable.
+/// @param state: new state of the selected DAC channel wave generation.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state)
+{
+ (state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the specified data holding register value for DAC channel1.
+/// @param alignement: Specifies the data alignement for DAC channel1.
+/// @param data : data to be loaded in the selected data holding register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data)
+{
+ *((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the specified data holding register value for DAC channel2.
+/// @param alignement: Specifies the data alignement for DAC channel2.
+/// @param data : data to be loaded in the selected data holding
+/// register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data)
+{
+ *((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the specified data holding register value for dual channel DAC.
+/// @param alignement: Specifies the data alignement for dual channel DAC.
+/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register.
+/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1)
+{
+ u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1));
+ *((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the last data output value of the selected DAC cahnnel.
+/// @param channel: the selected DAC channel.
+/// @retval The selected DAC channel data output value.
+////////////////////////////////////////////////////////////////////////////////
+u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel)
+{
+ return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2)));
+}
+/// @}
+
+/// @}
+
+/// @}
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
new file mode 100644
index 00000000..b51d1321
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_dbg.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_DBG_C
+
+// Files includes
+#include "types.h"
+#include "hal_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DBG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DBG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DBG peripheral.
+/// @param periph: DBG peripheral.
+/// @param state: new state of the specified DBG peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DBGMCU_Configure(u32 periph, FunctionalState state)
+{
+ (state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph);
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
new file mode 100644
index 00000000..5ec0dc95
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
@@ -0,0 +1,319 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_dma.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+
+// Define to prevent recursive inclusion
+#define _HAL_DMA_C_
+
+// Files includes
+#include "types.h"
+#include "hal_dma.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DMA_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DMA_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the DMA Channeln registers to their default reset
+/// values.
+/// @param select the DMA Channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_DeInit(DMA_Channel_TypeDef* channel)
+{
+ channel->CCR &= ~DMA_CCR_EN;
+ channel->CCR = 0;
+ channel->CNDTR = 0;
+ channel->CPAR = 0;
+ channel->CMAR = 0;
+ if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) {
+ DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+ }
+ else {
+ DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the DMA Channeln according to the specified
+/// parameters in the init_struct.
+/// @param select the DMA Channel.
+/// @param init_struct: pointer to a DMA_InitTypeDef structure that
+/// contains the configuration information for the specified DMA
+/// Channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct)
+{
+ MODIFY_REG(
+ channel->CCR,
+ (DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M),
+ ((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc |
+ (u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize |
+ (u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M));
+
+ MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload);
+ channel->CNDTR = init_struct->DMA_BufferSize;
+ channel->CPAR = init_struct->DMA_PeripheralBaseAddr;
+ channel->CMAR = init_struct->DMA_MemoryBaseAddr;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a DMA_InitTypeDef structure which will
+/// be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_StructInit(DMA_InitTypeDef* init_struct)
+{
+ init_struct->DMA_PeripheralBaseAddr = 0;
+ init_struct->DMA_MemoryBaseAddr = 0;
+ init_struct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ init_struct->DMA_BufferSize = 0;
+ init_struct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ init_struct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ init_struct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ init_struct->DMA_Mode = DMA_Mode_Normal;
+ init_struct->DMA_Priority = DMA_Priority_Low;
+ init_struct->DMA_M2M = DMA_M2M_Disable;
+
+ init_struct->DMA_Auto_reload = DMA_Auto_Reload_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DMA Channeln.
+/// @param channel: select the DMA Channel.
+/// @param state: new state of the DMA Channeln.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state)
+{
+ MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DMA Channeln interrupts.
+/// @param channel: select the DMA Channel.
+/// @param it: specifies the DMA interrupts sources to be enabled
+/// or disabled.
+/// This parameter can be any combination of the following values:
+/// @arg DMA_IT_TC: Transfer complete interrupt mask
+/// @arg DMA_IT_HT: Half transfer interrupt mask
+/// @arg DMA_IT_TE: Transfer error interrupt mask
+/// @param state: new state of the specified DMA interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state)
+{
+ (state) ? (channel->CCR |= it) : (channel->CCR &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the number of data units in the select the DMA Channel .
+/// @param channel: select the DMA Channel
+/// @param DataNumber: The number of data units in the current DMAy Channelx
+/// transfer.
+/// @note This function can only be used when the DMAy_Channelx is disabled.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length)
+{
+ channel->CNDTR = length;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the number of remaining data units in the current
+/// DMA Channeln transfer.
+/// @param channel: select the DMA Channel.
+/// @retval The number of remaining data units in the current DMA Channeln
+/// transfer.
+////////////////////////////////////////////////////////////////////////////////
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel)
+{
+ return channel->CNDTR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified DMA Channeln flag is set or not.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
+/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
+/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
+/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
+/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
+/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval The new state of DMAy_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag)
+{
+ if(flag >= DMA2_FLAG_GL1 ) {
+ return (DMA2->ISR & flag) ? SET : RESET;
+ }
+ return (DMA1->ISR & flag) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the DMA Channeln's pending flags.
+/// @param flag: specifies the flag to clear.
+/// This parameter can be any combination (for the same DMA) of the
+/// following values:
+/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
+/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
+/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
+/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
+/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
+/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ClearFlag(DMA_Flags_TypeDef flag)
+{
+ if(flag >= DMA2_FLAG_GL1 ) {
+ DMA2->IFCR = flag;
+ return ;
+ }
+ DMA1->IFCR = flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified DMA Channeln interrupt has occurred or
+/// not.
+/// @param it: specifies the DMA interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval The new state of DMAy_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it)
+{
+ if(it >= DMA2_IT_GL1 ) {
+ return (DMA2->ISR & it) ? SET : RESET;
+ }
+ return (DMA1->ISR & it) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the DMA Channeln's interrupt pending bits.
+/// @param it: specifies the DMA interrupt pending bit to clear.
+/// This parameter can be any combination (for the same DMA) of the
+/// following values:
+/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it)
+{
+ if(it >= DMA2_IT_GL1 ) {
+ DMA2->IFCR = it;
+ return ;
+ }
+ DMA1->IFCR = it;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the DMA Channeln's Peripheral address.
+/// @param channel : where n can be 1 to 7 for DMA1 to select the DMA Channel.
+/// @param address : DMA Peripheral address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address)
+{
+ channel->CPAR = address;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the DMA Channeln's Peripheral address.
+/// @param channel : select the DMA Channel.
+/// @param length : Transmit lengths.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length)
+{
+ channel->CNDTR = length;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the DMA Channeln's Peripheral address.
+/// @param channel :select the DMA Channel.
+/// @param address : DMA memery address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address)
+{
+ channel->CMAR = address;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the DMA Channeln's interrupt pending bits.
+/// @param it: specifies the DMA interrupt pending bit to clear.
+/// This parameter can be any combination (for the same DMA) of the
+/// following values:
+/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it)
+{
+ if(it >= DMA2_IT_GL1 ) {
+ DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+ DMA2->IFCR = it;
+ return ;
+ }
+ DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+ DMA1->IFCR = it;
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
new file mode 100644
index 00000000..ca662e97
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
@@ -0,0 +1,836 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_eth.c
+/// @author AE TEM
+/// @brief THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+#define _HAL_ETH_C_
+#include "hal_rcc.h"
+#include "hal_eth.h"
+#include "reg_eth.h"
+
+
+void ETH_DeInit(void)
+{
+ RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE);
+}
+
+void ETH_StructInit(ETH_InitTypeDef* ptr)
+{
+ ptr->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ///< PHY Auto-negotiation enabled
+ ptr->ETH_Watchdog = ETH_Watchdog_Enable; ///< MAC watchdog enabled: cuts off long frame
+ ptr->ETH_Jabber = ETH_Jabber_Enable; ///< MAC Jabber enabled in Half-duplex mode
+ ptr->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; ///< Ethernet interframe gap set to 96 bits
+ ptr->ETH_CarrierSense = ETH_CarrierSense_Enable; ///< Carrier Sense Enabled in Half-Duplex mode
+ ptr->ETH_Speed = ETH_Speed_100M; ///< PHY speed configured to 100Mbit/s
+ ptr->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; ///< Receive own Frames in Half-Duplex mode enabled
+ ptr->ETH_LoopbackMode = ETH_LoopbackMode_Disable; ///< MAC MII loopback disabled
+ ptr->ETH_Mode = ETH_Mode_FullDuplex; ///< Full-Duplex mode selected
+ ptr->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled
+ ptr->ETH_RetryTransmission = ETH_RetryTransmission_Enable; ///< Retry Transmission enabled for half-duplex mode
+ ptr->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; ///< Automatic PAD/CRC strip disable
+ ptr->ETH_BackOffLimit = ETH_BackOffLimit_10; ///< half-duplex mode retransmission Backoff time_limit = 10 slot time
+ ptr->ETH_DeferralCheck = ETH_DeferralCheck_Disable; ///< half-duplex mode Deferral check disabled
+ ptr->ETH_ReceiveAll = ETH_ReceiveAll_Disable; ///< Receive all frames disabled
+ ptr->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; ///< Source address filtering (on the optional MAC addresses) disabled
+ ptr->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; ///< Do not forward control frames that do not pass the address filtering
+ ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; ///< Disable reception of Broadcast frames
+ ptr->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; ///< Normal Destination address filtering (not reverse addressing)
+ ptr->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; ///< Promiscuous address filtering mode disabled
+ ptr->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ///< Perfect address filtering for multicast addresses
+ ptr->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; ///< Perfect address filtering for unicast addresses
+ ptr->ETH_HashTableHigh = 0x0; ///< Initialize hash table high and low regs
+ ptr->ETH_HashTableLow = 0x0;
+ ptr->ETH_PauseTime = 0x0; ///< Flow control config (flow control disabled)
+ ptr->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Enable;
+ ptr->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
+ ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+ ptr->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
+ ptr->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
+ ptr->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; ///< VLANtag config (VLAN field not checked)
+ ptr->ETH_VLANTagIdentifier = 0x0;
+
+ ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors
+ ptr->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ///< Store and forward mode enabled for receive
+ ptr->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; ///< Flush received frame that created FIFO overflow
+ ptr->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ///< Store and forward mode enabled for transmit
+ ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled)
+ ptr->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; ///< Disable forwarding frames with errors (short frames, CRC,...)
+ ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames
+ ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled)
+ ptr->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame
+ ptr->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; ///< DMA works on 32-bit aligned start source and destinations addresses
+ ptr->ETH_FixedBurst = ETH_FixedBurst_Enable; ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions
+ ptr->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; ///< DMA transfer max burst length = 32 beats = 32 x 32bits
+ ptr->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
+ ptr->ETH_DescriptorSkipLength = 0x0; ///< DMA Ring mode skip length = 0
+ ptr->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; ///< Equal priority (round-robin) between transmit and receive DMA engines
+}
+
+u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr)
+{
+ u32 hclk = RCC_GetHCLKFreq();
+ u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK;
+ u32 temp_val = 0;
+ hclk = 100000000;
+ ////////////////////////////////////////////////////////////////////////////
+ if (hclk >= 20000000 && hclk < 35000000) {
+ reg |= ETH_MACMIIAR_CR_Div16; ///< HCLK 20 ~ 35 MHz, /16
+ }
+ else if (hclk >= 35000000 && hclk < 60000000) {
+ reg |= ETH_MACMIIAR_CR_Div26; ///< HCLK 35 ~ 60 MHz, /26
+ }
+ else if (hclk >= 60000000 && hclk < 100000000) {
+ reg |= ETH_MACMIIAR_CR_Div42; ///< HCLK 60 ~ 100 MHz, /42
+ }
+ else if (hclk >= 100000000 && hclk < 150000000) {
+ reg |= ETH_MACMIIAR_CR_Div62; ///< HCLK 100 ~ 150 MHz, /62
+ }
+ else {
+ reg |= ETH_MACMIIAR_CR_Div102; ///< HCLK 150 ~ 168 MHz, /102
+ }
+
+ ETH->MACMIIAR = reg;
+
+ ////////////////////////////////////////////////////////////////////////////
+ ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset);
+ if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) {
+ // Wait for linked status
+ while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status));
+ ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation);
+ // Enable Auto-Negitation
+ while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) {
+
+ }
+ // Read the result of the Auto-Negitation
+ temp_val = ETH_ReadPHYRegister(phy_addr, 31);
+
+ if ((temp_val & 0x1C) == 0x4) {
+ ptr->ETH_Speed = ETH_Speed_10M;
+ ptr->ETH_Mode = ETH_Mode_HalfDuplex;
+ SYSCFG->CFGR2 &= ~(1 << 21);
+ }
+ else if((temp_val & 0x1C) == 0x14) {
+ ptr->ETH_Speed = ETH_Speed_10M;
+ ptr->ETH_Mode = ETH_Mode_FullDuplex;
+ SYSCFG->CFGR2 |= 1 << 21;
+ }
+ else if((temp_val & 0x1C) == 0x8) {
+ ptr->ETH_Speed = ETH_Speed_100M;
+ ptr->ETH_Mode = ETH_Mode_HalfDuplex;
+ SYSCFG->CFGR2 &= ~(1 << 21);
+ }
+ else if((temp_val & 0x1C) == 0x18) {
+ ptr->ETH_Speed = ETH_Speed_100M;
+ ptr->ETH_Mode = ETH_Mode_FullDuplex;
+ SYSCFG->CFGR2 |= 1 << 21;
+ }
+ }
+ else {
+ ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) |
+ (u16)(ptr->ETH_Speed >> 1)));
+ if(ptr->ETH_Speed == ETH_Speed_10M) {
+ SYSCFG->CFGR2 &= ~(1 << 21);
+ }
+ else {
+ SYSCFG->CFGR2 |= 1 << 21;
+ }
+ }
+
+ ////////////////////////////////////////////////////////////////////////////
+ ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK | (ptr->ETH_Watchdog |
+ ptr->ETH_Jabber |
+ ptr->ETH_InterFrameGap |
+ ptr->ETH_CarrierSense |
+ ptr->ETH_Speed |
+ ptr->ETH_ReceiveOwn |
+ ptr->ETH_LoopbackMode |
+ ptr->ETH_Mode |
+ ptr->ETH_ChecksumOffload |
+ ptr->ETH_RetryTransmission |
+ ptr->ETH_AutomaticPadCRCStrip |
+ ptr->ETH_DeferralCheck);
+
+ ETH->MACFFR = ptr->ETH_ReceiveAll |
+ ptr->ETH_SourceAddrFilter |
+ ptr->ETH_PassControlFrames |
+ ptr->ETH_BroadcastFramesReception |
+ ptr->ETH_DestinationAddrFilter |
+ ptr->ETH_PromiscuousMode |
+ ptr->ETH_MulticastFramesFilter |
+ ptr->ETH_UnicastFramesFilter;
+
+ ETH->MACHTHR = ptr->ETH_HashTableHigh;
+ ETH->MACHTLR = ptr->ETH_HashTableLow;
+
+ ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) |
+ ptr->ETH_ZeroQuantaPause |
+ ptr->ETH_PauseLowThreshold |
+ ptr->ETH_UnicastPauseFrameDetect |
+ ptr->ETH_ReceiveFlowControl |
+ ptr->ETH_TransmitFlowControl);
+
+ ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier;
+
+ ETH->DMAOMR = 0x00200004;
+ ETH->DMAIER = 0x0001A040;
+ ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats |
+ ptr->ETH_FixedBurst |
+ ptr->ETH_RxDMABurstLength | // !! if 4xPBL is selected for Tx or Rx it is applied for the other
+ ptr->ETH_TxDMABurstLength |
+ ptr->ETH_DescriptorSkipLength << 2 |
+ ptr->ETH_DMAArbitration);// |
+// ETH_DMABMR_USP); // Enable use of separate PBL for Rx and Tx
+
+ return ETH_SUCCESS;
+}
+
+void ETH_Start(void)
+{
+ ETH_MACTransmissionCmd(ENABLE);
+ ETH_MACReceptionCmd(ENABLE);
+ ETH_FlushTransmitFIFO();
+ ETH_DMATransmissionCmd(ENABLE);
+ ETH_DMAReceptionCmd(ENABLE);
+}
+
+void ETH_Stop(void)
+{
+ ETH_DMATransmissionCmd(DISABLE);
+ ETH_DMAReceptionCmd(DISABLE);
+ ETH_MACReceptionCmd(DISABLE);
+ ETH_FlushTransmitFIFO();
+ ETH_MACTransmissionCmd(DISABLE);
+}
+
+void ETH_MACTransmissionCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE);
+}
+
+void ETH_MACReceptionCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE);
+}
+
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+ return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA);
+}
+
+void ETH_InitiatePauseControlFrame(void)
+{
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+void ETH_BackPressureActivationCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA);
+}
+
+void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr)
+{
+ *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) =
+ (u32)mac_addr[5] << 8 |
+ (u32)mac_addr[4];
+
+ *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) =
+ (u32)mac_addr[3] << 24 |
+ (u32)mac_addr[2] << 16 |
+ (u32)mac_addr[1] << 8 |
+ (u32)mac_addr[0];
+}
+
+void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr)
+{
+ mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF;
+ mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF;
+ mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF;
+ mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF;
+ mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF;
+ mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF;
+}
+
+void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta)
+{
+ sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) :
+ ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE);
+}
+
+void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta)
+{
+ sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) :
+ ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA);
+}
+
+void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte)
+{
+ (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC;
+
+ (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte;
+}
+
+FrameTypeDef ETH_Get_Received_Frame(void)
+{
+ FrameTypeDef frame;
+
+ frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
+ frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR;
+ frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
+
+
+ DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+ return frame;
+}
+
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
+{
+ FrameTypeDef frame = {0};
+ __IO u32 desc_cnt = 0;
+
+ while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) {
+ desc_cnt++;
+
+ if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
+ !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+ DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+ DMA_RX_FRAME_infos->cnt = 1;
+ DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+ }
+ else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
+ (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+ DMA_RX_FRAME_infos->cnt++;
+ DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+ }
+ else {
+ DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
+ DMA_RX_FRAME_infos->cnt++;
+
+ if (DMA_RX_FRAME_infos->cnt == 1)
+ DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+
+ frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
+
+ frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ?
+ (DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) :
+ (DMARxDescToGet->BUF1ADDR);
+
+ frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
+
+ DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+ return frame;
+ }
+ }
+
+ return frame;
+}
+
+u32 ETH_Prepare_Transmit_Descriptors(u16 len)
+{
+ u32 cnt = 0, i = 0;
+ __IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet;
+
+ if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN)
+ return ETH_ERROR;
+
+ if(len > ETH_TX_BUF_SIZE) {
+ cnt = len / ETH_TX_BUF_SIZE;
+
+ if (len % ETH_TX_BUF_SIZE)
+ cnt++;
+ }
+ else {
+ cnt = 1;
+ }
+
+ if (cnt == 1) {
+ temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1);
+
+ temp_desc->BL |= ETH_DMA_TDES_FS |
+ ETH_DMA_TDES_LS |
+ (len & ETH_DMA_TDES_TBS1);
+
+ temp_desc->CS |= ETH_DMA_TDES_OWN;
+ temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
+ }
+ else {
+ for (i = 0; i < cnt; i++) {
+ temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS);
+
+ if (i == 0)
+ temp_desc->BL |= ETH_DMA_TDES_FS;
+
+ temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1;
+
+ if (i == (cnt - 1)) {
+ temp_desc->BL &= ~ETH_DMA_TDES_TBS1;
+ temp_desc->BL |= ETH_DMA_TDES_LS |
+ ((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1);
+ }
+
+ temp_desc->CS |= ETH_DMA_TDES_OWN;
+ temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
+ }
+ }
+
+ DMATxDescToSet = temp_desc;
+
+ if (ETH->DMASR & ETH_DMASR_TBUS) {
+ ETH->DMASR = ETH_DMASR_TBUS;
+ ETH->DMATPDR = 0;
+ }
+
+ return ETH_SUCCESS;
+}
+
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
+{
+ u32 i = 0;
+ ETH_DMADESCTypeDef* temp_desc;
+
+ DMARxDescToGet = ptr_desc;
+
+ for (i = 0; i < cnt; i++) {
+ temp_desc = ptr_desc + i;
+ temp_desc->CS = ETH_DMA_RDES_OWN;
+ temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE;
+ temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE];
+
+ if (i < cnt - 1) {
+ temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
+ }
+ else {
+ temp_desc->BUF2NDADDR = (u32)(ptr_desc);
+ }
+ }
+
+ ETH->DMARDLAR = (u32)ptr_desc;
+
+ DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
+}
+
+u32 ETH_CheckFrameReceived(void)
+{
+ if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+ (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+
+ DMA_RX_FRAME_infos->cnt++;
+
+ if (DMA_RX_FRAME_infos->cnt == 1) {
+ DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+ }
+ DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
+ return 1;
+ }
+ else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+ !(DMARxDescToGet->CS & ETH_DMA_RDES_LS) &&
+ (DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
+ DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+ DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0;
+ DMA_RX_FRAME_infos->cnt = 1;
+ }
+ else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+ !(DMARxDescToGet->CS & ETH_DMA_RDES_LS) &&
+ !(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
+ DMA_RX_FRAME_infos->cnt++;
+ DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+ }
+
+ return 0;
+}
+
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
+{
+ u32 i = 0;
+ ETH_DMADESCTypeDef* temp_desc;
+
+ DMATxDescToSet = ptr_desc;
+
+ for (i = 0; i < cnt; i++) {
+ temp_desc = ptr_desc + i;
+ temp_desc->BL = ETH_DMA_TDES_TCH;
+ temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]);
+
+ if (i < cnt - 1) {
+ temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
+ }
+ else {
+ temp_desc->BUF2NDADDR = (u32)(ptr_desc);
+ }
+ }
+
+ ETH->DMATDLAR = (u32)ptr_desc;
+}
+
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
+{
+ return (FlagStatus)(ptr_desc->CS & flag);
+}
+
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc)
+{
+ return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT;
+}
+
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
+{
+ ptr_desc->CS |= ETH_DMA_TDES_OWN;
+}
+
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+ sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC);
+}
+
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
+{
+ ptr_desc->CS |= val;
+}
+
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
+{
+ ptr_desc->CS |= val;
+}
+
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+ sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC);
+}
+
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+ sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH);
+}
+
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+ sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP);
+}
+
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size)
+{
+ ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT);
+}
+
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
+{
+ return (FlagStatus)(ptr_desc->CS & flag);
+}
+
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
+{
+ ptr_desc->CS |= ETH_DMA_RDES_OWN;
+}
+
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc)
+{
+ return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT;
+}
+
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+ sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC);
+}
+
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf)
+{
+ return (buf != ETH_DMA_RDES_Buffer1 ?
+ ((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) :
+ (ptr_desc->BL & ETH_DMA_RDES_RBS1));
+}
+
+u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc)
+{
+ u32 len = 0;
+
+ if ( !(ptr_desc->CS & ETH_DMA_RDES_OWN) &&
+ !(ptr_desc->CS & ETH_DMA_RDES_ES) &&
+ (ptr_desc->CS & ETH_DMA_RDES_LS)) {
+ len = ETH_GetDMARxDescFrameLength(ptr_desc);
+ }
+
+ return len;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+void ETH_SoftwareReset(void)
+{
+ ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+ return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR);
+}
+
+FlagStatus ETH_GetDMAFlagStatus(u32 flag)
+{
+ return (FlagStatus)(ETH->DMASR & flag);
+}
+
+void ETH_DMAClearFlag(u32 flag)
+{
+ ETH->DMASR = flag;
+}
+
+void ETH_DMAITConfig(u32 it, FunctionalState sta)
+{
+ sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it);
+}
+
+ITStatus ETH_GetDMAITStatus(u32 it)
+{
+ return (ITStatus)(ETH->DMASR & it);
+}
+
+void ETH_DMAClearITPendingBit(u32 it)
+{
+ ETH->DMASR = it;
+}
+
+u32 ETH_GetTransmitProcessState(void)
+{
+ return ETH->DMASR & ETH_DMASR_TS;
+}
+
+u32 ETH_GetReceiveProcessState(void)
+{
+ return ETH->DMASR & ETH_DMASR_RS;
+}
+
+void ETH_FlushTransmitFIFO(void)
+{
+ ETH->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+ return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF);
+}
+
+void ETH_DMATransmissionCmd(FunctionalState sta)
+{
+ sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST);
+}
+
+void ETH_DMAReceptionCmd(FunctionalState sta)
+{
+ sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR);
+}
+
+FlagStatus ETH_GetDMAOverflowStatus(u32 val)
+{
+ return (FlagStatus)(ETH->DMAMFBOCR & val);
+}
+
+u32 ETH_GetRxOverflowMissedFrameCounter(void)
+{
+ return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >>
+ ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT;
+}
+
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+ return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC;
+}
+
+u32 ETH_GetCurrentTxDescStartAddress(void)
+{
+ return ETH->DMACHTDR;
+}
+
+u32 ETH_GetCurrentRxDescStartAddress(void)
+{
+ return ETH->DMACHRDR;
+}
+
+u32 ETH_GetCurrentTxBufferAddress(void)
+{
+ return ETH->DMACHTBAR;
+}
+
+u32 ETH_GetCurrentRxBufferAddress(void)
+{
+ return ETH->DMACHRBAR;
+}
+
+void ETH_ResumeDMATransmission(void)
+{
+ ETH->DMATPDR = 0;
+}
+
+void ETH_ResumeDMAReception(void)
+{
+ ETH->DMARPDR = 0;
+}
+
+void ETH_SetReceiveWatchdogTimer(u8 val)
+{
+ ETH->DMARSWTR = val;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+u16 ETH_ReadPHYRegister(u16 addr, u16 reg)
+{
+ u32 dat;
+ // Set phy address and reg address, clear write flag
+ ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
+ (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
+ (reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) &
+ (~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB;
+
+ // Check busy flag
+ while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
+ dat = (u16)ETH->MACMIIDR;
+ if(dat == 0xFFFF) {
+ dat = 0;
+ }
+ return dat;
+}
+
+u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val)
+{
+ // Load data
+ ETH->MACMIIDR = val;
+
+ // Set phy address, reg address and write flag
+ ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
+ (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
+ (reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) |
+ ETH_MACMIIAR_MW |
+ ETH_MACMIIAR_MB;
+
+ // Check busy flag
+ while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
+
+ return ETH->MACMIIDR;
+}
+
+u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta)
+{
+ u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR);
+
+ sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback);
+
+ if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val))
+ return ETH_SUCCESS;
+
+ return ETH_ERROR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+void ETH_SetWakeUpFrameFilterRegister(u32* buf)
+{
+ u32 i = 0;
+
+ for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) {
+ ETH->MACRWUFFR = buf[i];
+ }
+}
+
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU);
+}
+
+FlagStatus ETH_GetPMTFlagStatus(u32 flag)
+{
+ return (FlagStatus)(ETH->MACPMTCSR & flag);
+}
+
+void ETH_WakeUpFrameDetectionCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE);
+}
+
+void ETH_MagicPacketDetectionCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE);
+}
+
+void ETH_PowerDownCmd(FunctionalState sta)
+{
+ sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+void ETH_MMCCounterFullPreset(void)
+{
+ ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
+}
+
+void ETH_MMCCounterHalfPreset(void)
+{
+ ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
+
+ ETH->MMCCR |= ETH_MMCCR_MCP;
+}
+
+void ETH_MMCCounterFreezeCmd(FunctionalState sta)
+{
+ sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF);
+}
+
+void ETH_MMCResetOnReadCmd(FunctionalState sta)
+{
+ sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR);
+}
+
+void ETH_MMCCounterRolloverCmd(FunctionalState sta)
+{
+ sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR);
+}
+
+void ETH_MMCCountersReset(void)
+{
+ ETH->MMCCR |= ETH_MMCCR_CR;
+}
+
+void ETH_MMCITConfig(u32 it, FunctionalState sta)
+{
+ if (it & 0x10000000) {
+ it &= 0xEFFFFFFF;
+
+ sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it);
+ }
+ else {
+ sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it);
+ }
+}
+
+ITStatus ETH_GetMMCITStatus(u32 it)
+{
+ if (it & 0x10000000) {
+ return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it));
+ }
+ else {
+ return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it));
+ }
+}
+
+u32 ETH_GetMMCRegister(u32 reg)
+{
+ return *(vu32*)(ETH_BASE + reg);
+}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
new file mode 100644
index 00000000..409d84d8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
@@ -0,0 +1,222 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_exti.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_EXTI_C_
+
+// Files includes
+#include "hal_exti.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup EXTI_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup EXTI_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the EXTI peripheral registers to their default reset
+/// values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the EXTI registers to their default reset values.
+/// @param None.
+/// @retval None.
+/// @note MEM_MODE bits are not affected by APB reset.
+/// @note MEM_MODE bits took the value from the user option bytes.
+/// @note CFGR2 register is not affected by APB reset.
+/// @note CLABBB configuration bits are locked when set.
+/// @note To unlock the configuration, perform a system reset.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_DeInit(void)
+{
+ u16 i;
+ // Clear all
+ exEXTI_LineDisable(~0x00000000);
+
+ // rc_w1
+ EXTI->PR = EXTI->PR;
+
+ // Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits
+ EXTI->CFGR &= EXTI_CFGR_MEMMODE;
+
+ // Set EXTICRx registers to reset value
+ for (i = 0; i < 4; i++) {
+ EXTI->CR[i] = 0;
+ }
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the GPIO pin used as EXTI Line.
+/// @param port_source_gpio: selects the GPIO port to be used as source for EXTI lines .
+/// @param pin_source: specifies the EXTI line to be configured.
+/// @note This parameter can be pin_source where x can be:
+/// For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source)
+{
+ EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03)));
+ EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the EXTI peripheral according to the specified
+/// parameters in the init_struct.
+/// @param init_struct: pointer to a EXTI_InitTypeDef structure that
+/// contains the configuration information for the EXTI peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_Init(EXTI_InitTypeDef* init_struct)
+{
+ if (init_struct->EXTI_LineCmd != DISABLE) {
+ EXTI->IMR &= ~init_struct->EXTI_Line;
+ EXTI->EMR &= ~init_struct->EXTI_Line;
+ if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
+ EXTI->IMR |= init_struct->EXTI_Line;
+ }
+ else {
+ EXTI->EMR |= init_struct->EXTI_Line;
+ }
+ EXTI->RTSR &= ~init_struct->EXTI_Line;
+ EXTI->FTSR &= ~init_struct->EXTI_Line;
+ if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
+ EXTI->RTSR |= init_struct->EXTI_Line;
+ EXTI->FTSR |= init_struct->EXTI_Line; // Rising and Faling afio
+ }
+ else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) {
+ EXTI->RTSR |= init_struct->EXTI_Line;
+ }
+ else {
+ EXTI->FTSR |= init_struct->EXTI_Line;
+ }
+ }
+ else {
+ if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
+ EXTI->IMR &= ~init_struct->EXTI_Line;
+ }
+ else {
+ EXTI->EMR &= ~init_struct->EXTI_Line;
+ }
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its reset value.
+/// @param init_struct: pointer to a EXTI_InitTypeDef structure which will
+/// be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_StructInit(EXTI_InitTypeDef* init_struct)
+{
+ init_struct->EXTI_Line = EXTI_LineNone;
+ init_struct->EXTI_Mode = EXTI_Mode_Interrupt;
+ init_struct->EXTI_Trigger = EXTI_Trigger_Falling;
+ init_struct->EXTI_LineCmd = DISABLE;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Generates a Software interrupt on selected EXTI line.
+/// @param line: specifies the EXTI line on which the software interrupt
+/// will be generated.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_GenerateSWInterrupt(u32 line)
+{
+ EXTI->SWIER |= line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified EXTI line flag is set or not.
+/// @param line: specifies the EXTI line flag to check.
+/// @retval The new state of line (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus EXTI_GetFlagStatus(u32 line)
+{
+ return (EXTI->PR & line) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the EXTI's line pending flags.
+/// @param line: specifies the EXTI lines flags to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_ClearFlag(u32 line)
+{
+ EXTI->PR = line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified EXTI line is asserted or not.
+/// @param line: specifies the EXTI line to check.
+/// @retval The new state of line (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus EXTI_GetITStatus(u32 line)
+{
+ return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the EXTI's line pending bits.
+/// @param line: specifies the EXTI lines to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_ClearITPendingBit(u32 line)
+{
+ EXTI->PR = line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Line Disable
+/// @param line: specifies the EXTI lines to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exEXTI_LineDisable(u32 line)
+{
+ EXTI->IMR &= ~line;
+ EXTI->EMR &= ~line;
+ EXTI->RTSR &= ~line;
+ EXTI->FTSR &= ~line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the EXTI's line all pending bits.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u32 exEXTI_GetAllFlagStatus(void)
+{
+ return EXTI->PR;
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
new file mode 100644
index 00000000..ecdc8be3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
@@ -0,0 +1,548 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_flash.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_FLASH_C_
+
+// Files includes
+#include "hal_flash.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FLASH_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FLASH_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the code latency value.
+/// @note This function can be used for all MM32 devices.
+/// @param latency: specifies the FLASH Latency value.
+/// This parameter can be one of the following values:
+/// @arg FLASH_Latency_0: FLASH Zero Latency cycle
+/// @arg FLASH_Latency_1: FLASH One Latency cycle
+/// @arg FLASH_Latency_2: FLASH Two Latency cycles
+/// @arg FLASH_Latency_3: FLASH Three Latency cycles
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_SetLatency(FLASH_Latency_TypeDef latency)
+{
+ FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Half cycle flash access.
+/// @note This function can be used for all MM32 devices.
+/// @param half_cycle_access: specifies the FLASH Half cycle Access mode.
+/// This parameter can be one of the following values:
+/// @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+/// @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access)
+{
+ FLASH->ACR &= ~FLASH_ACR_HLFCYA;
+ FLASH->ACR |= half_cycle_access;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Prefetch Buffer.
+/// @note This function can be used for all MM32 devices.
+/// @param prefetch_buffer: specifies the Prefetch buffer status.
+/// This parameter can be one of the following values:
+/// @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+/// @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer)
+{
+ FLASH->ACR &= ~FLASH_ACR_PRFTBE;
+ FLASH->ACR |= prefetch_buffer;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Locks the FLASH Program Erase Controller.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_Lock(void)
+{
+ FLASH->CR |= FLASH_CR_LOCK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Unlocks the FLASH Program Erase Controller.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_Unlock()
+{
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable to program the FLASH Option Byte.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_OPTB_Enable(void)
+{
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Erases a specified FLASH page.
+/// @note This function can be used for all MM32 devices.
+/// @param page_address: The page address to be erased.
+/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
+/// FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ErasePage(u32 page_address)
+{
+ FLASH->CR |= FLASH_CR_PER;
+ FLASH->AR = page_address;
+ FLASH->CR |= FLASH_CR_STRT;
+ return FLASH_WaitForLastOperation(EraseTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Erases all FLASH pages.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EraseAllPages()
+{
+ FLASH->AR = FLASH_BASE;
+ FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT);
+ return FLASH_WaitForLastOperation(EraseTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Erases the FLASH option bytes.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EraseOptionBytes()
+{
+ FLASH_OPTB_Enable();
+ FLASH->AR = OB_BASE;
+ FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT);
+ return FLASH_WaitForLastOperation(EraseTimeout);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs a half word at a specified address.
+/// @note This function can be used for all MM32 devices.
+/// @param address: specifies the address to be programmed.
+/// @param data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data)
+{
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(vu16*)address = data;
+
+
+ return FLASH_WaitForLastOperation(ProgramTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs a word at a specified address.
+/// @note This function can be used for all MM32 devices.
+/// @param address: specifies the address to be programmed.
+/// @param data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramWord(u32 address, u32 data)
+{
+ FLASH_Status ret = FLASH_ProgramHalfWord(address, data);
+ if (ret == FLASH_COMPLETE) {
+ ret = FLASH_ProgramHalfWord(address + 2, data >> 16);
+ }
+ return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs a byte at a specified Option Byte Data address.
+/// @note This function can be used for all MM32 devices.
+/// @param address: specifies the address to be programmed.
+/// This parameter can be 0x1FFFF804 or 0x1FFFF806.
+/// @param data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data)
+{
+ FLASH_Status ret;
+ __IO u16 temp;
+ FLASH_OPTB_Enable();
+ FLASH->CR |= FLASH_CR_OPTPG;
+ temp = (u16)(~data);
+ temp = (temp << 8) & 0xFF00;
+ temp = temp | (u16)data;
+ address = address & (~0x1);
+ *(vu16*)address = temp;
+ ret = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs a half word at a specified Option Byte Data address.
+/// @note This function can be used for all MM32 devices.
+/// @param address: specifies the address to be programmed.
+/// This parameter can be 0x1FFFF804 or 0x1FFFF806.
+/// @param data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data)
+{
+ FLASH_Status ret;
+ FLASH_OPTB_Enable();
+ FLASH->CR |= FLASH_CR_OPTPG;
+ *(vu16*)address = data;
+ ret = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Read protection for the specified address
+/// @note This function can be used for all MM32 devices.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramProtect(u32 address, u16 data)
+{
+ return FLASH_ProgramOptionHalfWord(address, data);
+
+// FLASH_Status ret;
+// ret = FLASH_ProgramOptionHalfWord(address, 0x7F80);
+//
+// if (ret == FLASH_COMPLETE) {
+// ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00);
+// }
+// return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Write protection for the specified address
+/// @note This function can be used for all MM32 devices.
+/// @param page: specifies the address of the pages to be write
+/// protected.
+/// This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000))
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EnableWriteProtection(u32 page)
+{
+ FLASH_Status ret;
+ u8 i;
+ for (i = 0; i < 4; i++) {
+ ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8)));
+ if (ret != FLASH_COMPLETE) {
+ break;
+ }
+ }
+ return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+/// @note This function can be used for all MM32 devices.
+/// @param ob_iwdg: Selects the IWDG mode
+/// @param ob_stop: Reset event when entering STOP mode.
+/// @param standby: Reset event when entering Standby mode.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby)
+{
+ FLASH_OPTB_Enable();
+ FLASH->CR |= FLASH_CR_OPTPG;
+ OB->USER = ob_iwdg;
+ OB->USER |= ob_stop;
+ OB->USER |= standby;
+ OB->USER |= 0xF8;
+ // OB->USER = iwdg | stop | stdby | 0xF8;
+ return FLASH_WaitForLastOperation(ProgramTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the FLASH User Option Bytes values.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+/// and RST_STDBY(Bit2).
+////////////////////////////////////////////////////////////////////////////////
+u32 FLASH_GetUserOptionByte()
+{
+ return (FLASH->OBR >> 2);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the FLASH Write Protection Option Bytes Register value.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval The FLASH Write Protection Option Bytes Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 FLASH_GetWriteProtectionOptionByte()
+{
+ return (FLASH->WRPR);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval FLASH Prefetch Buffer Status (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+ return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified FLASH interrupts.
+/// @note This function can be used for all MM32 devices.
+/// @param interrupt: specifies the FLASH interrupt sources to be enabled or
+/// disabled.
+/// @param state: new state of the specified Flash interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state)
+{
+ (state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified FLASH flag is set or not.
+/// @note This function can be used for all MM32 devices.
+/// @param flag: specifies the FLASH flags to clear.
+/// This parameter can be one of the following values:
+/// @arg FLASH_FLAG_BSY: FLASH Busy flag
+/// @arg FLASH_FLAG_PGERR: FLASH Program error flag
+/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+/// @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
+/// @retval The new state of FLASH_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus FLASH_GetFlagStatus(u16 flag)
+{
+ return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the FLASH's pending flags.
+/// @note This function can be used for all MM32 devices.
+/// @param flag: specifies the FLASH flags to clear.
+/// This parameter can be any combination of the following values:
+/// @arg FLASH_FLAG_PGERR: FLASH Program error flag
+/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_ClearFlag(u16 flag)
+{
+ FLASH->SR = flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the FLASH Status.
+/// @note This function can be used for all MM32 devices.
+/// @param None.
+/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
+/// FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_GetStatus()
+{
+ return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY))
+ ? FLASH_BUSY
+ : ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG
+ : ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+/// @note This function can be used for all MM32 devices
+/// @param time_out: FLASH programming time_out
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_WaitForLastOperation(u32 time_out)
+{
+ u32 i;
+ FLASH_Status ret;
+ do {
+ ret = FLASH_GetStatus();
+ time_out--;
+ for (i = 0xFF; i != 0; i--)
+ ;
+ } while ((ret == FLASH_BUSY) && (time_out != 0x00));
+
+ FLASH->CR = 0;
+ FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR;
+ return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Erases a specified FLASH page.
+/// @note This function can be used for all MM32 devices.
+/// @param Page_Address: The page address to be erased.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_EraseEE(u32 page_address)
+{
+ FLASH_Unlock();
+ FLASH_ErasePage(page_address);
+ FLASH_Lock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs a buffer at a specified address.
+/// @note This function can be used for all MM32 devices.
+/// @param *buf: the pointer of the buffer to be programmed.
+/// @param addr: specifies the address to be programmed.
+/// @param len: the number of bytes in the buffer.
+/// This parameter can only be even.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len)
+{
+ u16 i;
+ FLASH_Unlock();
+ for (i = 0; i < len / 2; i++) {
+ FLASH_ProgramHalfWord(addr, *buf);
+ addr += 2;
+ buf++;
+ }
+ FLASH_Lock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Determine if the data that at the ptr address with the length is len
+/// is empty.
+/// @note This function can be used for all MM32 devices.
+/// @param *ptr: the pointer of the starting address.
+/// @param len: the number of bytes.
+/// This parameter can only be even.
+/// @retval 1 presents the data is empty,
+/// 0 presents the data has been written.
+////////////////////////////////////////////////////////////////////////////////
+u8 exFLASH_FindEmpty(u16* ptr, u16 len)
+{
+ u16 i;
+ for (i = 0; i < (len / 2); i++) {
+ if (*(ptr + i) != 0xffff)
+ return 0;
+ }
+ return 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Locate the writable area on the specified address.
+/// @note This function can be used for all MM32 devices.
+/// @param page_address: specifies the beginning of the EEprom.
+/// The EEprom can be some continuously pages in the flash.
+/// @param len: the number of bytes to be written.
+/// This parameter can only be even.
+/// @retval the pointer of the starting address.
+////////////////////////////////////////////////////////////////////////////////
+void* exFLASH_Locate(u32 page_address, u16 len)
+{
+ u16 i;
+ u16* ptr = (u16*)page_address;
+ for (i = 0; i < (0x0800 / len); i++) {
+ if (exFLASH_FindEmpty(ptr, len)) {
+ if (i == 0)
+ return 0;
+ break;
+ }
+ ptr += len / 2;
+ }
+ return ptr;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Programs a buffer at a specified address.
+/// @note This function can be used for all MM32 devices.
+/// @param *buf: the pointer of the buffer to be programmed.
+/// @param page_address: specifies the beginning of the EEprom.
+/// The EEprom can be some continuously pages in the flash.
+/// @param len: the number of bytes in the buffer.
+/// This parameter can only be even.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len)
+{
+ u16* ptr = exFLASH_Locate(page_address, len);
+ if (ptr == 0) {
+ exFLASH_EraseEE(page_address + 0x000);
+ exFLASH_EraseEE(page_address + 0x400);
+ exFLASH_ProgramEE(buf, page_address, len);
+ }
+ else {
+ if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) {
+ exFLASH_EraseEE(page_address + 0x400);
+ exFLASH_ProgramEE(buf, (u32)ptr, len);
+ }
+ else if (ptr == (u16*)(page_address + 0x0800)) {
+ exFLASH_EraseEE(page_address + 0x000);
+ exFLASH_ProgramEE(buf, (u32)page_address, len);
+ }
+ else {
+ exFLASH_ProgramEE(buf, (u32)ptr, len);
+ }
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Read the beginning address of the last written data.
+/// @note This function can be used for all MM32 devices.
+/// @param page_address: specifies the beginning of the EEprom.
+/// The EEprom can be some continuously pages in the flash.
+/// @param len: the number of bytes have been written.
+/// This parameter can only be even.
+/// @retval the beginning address of the last written data.
+/// 0 presents that this is the first time to use this as EEprom.
+////////////////////////////////////////////////////////////////////////////////
+void* exFLASH_ReadEE(u32 page_address, u16 len)
+{
+ u16* ptr = exFLASH_Locate(page_address, len);
+ return (ptr == 0) ? 0 : (ptr - len / 2);
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
new file mode 100644
index 00000000..b4b665a0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
@@ -0,0 +1,124 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_fsmc.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS.
+/// Interface with SRAM, PSRAM, NOR memories
+/// Interrupts and flags management
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_FSMC_C_
+
+// Files includes
+#include "reg_rcc.h"
+#include "reg_syscfg.h"
+#include "hal_fsmc.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FSMC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FSMC_Exported_Functions
+/// @{
+
+
+void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct)
+{
+ init_struct->FSMC_Mode = FSMC_Mode_NorFlash;
+ init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX;
+
+ init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0;
+ init_struct->FSMC_MemSize = FSMC_MemSize_64MB;
+ init_struct->FSMC_MemType = FSMC_MemType_NorSRAM;
+}
+void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct)
+{
+
+ init_struct->FSMC_SMReadPipe = 0;
+ init_struct->FSMC_ReadyMode = 0;
+ init_struct->FSMC_WritePeriod = 0x2;
+ init_struct->FSMC_WriteHoldTime = 1;
+ init_struct->FSMC_AddrSetTime = 3;
+ init_struct->FSMC_ReadPeriod = 0x1;
+ init_struct->FSMC_DataWidth = FSMC_DataWidth_16bits;
+}
+void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct)
+{
+ SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN);
+ SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \
+ (u32)init_struct->FSMC_AddrDataMode;
+
+ FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \
+ (u32)init_struct->FSMC_MemSize | \
+ (u32)init_struct->FSMC_MemType;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initialize the FSMC_NORSRAM Timing according to the specified
+/// parameters in the FSMC_NORSRAM_TimingTypeDef
+/// @param FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure
+/// @param Bank: NORSRAM bank number
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank)
+{
+ // Set FSMC_NORSRAM device timing parameters
+ if(bank == FSMC_NORSRAM_BANK0) {
+ FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+ FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0;
+ FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos;
+ }
+ else if(bank == FSMC_NORSRAM_BANK1) {
+ FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+ FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1;
+ FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos;
+ }
+ else if(bank == FSMC_NORSRAM_BANK2) {
+ FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
+ (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+ FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2;
+ FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos;
+ }
+}
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
new file mode 100644
index 00000000..4363338f
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
@@ -0,0 +1,344 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_gpio.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_GPIO_C_
+
+// Files includes
+#include "reg_exti.h"
+#include "hal_rcc.h"
+#include "hal_gpio.h"
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup GPIO_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup GPIO_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the gpio peripheral registers to their default reset
+/// values.
+/// @param gpio: select the GPIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_DeInit(GPIO_TypeDef* gpio)
+{
+ switch (*(vu32*)&gpio) {
+ case (u32)GPIOA:
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE);
+ break;
+ case (u32)GPIOB:
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE);
+ break;
+ case (u32)GPIOC:
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE);
+ break;
+ case (u32)GPIOD:
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE);
+ break;
+ case (u32)GPIOE:
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the Alternate Functions (remap, event control
+/// and EXTI configuration) registers to their default reset values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_AFIODeInit()
+{
+ GPIOA->AFRL = 0xFFFFFFFF;
+ GPIOA->AFRH = 0xF00FFFFF; // PA14:SWCLK, PA13:PSWDIO
+ GPIOB->AFRL = 0xFFFFFFFF;
+ GPIOB->AFRH = 0xFFFFFFFF;
+ GPIOC->AFRL = 0xFFFFFFFF;
+ GPIOC->AFRH = 0xFFFFFFFF;
+ GPIOD->AFRL = 0xFFFFFFFF;
+ GPIOD->AFRH = 0xFFFFFFFF;
+ GPIOE->AFRL = 0xFFFFFFFF;
+ GPIOE->AFRH = 0xFFFFFFFF;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the gpio peripheral according to the specified
+/// parameters in the init_struct.
+/// @param gpio: select the GPIO peripheral.
+/// @param init_struct: pointer to a GPIO_InitTypeDef structure that
+/// contains the configuration information for the specified GPIO
+/// peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct)
+{
+ u8 idx;
+ u8 i;
+ u32 tmp;
+ __IO u32* reg ;
+
+ // 1x
+ u32 dat = init_struct->GPIO_Mode & 0x0F;
+ if (init_struct->GPIO_Mode & 0x10)
+ dat |= init_struct->GPIO_Speed;
+
+ // 0x
+ reg = &gpio->CRL;
+ for (i = 0; i < 8; i++) {
+ idx = i * 4;
+ if ((init_struct->GPIO_Pin) & (1 << i)) {
+ *reg = (*reg & ~(0xF << idx)) | (dat << idx);
+ }
+ }
+
+ reg = &gpio->CRH;
+ tmp = init_struct->GPIO_Pin >> 8;
+ for (i = 0; i < 8; i++) {
+ idx = i * 4;
+ if (tmp & (1 << i)) {
+ *reg = (*reg & ~(0xF << idx)) | (dat << idx);
+ }
+ }
+
+ // 2x,4x
+ if (init_struct->GPIO_Mode == GPIO_Mode_IPD)
+ gpio->BRR |= init_struct->GPIO_Pin;
+ else if (init_struct->GPIO_Mode == GPIO_Mode_IPU)
+ gpio->BSRR |= init_struct->GPIO_Pin;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a GPIO_InitTypeDef structure
+/// which will be initialized.
+/// @retval : None
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_StructInit(GPIO_InitTypeDef* init_struct)
+{
+ // Reset GPIO init structure parameters values
+ init_struct->GPIO_Pin = GPIO_Pin_All;
+ init_struct->GPIO_Speed = GPIO_Speed_2MHz;
+ init_struct->GPIO_Mode = GPIO_Mode_FLOATING;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads the input data of specified GPIO port pin.
+/// @param gpio: select the GPIO peripheral.
+/// @param pin: specifies the port pin to be read.
+/// This parameter can be GPIO_Pin_x where x can be (0..15).
+/// @retval The input port pin value.
+////////////////////////////////////////////////////////////////////////////////
+bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin)
+{
+ return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads all GPIO port pins input data.
+/// @param gpio: select the GPIO peripheral.
+/// @retval GPIO port input data value.
+////////////////////////////////////////////////////////////////////////////////
+u16 GPIO_ReadInputData(GPIO_TypeDef* gpio)
+{
+ return gpio->IDR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads the output data of specified GPIO port pin.
+/// @param gpio: select the GPIO peripheral.
+/// @param pin: specifies the port bit to be read.
+/// This parameter can be GPIO_Pin_x where x can be (0..15).
+/// @retval The output port pin value.
+////////////////////////////////////////////////////////////////////////////////
+bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin)
+{
+ return (gpio->ODR & pin) ? Bit_SET : Bit_RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads all GPIO port pins output data.
+/// @param gpio: select the GPIO peripheral.
+/// @retval GPIO port output data value.
+////////////////////////////////////////////////////////////////////////////////
+u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio)
+{
+ return gpio->ODR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the selected GPIO port pin.
+/// @param gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param pin: specifies the port pins to be written.
+/// This parameter can be any combination of GPIO_Pin_x where x can be
+/// (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin)
+{
+ gpio->BSRR = pin;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the selected GPIO port bit.
+/// @param gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param pin: specifies the port pins to be written.
+/// This parameter can be any combination of GPIO_Pin_x where x can be
+/// (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin)
+{
+ gpio->BRR = pin;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets or clears the selected GPIO port pin.
+/// @param gpio: select the GPIO peripheral.
+/// @param pin: specifies the port bit to be written.
+/// This parameter can be one of GPIO_Pin_x where x can be (0..15).
+/// @param value: specifies the value to be written to the selected bit.
+/// This parameter can be one of the BitAction enum values:
+/// @arg Bit_RESET: to clear the port pin
+/// @arg Bit_SET: to set the port pin
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value)
+{
+ (value) ? (gpio->BSRR = pin) : (gpio->BRR = pin);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Writes data to all GPIO port pins.
+/// @param gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param value: specifies the value to be written to the port output data
+/// register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_Write(GPIO_TypeDef* gpio, u16 value)
+{
+ gpio->ODR = value;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Locks GPIO Pins configuration.
+/// @param gpio: to select the GPIO peripheral.
+/// @param pin: specifies the port bit to be written.
+/// This parameter can be any combination of GPIO_Pin_x where x can be
+/// (0..15).
+/// @param state: new lock state of the port pin.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state)
+{
+ (state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Locks GPIO Pins configuration registers until next system reset.
+/// @param gpio: to select the GPIO peripheral.
+/// @param pin: specifies the port bit to be written.
+/// This parameter can be any combination of GPIO_Pin_x where x can be
+/// (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin)
+{
+ gpio->LCKR = GPIO_LCKR_LCKK | pin;
+ gpio->LCKR = pin;
+ gpio->LCKR = GPIO_LCKR_LCKK | pin;
+ gpio->LCKR;
+ gpio->LCKR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the port pin remapping.
+/// @param remap: selects the pin to remap.
+/// @param mask: the corresponding remapping mask of the remapping pin.
+/// @param state: new state of the port pin remapping.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Writes data to the specified GPIO data port.
+/// @param gpio: select the GPIO peripheral.
+/// @param pin: specifies the pin for the Alternate function.
+/// This parameter can be GPIO_PinSourcex where x can be (0..15) for
+/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
+/// @param alternate_function: selects the pin to used as Alternate function.
+/// This parameter can be the GPIO_AF_x where x can be (0..7).
+/// @note The pin should be used for Digital IP.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function)
+{
+ u8 shift = (pin & 0x07) * 4;
+ u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
+ *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the remap function and AF function of the GPIO pin.
+/// @param gpio:select the GPIO peripheral.
+/// @param pin: specifies the pin for the Alternate function.
+/// This parameter can be GPIO_Pin_x where x can be (0..15) for
+/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
+/// @param remap: selects the pin to remap.
+/// @param alternate_function: selects the pin to used as Alternate function.
+/// This parameter can be the GPIO_AF_x where x can be (0..7).
+/// @note The pin should be used for Digital IP.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function)
+{
+ u8 i;
+ u8 shift;
+ u32* ptr;
+
+ if (alternate_function >= 0) {
+ for (i = 0; i < 32; i++) {
+ if (pin & 0x01) {
+ pin = i;
+ break;
+ }
+ pin >>= 1;
+ }
+
+ shift = (pin & 0x07) * 4;
+ ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
+ *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
+ }
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
new file mode 100644
index 00000000..855236a6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
@@ -0,0 +1,526 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_i2c.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_I2C_C_
+
+// Files includes
+#include "hal_i2c.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup I2C_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup I2C_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the i2c peripheral registers to their default
+/// reset values.
+/// @param i2c: where n can be 1 or 2 to select the I2C peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DeInit(I2C_TypeDef* i2c)
+{
+ switch (*(vu32*)&i2c) {
+ case (u32)I2C1: // I2C1_BASE:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1);
+ break;
+ case (u32)I2C2: // I2C2_BASE:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the i2c peripheral according to the specified
+/// parameters in the init_struct.
+/// @param i2c: select the I2C peripheral.
+/// @param init_struct: pointer to a I2C_InitTypeDef structure that
+/// contains the configuration information for the specified
+/// I2C peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct)
+{
+ u32 pclk1 = HSI_VALUE;
+ u32 minSclLowTime = 0;
+ u32 i2cPeriod = 0;
+ u32 pclk1Period = 0;
+
+
+ i2c->IC_ENABLE &= ~I2C_ENR_ENABLE;
+
+
+ pclk1 = RCC_GetPCLK1Freq();
+ pclk1Period = 1000000000 / pclk1;
+ i2cPeriod = 1000000000 / init_struct->I2C_ClockSpeed;
+
+ minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ;
+ i2cPeriod = 82 / pclk1Period;
+
+ if (init_struct->I2C_ClockSpeed <= 100000) {
+ i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2;
+ i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT);
+ }
+ else {
+ i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4;
+ i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod);
+ }
+
+ i2c->IC_CON &= ~(I2C_CR_EMPINT | \
+ I2C_CR_SLAVEDIS | \
+ I2C_CR_REPEN | \
+ I2C_CR_MASTER10 | \
+ I2C_CR_SLAVE10 | \
+ I2C_CR_FAST | \
+ I2C_CR_MASTER);
+
+ i2c->IC_CON = I2C_CR_EMPINT | \
+ I2C_CR_REPEN | \
+ ((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \
+ ((init_struct->I2C_Mode) ? I2C_CR_MASTER : 0x00);
+ i2c->IC_INTR_MASK &= INTR_MASK;
+
+ i2c->IC_RX_TL = 0x00;
+ i2c->IC_TX_TL = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct: pointer to an I2C_InitTypeDef structure
+/// which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_StructInit(I2C_InitTypeDef* init_struct)
+{
+ init_struct->I2C_Mode = I2C_CR_MASTER;
+ init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS;
+ init_struct->I2C_Speed = I2C_CR_STD;
+ init_struct->I2C_ClockSpeed = 100000;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified I2C peripheral.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the i2c peripheral. This parameter
+/// can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+ (state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified I2C DMA requests.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the I2C DMA transfer.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+ if (state) {
+ if (I2C_DMA_DIR == TDMAE_SET)
+ i2c->IC_DMA_CR |= TDMAE_SET;
+
+ else
+ i2c->IC_DMA_CR |= RDMAE_SET;
+ }
+ else
+ i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Generates i2c communication START condition.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the I2C START condition generation.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state)
+{
+ (state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Generates i2c communication STOP condition.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the I2C STOP condition generation.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state)
+{
+ u16 overTime = 3000;
+
+ i2c->IC_ENABLE |= I2C_ENR_ABORT;
+
+ while (i2c->IC_ENABLE & I2C_ENR_ABORT) {
+ if (overTime-- == 0)
+ break;
+ }
+ i2c->IC_CLR_TX_ABRT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the specified I2C own address2.
+/// @param i2c: select the I2C peripheral.
+/// @param addr: specifies the 7bit I2C own address2.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr)
+{
+ MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified I2C dual addressing mode.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the I2C dual addressing mode.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+ (state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified I2C general call feature.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the I2C General call.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+ (state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified I2C interrupts.
+/// @param i2c: select the I2C peripheral.
+/// @param it: specifies the I2C interrupts sources to be enabled
+/// or disabled.
+/// This parameter can be any combination of the following values:
+/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt mask
+/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask
+/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask
+/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask
+/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask
+/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask
+/// @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode)
+/// @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode)
+/// @arg I2C_IT_ACTIVITY : I2C activity interrupt mask
+/// @arg I2C_IT_STOP_DET : stop condition interrupt mask
+/// @arg I2C_IT_START_DET : start condition interrupt mask
+/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask
+/// @param state: new state of the specified I2C interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state)
+{
+ if (it == I2C_IT_RX_FULL)
+ I2C_ReadCmd(i2c);
+ (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sends a data byte through the i2c peripheral.
+/// @param i2c: select the I2C peripheral.
+/// @param dat: Byte to be transmitted..
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendData(I2C_TypeDef* i2c, u8 dat)
+{
+ i2c->IC_DATA_CMD = dat;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the most recent received data by the i2c peripheral.
+/// @param i2c: select the I2C peripheral.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ReadCmd(I2C_TypeDef* i2c)
+{
+ i2c->IC_DATA_CMD = I2C_DR_CMD;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the most recent received data by the i2c peripheral.
+/// @param i2c: select the I2C peripheral.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+u8 I2C_ReceiveData(I2C_TypeDef* i2c)
+{
+ I2C_CMD_DIR = 0;
+ return (u8)i2c->IC_DATA_CMD;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Transmits the address byte to select the slave device.
+/// @param i2c: select the I2C peripheral.
+/// @param addr: specifies the slave address which will be transmitted
+/// @param dir: specifies whether the I2C device will be a
+/// Transmitter or a Receiver.
+/// This parameter can be one of the following values
+/// @arg I2C_Direction_Transmitter: Transmitter mode
+/// @arg I2C_Direction_Receiver: Receiver mode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir)
+{
+ i2c->IC_TAR = addr >> 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads the specified I2C register and returns its value.
+/// @param i2c: select the I2C peripheral.
+/// @param reg: specifies the register to read.
+/// This parameter can be one of the following values:
+/// @retval The value of the read register.
+////////////////////////////////////////////////////////////////////////////////
+u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg)
+{
+ return (*(vu16*)(*((u32*)&i2c) + reg));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the last i2c Event.
+/// @param i2c: select the I2C peripheral.
+/// @retval The last event
+////////////////////////////////////////////////////////////////////////////////
+u32 I2C_GetLastEvent(I2C_TypeDef* i2c)
+{
+ return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the last i2c Event is equal to the one passed
+/// as parameter.
+/// @param i2c: select the I2C peripheral.
+/// @param event: specifies the event to be checked.
+/// This parameter can be one of the following values:
+/// @arg I2C_EVENT_RX_UNDER : Rx Buffer is empty event
+/// @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event
+/// @arg I2C_EVENTT_RX_FULL : Rx buffer full event
+/// @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event
+/// @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event
+/// @arg I2C_EVENT_RD_REQ : I2C work as slave or master event
+/// @arg I2C_EVENT_TX_ABRT : TX error event(Master mode)
+/// @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode)
+/// @arg I2C_EVENT_ACTIVITY : I2C activity event
+/// @arg I2C_EVENT_STOP_DET : stop condition event
+/// @arg I2C_EVENT_START_DET: start condition event
+/// @arg I2C_EVENT_GEN_CALL : a general call address and ack event
+/// - SUCCESS: Last event is equal to the I2C_EVENT
+/// - ERROR: Last event is different from the I2C_EVENT
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event)
+{
+ if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) {
+ i2c->IC_DATA_CMD = I2C_DR_CMD;
+ I2C_CMD_DIR = 1;
+ }
+
+ return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified I2C flag is set or not.
+/// @param i2c: select the I2C peripheral.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
+/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag
+/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag
+/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
+/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
+/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
+/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
+/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
+/// @arg I2C_FLAG_ACTIVITY : I2C activity flag
+/// @arg I2C_FLAG_STOP_DET : stop condition flag
+/// @arg I2C_FLAG_START_DET: start condition flag
+/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
+/// @retval The new state of I2C_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag)
+{
+ if (flag & 0x8000)
+ return ((i2c->IC_STATUS & flag) ? SET : RESET);
+
+ if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) {
+ i2c->IC_DATA_CMD = I2C_DR_CMD;
+ I2C_CMD_DIR = 1;
+ }
+ return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the i2c's pending flags.
+/// @param i2c: select the I2C peripheral.
+/// @param flag: specifies the flag to clear.
+/// This parameter can be any combination of the following values:
+/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
+/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag
+/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag
+/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
+/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
+/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
+/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
+/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
+/// @arg I2C_FLAG_ACTIVITY : I2C activity flag
+/// @arg I2C_FLAG_STOP_DET : stop condition flag
+/// @arg I2C_FLAG_START_DET: start condition flag
+/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag)
+{
+ if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER)
+ i2c->IC_CLR_RX_UNDER;
+ if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER)
+ i2c->IC_CLR_RX_OVER;
+ if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER)
+ i2c->IC_CLR_TX_OVER;
+ if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ)
+ i2c->IC_CLR_RD_REQ;
+ if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT)
+ i2c->IC_CLR_TX_ABRT;
+ if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE)
+ i2c->IC_CLR_RX_DONE;
+ if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY)
+ i2c->IC_CLR_ACTIVITY;
+ if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET)
+ i2c->IC_CLR_STOP_DET;
+ if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET)
+ i2c->IC_CLR_START_DET;
+ if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL)
+ i2c->IC_CLR_GEN_CALL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified I2C interrupt has occurred or not.
+/// @param i2c: select the I2C peripheral.
+/// @param it: specifies the interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
+/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
+/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt
+/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
+/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
+/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
+/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
+/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
+/// @arg I2C_IT_ACTIVITY : I2C activity interrupt
+/// @arg I2C_IT_STOP_DET : stop condition interrupt
+/// @arg I2C_IT_START_DET: start condition interrupt
+/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
+/// @retval The new state of I2C_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it)
+{
+ return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the i2c interrupt pending bits.
+/// @param i2c: select the I2C peripheral.
+/// @param it: specifies the interrupt pending bit to clear.
+/// This parameter can be any combination of the following values:
+/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
+/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
+/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt
+/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
+/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
+/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
+/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
+/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
+/// @arg I2C_IT_ACTIVITY : I2C activity interrupt
+/// @arg I2C_IT_STOP_DET : stop condition interrupt
+/// @arg I2C_IT_START_DET: start condition interrupt
+/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it)
+{
+ if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER)
+ i2c->IC_CLR_RX_UNDER;
+ if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER)
+ i2c->IC_CLR_RX_OVER;
+ if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER)
+ i2c->IC_CLR_TX_OVER;
+ if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ)
+ i2c->IC_CLR_RD_REQ;
+ if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT)
+ i2c->IC_CLR_TX_ABRT;
+ if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE)
+ i2c->IC_CLR_RX_DONE;
+ if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY)
+ i2c->IC_CLR_ACTIVITY;
+ if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET)
+ i2c->IC_CLR_STOP_DET;
+ if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET)
+ i2c->IC_CLR_START_DET;
+ if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL)
+ i2c->IC_CLR_GEN_CALL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// New Function Interface
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures slave address.
+/// @param i2c: select the I2C peripheral.
+/// @param addr: specifies the slave address which will be transmitted
+/// This parameter can be one of the following values
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr)
+{
+ WRITE_REG(i2c->IC_SAR, addr >> 1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the I2C slave mode.
+/// @param i2c: select the I2C peripheral.
+/// @param state: new state of the specified I2C interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state)
+{
+ (state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS);
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
new file mode 100644
index 00000000..06b49fb2
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
@@ -0,0 +1,208 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_iwdg.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_IWDG_C_
+
+// Files includes
+#include "hal_iwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup IWDG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup IWDG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables write access to IWDG_PR and IWDG_RLR
+/// registers.
+/// @param write_access: new state of write access to IWDG_PR and
+/// IWDG_RLR registers.
+/// This parameter can be one of the following values:
+/// @arg IWDG_WriteAccess_Enable: Enable write access to
+/// IWDG_PR and IWDG_RLR registers
+/// @arg IWDG_WriteAccess_Disable: Disable write access to
+/// IWDG_PR and IWDG_RLR registers
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_WriteAccessCmd(u16 write_access)
+{
+ IWDG->KR = write_access;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets IWDG Prescaler value.
+/// @param prescaler: specifies the IWDG Prescaler value.
+/// This parameter can be one of the following values:
+/// @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+/// @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+/// @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+/// @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+/// @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+/// @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+/// @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_SetPrescaler(u8 prescaler)
+{
+ IWDG->PR = prescaler;
+ PVU_CheckStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set IWDG reload value.
+/// @param reload: specifies the IWDG reload value.
+/// This parameter must be a number between 0 and 0x0FFF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_SetReload(u16 reload)
+{
+ IWDG->RLR = reload;
+ RVU_CheckStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Get IWDG reload value.
+/// @param None.
+/// @retval reload: specifies the IWDG reload value.
+////////////////////////////////////////////////////////////////////////////////
+u32 IWDG_GetReload(void)
+{
+ return IWDG->RLR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reloads IWDG counter with value defined in the reload register
+/// (write access to IWDG_PR and IWDG_RLR registers disabled).
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_Reload;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
+/// disabled).
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_Enable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified IWDG flag is set or not.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+/// @arg IWDG_FLAG_RVU: reload Value Update on going
+/// @retval The new state of flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus IWDG_GetFlagStatus(u16 flag)
+{
+ return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks prescaler value has been updated.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PVU_CheckStatus(void)
+{
+ while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks count relead value has been updated.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RVU_CheckStatus(void)
+{
+ while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG overflow configuration.
+/// @param overflow_config
+/// @arg IWDG_Overflow_Interrupt: Interrupt after overflow.
+/// @arg IWDG_Overflow_Reset: Reset after overflow.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config)
+{
+ IWDG->CR &= ~IWDG_CR_IRQSEL;
+ IWDG->CR |= overflow_config;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clear interrupt flag
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ClearITPendingBit(void)
+{
+ IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clear interrupt flag
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ClearIT(void)
+{
+ IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable IWDG interrupt function
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_EnableIT(void)
+{
+ IWDG->CR |= IWDG_CR_IRQSEL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Disable IWDG interrupt function
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_Reset(void)
+{
+ IWDG->CR &= ~IWDG_CR_IRQSEL;
+}
+
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
new file mode 100644
index 00000000..598d6d07
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_misc.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_MISC_C_
+
+// Files includes
+#include "hal_misc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MSIC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MISC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the NVIC interrupt vector table.
+/// @param vect_tab
+/// This parameter can be any combination of the following values:
+/// @arg NVIC_VectTab_RAM
+/// @arg NVIC_VectTab_FLASH
+/// @param offset
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_SetVectorTable(u32 vect_tab, u32 offset)
+{
+ SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the NVIC interrupt priority group.
+/// @param priority_group
+/// This parameter can be any combination of the following values:
+/// @arg NVIC_PriorityGroup_0
+/// @arg NVIC_PriorityGroup_1
+/// @arg NVIC_PriorityGroup_2
+/// @arg NVIC_PriorityGroup_3
+/// @arg NVIC_PriorityGroup_4
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_PriorityGroupConfig(u32 priority_group)
+{
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC initialization.
+/// @param init_struct
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_Init(NVIC_InitTypeDef* init_struct)
+{
+ if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
+ u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
+
+ pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
+ (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri)))
+ << 0x04;
+
+ NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
+ NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+ }
+ else {
+ NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+ }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC initialized extension function.
+/// @param init_struct
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exNVIC_Init(exNVIC_Init_TypeDef* init_struct)
+{
+ u32 pri;
+
+ if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
+ pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
+
+ pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
+ (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04;
+
+ NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
+ NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+ }
+ else {
+ NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+ }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief System low power mode configuration.
+/// @param low_power_mode
+/// This parameter can be any combination of the following values:
+/// @arg NVIC_LP_SEVONPEND
+/// @arg NVIC_LP_SLEEPDEEP
+/// @arg NVIC_LP_SLEEPONEXIT
+/// @param state: new state of the low power mode.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state)
+{
+ (state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SysTick clock source configuration.
+/// @param systick_clk_source
+/// This parameter can be any combination of the following values:
+/// @arg SysTick_CLKSource_EXTCLK
+/// @arg SysTick_CLKSource_HCLK
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SysTick_CLKSourceConfig(u32 systick_clk_source)
+{
+ (systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \
+ : (SysTick->CTRL &= ~SysTick_CLKSource_HCLK);
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
new file mode 100644
index 00000000..e39bf3f3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
@@ -0,0 +1,215 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_pwr.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define __HAL_PWR_C_
+
+// Files includes
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_syscfg.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup PWR_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup PWR_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the PWR peripheral registers to their default reset
+/// values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_DeInit(void)
+{
+ exRCC_APB1PeriphReset(RCC_APB1ENR_PWR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables access to the RTC and backup registers.
+/// @param state: new state of the access to the RTC and backup
+/// registers. This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_BackupAccessCmd(FunctionalState state)
+{
+ (state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Power Voltage Detector(PVD).
+/// @param state: new state of the PVD.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_PVDCmd(FunctionalState state)
+{
+ (state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the voltage threshold detected by the Power Voltage
+/// Detector(PVD).
+/// @param pvd_level: specifies the PVD detection level
+/// This parameter can be one of the following values:
+/// @arg emPVD_LEVEL0 : PVD detection level set to 1.7V
+/// @arg emPVD_LEVEL1 : PVD detection level set to 2.0V
+/// @arg emPVD_LEVEL2 : PVD detection level set to 2.3V
+/// @arg emPVD_LEVEL3 : PVD detection level set to 2.6V
+/// @arg emPVD_LEVEL4 : PVD detection level set to 2.9V
+/// @arg emPVD_LEVEL5 : PVD detection level set to 3.2V
+/// @arg emPVD_LEVEL6 : PVD detection level set to 3.5V
+/// @arg emPVD_LEVEL7 : PVD detection level set to 3.8V
+/// @arg emPVD_LEVEL8 : PVD detection level set to 4.1V
+/// @arg emPVD_LEVEL9 : PVD detection level set to 4.4V
+/// @arg emPVD_LEVEL10: PVD detection level set to 4.7V
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level)
+{
+ SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the WakeUp Pin functionality.
+/// @param state: new state of the WakeUp Pin functionality.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_WakeUpPinCmd(FunctionalState state)
+{
+ (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the WakeUp Pin functionality.
+/// @param state: new state of the WakeUp Pin functionality.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state)
+{
+ (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enters STOP mode.
+/// @param regulator: specifies the regulator state in STOP mode.
+/// This parameter can be one of the following values:
+/// @arg PWR_Regulator_ON: STOP mode with regulator ON
+/// @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
+/// @param stop_entry: specifies if STOP mode in entered with WFI or WFE
+/// instruction.
+/// This parameter can be one of the following values:
+/// @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+/// @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry)
+{
+
+ MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator);
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(stop_entry == PWR_STOPEntry_WFI) {
+ __WFI();
+ }
+ else {
+ __WFE();
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enters STANDBY mode.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_EnterSTANDBYMode(void)
+{
+ PWR->CR |= PWR_CR_PDDS;
+ PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6;
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+#if defined(__CC_ARM)
+ __force_stores();
+#endif
+ __WFI();
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified PWR flag is set or not.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg PWR_FLAG_WU: Wake Up flag
+/// @arg PWR_FLAG_SB: StandBy flag
+/// @arg PWR_FLAG_PVDO: PVD Output
+/// @retval The new state of PWR_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus PWR_GetPVDOFlagStatus(u32 flag)
+{
+ return (FlagStatus)(SYSCFG->PDETCSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the PWR's pending flags.
+/// @param flag: specifies the flag to clear.
+/// This parameter can be one of the following values:
+/// @arg PWR_FLAG_WU: Wake Up flag
+/// @arg PWR_FLAG_SB: StandBy flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_ClearPVDOFlag(u32 flag)
+{
+ PWR->CR |= flag << 2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified PWR flag is set or not.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg PWR_FLAG_WU: Wake Up flag
+/// @arg PWR_FLAG_SB: StandBy flag
+/// @arg PWR_FLAG_PVDO: PVD Output
+/// @retval The new state of PWR_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus PWR_GetFlagStatus(u32 flag)
+{
+ return (FlagStatus)(PWR->CSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the PWR's pending flags.
+/// @param flag: specifies the flag to clear.
+/// This parameter can be one of the following values:
+/// @arg PWR_FLAG_WU: Wake Up flag
+/// @arg PWR_FLAG_SB: StandBy flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_ClearFlag(u32 flag)
+{
+ PWR->CR |= flag << 2;
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
new file mode 100644
index 00000000..5e2bd1a8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
@@ -0,0 +1,995 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_rcc.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_RCC_C_
+
+// Files includes
+#include "mm32_reg.h"
+#include "hal_rcc.h"
+
+
+
+u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RCC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RCC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Resets the RCC clock configuration to default state.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DeInit()
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON );
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP);
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+ CLEAR_REG(RCC->CFGR);
+ CLEAR_REG(RCC->CIR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the External High Speed oscillator (HSE).
+/// @param state: specifies the new state of HSE.
+/// This parameter can be one of the following values:
+/// @arg RCC_HSE_OFF: HSE oscillator OFF
+/// @arg RCC_HSE_ON: HSE oscillator ON
+/// @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HSEConfig(RCCHSE_TypeDef state)
+{
+ RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON);
+ switch (state) {
+ case RCC_HSE_Bypass:
+ RCC->CR |= RCC_CR_HSEBYP;
+ RCC->CR |= RCC_CR_HSEON;
+ break;
+ case RCC_HSE_ON:
+ RCC->CR |= RCC_CR_HSEON;
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified RCC flag is set or not.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+/// @arg RCC_FLAG_PLLRDY: PLL clock ready
+/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+/// @arg RCC_FLAG_PINRST: Pin reset
+/// @arg RCC_FLAG_PORRST: POR/PDR reset
+/// @arg RCC_FLAG_SFTRST: Software reset
+/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+/// @arg RCC_FLAG_LPWRRST: Low Power reset
+/// @retval The new state of flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag)
+{
+ return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) &
+ (1 << (flag & 0x1F)))
+ ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Waits for HSE start-up.
+/// @param None.
+/// @retval An ErrorStatus enumuration value:
+/// - SUCCESS: HSE oscillator is stable and ready to use
+/// - ERROR: HSE oscillator not yet ready
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ u32 StartUpCounter = 0;
+
+ FlagStatus HSEStatus;
+
+ do {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Waits for flag start-up.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+/// @arg RCC_FLAG_PLLRDY: PLL clock ready
+/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+/// @arg RCC_FLAG_PINRST: Pin reset
+/// @arg RCC_FLAG_PORRST: POR/PDR reset
+/// @arg RCC_FLAG_SFTRST: Software reset
+/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+/// @retval An ErrorStatus enumuration value:
+/// - SUCCESS: HSE oscillator is stable and ready to use
+/// - ERROR: HSE oscillator not yet ready
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag)
+{
+ u32 StartUpCounter = 0;
+
+ while (RCC_GetFlagStatus(flag) == RESET) {
+ if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) {
+ return ERROR;
+ }
+ }
+ return SUCCESS;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Internal High Speed oscillator (HSI).
+/// @param state: new state of the HSI.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HSICmd(FunctionalState state)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the system clock (SYSCLK).
+/// @param sys_clk_source: specifies the clock source used as system
+/// clock. This parameter can be one of the following values:
+/// @arg RCC_HSI: specifies HSI as system clock
+/// @arg RCC_HSE: specifies HSE as system clock
+/// @arg RCC_PLL: specifies PLL as system clock
+/// @arg RCC_LSI: specifies LSI as system clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the PLL clock source and DM DN factor.
+/// This function must be used only when the PLL is disabled.
+/// @param plldn: specifies the PLL multiplication factor.
+/// This parameter can be RCC_PLLMul_x where x:[31:26]
+/// @param plldm: specifies the PLL Divsior factor.
+/// This parameter can be RCC_Divsior_x where x:[22:20]
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLDMDNConfig(u32 plldn, u32 plldm)
+{
+ MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the PLL.
+/// The PLL can not be disabled if it is used as system clock.
+/// @param state: new state of the PLL.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLCmd(FunctionalState state)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the PLL clock source and multiplication factor.
+/// This function must be used only when the PLL is disabled.
+/// @param pll_src: specifies the PLL entry clock source.
+/// This parameter can be one of the following values:
+/// @arg RCC_HSI_Div4: HSI oscillator clock divided
+/// by 4 selected as PLL clock entry
+/// @arg RCC_HSE_Div1: HSE oscillator clock selected
+/// as PLL clock entry
+/// @arg RCC_HSE_Div2: HSE oscillator clock divided
+/// by 2 selected as PLL clock entry
+/// @param pll_mul: specifies the PLL multiplication factor.
+/// This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul)
+{
+ const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01, // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2;
+ 0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01, // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2;
+ 0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01, // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2;
+ 0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01
+ }; // Frclk*28/2; Frclk*30/2; // Frclk*32/2;
+ MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src);
+ RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the USB clock (USBCLK).
+/// @param usb_clk_src: specifies the USB clock source.
+/// This clock is derived from the PLL output.
+/// This parameter can be one of the following values:
+/// @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+/// @arg RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB
+/// clock source
+/// @arg RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB
+/// clock source
+/// @arg RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB
+/// clock source
+/// @arg RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB
+/// clock source
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the clock source used as system clock.
+/// @param None.
+/// @retval The clock source used as system clock. The returned value can
+/// be one of the following:
+/// - 0x00: HSI/6 used as system clock
+/// - 0x04: HSE used as system clock
+/// - 0x08: PLL used as system clock
+////////////////////////////////////////////////////////////////////////////////
+u8 RCC_GetSYSCLKSource(void)
+{
+ return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the AHB clock (hclk).
+/// @param sys_clk: defines the AHB clock divider. This clock is derived
+/// from the system clock (SYSCLK).
+/// This parameter can be one of the following values:
+/// @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+/// @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+/// @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+/// @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+/// @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+/// @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+/// @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+/// @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+/// @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the Low Speed APB clock (pclk1).
+/// @param hclk: defines the APB1 clock divider. This clock is derived from
+/// the AHB clock (hclk).
+/// This parameter can be one of the following values:
+/// @arg RCC_HCLK_Div1: APB1 clock = hclk
+/// @arg RCC_HCLK_Div2: APB1 clock = hclk/2
+/// @arg RCC_HCLK_Div4: APB1 clock = hclk/4
+/// @arg RCC_HCLK_Div8: APB1 clock = hclk/8
+/// @arg RCC_HCLK_Div16: APB1 clock = hclk/16
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the High Speed APB clock (pclk2).
+/// @param hclk: defines the APB2 clock divider. This clock is derived from
+/// the AHB clock (hclk).
+/// This parameter can be one of the following values:
+/// @arg RCC_HCLK_Div1: APB2 clock = hclk
+/// @arg RCC_HCLK_Div2: APB2 clock = hclk/2
+/// @arg RCC_HCLK_Div4: APB2 clock = hclk/4
+/// @arg RCC_HCLK_Div8: APB2 clock = hclk/8
+/// @arg RCC_HCLK_Div16: APB2 clock = hclk/16
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the ADC clock (ADCCLK).
+/// @param pclk2: defines the ADC clock divider. This clock is derived from
+/// the APB2 clock (pclk2).
+/// This parameter can be one of the following values:
+/// @arg RCC_PCLK2_Div2: ADC clock = pclk2/2
+/// @arg RCC_PCLK2_Div4: ADC clock = pclk2/4
+/// @arg RCC_PCLK2_Div6: ADC clock = pclk2/6
+/// @arg RCC_PCLK2_Div8: ADC clock = pclk2/8
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2)
+{
+ MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the External Low Speed oscillator (LSE).
+/// @param state: specifies the new state of the LSE.
+/// This parameter can be one of the following values:
+/// @arg RCC_LSE_OFF: LSE oscillator OFF
+/// @arg RCC_LSE_ON: LSE oscillator ON
+/// @arg RCC_LSE_Bypass: LSE oscillator bypassed with external
+/// clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_LSEConfig(RCC_LSE_TypeDef state)
+{
+ RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
+
+ switch (state) {
+ case RCC_LSE_Bypass:
+ RCC->BDCR |= RCC_BDCR_LSEBYP;
+ RCC->BDCR |= RCC_BDCR_LSEON;
+ break;
+ case RCC_LSE_ON:
+ RCC->BDCR |= RCC_BDCR_LSEON;
+ break;
+ default:
+ break;
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the RTC clock (RTCCLK).
+/// Once the RTC clock is selected it can be changed unless the
+/// Backup domain is reset.
+/// @param rtc_clk_src: specifies the RTC clock source.
+/// This parameter can be one of the following values:
+/// @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+/// @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+/// @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
+/// selected as RTC clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the RTC clock.
+/// This function must be used only after the RTC clock was
+/// selected using the RCC_RTCCLKConfig function.
+/// @param state: new state of the RTC clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_RTCCLKCmd(FunctionalState state)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Internal Low Speed oscillator (LSI).
+/// LSI can not be disabled if the IWDG is running.
+/// @param state: new state of the LSI.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_LSICmd(FunctionalState state)
+{
+// u32 j;
+ MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the clock frequency of different on chip clocks.
+/// @param None.
+/// @retval sys_clk : System clock frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetSysClockFreq(void)
+{
+ u32 result;
+ u32 clock, mul, div;
+ switch (RCC->CFGR & RCC_CFGR_SWS) {
+ case RCC_CFGR_SWS_LSI:
+ result = LSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE:
+ result = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL:
+ clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE)
+ : HSI_VALUE_PLL_ON;
+ mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1;
+ div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1;
+
+ result = clock * mul / div;
+ break;
+ default:
+ result = HSI_VALUE;
+ break;
+ }
+ return result;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the hclk frequency of different on chip clocks.
+/// @param None.
+/// @retval hclk frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetHCLKFreq(void)
+{
+ return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the pclk1 frequency of different on chip clocks.
+/// @param None.
+/// @retval pclk1 frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetPCLK1Freq(void)
+{
+ return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the pclk2 frequency of different on chip clocks.
+/// @param None.
+/// @retval pclk2 frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetPCLK2Freq(void)
+{
+ return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the frequency of different on chip clocks.
+/// @param clk: pointer to a RCC_ClocksTypeDef structure which
+/// will hold the clocks frequency.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk)
+{
+ u8 tbADCPresc[] = {2, 4, 6, 8};
+
+ clk->SYSCLK_Frequency = RCC_GetSysClockFreq();
+ clk->HCLK_Frequency = RCC_GetHCLKFreq();
+ clk->PCLK1_Frequency = RCC_GetPCLK1Freq();
+ clk->PCLK2_Frequency = RCC_GetPCLK2Freq();
+
+ clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos];
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the AHB peripheral clock.
+/// @param ahb_periph: specifies the AHB peripheral to gates its clock.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+ (state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
+}
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+ (state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph);
+}
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+ (state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+/// @param apb2_periph: specifies the APB2 peripheral to gates its
+/// clock.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state)
+{
+ (state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+/// @param apb1_periph: specifies the APB1 peripheral to gates its
+/// clock.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state)
+{
+ (state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases High Speed APB (APB2) peripheral reset.
+/// @param apb2_periph: specifies the APB2 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral reset.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state)
+{
+ (state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param apb1_periph: specifies the APB1 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state)
+{
+ (state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed AHB peripheral reset.
+/// @param ahb_periph: specifies the AHB peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+ (state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed AHB2 peripheral reset.
+/// @param ahb_periph: specifies the AHB peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+ (state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed AHB2 peripheral reset.
+/// @param ahb_periph: specifies the AHB peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @param state: new state of the specified peripheral clock.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+ (state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases the Backup domain reset.
+/// @param state: new state of the Backup domain reset.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_BackupResetCmd(FunctionalState state)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the Clock Security System.
+/// @param state: new state of the Clock Security System..
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClockSecuritySystemCmd(FunctionalState state)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the clock source to output on MCO pin.
+/// @param mco_src: specifies the clock source to output.
+/// This parameter can be one of the following values:
+/// @arg RCC_MCO_NoClock: No clock selected
+/// @arg RCC_MCO_LSI: LSI oscillator clock selected
+/// @arg RCC_MCO_LSE: LSE oscillator clock selected
+/// @arg RCC_MCO_SYSCLK: System clock selected
+/// @arg RCC_MCO_HSI: HSI oscillator clock selected
+/// @arg RCC_MCO_HSE: HSE oscillator clock selected
+/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_MCOConfig(RCC_MCO_TypeDef mco_src)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the RCC reset flags.
+/// The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+/// RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+/// RCC_FLAG_LPWRRST
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClearFlag(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified RCC interrupts.
+/// @param it: specifies the RCC interrupt sources to be enabled or
+/// disabled.
+/// This parameter can be any combination of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @param state: new state of the specified RCC interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state)
+{
+ (state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified RCC interrupt has occurred or not.
+/// @param it: specifies the RCC interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @arg RCC_IT_CSS: Clock Security System interrupt
+/// @retval The new state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus RCC_GetITStatus(RCC_IT_TypeDef it)
+{
+ return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the RCC�?interrupt pending bits.
+/// @param it: specifies the interrupt pending bit to clear.
+/// This parameter can be any combination of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @arg RCC_IT_CSS: Clock Security System interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClearITPendingBit(u8 it)
+{
+ SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param apb1_periph: specifies the APB1 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphReset(u32 apb1_periph)
+{
+ RCC->APB1RSTR |= apb1_periph;
+ RCC->APB1RSTR &= ~apb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed APB (APB2) peripheral reset.
+/// @param apb2_periph: specifies the APB2 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphReset(u32 apb2_periph)
+{
+ RCC->APB2RSTR |= apb2_periph;
+ RCC->APB2RSTR &= ~apb2_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset.
+/// @param ahb1_periph: specifies the AHB1 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphReset(u32 ahb1_periph)
+{
+ RCC->AHBRSTR |= ahb1_periph;
+ RCC->AHBRSTR &= ~ahb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+//
+// New Function Interface
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param apb1_periph: specifies the APB1 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_APB1PeriphReset(u32 apb1_periph)
+{
+ RCC->APB1RSTR |= apb1_periph;
+ RCC->APB1RSTR &= ~apb1_periph;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief
+/// @param
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_BackupReset()
+{
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases High Speed APB (APB2) peripheral reset.
+/// @param apb2_periph: specifies the APB2 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_APB2PeriphReset(u32 apb2_periph)
+{
+ RCC->APB2RSTR |= apb2_periph;
+ RCC->APB2RSTR &= ~apb2_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset.
+/// @param ahb1_periph: specifies the AHB1 peripheral to reset.
+/// This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_AHBPeriphReset(u32 ahb1_periph)
+{
+ RCC->AHBRSTR |= ahb1_periph;
+ RCC->AHBRSTR &= ~ahb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Disable systick
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_SystickDisable()
+{
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable systick
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_SystickEnable(u32 sys_tick_period)
+{
+ SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period);
+}
+
+/*
+(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
+(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
+(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
+*/
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified ADC peripheral Clock.
+/// @param peripheral:select the ADC peripheral.
+/// @param state: new state of the ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state)
+{
+ switch (*(vu32*)&peripheral) {
+
+ case ADC1_BASE:
+ (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1);
+ break;
+ case ADC2_BASE:
+ (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2);
+ break;
+ case ADC3_BASE:
+ (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3);
+ break;
+ default:
+ break;
+ }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified BKP peripheral Clock.
+/// @param peripheral:select the BKP peripheral.
+/// @param state: new state of the BKP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state)
+{
+ if(BKP == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP);
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR);
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified CAN peripheral Clock.
+/// @param peripheral:select the CAN peripheral.
+/// @param state: new state of the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state)
+{
+ if(CAN1 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN);
+ }
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified COMP peripheral Clock.
+/// @param peripheral:select the COMP peripheral.
+/// @param state: new state of the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state)
+{
+ if(COMP == peripheral) {
+ (state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP);
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified CRC peripheral Clock.
+/// @param peripheral:select the CRC peripheral.
+/// @param state: new state of the CRC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state)
+{
+ if(CRC == peripheral) {
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC);
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DAC peripheral Clock.
+/// @param peripheral:select the DAC peripheral.
+/// @param state: new state of the DAC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state)
+{
+ if(DAC == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC);
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified DMA peripheral Clock.
+/// @param peripheral:select the DMA peripheral.
+/// @param state: new state of the DMA peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state)
+{
+ if(DMA1 == peripheral) {
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1);
+ }
+ if(DMA2 == peripheral) {
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2);
+ }
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified GPIO peripheral Clock.
+/// @param peripheral:select the GPIO peripheral.
+/// @param state: new state of the GPIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state)
+{
+ switch (*(vu32*)&peripheral) {
+ case (u32)GPIOA:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA);
+ break;
+ case (u32)GPIOB:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB);
+ break;
+ case (u32)GPIOC:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC);
+ break;
+ case (u32)GPIOD:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD);
+ break;
+ case (u32)GPIOE:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE);
+ break;
+ case (u32)GPIOF:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF);
+ break;
+ case (u32)GPIOG:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG);
+ break;
+ case (u32)GPIOH:
+ (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH);
+ break;
+ default:
+ break;
+ }
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the uart peripheral registers to their
+/// default reset values.
+/// @param peripheral: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state)
+{
+ if(UART2 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
+ }
+ if(UART1 == peripheral) {
+ (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
+ }
+ if(UART3 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
+ }
+ if(UART4 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
+ }
+ if(UART5 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
+ }
+ if(UART6 == peripheral) {
+ (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
+ }
+ if(UART7 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
+ }
+ if(UART8 == peripheral) {
+ (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
+ }
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
new file mode 100644
index 00000000..b02c6750
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
@@ -0,0 +1,234 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_rtc.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_RTC_C_
+
+// Files includes
+#include "hal_rtc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RTC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RTC_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified RTC interrupts.
+/// @param it: specifies the RTC interrupts sources to be enabled or
+/// disabled.
+/// This parameter can be any combination of the following values:
+/// @arg RTC_IT_OW: Overflow interrupt
+/// @arg RTC_IT_ALR: Alarm interrupt
+/// @arg RTC_IT_SEC: Second interrupt
+/// @param state: new state of the specified RTC interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state)
+{
+ (state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it);
+// RTC_WaitForLastTask();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enters the RTC configuration mode.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_EnterConfigMode(void)
+{
+// PWR->CR |= PWR_CR_DBP;
+ RTC->CSR |= RTC_CSR_CNF;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Exits from the RTC configuration mode.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ExitConfigMode(void)
+{
+ RTC->CSR &= ~RTC_CSR_CNF;
+ while (!(RTC->CSR & RTC_CSR_RTOFF));
+// PWR->CR &= ~PWR_CR_DBP;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the RTC counter value.
+/// @param None.
+/// @retval RTC counter value.
+////////////////////////////////////////////////////////////////////////////////
+u32 RTC_GetCounter(void)
+{
+ u32 dat = RTC->CNTH << 16;
+ return (RTC->CNTL | dat);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the RTC counter value.
+/// @param count: RTC counter new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetCounter(u32 count)
+{
+ RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+ RTC->CNTH = count >> 16;
+ RTC->CNTL = count;
+ RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+// while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the RTC prescaler value.
+/// @param prescaler: RTC prescaler new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetPrescaler(u32 prescaler)
+{
+ RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+ RTC->PRLH = prescaler >> 16;
+ RTC->PRLL = prescaler;
+ RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+// while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the RTC alarm value.
+/// @param alarm: RTC alarm new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetAlarm(u32 alarm)
+{
+ RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+ RTC->ALRH = alarm >> 16;
+ RTC->ALRL = alarm;
+ RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+// while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the RTC divider value.
+/// @param None.
+/// @retval RTC Divider value.
+////////////////////////////////////////////////////////////////////////////////
+u32 RTC_GetDivider(void)
+{
+ u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16);
+ return (RTC->DIVL | dat);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Waits until last write operation on RTC registers has finished.
+/// @note This function must be called before any write to RTC registers.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_WaitForLastTask(void)
+{
+ while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+/// are synchronized with RTC APB clock.
+/// @note This function must be called before any read operation after an APB
+/// reset or an APB clock stop.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_WaitForSynchro(void)
+{
+ RTC->CSR &= ~RTC_CSR_RSF;
+ while (!(RTC->CSR & RTC_CSR_RSF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified RTC flag is set or not.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one the following values:
+/// @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+/// @arg RTC_FLAG_RSF: Registers Synchronized flag
+/// @arg RTC_FLAG_OW: Overflow flag
+/// @arg RTC_FLAG_ALR: Alarm flag
+/// @arg RTC_FLAG_SEC: Second flag
+/// @retval The state of RTC_FLAG (SET or RESET).
+/////////////////////////////////////////////////////////////////////////////////
+FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag)
+{
+ return (FlagStatus)(RTC->CSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the RTC's pending flags.
+/// @param flag: specifies the flag to clear.
+/// This parameter can be any combination of the following values:
+/// @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only
+/// after an APB reset or an APB Clock stop.
+/// @arg RTC_FLAG_OW: Overflow flag
+/// @arg RTC_FLAG_ALR: Alarm flag
+/// @arg RTC_FLAG_SEC: Second flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ClearFlag(RTC_FLAG_TypeDef flag)
+{
+ RTC->CSR &= ~flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified RTC interrupt has occurred or not.
+/// @param it: specifies the RTC interrupts sources to check.
+/// This parameter can be one of the following values:
+/// @arg RTC_IT_OW: Overflow interrupt
+/// @arg RTC_IT_ALR: Alarm interrupt
+/// @arg RTC_IT_SEC: Second interrupt
+/// @retval The state of the RTC_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus RTC_GetITStatus(RTC_IT_TypeDef it)
+{
+ return (ITStatus)(RTC->CSR & it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the RTC's interrupt pending bits.
+/// @param it: specifies the interrupt pending bit to clear.
+/// This parameter can be any combination of the following values:
+/// @arg RTC_IT_OW: Overflow interrupt
+/// @arg RTC_IT_ALR: Alarm interrupt
+/// @arg RTC_IT_SEC: Second interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ClearITPendingBit(RTC_IT_TypeDef it)
+{
+// RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+ RTC->CSR &= ~it;
+// RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
new file mode 100644
index 00000000..4b1bd70e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
@@ -0,0 +1,527 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_sdio.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_SDIO_C_
+#include "reg_sdio.h"
+#include "hal_sdio.h"
+#include "hal_rcc.h"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SDIO_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SDIO_Exported_Functions
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the SDIO peripheral registers to their default reset
+/// values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_DeInit(void)
+{
+ RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each SDIO_InitStruct member with its default value.
+/// @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+/// will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ // SDIO_InitStruct members default value
+ SDIO_InitStruct->SDIO_MDEN = 0;
+ SDIO_InitStruct->SDIO_DATWT = 0;
+ SDIO_InitStruct->SDIO_SelPTSM = 0;
+ SDIO_InitStruct->SDIO_CLKSP = 0;
+ SDIO_InitStruct->SDIO_OUTM = 0;
+ SDIO_InitStruct->SDIO_SelSM = 0;
+ SDIO_InitStruct->SDIO_OPMSel = 0;
+}
+
+
+///
+/// @brief Fills each SDIO_DataInitStruct member with its default value.
+/// @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+/// will be initialized.
+/// @retval None
+///
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ /* SDIO_DataInitStruct members default value */
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+// SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+// SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+///
+/// @brief Initializes the SDIO data path according to the specified
+/// parameters in the SDIO_DataInitStruct.
+/// @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+/// contains the configuration information for the SDIO command.
+/// @retval None
+///
+//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+//{
+// u32 tmpreg = 0;
+
+// /*---------------------------- SDIO DTIMER Configuration ---------------------*/
+// /* Set the SDIO Data TimeOut value */
+// SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+// /*---------------------------- SDIO DLEN Configuration -----------------------*/
+// /* Set the SDIO DataLength value */
+// SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength;
+
+// /*---------------------------- SDIO DCTRL Configuration ----------------------*/
+// /* Get the SDIO DCTRL value */
+// tmpreg = SDIO->DCTRL;
+// /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+// tmpreg &= DCTRL_CLEAR_MASK;
+// /* Set DEN bit according to SDIO_DPSM value */
+// /* Set DTMODE bit according to SDIO_TransferMode value */
+// /* Set DTDIR bit according to SDIO_TransferDir value */
+// /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+// tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;//
+// //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+// /* Write to SDIO DCTRL */
+// SDIO->DCTRL = tmpreg;
+//}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief The frequency division factor is configured to generate the SDIO clock.
+/// @param value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2)
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClockSet(u32 value)
+{
+// SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK;
+ SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F));
+// SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the SDIO peripheral according to the specified
+/// parameters in the SDIO_InitStruct.
+/// @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+/// that contains the configuration information for the SDIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ SDIO->MMC_CTRL &= 0x700;
+ SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM |
+ SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP |
+ SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT |
+ SDIO_InitStruct->SDIO_MDEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the SDIO interrupts.
+/// @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+/// state : new state of the specified SDIO interrupts.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state)
+{
+ (state) ? (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the SDIO CRC.
+/// @param SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled.
+/// state : new state of the specified SDIO CRC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state)
+{
+ (state) ? (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Port transfer speed mode.
+/// @param clkdiv : High/low speed.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Clock_Set(u8 clkdiv)
+{
+ SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM;
+ (clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Turn off the SDIO switch.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error SD_PowerOFF(void)
+{
+ SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN);
+ return SD_OK;
+}
+///
+/// @brief Fills each SDIO_CmdInitStruct member with its default value.
+/// @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+/// structure which will be initialized.
+/// @retval None
+///
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+ /* SDIO_CmdInitStruct members default value */
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+// SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO sends command functions.
+/// @param cmdindex : Type the command.
+/// waitrsp : Expected correspondence.
+/// arg : parameter.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg)
+{
+ SDIO->CMD_BUF0 = (arg >> 0) & 0xFF;
+ SDIO->CMD_BUF1 = (arg >> 8) & 0xFF;
+ SDIO->CMD_BUF2 = (arg >> 16) & 0xFF;
+ SDIO->CMD_BUF3 = (arg >> 24) & 0xFF;
+ SDIO->CMD_BUF4 = 0x40 | cmdindex;
+ SDIO->CLR_MMC_INT |= 0;
+ SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR;
+ while(1) {
+ if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) {
+ SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC;
+ break;
+ }
+ }
+ if(waitrsp == SDIO_Response_Short) {
+ SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \
+ SDIO_MMC_IO_AUTOTR | \
+ SDIO_MMC_IO_RESPCMDSEL;
+ }
+ else if(waitrsp == SDIO_Response_Long) {
+ SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \
+ SDIO_MMC_IO_AUTOTR | \
+ SDIO_MMC_IO_RESPCMDSEL | \
+ SDIO_MMC_IO_CID_CSDRD;
+ }
+ else {
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Check the execution status of CMD0.
+/// @param None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdError(void)
+{
+ SD_Error errorstatus = SD_OK;
+ u32 timeout = SDIO_CMD0TIMEOUT;
+ while (timeout--) {
+ if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0))
+ break;
+ }
+ if (timeout == 0)
+ return SD_CMD_RSP_TIMEOUT;
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+ return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Check the error status of the R1 response.
+/// @param cmd : Current command.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp1Error(u8 cmd)
+{
+ u32 status;
+ u32 response;
+ while(1) {
+ status = SDIO->CLR_MMC_INT ;
+ if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+ break;
+ }
+ if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+ return SD_CMD_RSP_TIMEOUT;
+ }
+ if(status & (SDIO_CLR_MMC_INT_CRCEMC)) {
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+ return SD_CMD_CRC_FAIL;
+ }
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+
+ if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
+ return SD_ILLEGAL_CMD;
+ }
+ response = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0;
+ return (SD_Error)(response & SD_OCR_ERRORBITS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Check the execution status of CMD2.
+/// @param None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp2Error(void)
+{
+ SD_Error errorstatus = SD_OK;
+ u32 status;
+ u32 timeout = SDIO_CMD0TIMEOUT;
+ while(timeout--) {
+ status = SDIO->CLR_MMC_INT ;
+ if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+ break;
+ }
+ if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) {
+ errorstatus = SD_CMD_RSP_TIMEOUT;
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+ return errorstatus;
+ }
+ if(status & SDIO_CLR_MMC_INT_CRCEMC) {
+ errorstatus = SD_CMD_CRC_FAIL;
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+ }
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+ return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Check the execution status of CMD3.
+/// @param None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp3Error(void)
+{
+ u32 status;
+ while(1) {
+ status = SDIO->CLR_MMC_INT ;
+ if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+ break;
+ }
+ if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+ return SD_CMD_RSP_TIMEOUT;
+ }
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+ return SD_OK;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Check the execution status of CMD6.
+/// @param None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp6Error(u8 cmd, u16* prca)
+{
+ SD_Error errorstatus = SD_OK;
+ u32 status;
+ u32 rspr1;
+ while(1) {
+ status = SDIO->CLR_MMC_INT ;
+ if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+ break;
+ }
+ if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+ return SD_CMD_RSP_TIMEOUT;
+ }
+ if(status & SDIO_CLR_MMC_INT_CRCEMC) {
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+ return SD_CMD_CRC_FAIL;
+ }
+ if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
+ return SD_ILLEGAL_CMD;
+ }
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+ rspr1 = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0;
+ if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) {
+ *prca = (u16)(rspr1 >> 16);
+ return errorstatus;
+ }
+ if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) {
+ return SD_GENERAL_UNKNOWN_ERROR;
+ }
+ if(rspr1 & SD_R6_ILLEGAL_CMD) {
+ return SD_ILLEGAL_CMD;
+ }
+ if(rspr1 & SD_R6_COM_CRC_FAILED) {
+ return SD_COM_CRC_FAILED;
+ }
+ return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Check the execution status of CMD7.
+/// @param None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp7Error(void)
+{
+ SD_Error errorstatus = SD_OK;
+ u32 status;
+ u32 timeout = SDIO_CMD0TIMEOUT;
+ while(timeout--) {
+ status = SDIO->CLR_MMC_INT ;
+ if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+ break;
+ }
+ if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout
+ errorstatus = SD_CMD_RSP_TIMEOUT;
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+ return errorstatus;
+ }
+ if(status & SDIO_CLR_MMC_INT_CMDDMC) {
+ errorstatus = SD_OK;
+ SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC;
+ }
+ return errorstatus;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Write data direction block size configuration.
+/// @param datatimeout : maximum latency.
+/// datalen : data len
+/// blksize : block count.
+/// dir : direction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir)
+{
+ u32 tmpreg, tmpreg1, tmpreg2 = 0;
+ tmpreg = SDIO->MMC_IO_MBCTL;
+ tmpreg1 = SDIO->MMC_IO;
+ tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD);
+ if (datatimeout < 100) {
+ SDIO->MMC_TIMEOUTCNT = datatimeout;
+ }
+ else if (datatimeout < 10000) {
+ SDIO->MMC_TIMEOUTCNT = datatimeout / 100;
+ tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
+ }
+ else if (datatimeout < 1000000) {
+ SDIO->MMC_TIMEOUTCNT = datatimeout / 10000;
+ tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2;
+ }
+ else {
+ SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000;
+ tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
+ }
+ SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ;
+ SDIO->MMC_BLOCKCNT = blksize;
+ if (dir == 0) {
+ tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD;
+ tmpreg1 |= SDIO_MMC_IO_TRANSFDIR;
+ tmpreg2 |= SDIO_BUF_CTLL_SBAD;
+ }
+ else {
+ tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD);
+ tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR);
+ tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD);
+ }
+ SDIO->MMC_IO_MBCTL = tmpreg;
+ SDIO->MMC_IO = tmpreg1;
+ SDIO->BUF_CTL = tmpreg2;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the SDIO's Flag pending bits.
+/// @param SDIO_IT: specifies the flag pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClearFlag(u32 SDIO_FLAG)
+{
+ SDIO->CLR_MMC_INT |= SDIO_FLAG;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the SDIO's interrupt pending bits.
+/// @param SDIO_IT: specifies the interrupt pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClearITPendingBit(u32 SDIO_IT)
+{
+ SDIO->CLR_MMC_INT |= SDIO_IT;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified SDIO flag is set or not.
+/// @param SDIO_FLAG: specifies the flag to check.
+/// @retval The new state of SDIO_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
+{
+ return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Reads the value of the data transfer timeout count
+/// @param None.
+/// @retval timeout count.
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_GetTimeOutCounter(void)
+{
+ return (SDIO->MMC_TIMEOUTCNT & 0xFF);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Read one data word from FIFO.
+/// @param None.
+/// @retval Data received.
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_ReadData(void)
+{
+ return SDIO->FIFO;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Write one data word to FIFO.
+/// @param tempbuff : Write data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_WriteData(u32 tempbuff)
+{
+ SDIO->FIFO = tempbuff;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns number of remaining data bytes to be transferred.
+/// @param None
+/// @retval Number of remaining data bytes to be transferred
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_GetDataCounter(void)
+{
+ return SDIO->MMC_BYTECNTL;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable or Dsiable DMA .
+/// @param tempbuff : Write data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_DMACmd(FunctionalState state)
+{
+ (state) ? ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN);
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
new file mode 100644
index 00000000..3d8c286a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
@@ -0,0 +1,648 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_spi.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_SPI_C_
+#include
+// Files includes
+#include "hal_spi.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SPI_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup SPI_Exported_Functions
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the spi peripheral registers to their
+/// default reset values.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_DeInit(SPI_TypeDef* spi)
+{
+ switch (*(vu32*)&spi) {
+ case (u32)SPI2: // SPI2_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE);
+ break;
+ case (u32)SPI3: // SPI3_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE);
+ break;
+ case (u32)SPI1: // SPI1_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the spi peripheral according to the specified
+/// parameters in the init_struct .
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param init_struct: pointer to a SPI_InitTypeDef structure
+/// that contains the configuration information for the
+/// specified SPI peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct)
+{
+ if (init_struct->SPI_DataSize == SPI_DataSize_32b) {
+ SET_BIT(spi->GCR, SPI_GCR_DWSEL);
+ }
+ else {
+ CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL);
+ }
+ MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS);
+ MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode);
+ MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit);
+ MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL);
+ MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA);
+
+ SET_BIT(spi->CCR, SPI_CCR_SPILEN);
+
+ MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler);
+
+ if (init_struct->SPI_DataWidth >= 32) {
+ MODIFY_REG(spi->ECR, ECR_Mask, 0);
+ }
+ else {
+ MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth);
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct: pointer to a SPI_InitTypeDef structure
+/// which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_StructInit(SPI_InitTypeDef* init_struct)
+{
+ init_struct->SPI_Mode = SPI_Mode_Slave;
+ init_struct->SPI_DataSize = SPI_DataSize_8b;
+ init_struct->SPI_DataWidth = 8;
+ init_struct->SPI_CPOL = SPI_CPOL_Low;
+ init_struct->SPI_CPHA = SPI_CPHA_1Edge;
+ init_struct->SPI_NSS = SPI_NSS_Soft;
+ init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ init_struct->SPI_FirstBit = SPI_FirstBit_MSB;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified SPI peripheral.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param state: new state of the spi peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified SPI interrupts.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:SPI1, SPI2.
+/// @param interrupt: specifies the SPI interrupt sources to be
+/// enabled or disabled.
+/// This parameter can be one of the following values:
+/// @arg SPI_IT_TXEPT: Transmitter empty interrupt
+/// @arg SPI_IT_RXFULL: RX FIFO full interrupt
+/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
+/// @arg SPI_IT_RXOERR: Receive overrun error interrupt
+/// @arg SPI_IT_UNDERRUN: underrun interrupt
+/// @arg SPI_IT_RX: Receive data available interrupt
+/// @arg SPI_IT_TX: Transmit FIFO available interrupt
+/// @param state: new state of the specified spi interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state)
+{
+ if (state) {
+ SET_BIT(spi->GCR, (u32)SPI_GCR_IEN);
+ SET_BIT(spi->IER, (u32)interrupt);
+ }
+ else {
+ CLEAR_BIT(spi->IER, interrupt);
+ CLEAR_BIT(spi->GCR, SPI_GCR_IEN);
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the SPI DMA interface.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param state: new state of the DMA Request sources.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief configure tn Fifo trigger level bit.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param fifo_trigger_value: specifies the Fifo trigger level
+/// This parameter can be any combination of the following values:
+/// SPI_TXTLF : SPI TX FIFO Trigger value set
+/// SPI_RXTLF : SPI RX FIFO Trigger value set
+/// @param state: new state of the selected SPI transfer request.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Transmits a Data through the spi peripheral.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param data : Data to be transmitted.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_SendData(SPI_TypeDef* spi, u32 data)
+{
+ u16 templen;
+ __asm volatile("cpsid i");
+
+ WRITE_REG(spi->TDR, data);
+
+ templen = READ_REG(spi->ECR);
+ if(templen == 0)
+ templen = 32;
+ if (templen > 8)
+ WRITE_REG(spi->TDR, data >> 8);
+ if (templen > 16)
+ WRITE_REG(spi->TDR, data >> 16);
+ if (templen > 24)
+ WRITE_REG(spi->TDR, data >> 24);
+ __asm volatile("cpsie i");
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the most recent received data by the spi peripheral.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+u32 SPI_ReceiveData(SPI_TypeDef* spi)
+{
+ u32 temp;
+ u8 templen;
+ __asm volatile("cpsid i");
+
+ temp = READ_REG(spi->RDR);
+
+ templen = READ_REG(spi->ECR);
+ if(templen == 0)
+ templen = 32;
+ if (templen > 8)
+ temp |= (u32)(READ_REG(spi->RDR) << 8);
+ if (templen > 16)
+ temp |= (u32)(READ_REG(spi->RDR) << 16);
+ if (templen > 24)
+ temp |= (u32)(READ_REG(spi->RDR) << 24);
+
+ __asm volatile("cpsie i");
+
+ return temp;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Slave chip csn single by selected
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param state: new state of the selected SPI CS pin
+/// request.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the NSS pin control mode for the selected SPI.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param nss: specifies the SPI NSS internal state.
+/// This parameter can be one of the following values:
+/// @arg SPI_NSS_Soft: NSS pin control by software
+/// @arg SPI_NSS_Hard: NSS pin control by hardware
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss)
+{
+ (nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the data size for the selected SPI.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param data_size: specifies the SPI data size.
+/// This parameter can be one of the following values:
+/// 0 to 31, 0 = 32b, 1 = 1b, 2 = 2b
+/// @arg DataSize : 0 to 31
+/// @retval None.
+/// @retval None.
+bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size)
+{
+ if (data_size > 32)
+ return false;
+ data_size &= 0x1F;
+ WRITE_REG(spi->ECR, data_size);
+ return true;
+}
+
+//////////////////////////////////////////////////////////////////////////////////
+void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize)
+{
+ CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b);
+ SET_BIT(spi->GCR, (u32)SPI_DataSize);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the data transfer direction in bi-directional mode
+/// for the specified SPI.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param direction: specifies the data transfer direction in
+/// bi-directional mode.
+/// This parameter can be one of the following values:
+/// @arg SPI_Direction_Tx: Selects Tx transmission direction
+/// @arg SPI_Direction_Rx: Selects Rx receive direction
+/// @arg SPI_Disable_Tx: Selects Rx receive direction
+/// @arg SPI_Disable_Rx: Selects Rx receive direction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction)
+{
+ switch (direction) {
+ case SPI_Direction_Rx:
+ SET_BIT(spi->GCR, SPI_GCR_RXEN);
+ break;
+ case SPI_Direction_Tx:
+ SET_BIT(spi->GCR, SPI_GCR_TXEN);
+ break;
+ case SPI_Disable_Rx:
+ CLEAR_BIT(spi->GCR, SPI_GCR_RXEN);
+ break;
+ case SPI_Disable_Tx:
+ CLEAR_BIT(spi->GCR, SPI_GCR_TXEN);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified SPI flag is set or not.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param flag: specifies the SPI flag to check.
+/// This parameter can be one of the following values:
+/// @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag
+/// @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
+/// @arg SPI_FLAG_TXFULL: Tx buffer full flag
+/// @arg SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag.
+/// @retval The new state of SPI_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag)
+{
+// u8 number;
+ return (spi->SR & flag) ? SET : RESET;
+// if (spi->ECR == 8 || spi->ECR == 0)
+// return (spi->SR & SPI_FLAG) ? SET : RESET;
+// else {
+// if ((spi->ECR > 0) && (spi->ECR <= 8))
+// number = 1;
+// else if ((spi->ECR) <= 16)
+// number = 2;
+// else if ((spi->ECR) <= 24)
+// number = 3;
+// else if (((spi->ECR) <= 31) || (spi->ECR == 0))
+// number = 4;
+// return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET;
+// }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified SPI interrupt has occurred or not.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param interrupt: specifies the SPI interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg SPI_IT_TX: Tx buffer empty interrupt
+/// @arg SPI_IT_RX: Rx buffer interrupt
+/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
+/// @arg SPI_IT_RXOVER: RX OVER Error interrupt
+/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
+/// @arg SPI_IT_RXFULL: Rx buffer full interrupt
+/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
+/// @retval The new state of SPI_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
+{
+ return (spi->ISR & interrupt) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the spi interrupt pending bit.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param interrupt: specifies the SPI interrupt pending bit to clear.
+/// @arg SPI_IT_TX: Tx buffer empty interrupt
+/// @arg SPI_IT_RX: Rx buffer interrupt
+/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
+/// @arg SPI_IT_RXOVER: RX OVER Error interrupt
+/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
+/// @arg SPI_IT_RXFULL: Rx buffer full interrupt
+/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
+/// This function clears only ERR intetrrupt pending bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
+{
+ SET_BIT(spi->ICR, interrupt);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI Hole a count Received bytes in next receive process.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param number: specifies the SPI receive Number.
+/// This parament can be 1-65535.
+/// This function can use only in SPI master single receive mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_RxBytes(SPI_TypeDef* spi, u16 number)
+{
+ WRITE_REG(spi->RDNR, number);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief slave mode tx data transmit phase adjust set.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param adjust_value: slave mode tx data transmit phase adjust enum.
+/// This parament can be :
+/// SPI_SlaveAdjust_FAST: fast speed use
+/// SPI_SlaveAdjust_LOW: low speed use
+/// This function can use only in SPI master single receive mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value)
+{
+ (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables all SPI interrupts.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param state: new state of all spi interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified SPI interrupts.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param interrupt: specifies the SPI interrupt sources to be enabled or disabled.
+/// This parameter can be one of the following values:
+/// @arg SPI_IT_TXEPT: Transmitter empty interrupt
+/// @arg SPI_IT_RXFULL: RX FIFO full interrupt
+/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
+/// @arg SPI_IT_RXOERR: Receive overrun error interrupt
+/// @arg SPI_IT_UNDERRUN: underrun interrupt
+/// @arg SPI_IT_RX: Receive data available interrupt
+/// @arg SPI_IT_TX: Transmit FIFO available interrupt
+/// @param state: new state of the specified spi interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the SPI DMA request.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param state: new state of the DMA Request.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set or reset Slave chip csn signal output
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param state: new state of Slave chip csn signal output.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief tx data and rx data phase adjust.
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2.
+/// @param adjust_value: choose adjust mode.
+/// This parament can be :
+/// SPI_DataEdgeAdjust_LOW,
+/// SPI_DataEdgeAdjust_FAST
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value)
+{
+ // master mode
+ if (spi->GCR & SPI_GCR_MODE) {
+ adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
+ }
+ // slave mode
+ else {
+ adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE);
+ }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set or reset i2s
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2, SPI3.
+/// @param state: new state of Slave chip csn signal output.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state)
+{
+ (state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief i2s Config
+/// @param spi: Select the SPI peripheral.
+/// This parameter can be one of the following values:
+/// SPI1, SPI2, SPI3.
+/// @param state: new state of Slave chip csn signal output.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct)
+{
+ u32 i2sdiv = 2;
+ u32 tmpreg = 0;
+ u32 packetlength = 1;
+ u32 result = 0, yushu = 0;
+ u32 sourceclock = 0;
+ RCC_ClocksTypeDef RCC_Clocks;
+
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) {
+ i2sdiv = 2;
+ }
+ else {
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) {
+ packetlength = 1;
+ }
+ else {
+ packetlength = 2;
+ }
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ if((SPI2 == spi) || (SPI3 == spi)) {
+ sourceclock = RCC_Clocks.PCLK1_Frequency;
+ }
+ else {
+ sourceclock = RCC_Clocks.PCLK2_Frequency;
+ }
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) {
+ result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq));
+ yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq));
+ if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) {
+ result = result + 1;
+ }
+ i2sdiv = result;
+ if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) {
+ i2sdiv = 2;
+ }
+ }
+ else {
+ result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
+ yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
+ if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) {
+ result = result + 1;
+ }
+ if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) {
+ i2sdiv = 1;
+ }
+ }
+ }
+ if(I2S_CPOL_High == I2S_InitStruct->I2S_CPOL) {
+ spi->CCTL |= SPI_CCR_CPOL;
+ }
+ else {
+ spi->CCTL &= ~SPI_CCR_CPOL;
+ }
+
+ spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos;
+
+ if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) {
+ spi->GCTL |= SPI_GCR_MODE;
+ }
+ else {
+ spi->GCTL &= ~SPI_GCR_MODE;
+ }
+ if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) {
+ spi->GCTL |= SPI_GCR_TXEN;
+ spi->GCTL &= ~SPI_GCR_RXEN;
+ }
+ else {
+ spi->GCTL &= ~SPI_GCR_TXEN;
+ spi->GCTL |= SPI_GCR_RXEN;
+ }
+// tmpreg = spi->GCTL;
+// tmpreg &= ~(1 << 2);
+// tmpreg |= (u16)(I2S_InitStruct->I2S_Mode);
+// spi->GCTL = tmpreg;
+//
+ tmpreg = 0;
+ tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \
+ (I2S_InitStruct->I2S_MCLKOutput) | \
+ (I2S_CFGR_SPI_I2S) | \
+ (I2S_InitStruct->I2S_Standard) | \
+ (I2S_InitStruct->I2S_DataFormat);
+ spi->CFGR &= ~I2S_CFGR_I2SDIV;
+ spi->CFGR |= tmpreg;
+
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
new file mode 100644
index 00000000..e798bc46
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
@@ -0,0 +1,1875 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_tim.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_TIM_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_tim.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup TIM_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup TIM_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the tim peripheral registers to their default reset values.
+/// @param tim: select the TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DeInit(TIM_TypeDef* tim)
+{
+ switch (*(vu32*)&tim) {
+ case (u32)TIM1:
+ exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1);
+ break;
+ case (u32)TIM2:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2);
+ break;
+ case (u32)TIM3:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3);
+ break;
+ case (u32)TIM4:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4);
+ break;
+
+ case (u32)TIM5:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5);
+ break;
+ case (u32)TIM6:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6);
+ break;
+ case (u32)TIM7:
+ exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7);
+ break;
+
+ case (u32)TIM8:
+ exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8);
+ break;
+
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the tim Time Base Unit peripheral according to
+/// the specified parameters in the init_struct.
+/// @param tim: select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_TimeBaseInitTypeDef
+/// structure that contains the configuration information for the
+/// specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct)
+{
+ MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision);
+
+ if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8))
+ MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode);
+
+ if ((tim == TIM1) || (tim == TIM8) )
+
+ MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter);
+
+ WRITE_REG(tim->ARR, init_struct->TIM_Period);
+ WRITE_REG(tim->PSC, init_struct->TIM_Prescaler);
+ WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the tim Channel1 according to the specified
+/// parameters in the init_struct.
+/// @param tim: select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \
+ ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState));
+ WRITE_REG(tim->CCR1, init_struct->TIM_Pulse);
+
+ if ((tim == TIM1) || (tim == TIM8)) {
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \
+ ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState));
+ MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \
+ ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState));
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the tim Channel2 according to the specified
+/// parameters in the init_struct.
+/// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \
+ (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4));
+ WRITE_REG(tim->CCR2, init_struct->TIM_Pulse);
+
+ if ((tim == TIM1) || (tim == TIM8)) {
+ MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \
+ (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4));
+ MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \
+ (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2));
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the tim Channel3 according to the specified
+/// parameters in the init_struct.
+/// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \
+ (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8));
+ WRITE_REG(tim->CCR3, init_struct->TIM_Pulse);
+
+ if ((tim == TIM1) || (tim == TIM8)) {
+ MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \
+ (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8));
+ MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \
+ (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4));
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the tim Channel4 according to the specified
+/// parameters in the init_struct.
+/// @param tim:select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, (init_struct->TIM_OCMode) << 8);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, \
+ (init_struct->TIM_OCPolarity << 12) | (init_struct->TIM_OutputState << 12));
+ WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
+
+ if ((tim == TIM1) || (tim == TIM8))
+ MODIFY_REG(tim->CR2, TIM_CR2_OIS4, init_struct->TIM_OCIdleState << 6);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the TIM peripheral according to the specified
+/// parameters in the init_struct.
+/// @param tim: select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_ICInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
+{
+ switch (init_struct->TIM_Channel) {
+ case TIM_Channel_1:
+ TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+ TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
+ break;
+ case TIM_Channel_2:
+ TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+ TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
+ break;
+ case TIM_Channel_3:
+ TI3_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+ TIM_SetIC3Prescaler(tim, init_struct->TIM_ICPrescaler);
+ break;
+ case TIM_Channel_4:
+ TI4_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+ TIM_SetIC4Prescaler(tim, init_struct->TIM_ICPrescaler);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the TIM peripheral according to the specified
+/// parameters in the init_struct to measure an external PWM signal.
+/// @param tim: select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_ICInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
+{
+ u16 icoppositepolarity = TIM_ICPolarity_Rising;
+ u16 icoppositeselection = TIM_ICSelection_DirectTI;
+ icoppositepolarity = (init_struct->TIM_ICPolarity == TIM_ICPolarity_Rising) ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising;
+ icoppositeselection =
+ (init_struct->TIM_ICSelection == TIM_ICSelection_DirectTI) ? TIM_ICSelection_IndirectTI : TIM_ICSelection_DirectTI;
+ if (init_struct->TIM_Channel == TIM_Channel_1) {
+ TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+ TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
+ TI2_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
+ TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
+ }
+ else {
+ TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+ TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
+ TI1_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
+ TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+/// the OSSR State and the AOE(automatic output enable).
+/// @param tim: select the TIM
+/// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure that
+/// contains the BDTR Register configuration information for the TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct)
+{
+ tim->BDTR = (u32)init_struct->TIM_OSSRState | init_struct->TIM_OSSIState | init_struct->TIM_LOCKLevel |
+ init_struct->TIM_DeadTime | init_struct->TIM_Break | init_struct->TIM_BreakPolarity |
+ init_struct->TIM_AutomaticOutput;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a TIM_TimeBaseInitTypeDef
+/// structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct)
+{
+ init_struct->TIM_Period = 0xFFFFFFFF;
+ init_struct->TIM_Prescaler = 0x0000;
+ init_struct->TIM_ClockDivision = TIM_CKD_DIV1;
+ init_struct->TIM_CounterMode = TIM_CounterMode_Up;
+ init_struct->TIM_RepetitionCounter = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a TIM_OCInitTypeDef structure which will
+/// be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct)
+{
+ init_struct->TIM_OCMode = TIM_OCMode_Timing;
+ init_struct->TIM_OutputState = TIM_OutputState_Disable;
+ init_struct->TIM_OutputNState = TIM_OutputNState_Disable;
+ init_struct->TIM_Pulse = 0x00000000;
+ init_struct->TIM_OCPolarity = TIM_OCPolarity_High;
+ init_struct->TIM_OCNPolarity = TIM_OCNPolarity_High;
+ init_struct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+ init_struct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct: pointer to a TIM_ICInitTypeDef structure which will
+/// be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct)
+{
+ init_struct->TIM_Channel = TIM_Channel_1;
+ init_struct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ init_struct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ init_struct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ init_struct->TIM_ICFilter = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each init_struct member with its default value.
+/// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure which
+/// will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct)
+{
+ init_struct->TIM_OSSRState = TIM_OSSRState_Disable;
+ init_struct->TIM_OSSIState = TIM_OSSIState_Disable;
+ init_struct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+ init_struct->TIM_DeadTime = 0x00;
+ init_struct->TIM_Break = TIM_Break_Disable;
+ init_struct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+ init_struct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified TIM peripheral.
+/// @param tim: where x can be 1 to 17 to select the tim peripheral.
+/// @param state: new state of the tim peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR1, TIM_CR1_CEN) : CLEAR_BIT(tim->CR1, TIM_CR1_CEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the TIM peripheral Main Outputs.
+/// @param tim: where x can be 1, 8, 16 or 17 to select the tim peripheral.
+/// @param state: new state of the TIM peripheral Main Outputs.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->BDTR, TIM_BDTR_MOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_MOEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified TIM interrupts.
+/// @param tim: select the tim peripheral.
+/// @param it: specifies the TIM interrupts sources to be enabled or disabled.
+/// This parameter can be any combination of the following values:
+/// @arg TIM_IT_Update: TIM update Interrupt source
+/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+/// @arg TIM_IT_COM: TIM Commutation Interrupt source
+/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+/// @arg TIM_IT_Break: TIM Break Interrupt source
+/// @note
+/// - Partial timer can have TIM_IT_Update or TIM_IT_CC1.
+/// - TIM_IT_Break is used only with partial timer.
+/// - TIM_IT_COM is used only with partial timer.
+/// @param state: new state of the TIM interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state) //TIMIT_TypeDef
+{
+ (state) ? SET_BIT(tim->DIER, it) : CLEAR_BIT(tim->DIER, it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim event to be generate by software.
+/// @param tim: select the TIM peripheral.
+/// @param source: specifies the event source.
+/// This parameter can be one or more of the following values:
+/// @arg TIM_EventSource_Update: Timer update Event source
+/// @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+/// @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+/// @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+/// @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+/// @arg TIM_EventSource_COM: Timer COM event source
+/// @arg TIM_EventSource_Trigger: Timer Trigger Event source
+/// @arg TIM_EventSource_Break: Timer Break event source
+/// @note
+/// - TIM_EventSource_COM and TIM_EventSource_Break are used only with partial timer.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source)
+{
+ WRITE_REG(tim->EGR, source);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim's DMA interface.
+/// @param tim: select the TIM peripheral.
+/// @param dma_base: DMA Base address.
+/// This parameter can be one of the following values:
+/// @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+/// TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+/// TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+/// TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+/// TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+/// TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+/// TIM_DMABase_DCR.
+/// @param length: DMA Burst length.
+/// This parameter can be one value between:
+/// TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length)
+{
+ WRITE_REG(tim->DCR, ((u32)dma_base) | ((u32)length));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim's DMA Requests.
+/// @param tim: select the TIM peripheral.
+/// @param source: specifies the DMA Request sources.
+/// This parameter can be any combination of the following values:
+/// @arg TIM_DMA_Update: TIM update Interrupt source
+/// @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+/// @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+/// @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+/// @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+/// @arg TIM_DMA_COM: TIM Commutation DMA source
+/// @arg TIM_DMA_Trigger: TIM Trigger DMA source
+/// @param state: new state of the DMA Request sources.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->DIER, source) : CLEAR_BIT(tim->DIER, source);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim internal Clock
+/// @param tim: select the TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_InternalClockConfig(TIM_TypeDef* tim)
+{
+ CLEAR_BIT(tim->SMCR, TIM_SMCR_SMS);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Internal Trigger as External Clock
+/// @param tim: select the TIM peripheral.
+/// @param source: Trigger source.
+/// This parameter can be one of the following values:
+/// @arg TIM_TS_ITR0: Internal Trigger 0
+/// @arg TIM_TS_ITR1: Internal Trigger 1
+/// @arg TIM_TS_ITR2: Internal Trigger 2
+/// @arg TIM_TS_ITR3: Internal Trigger 3
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source)
+{
+ TIM_SelectInputTrigger(tim, source);
+ SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Trigger as External Clock
+/// @param tim: select the TIM peripheral.
+/// @param source: Trigger source.
+/// This parameter can be one of the following values:
+/// @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+/// @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+/// @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+/// @param polarity: specifies the TIx Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @param filter : specifies the filter value.
+/// This parameter must be a value between 0x0 and 0xF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter)
+{
+ (source == TIM_TIxExternalCLK1Source_TI2) ? (TI2_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter))
+ : (TI1_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter));
+ TIM_SelectInputTrigger(tim, (TIMTS_TypeDef)source);
+ SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim External Trigger (ETR).
+/// @param tim: select the TIM peripheral.
+/// @param psc: The external Trigger Prescaler.
+/// This parameter can be one of the following values:
+/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+/// @param polarity: The external Trigger Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+/// @param filter: External Trigger Filter.
+/// This parameter must be a value between 0x00 and 0x0F
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
+{
+ CLEAR_BIT(tim->SMCR, TIM_SMCR_ECEN);
+ MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity);
+ MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc);
+ MODIFY_REG(tim->SMCR, TIM_SMCR_ETF, filter << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the External clock Mode1
+/// @param tim: select the TIM peripheral.
+/// @param psc: The external Trigger Prescaler.
+/// This parameter can be one of the following values:
+/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+/// @param polarity: The external Trigger Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+/// @param filter: External Trigger Filter.
+/// This parameter must be a value between 0x00 and 0x0F
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
+{
+ TIM_ETRConfig(tim, psc, polarity, filter);
+ MODIFY_REG(tim->SMCR, TIM_SMCR_TS | TIM_SMCR_SMS, ((u32)TIM_TS_ETRF) | ((u32)TIM_SlaveMode_External1));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the External clock Mode2
+/// @param tim: select the TIM peripheral.
+/// @param psc: The external Trigger Prescaler.
+/// This parameter can be one of the following values:
+/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+/// @param polarity: The external Trigger Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+/// @param filter: External Trigger Filter.
+/// This parameter must be a value between 0x00 and 0x0F
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
+{
+ TIM_ETRConfig(tim, psc, polarity, filter);
+ SET_BIT(tim->SMCR, TIM_SMCR_ECEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Prescaler.
+/// @param tim: select the TIM peripheral.
+/// @param prescaler: specifies the Prescaler Register value
+/// @param reloadMode: specifies the TIM Prescaler Reload mode
+/// This parameter can be one of the following values:
+/// @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+/// @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reloadMode)
+{
+ WRITE_REG(tim->PSC, prescaler);
+ WRITE_REG(tim->EGR, reloadMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Specifies the tim Counter Mode to be used.
+/// @param tim:select the TIM peripheral.
+/// @param counter_mode: specifies the Counter Mode to be used
+/// This parameter can be one of the following values:
+/// @arg TIM_CounterMode_Up: TIM Up Counting Mode
+/// @arg TIM_CounterMode_Down: TIM Down Counting Mode
+/// @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+/// @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+/// @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode)
+{
+ MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, counter_mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the Input Trigger source
+/// @param tim: select the TIM peripheral.
+/// @param source: The Input Trigger source.
+/// This parameter can be one of the following values:
+/// @arg TIM_TS_ITR0: Internal Trigger 0
+/// @arg TIM_TS_ITR1: Internal Trigger 1
+/// @arg TIM_TS_ITR2: Internal Trigger 2
+/// @arg TIM_TS_ITR3: Internal Trigger 3
+/// @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+/// @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+/// @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+/// @arg TIM_TS_ETRF: External Trigger input
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source)
+{
+ MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Encoder Interface.
+/// @param tim: select the TIM peripheral.
+/// @param encoder_mode: specifies the tim Encoder Mode.
+/// This parameter can be one of the following values:
+/// @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+/// @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+/// @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+/// on the level of the other input.
+/// @param ic1_polarity: specifies the IC1 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Falling: IC Falling edge.
+/// @arg TIM_ICPolarity_Rising: IC Rising edge.
+/// @param ic2_polarity: specifies the IC2 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Falling: IC Falling edge.
+/// @arg TIM_ICPolarity_Rising: IC Rising edge.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim,
+ TIMSMSENCODER_Typedef encoder_mode,
+ TIMICP_Typedef ic1_polarity,
+ TIMICP_Typedef ic2_polarity)
+{
+ MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, encoder_mode);
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_CC2S, TIM_CCMR1_CC1S_DIRECTTI | TIM_CCMR1_CC2S_DIRECTTI);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC2P, ic1_polarity | (ic2_polarity << 4));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces the tim output 1 waveform to active or inactive level.
+/// @param tim: select the TIM peripheral.
+/// @param forced_action: specifies the forced Action to be set to the output waveform.
+/// This parameter can be one of the following values:
+/// @arg TIM_ForcedAction_Active: Force active level on OC1REF
+/// @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, forced_action);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces the tim output 2 waveform to active or inactive level.
+/// @param tim: select the TIM peripheral.
+/// @param forced_action: specifies the forced Action to be set to the output waveform.
+/// This parameter can be one of the following values:
+/// @arg TIM_ForcedAction_Active: Force active level on OC2REF
+/// @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, forced_action << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces the tim output 3 waveform to active or inactive level.
+/// @param tim: select the TIM peripheral.
+/// @param forced_action: specifies the forced Action to be set to the output waveform.
+/// This parameter can be one of the following values:
+/// @arg TIM_ForcedAction_Active: Force active level on OC3REF
+/// @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, forced_action);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Forces the tim output 4 waveform to active or inactive level.
+/// @param tim: select the TIM peripheral.
+/// @param forced_action: specifies the forced Action to be set to the output waveform.
+/// This parameter can be one of the following values:
+/// @arg TIM_ForcedAction_Active: Force active level on OC4REF
+/// @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, forced_action << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables tim peripheral Preload register on ARR.
+/// @param tim: select the TIM peripheral.
+/// @param state: new state of the tim peripheral Preload register
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR1, TIM_CR1_ARPEN) : CLEAR_BIT(tim->CR1, TIM_CR1_ARPEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the TIM peripheral Commutation event.
+/// @param tim: select the tim peripheral.
+/// @param state: new state of the Commutation event.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR2, TIM_CR2_CCUS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCUS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the tim peripheral Capture Compare DMA source.
+/// @param tim: select the TIM peripheral.
+/// @param state: new state of the Capture Compare DMA source
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR2, TIM_CR2_CCDS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCDS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+/// @param tim: select the tim peripheral.
+/// @param state: new state of the Capture Compare Preload Control bit
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR2, TIM_CR2_CCPC) : CLEAR_BIT(tim->CR2, TIM_CR2_CCPC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim peripheral Preload register on CCR1.
+/// @param tim: select the TIM peripheral.
+/// @param preload: new state of the tim peripheral Preload register
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPreload_Enable
+/// @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1PEN, preload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim peripheral Preload register on CCR2.
+/// @param tim: select the TIM peripheral.
+/// @param preload: new state of the tim peripheral Preload register
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPreload_Enable
+/// @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2PEN, preload << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim peripheral Preload register on CCR3.
+/// @param tim: select the TIM peripheral.
+/// @param preload: new state of the tim peripheral Preload register
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPreload_Enable
+/// @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3PEN, preload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim peripheral Preload register on CCR4.
+/// @param tim: select the TIM peripheral.
+/// @param preload: new state of the tim peripheral Preload register
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPreload_Enable
+/// @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4PEN, preload << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Output Compare 1 Fast feature.
+/// @param tim: select the TIM peripheral.
+/// @param fast: new state of the Output Compare Fast Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCFast_Enable: TIM output compare fast enable
+/// @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1FEN, fast);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Output Compare 2 Fast feature.
+/// @param tim: select the TIM peripheral.
+/// @param fast: new state of the Output Compare Fast Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCFast_Enable: TIM output compare fast enable
+/// @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2FEN, fast << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Output Compare 3 Fast feature.
+/// @param tim: select the TIM peripheral.
+/// @param fast: new state of the Output Compare Fast Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCFast_Enable: TIM output compare fast enable
+/// @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3FEN, fast);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Output Compare 4 Fast feature.
+/// @param tim: select the TIM peripheral.
+/// @param fast: new state of the Output Compare Fast Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCFast_Enable: TIM output compare fast enable
+/// @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4FEN, fast << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears or safeguards the OCREF1 signal on an external event
+/// @param tim: select the TIM peripheral.
+/// @param clear: new state of the Output Compare Clear Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCClear_Enable: TIM Output clear enable
+/// @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1CEN, clear);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears or safeguards the OCREF2 signal on an external event
+/// @param tim: select the TIM peripheral.
+/// @param clear: new state of the Output Compare Clear Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCClear_Enable: TIM Output clear enable
+/// @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2CEN, clear << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears or safeguards the OCREF3 signal on an external event
+/// @param tim: select the TIM peripheral.
+/// @param clear: new state of the Output Compare Clear Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCClear_Enable: TIM Output clear enable
+/// @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3CEN, clear);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears or safeguards the OCREF4 signal on an external event
+/// @param tim: select the TIM peripheral.
+/// @param clear: new state of the Output Compare Clear Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCClear_Enable: TIM Output clear enable
+/// @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4CEN, clear << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 1 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC1 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPolarity_High: Output Compare active high
+/// @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1P, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Channel 1N polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC1N Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCNPolarity_High: Output Compare active high
+/// @arg TIM_OCNPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1NP, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 2 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC2 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPolarity_High: Output Compare active high
+/// @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC2P, polarity << 4);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Channel 2N polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC2N Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCNPolarity_High: Output Compare active high
+/// @arg TIM_OCNPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC2NP, polarity << 4);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 3 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC3 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPolarity_High: Output Compare active high
+/// @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC3P, polarity << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Channel 3N polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC3N Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCNPolarity_High: Output Compare active high
+/// @arg TIM_OCNPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC3NP, polarity << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 4 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC4 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPolarity_High: Output Compare active high
+/// @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC4P, polarity << 12);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the TIM Capture Compare Channel x.
+/// @param tim: select the TIM peripheral.
+/// @param channel: specifies the TIM Channel
+/// This parameter can be one of the following values:
+/// @arg TIM_Channel_1: TIM Channel 1
+/// @arg TIM_Channel_2: TIM Channel 2
+/// @arg TIM_Channel_3: TIM Channel 3
+/// @arg TIM_Channel_4: TIM Channel 4
+/// @arg TIM_Channel_5: TIM Channel 5(Only for some MM32 TIM1/8)
+/// @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+/// This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1EN << channel, ccx_en << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the TIM Capture Compare Channel xN.
+/// @param tim: select the TIM peripheral.
+/// @param channel: specifies the TIM Channel
+/// This parameter can be one of the following values:
+/// @arg TIM_Channel_1: TIM Channel 1
+/// @arg TIM_Channel_2: TIM Channel 2
+/// @arg TIM_Channel_3: TIM Channel 3
+/// @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+/// This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en)
+{
+ if (channel != TIM_Channel_4)
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1NEN << channel, ccxn_en << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the TIM Output Compare Mode.
+/// @note This function disables the selected channel before changing the Output
+/// Compare Mode.
+/// User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+/// @param tim: select the TIM peripheral.
+/// @param channel: specifies the TIM Channel
+/// This parameter can be one of the following values:
+/// @arg TIM_Channel_1: TIM Channel 1
+/// @arg TIM_Channel_2: TIM Channel 2
+/// @arg TIM_Channel_3: TIM Channel 3
+/// @arg TIM_Channel_4: TIM Channel 4
+/// @param mode: specifies the TIM Output Compare Mode.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCMode_Timing
+/// @arg TIM_OCMode_Active
+/// @arg TIM_OCMode_Toggle
+/// @arg TIM_OCMode_PWM1
+/// @arg TIM_OCMode_PWM2
+/// @arg TIM_ForcedAction_Active
+/// @arg TIM_ForcedAction_InActive
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode)
+{
+ CLEAR_BIT(tim->CCER, TIM_CCER_CC1EN << channel);
+ switch (channel) {
+ case TIM_Channel_1:
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, mode);
+ break;
+ case TIM_Channel_2:
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, mode << 8);
+ break;
+ case TIM_Channel_3:
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, mode);
+ break;
+ case TIM_Channel_4:
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, mode << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or Disables the tim Update event.
+/// @param tim: select the TIM peripheral.
+/// @param state: new state of the tim UDIS bit
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR1, TIM_CR1_UDIS) : CLEAR_BIT(tim->CR1, TIM_CR1_UDIS);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Update Request Interrupt source.
+/// @param tim: select the TIM peripheral.
+/// @param source: specifies the Update source.
+/// This parameter can be one of the following values:
+/// @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+/// or the setting of UG bit, or an update generation
+/// through the slave mode controller.
+/// @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source)
+{
+ MODIFY_REG(tim->CR1, TIM_CR1_URS, source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim's Hall sensor interface.
+/// @param tim: select the TIM peripheral.
+/// @param state: new state of the tim Hall sensor interface.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->CR2, TIM_CR2_TI1S) : CLEAR_BIT(tim->CR2, TIM_CR2_TI1S);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the tim's One Pulse Mode.
+/// @param tim: select the TIM peripheral.
+/// @param mode: specifies the OPM Mode to be used.
+/// This parameter can be one of the following values:
+/// @arg TIM_OPMode_Single
+/// @arg TIM_OPMode_Repetitive
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode)
+{
+ MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the tim Trigger Output Mode.
+/// @param tim:select the TIM peripheral.
+/// @param source: specifies the Trigger Output source.
+/// This paramter can be one of the following values:
+/// - For all tim
+/// @arg TIM_TRIGSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
+/// @arg TIM_TRIGSource_Enable: The Counter Enable CEN is used as the trigger output (TRIG).
+/// @arg TIM_TRIGSource_Update: The update event is selected as the trigger output (TRIG).
+/// @arg TIM_TRIGSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+/// is to be set, as soon as a capture or compare match occurs (TRIG).
+/// @arg TIM_TRIGSource_OC1Ref: OC1REF signal is used as the trigger output (TRIG).
+/// @arg TIM_TRIGSource_OC2Ref: OC2REF signal is used as the trigger output (TRIG).
+/// @arg TIM_TRIGSource_OC3Ref: OC3REF signal is used as the trigger output (TRIG).
+/// @arg TIM_TRIGSource_OC4Ref: OC4REF signal is used as the trigger output (TRIG).
+///
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source)
+{
+ MODIFY_REG(tim->CR2, TIM_CR2_MMS, source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the tim Slave Mode.
+/// @param tim: select the TIM peripheral.
+/// @param mode: specifies the Timer Slave Mode.
+/// This parameter can be one of the following values:
+/// @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+/// the counter and triggers an update of the registers.
+/// @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
+/// @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
+/// @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode)
+{
+ MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets or Resets the tim Master/Slave Mode.
+/// @param tim: select the TIM peripheral.
+/// @param mode: specifies the Timer Master Slave Mode.
+/// This parameter can be one of the following values:
+/// @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+/// and its slaves (through TRIG).
+/// @arg TIM_MasterSlaveMode_Disable: No action
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode)
+{
+ MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Counter Register value
+/// @param tim: select the TIM peripheral.
+/// @param auto_reload: specifies the Counter register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload)
+{
+ WRITE_REG(tim->ARR, auto_reload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Input Capture 1 prescaler.
+/// @param tim: select the TIM peripheral.
+/// @param psc: specifies the Input Capture1 prescaler new value.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPSC_DIV1: no prescaler
+/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Input Capture 2 prescaler.
+/// @param tim: select the TIM peripheral.
+/// @param psc: specifies the Input Capture2 prescaler new value.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPSC_DIV1: no prescaler
+/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC2PSC, psc << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Input Capture 3 prescaler.
+/// @param tim: select the TIM peripheral.
+/// @param psc: specifies the Input Capture3 prescaler new value.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPSC_DIV1: no prescaler
+/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Input Capture 4 prescaler.
+/// @param tim: select the TIM peripheral.
+/// @param psc: specifies the Input Capture4 prescaler new value.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPSC_DIV1: no prescaler
+/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC4PSC, psc << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Clock Division value.
+/// @param tim: select
+/// the TIM peripheral.
+/// @param clock_div: specifies the clock division value.
+/// This parameter can be one of the following value:
+/// @arg TIM_CKD_DIV1: TDTS = Tck_tim
+/// @arg TIM_CKD_DIV2: TDTS = 2 * Tck_tim
+/// @arg TIM_CKD_DIV4: TDTS = 4 * Tck_tim
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div)
+{
+ MODIFY_REG(tim->CR1, TIM_CR1_CKD, clock_div);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Counter Register value
+/// @param tim: select the TIM peripheral.
+/// @param counter: specifies the Counter register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCounter(TIM_TypeDef* tim, u32 counter)
+{
+ if ((tim == TIM2) || (tim == TIM5))
+ WRITE_REG(tim->CNT, (u32)counter);
+ else
+ WRITE_REG(tim->CNT, (u16)counter);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Capture Compare1 Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare)
+{
+ if ((tim == TIM2) || (tim == TIM5))
+ WRITE_REG(tim->CCR1, (u32)compare);
+ else
+ WRITE_REG(tim->CCR1, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Capture Compare2 Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare2 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare)
+{
+ if ((tim == TIM2) || (tim == TIM5))
+ WRITE_REG(tim->CCR2, (u32)compare);
+ else
+ WRITE_REG(tim->CCR2, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Capture Compare3 Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare3 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare)
+{
+ if ((tim == TIM2) || (tim == TIM5))
+ WRITE_REG(tim->CCR3, (u32)compare);
+ else
+ WRITE_REG(tim->CCR3, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Capture Compare4 Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare4 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare)
+{
+ if ((tim == TIM2) || (tim == TIM5))
+ WRITE_REG(tim->CCR4, (u32)compare);
+ else
+ WRITE_REG(tim->CCR4, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Input Capture 1 value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 1 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture1(TIM_TypeDef* tim)
+{
+ return tim->CCR1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Input Capture 2 value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 2 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture2(TIM_TypeDef* tim)
+{
+ return tim->CCR2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Input Capture 3 value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 3 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture3(TIM_TypeDef* tim)
+{
+ return tim->CCR3;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Input Capture 4 value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 4 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture4(TIM_TypeDef* tim)
+{
+ return tim->CCR4;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Counter value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Counter Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCounter(TIM_TypeDef* tim)
+{
+ return tim->CNT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Prescaler value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Prescaler Register value.
+////////////////////////////////////////////////////////////////////////////////
+u16 TIM_GetPrescaler(TIM_TypeDef* tim)
+{
+ return tim->PSC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified TIM flag is set or not.
+/// @param tim: select the TIM peripheral.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg TIM_FLAG_Update: TIM update Flag
+/// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+/// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+/// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+/// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+/// @arg TIM_FLAG_COM: TIM Commutation Flag
+/// @arg TIM_FLAG_Trigger: TIM Trigger Flag
+/// @arg TIM_FLAG_Break: TIM Break Flag
+/// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+/// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+/// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+/// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+/// @note
+/// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+/// - TIM_FLAG_Break is used only with TIM1 and TIM8.
+/// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval State: The new state of TIM_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
+{
+ return ((tim->SR & flag) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the tim's pending flags.
+/// @param tim: select the TIM peripheral.
+/// @param flag: specifies the flag bit to clear.
+/// This parameter can be any combination of the following values:
+/// @arg TIM_FLAG_Update: TIM update Flag
+/// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+/// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+/// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+/// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+/// @arg TIM_FLAG_COM: TIM Commutation Flag
+/// @arg TIM_FLAG_Trigger: TIM Trigger Flag
+/// @arg TIM_FLAG_Break: TIM Break Flag
+/// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+/// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+/// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+/// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+/// @note
+/// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+/// - TIM_FLAG_Break is used only with TIM1 and TIM8.
+/// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
+{
+ CLEAR_BIT(tim->SR, flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the TIM interrupt has occurred or not.
+/// @param tim: select the TIM peripheral.
+/// @param it: specifies the TIM interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg TIM_IT_Update: TIM update Interrupt source
+/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+/// @arg TIM_IT_COM: TIM Commutation Interrupt source
+/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+/// @arg TIM_IT_Break: TIM Break Interrupt source
+/// @note
+/// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+/// - TIM_IT_Break is used only with TIM1 and TIM8.
+/// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval State: The new state of the TIM_IT(SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it)
+{
+ return (((tim->SR & it) && (tim->DIER & it)) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the tim's interrupt pending bits.
+/// @param tim: select the TIM peripheral.
+/// @param it: specifies the pending bit to clear.
+/// This parameter can be any combination of the following values:
+/// @arg TIM_IT_Update: TIM1 update Interrupt source
+/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+/// @arg TIM_IT_COM: TIM Commutation Interrupt source
+/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+/// @arg TIM_IT_Break: TIM Break Interrupt source
+/// @note
+/// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+/// - TIM_IT_Break is used only with TIM1 and TIM8.
+/// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it) //TIMIT_TypeDef
+{
+ CLEAR_BIT(tim->SR, it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 1 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the IC1 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+ (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 2 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the IC2 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+ (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 3 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the IC3 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+ (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 4 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the IC4 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+ (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P);
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim Capture Compare 5 Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare5 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare)
+{
+ WRITE_REG(tim->CCR5, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Gets the tim Input Capture 5 value.
+/// @param tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 5 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture5(TIM_TypeDef* tim)
+{
+ return tim->CCR5;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the tim Channel5 according to the specified
+/// parameters in the init_struct.
+/// @param tim: select the TIM peripheral.
+/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
+/// contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+ MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5M, (init_struct->TIM_OCMode) << 4);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC5EN | TIM_CCER_CC5P,
+ (init_struct->TIM_OCPolarity << 16) | (init_struct->TIM_OutputState << 16));
+ WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
+
+ if ((tim == TIM1) || (tim == TIM8))
+ MODIFY_REG(tim->CR2, TIM_CR2_OIS5, init_struct->TIM_OCIdleState << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim peripheral Preload register on CCR5.
+/// @param tim: select the TIM peripheral.
+/// @param preload: new state of the tim peripheral Preload register
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPreload_Enable
+/// @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+ MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5PEN, preload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim channel 5 polarity.
+/// @param tim: select the TIM peripheral.
+/// @param polarity: specifies the OC5 Polarity
+/// This parameter can be one of the following values:
+/// @arg TIM_OCPolarity_High: Output Compare active high
+/// @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+ MODIFY_REG(tim->CCER, TIM_CCER_CC5P, polarity << 16);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configures the tim Output Compare 5 Fast feature.
+/// @param tim: select the TIM peripheral.
+/// @param fast: new state of the Output Compare Fast Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCFast_Enable: TIM output compare fast enable
+/// @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+ MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5FEN, fast);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears or safeguards the OCREF4 signal on an external event
+/// @param tim: select the TIM peripheral.
+/// @param clear: new state of the Output Compare Clear Enable Bit.
+/// This parameter can be one of the following values:
+/// @arg TIM_OCClear_Enable: TIM Output clear enable
+/// @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+ MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5CEN, clear);
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the tim complementary PWM output Status after Break.
+/// @param tim: select the TIM peripheral.
+/// @param state: new state of the tim complementary PWM output.
+/// This parameter can be: ENABLE or DISABLE.
+/// @arg ENABLE: Direct output enable, no longer waiting for output after dead time.
+/// @arg DISABLE: Direct output disable, output waiting for dead time.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state)
+{
+ (state) ? SET_BIT(tim->BDTR, TIM_BDTR_DOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_DOEN);
+}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Private_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configure the TI1 as Input.
+/// @param tim: select the TIM peripheral.
+/// @param polarity : The Input Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @param selection: specifies the input to be used.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+/// @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+/// @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+/// @param filter: Specifies the Input Capture Filter.
+/// This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_IC1F, (filter << 4) | selection);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC1EN | TIM_CCER_CC1P, polarity | TIM_CCER_CC1EN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configure the TI2 as Input.
+/// @param tim: select the TIM peripheral.
+/// @param polarity : The Input Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @param selection: specifies the input to be used.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+/// @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+/// @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+/// @param filter: Specifies the Input Capture Filter.
+/// This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+ MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC2S | TIM_CCMR1_IC2F, (filter << 12) | (selection << 8));
+ MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, (polarity << 4) | TIM_CCER_CC2EN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configure the TI3 as Input.
+/// @param tim: select the TIM peripheral.
+/// @param polarity : The Input Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @param selection: specifies the input to be used.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+/// @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+/// @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+/// @param filter: Specifies the Input Capture Filter.
+/// This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC3S | TIM_CCMR2_IC3F, (filter << 4) | selection);
+ MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, (polarity << 8) | TIM_CCER_CC3EN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Configure the TI4 as Input.
+/// @param tim: select the TIM peripheral.
+/// @param polarity : The Input Polarity.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICPolarity_Rising
+/// @arg TIM_ICPolarity_Falling
+/// @param selection: specifies the input to be used.
+/// This parameter can be one of the following values:
+/// @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+/// @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+/// @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+/// @param filter: Specifies the Input Capture Filter.
+/// This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+ MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC4S | TIM_CCMR2_IC4F, (filter << 12) | (selection << 8));
+ MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, (polarity << 12) | TIM_CCER_CC4EN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified TIM PWM shift /DMA reqeat.
+/// @param tim: select the tim peripheral.
+/// @param it: Specifies the TIM PWM shift channel to enable or disable.
+/// This parameter can be any combination of the following values:
+/// @arg TIM_PDER_CCDREPE: TIM DMA reqeat enable bit
+/// @arg TIM_PDER_CCR1SHIFTEN: TIM Channel 1 output PWM phase shift enable bit
+/// @arg TIM_PDER_CCR2SHIFTEN: TIM Channel 2 output PWM phase shift enable bit
+/// @arg TIM_PDER_CCR3SHIFTEN: TIM Channel 3 output PWM phase shift enable bit
+/// @arg TIM_PDER_CCR4SHIFTEN: TIM Channel 4 output PWM phase shift enable bit
+/// @arg TIM_PDER_CCR5SHIFTEN: TIM Channel 5 output PWM phase shift enable bit
+/// @param state: new state of the TIM interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)//TIMIT_TypeDef
+{
+ (state) ? SET_BIT(tim->PDER, it) : CLEAR_BIT(tim->PDER, it);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim CCR1 shift Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift)
+{
+ if (tim == TIM1)
+ WRITE_REG(tim->CCR1FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim CCR2 shift Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift)
+{
+ if (tim == TIM1)
+ WRITE_REG(tim->CCR2FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim CCR3 shift Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift)
+{
+ if (tim == TIM1)
+ WRITE_REG(tim->CCR3FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim CCR4 shift Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift)
+{
+ if (tim == TIM1)
+ WRITE_REG(tim->CCR4FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the tim CCR5 shift Register value
+/// @param tim: select the TIM peripheral.
+/// @param compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift)
+{
+ if (tim == TIM1)
+ WRITE_REG(tim->CCR5FALL, (u32)shift);
+
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
new file mode 100644
index 00000000..2a0578f9
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
@@ -0,0 +1,502 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_uart.c
+/// @file hal_uart.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_UART_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_uart.h"
+#include "hal_gpio.h"
+#include "hal_dma.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup UART_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup UART_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the uart peripheral registers to their
+/// default reset values.
+/// @param uart: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_DeInit(UART_TypeDef* uart)
+{
+
+
+ if(UART2 == uart) {
+ exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
+ }
+ if(UART1 == uart) {
+ exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
+ }
+ if(UART3 == uart) {
+ exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
+ }
+ if(UART4 == uart) {
+ exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
+ }
+ if(UART5 == uart) {
+ exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
+ }
+ if(UART6 == uart) {
+ exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
+ }
+ if(UART7 == uart) {
+ exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
+ }
+ if(UART8 == uart) {
+ exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
+ }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Initializes the uart peripheral according to the specified
+/// parameters in the UART_InitStruct .
+/// @param uart: Select the UART or the UART peripheral.
+/// @param init_struct: pointer to a UART_InitTypeDef structure
+/// that contains the configuration information for the
+/// specified UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct)
+{
+ u32 apbclock = 0x00;
+ // UART CCR Configuration
+ MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength);
+
+
+ MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits);
+
+ MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity);
+
+ // UART GCR Configuration
+ MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode);
+ MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl);
+
+ //UART BRR Configuration
+ //Configure the UART Baud Rate
+ if (uart == UART1) {
+
+ apbclock = RCC_GetPCLK2Freq();
+ }
+ else {
+ apbclock = RCC_GetPCLK1Freq();
+ }
+ // Determine the UART_baud
+ uart->BRR = (apbclock / init_struct->BaudRate) / 16;
+ uart->FRA = (apbclock / init_struct->BaudRate) % 16;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Fills each UART_InitStruct member with its default value.
+/// @param init_struct: pointer to a UART_InitTypeDef structure
+/// which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_StructInit(UART_InitTypeDef* init_struct)
+{
+ // UART_InitStruct members default value
+ init_struct->BaudRate = 9600;
+ init_struct->WordLength = UART_WordLength_8b;
+ init_struct->StopBits = UART_StopBits_1;
+ init_struct->Parity = UART_Parity_No;
+ init_struct->Mode = UART_GCR_RX | UART_GCR_TX;
+ init_struct->HWFlowControl = UART_HWFlowControl_None;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified UART peripheral.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the uart peripheral.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Cmd(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the specified UART interrupts.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param it: specifies the UART interrupt sources to be
+/// enabled or disabled.
+/// This parameter can be one of the following values:
+/// @arg UART_IT_ERR: Error interrupt(Frame error,)
+/// @arg UART_IT_PE: Parity Error interrupt
+/// @arg UART_OVER_ERR: overrun Error interrupt
+/// @arg UART_IT_RXIEN: Receive Data register interrupt
+/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
+///
+/// @param state: new state of the specified uart interrupts.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state)
+{
+ (state) ? (uart->IER |= it) : (uart->IER &= ~it);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the UART DMA interface.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param dma_request: specifies the DMA request.
+/// This parameter can be any combination of the following values:
+/// @arg UART_DMAReq_EN: UART DMA transmit request
+///
+/// @param state: new state of the DMA Request sources.
+/// This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state)
+{
+ MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Transmits single data through the uart peripheral.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param Data: the data to transmit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SendData(UART_TypeDef* uart, u16 value)
+{
+ // Transmit Data
+ WRITE_REG(uart->TDR, (value & 0xFFU));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the most recent received data by the uart peripheral.
+/// @param uart: Select the UART or the UART peripheral.
+/// @retval The received data.
+////////////////////////////////////////////////////////////////////////////////
+u16 UART_ReceiveData(UART_TypeDef* uart)
+{
+ // Receive Data
+ return (u16)(uart->RDR & 0xFFU);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified UART flag is set or not.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param flag: specifies the flag to check.
+/// This parameter can be one of the following values:
+/// @arg UART_FLAG_TXEMPTY: Transmit data register empty flag
+/// @arg UART_FLAG_TXFULL: Transmit data buffer full
+/// @arg UART_FLAG_RXAVL: RX Buffer has a byte flag
+/// @arg UART_FLAG_TXEPT: tx and shifter are emptys flag
+/// @retval The new state of UART_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag)
+{
+ return (uart->CSR & flag) ? SET : RESET;
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the specified UART interrupt has occurred or not.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param it: specifies the UART interrupt source to check.
+/// This parameter can be one of the following values:
+/// @arg UART_IT_ERR: Error interrupt(Frame error,)
+/// @arg UART_IT_PE: Parity Error interrupt
+/// @arg UART_OVER_ERR: overrun Error interrupt
+/// @arg UART_IT_RXIEN: Receive Data register interrupt
+/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
+/// @retval The new state of UART_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it)
+{
+ return (uart->ISR & it) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears the uart interrupt pending bits.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param it: specifies the interrupt pending bit to clear.
+/// This parameter can be one of the following values:
+/// @arg UART_IT_ERR: Error interrupt(Frame error,)
+/// @arg UART_IT_PE: Parity Error interrupt
+/// @arg UART_OVER_ERR: overrun Error interrupt
+/// @arg UART_IT_RXIEN: Receive Data register interrupt
+/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it)
+{
+ //clear UART_IT pendings bit
+ uart->ICR = it;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Selects the UART WakeUp method.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param mode: specifies the UART wakeup method.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode)
+{
+ MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Determines if the UART is in mute mode or not.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the UART mute mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the address of the UART Rx Address.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param address: Indicates the address of the UART Rx Address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetRXAddress(UART_TypeDef* uart, u8 address)
+{
+ MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the address of the UART Rx MASK.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param address: Indicates the address of the UART Rx MASK.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetRXMASK(UART_TypeDef* uart, u8 address)
+{
+ MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ENBALE or DISABLE the UART's 9bit.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the UART 9 bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the UART's 9bit Level.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the UART 9 bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the UART's 9bit Polarity.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param polarity: new state of the UART 9 bit Polarity.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity)
+{
+ MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Set the UART's 9bit Automatic Toggle.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the UART 9 bit Automatic Toggle.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the UART Half Duplex communication.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the UART Communication.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the specified UART guard time.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param guard_time: specifies the guard time.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time)
+{
+ MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos);
+ // Clear the UART Guard time
+ // uart->SCR &= SCR_SCFCNT_Mask;
+ // Set the UART guard time
+ // uart->SCR |= (u16)((u16)guard_time << 0x04);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables the UART's Smart Card mode.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the Smart Card mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables or disables NACK transmission.
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the NACK transmission.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state)
+{
+ MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Transmits break characters.
+/// @param uart: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SendBreak(UART_TypeDef* uart)
+{
+ SET_BIT(uart->CCR, UART_CCR_BRK);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enable or Disable Auto Baud-Rate Detection
+/// @param uart: Select the UART or the UART peripheral.
+/// @param state: new state of the UART AutoBaudRate Detection.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state)
+{
+ state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief AutoBaudRate.
+/// @param uart: Select the UART or the UART peripheral.
+/// value: special character.
+/// state: ENABLE/DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state)
+{
+ CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN);
+ //This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0).
+
+ if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) {
+ //UART measures the duration of the start bit (falling edge) to first rising edge
+ //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = one bit
+ //___ _ _______
+ // |_|1 x x x x x x x| = Bxxxx xxx1 F to U = 1 start bit
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 );
+ }
+ else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE)) {
+ //UART measures the duration of the start bit (falling edge) to first rising edge
+ //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = two bit
+ //___ _ _______
+ // |_ _|1 x x x x x x| = Bxxxx xx10 F to U = 2
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1);
+ }
+ else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) {
+ //UART measures the duration of the start bit (falling edge) to first rising edge
+ //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = four bit
+ //___ _ _______
+ // |_ _ _ _|1 x x x x| = Bxxxx 1000 F to U = 4
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2);
+ }
+ else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80)) {
+ //UART measures the duration of the start bit (falling edge) to first rising edge
+ //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = eight bit
+ //___ _ ______
+ // |_ _ _ _ _ _ _ _|1 = B1000 0000 F to U = 8
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3);
+ }
+ else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) {
+ //UART measures the duration of the start bit (falling edge) to next falling edge
+ //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = two bit
+ //___ _ ______
+ // |_|1|_|x x x x x x| = Bxxxx xx01 F to F = 2 0x55 and Falling to Falling
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_BITCNT_MODE1);
+ }
+ else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7)) {
+ //UART measures the duration of the start bit (falling edge) to next falling edge
+ //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = four bit
+ //___ _ _ _ ______
+ // |_|1 1 1|_|x x x x| = Bxxxx 0111 F to F = 4
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_BITCNT_MODE2);
+ }
+ else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) {
+ //UART measures the duration of the start bit (falling edge) to next falling edge
+ //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit
+ //___ _ _ _ _ _ _ _ ______
+ // |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_BITCNT_MODE3);
+ }
+
+ else {
+ //UART measures the duration of the start bit (falling edge) to next falling edge
+ //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit
+ //___ _ _ _ _ _ _ _ ______
+ // |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F
+ //
+ MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+ UART_ABRCR_BITCNT_MODE3);
+ }
+ if(state == ENABLE) {
+ SET_BIT(uart->ABRCR, UART_ABRCR_ABREN);
+ }
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
new file mode 100644
index 00000000..e51bfcad
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
@@ -0,0 +1,55 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_uid.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_UID_C_
+
+// Files includes
+#include "hal_uid.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup UID_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup UID_Exported_Functions
+/// @{
+
+u8 device_id_data[12] = {0};
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Get device ID.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GetChipUID(void)
+{
+ u8 i;
+
+ for (i = 0; i < 12; i++) {
+ device_id_data[i] = *((vu8*)(UID_BASE + i));
+ }
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
new file mode 100644
index 00000000..9d771396
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
@@ -0,0 +1,131 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_ver.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_VER_C_
+
+// Files includes
+#include "hal_ver.h"
+
+
+// MM32 Library version is 0.90
+
+#define __MM32_LIB_VERSION_MAIN (0x0U) //!< [31:24] main version
+#define __MM32_LIB_VERSION_SUB1 (0x9U) //!< [23:16] sub1 version
+#define __MM32_LIB_VERSION_SUB2 (0x0U) //!< [15:8] sub2 version
+#define __MM32_LIB_VERSION_RC (0x00U) //!< [7:0] release candidate
+#define __MM32_LIB_VERSION ((__MM32_LIB_VERSION_MAIN << 24U)\
+ |(__MM32_LIB_VERSION_SUB1 << 16U)\
+ |(__MM32_LIB_VERSION_SUB2 << 8U )\
+ |(__MM32_LIB_VERSION_RC))
+
+// MM32 Library release date is 2021-05-10 (YYYY-MM-DD)
+#define __MM32_LIB_RELESE_YEARH (0x20U) //!< [31:24] release year high
+#define __MM32_LIB_RELESE_YEARL (0x21U) //!< [23:16] release year low
+#define __MM32_LIB_RELESE_MONTH (0x05U) //!< [15:8] release month
+#define __MM32_LIB_RELESE_DAY (0x10U) //!< [7:0] release day
+#define __MM32_LIB_RELESE_DATE ((__MM32_LIB_RELESE_YEARH << 24U)\
+ |(__MM32_LIB_RELESE_YEARL << 16U)\
+ |(__MM32_LIB_RELESE_MONTH << 8U )\
+ |(__MM32_LIB_RELESE_DAY))
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup VER_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup Lib and chipset_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief This method returns the Lib revision.
+/// @param None.
+/// @retval return the Lib version.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_MM32LibVersion(void)
+{
+ return __MM32_LIB_VERSION;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief This method returns the Lib release date.
+/// @param None.
+/// @retval return the Lib release date.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_MM32LibReleaseDate(void)
+{
+ return __MM32_LIB_RELESE_DATE;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the device revision identifier.
+/// @param None.
+/// @retval return the device revision identifier.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetREVID(void)
+{
+ return((DBGMCU->IDCODE) & 0xF );
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns the device identifier..
+/// @param None.
+/// @retval return the device Device identifier.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetDEVID(void)
+{
+ return((DBGMCU->IDCODE) );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns first word of the unique device identifier (UID based on 96 bits)
+/// @param None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw0(void)
+{
+ return(READ_REG(*((vu32*)UID_BASE)));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns second word of the unique device identifier (UID based on 96 bits)
+/// @param None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw1(void)
+{
+ return(READ_REG(*((vu32*)(UID_BASE + 4U))));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Returns third word of the unique device identifier (UID based on 96 bits)
+/// @param None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw2(void)
+{
+ return(READ_REG(*((vu32*)(UID_BASE + 8U))));
+}
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
new file mode 100644
index 00000000..05d74b59
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file hal_wwdg.c
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_WWDG_C_
+
+// Files includes
+#include "hal_wwdg.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup WWDG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup WWDG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Deinitializes the WWDG peripheral registers to their default reset
+/// values.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_DeInit()
+{
+ exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the WWDG Prescaler.
+/// @param WWDG_Prescaler: specifies the WWDG Prescaler.
+/// This parameter can be one of the following values:
+/// @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1
+/// @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2
+/// @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4
+/// @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetPrescaler(u32 prescaler)
+{
+ WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the WWDG window value.
+/// @param WindowValue: specifies the window value to be compared to the
+/// downcounter.
+/// This parameter value must be lower than 0x80.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetWindowValue(u8 window_value)
+{
+ WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables the WWDG Early Wakeup interrupt(EWI).
+/// @note Once enabled this interrupt cannot be disabled except by a system
+/// reset.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_EnableIT()
+{
+ WWDG->CFGR |= WWDG_CFGR_EWI;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Sets the WWDG counter value.
+/// @param Counter: specifies the watchdog counter value.
+/// This parameter must be a number between 0x40 and 0x7F (to prevent
+/// generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetCounter(u8 count)
+{
+ WWDG->CR = count & WWDG_CFGR_WINDOW;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables WWDG and load the counter value.
+/// @param Counter: specifies the watchdog counter value.
+/// This parameter must be a number between 0x40 and 0x7F (to prevent
+/// generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u32 WWDG_GetCounter()
+{
+ return WWDG->CR & WWDG_CR_CNT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Enables WWDG and load the counter value.
+/// @param Counter: specifies the watchdog counter value.
+/// This parameter must be a number between 0x40 and 0x7F (to prevent
+/// generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_Enable(u8 count)
+{
+ WWDG->CR = WWDG_CR_WDGA | count;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Checks whether the Early Wakeup interrupt flag is set or not.
+/// @param None.
+/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus WWDG_GetFlagStatus()
+{
+ return WWDG->SR ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clears Early Wakeup interrupt flag.
+/// @param None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_ClearFlag()
+{
+ WWDG->SR &= ~WWDG_SR_EWIF;
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
new file mode 100644
index 00000000..1a85c131
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
@@ -0,0 +1,23 @@
+///-----------------------------------------------------------------------------
+/// @file mm32_device.h
+/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
+/// microcontroller devices
+///
+/// This is a convenience header file for defining the part number on the
+/// build command line, instead of specifying the part specific header file.
+///
+/// Example: Add MM32 series to your build options, to define part
+/// Add "#include "mm32_device.h" to your source files
+///
+///
+///
+///
+///-----------------------------------------------------------------------------
+
+#ifndef __MM32_DEVICE_H
+#define __MM32_DEVICE_H
+
+#include "mm32_reg.h"
+
+#endif // __MM32_DEVICE_H
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
new file mode 100644
index 00000000..dfba8421
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
@@ -0,0 +1,71 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file mm32_reg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+////////////////////////////////////////////////////////////////////////////////
+#ifndef __MM32_REG_H
+#define __MM32_REG_H
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#include "reg_common.h"
+#include "reg_adc.h"
+#include "reg_bkp.h"
+#include "reg_can.h"
+#include "reg_comp.h"
+#include "reg_crc.h"
+#include "reg_crs.h"
+#include "reg_dac.h"
+#include "reg_dbg.h"
+#include "reg_dma.h"
+#include "reg_exti.h"
+#include "reg_eth.h"
+#include "reg_flash.h"
+#include "reg_gpio.h"
+#include "reg_i2c.h"
+#include "reg_iwdg.h"
+#include "reg_pwm.h"
+#include "reg_pwr.h"
+#include "reg_rcc.h"
+#include "reg_rtc.h"
+#include "reg_sdio.h"
+#include "reg_spi.h"
+#include "reg_syscfg.h"
+#include "reg_tim.h"
+#include "reg_uart.h"
+#include "reg_usb_otg_fs.h"
+#include "reg_wwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+#include "mm32_reg_redefine_v1.h"
+////////////////////////////////////////////////////////////////////////////////
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __MM32_REG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
new file mode 100644
index 00000000..6cdd79ea
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
@@ -0,0 +1,1175 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file mm32_reg_define_v1.H
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE define for version compatibility define
+/// FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __MM32_REG_DEFINE_V1_H
+#define __MM32_REG_DEFINE_V1_H
+
+// Files includes
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for register
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for ADC of MCU register
+////////////////////////////////////////////////////////////////////////////////
+
+#define ADC_COMP_IRQHandler ADC1_COMP_IRQHandler
+
+#define ADDATA_DATA ADC_DR_DATA
+
+#define ADDATA_CHANNELSEL ADC_DR_CH
+#define ADDATA_CHANNELSEL_0 ADC_DR_CH0
+#define ADDATA_CHANNELSEL_1 ADC_DR_CH1
+#define ADDATA_CHANNELSEL_2 ADC_DR_CH2
+#define ADDATA_CHANNELSEL_3 ADC_DR_CH3
+#define ADDATA_CHANNELSEL_4 ADC_DR_CH4
+#define ADDATA_CHANNELSEL_5 ADC_DR_CH5
+#define ADDATA_CHANNELSEL_6 ADC_DR_CH6
+#define ADDATA_CHANNELSEL_7 ADC_DR_CH7
+
+
+
+
+#define ADDATA_CHANNELSEL_CH8 ADC_DR_CH8
+#define ADDATA_CHANNELSEL_CH9 ADC_DR_CH9
+#define ADDATA_CHANNELSEL_CH10 ADC_DR_CH10
+#define ADDATA_CHANNELSEL_CH11 ADC_DR_CH11
+#define ADDATA_CHANNELSEL_CH12 ADC_DR_CH12
+#define ADDATA_CHANNELSEL_CH13 ADC_DR_CH13
+#define ADDATA_CHANNELSEL_CH14 ADC_DR_CH14
+#define ADDATA_CHANNELSEL_CH15 ADC_DR_CH15
+#define ADDATA_CHANNELSEL_TempSensor ADC_DR_TempSensor
+#define ADDATA_CHANNELSEL_VolSensor ADC_DR_VoltRef
+
+
+#define ADDATA_OVERRUN ADC_DR_OVERRUN
+#define ADDATA_VALID ADC_DR_VALID
+
+#define ADCFG_ADEN ADC_CFGR_ADEN
+#define ADCFG_ADWEN ADC_CFGR_ADWEN
+
+#define ADCFG_RSLTCTL ADC_CFGR_RSLTCTL
+#define ADCFG_RSLTCTL_12 ADC_CFGR_RSLTCTL_12
+#define ADCFG_RSLTCTL_11 ADC_CFGR_RSLTCTL_11
+#define ADCFG_RSLTCTL_10 ADC_CFGR_RSLTCTL_10
+#define ADCFG_RSLTCTL_9 ADC_CFGR_RSLTCTL_9
+#define ADCFG_RSLTCTL_8 ADC_CFGR_RSLTCTL_8
+
+
+#define ADCFG_TSEN ADC_CFGR_TEN
+#define ADCFG_VSEN ADC_CFGR_VEN
+
+#define ADCFG_ADCPRE ADC_CFGR_PRE
+#define ADCFG_ADCPRE_2 ADC_CFGR_PRE_2
+#define ADCFG_ADCPRE_4 ADC_CFGR_PRE_4
+#define ADCFG_ADCPRE_6 ADC_CFGR_PRE_6
+#define ADCFG_ADCPRE_8 ADC_CFGR_PRE_8
+#define ADCFG_ADCPRE_10 ADC_CFGR_PRE_10
+#define ADCFG_ADCPRE_12 ADC_CFGR_PRE_12
+#define ADCFG_ADCPRE_14 ADC_CFGR_PRE_14
+#define ADCFG_ADCPRE_16 ADC_CFGR_PRE_16
+#define ADCFG_SAMCTL ADC_CFGR_SAMCTL
+#define ADCFG_SAMCTL_1_5 ADC_CFGR_SAMCTL_1_5
+#define ADCFG_SAMCTL_7_5 ADC_CFGR_SAMCTL_7_5
+#define ADCFG_SAMCTL_13_5 ADC_CFGR_SAMCTL_13_5
+#define ADCFG_SAMCTL_28_5 ADC_CFGR_SAMCTL_28_5
+#define ADCFG_SAMCTL_41_5 ADC_CFGR_SAMCTL_41_5
+#define ADCFG_SAMCTL_55_5 ADC_CFGR_SAMCTL_55_5
+#define ADCFG_SAMCTL_71_5 ADC_CFGR_SAMCTL_71_5
+#define ADCFG_SAMCTL_239_5 ADC_CFGR_SAMCTL_239_5
+
+
+#define ADCFG_ADCPRE_3 ADC_CFGR_PRE_3
+#define ADCFG_ADCPRE_5 ADC_CFGR_PRE_5
+#define ADCFG_ADCPRE_7 ADC_CFGR_PRE_7
+#define ADCFG_ADCPRE_9 ADC_CFGR_PRE_9
+#define ADCFG_ADCPRE_11 ADC_CFGR_PRE_11
+#define ADCFG_ADCPRE_13 ADC_CFGR_PRE_13
+#define ADCFG_ADCPRE_15 ADC_CFGR_PRE_15
+#define ADCFG_ADCPRE_17 ADC_CFGR_PRE_17
+#define ADCFG_SAMCTL_2_5 ADC_CFGR_SAMCTL_2_5
+#define ADCFG_SAMCTL_3_5 ADC_CFGR_SAMCTL_3_5
+#define ADCFG_SAMCTL_4_5 ADC_CFGR_SAMCTL_4_5
+#define ADCFG_SAMCTL_5_5 ADC_CFGR_SAMCTL_5_5
+#define ADCFG_SAMCTL_6_5 ADC_CFGR_SAMCTL_6_5
+
+#define ADCR_ADIE ADC_CR_ADIE
+#define ADCR_ADWIE ADC_CR_ADWIE
+#define ADCR_TRGEN ADC_CR_TRGEN
+#define ADCR_DMAEN ADC_CR_DMAEN
+#define ADCR_ADST ADC_CR_ADST
+#define ADCR_ADMD ADC_CR_MODE
+#define ADCR_ADMD_SINGLE ADC_CR_IMM
+#define ADCR_ADMD_PERIOD ADC_CR_SCAN
+#define ADCR_ADMD_CONTINUE ADC_CR_CONTINUE
+#define ADC_Mode_Single ADC_CR_IMM
+#define ADC_Mode_Single_Period ADC_CR_SCAN
+#define ADC_Mode_Continuous_Scan ADC_CR_CONTINUE
+
+
+#define ADCR_ALIGN ADC_CR_ALIGN
+#define ADCR_ALIGN_LEFT ADC_CR_LEFT
+#define ADCR_ALIGN_RIGHT ADC_CR_RIGHT
+#define ADCR_CMPCH_Pos ADC_CR_CMPCH_Pos
+#define ADCR_CMPCH ADC_CR_CMPCH
+#define ADCR_CMPCH_0 ADC_CR_CMPCH_0
+#define ADCR_CMPCH_1 ADC_CR_CMPCH_1
+#define ADCR_CMPCH_2 ADC_CR_CMPCH_2
+#define ADCR_CMPCH_4 ADC_CR_CMPCH_4
+#define ADCR_CMPCH_5 ADC_CR_CMPCH_5
+#define ADCR_CMPCH_6 ADC_CR_CMPCH_6
+#define ADCR_CMPCH_7 ADC_CR_CMPCH_7
+#define ADCR_CMPCH_8 ADC_CR_CMPCH_8
+#define ADCR_CMPCH_9 ADC_CR_CMPCH_9
+#define ADCR_CMPCH_10 ADC_CR_CMPCH_10
+#define ADCR_CMPCH_11 ADC_CR_CMPCH_11
+#define ADCR_CMPCH_13 ADC_CR_CMPCH_13
+#define ADCR_CMPCH_14 ADC_CR_CMPCH_14
+#define ADCR_CMPCH_ALL ADC_CR_CMPCH_ALL
+
+
+#define ADCR_TRGSEL ADC_CR_TRGSEL
+#define ADCR_TRGSEL_T1_CC1 ADC_CR_T1_CC1
+#define ADCR_TRGSEL_T1_CC2 ADC_CR_T1_CC2
+#define ADCR_TRGSEL_T1_CC3 ADC_CR_T1_CC3
+#define ADCR_TRGSEL_T2_CC2 ADC_CR_T2_CC2
+#define ADCR_TRGSEL_T3_TRGO ADC_CR_T3_TRIG
+#define ADCR_TRGSEL_EXTI_11 ADC_CR_EXTI_11
+
+
+
+#define ADCR_TRGSEL_T1_CC4_CC5 ADC_CR_T1_CC4_CC5
+#define ADCR_TRGSEL_T3_CC1 ADC_CR_T3_CC1
+#define ADCR_TRGSEL_T1_TRGO ADC_CR_T1_TRIG
+#define ADCR_TRGSEL_T8_CC4 ADC_CR_T8_CC4
+#define ADCR_TRGSEL_T8_CC4_CC5 ADC_CR_T8_CC4_CC5
+#define ADCR_TRGSEL_T2_CC1 ADC_CR_T2_CC1
+#define ADCR_TRGSEL_T3_CC4 ADC_CR_T3_CC4
+#define ADCR_TRGSEL_T2_TRGO ADC_CR_T2_TRIG
+#define ADCR_TRGSEL_T8_CC5 ADC_CR_T8_CC5
+#define ADCR_TRGSEL_EXTI_15 ADC_CR_EXTI_15
+#define ADCR_TRGSEL_TIM1_CC4 ADC_CR_TIM1_CC4
+#define ADCR_TRGSEL_TIM1_CC5 ADC_CR_TIM1_CC5
+#define ADCR_SCANDIR ADC_CR_SCANDIR
+#define ADCR_TRGSHIFT ADC_CR_TRGSHIFT
+#define ADCR_TRGSHIFT_0 ADC_CR_TRGSHIFT_0
+#define ADCR_TRGSHIFT_4 ADC_CR_TRGSHIFT_4
+#define ADCR_TRGSHIFT_16 ADC_CR_TRGSHIFT_16
+#define ADCR_TRGSHIFT_32 ADC_CR_TRGSHIFT_32
+#define ADCR_TRGSHIFT_64 ADC_CR_TRGSHIFT_64
+#define ADCR_TRGSHIFT_128 ADC_CR_TRGSHIFT_128
+#define ADCR_TRGSHIFT_256 ADC_CR_TRGSHIFT_256
+#define ADCR_TRGSHIFT_512 ADC_CR_TRGSHIFT_512
+#define ADCR_CALIBEN ADC_CR_CALIBEN
+#define ADCR_CALIBSEL ADC_CR_CALIBSEL
+
+#define ADCHS_CHEN0 ADC_CHSR_CH0
+#define ADCHS_CHEN1 ADC_CHSR_CH1
+#define ADCHS_CHEN2 ADC_CHSR_CH2
+#define ADCHS_CHEN3 ADC_CHSR_CH3
+#define ADCHS_CHEN4 ADC_CHSR_CH4
+#define ADCHS_CHEN5 ADC_CHSR_CH5
+#define ADCHS_CHEN6 ADC_CHSR_CH6
+#define ADCHS_CHEN7 ADC_CHSR_CH7
+#define ADCHS_ALL ADC_CHSR_CHALL
+
+
+#define ADCHS_CHEN8 ADC_CHSR_CH8
+#define ADCHS_CHEN9 ADC_CHSR_CH9
+#define ADCHS_CHENTS ADC_CHSR_CHT
+#define ADCHS_CHENVS ADC_CHSR_CHV
+#define ADCHS_CHEN8 ADC_CHSR_CH8
+#define ADCHS_CHEN9 ADC_CHSR_CH9
+#define ADCHS_CHEN10 ADC_CHSR_CH10
+#define ADCHS_CHEN11 ADC_CHSR_CH11
+#define ADCHS_CHEN12 ADC_CHSR_CH12
+#define ADCHS_CHEN13 ADC_CHSR_CH13
+#define ADCHS_CHEN14 ADC_CHSR_CH14
+#define ADCHS_CHEN15 ADC_CHSR_CH15
+#define ADCHS_CHENTS ADC_CHSR_CHT
+#define ADCHS_CHENVS ADC_CHSR_CHV
+
+
+#define ADCMPR_CMPLDATA ADC_CMPR_CMPLDATA
+#define ADCMPR_CMPHDATA ADC_CMPR_CMPHDATA
+
+#define ADSTA_ADIF ADC_SR_ADIF
+#define ADSTA_ADWIF ADC_SR_ADWIF
+#define ADSTA_BUSY ADC_SR_BUSY
+#define ADSTA_CHANNEL ADC_SR_CH
+#define ADSTA_CHANNEL_CH0 ADC_SR_CH0
+#define ADSTA_CHANNEL_CH1 ADC_SR_CH1
+#define ADSTA_CHANNEL_CH2 ADC_SR_CH2
+#define ADSTA_CHANNEL_CH3 ADC_SR_CH3
+#define ADSTA_CHANNEL_CH4 ADC_SR_CH4
+#define ADSTA_CHANNEL_CH5 ADC_SR_CH5
+#define ADSTA_CHANNEL_CH6 ADC_SR_CH6
+#define ADSTA_CHANNEL_CH7 ADC_SR_CH7
+#define ADSTA_CHANNEL_CH8 ADC_SR_CH8
+#define ADSTA_CHANNEL_CH9 ADC_SR_CH9
+#define ADSTA_CHANNEL_CH10 ADC_SR_CH10
+#define ADSTA_CHANNEL_CH11 ADC_SR_CH11
+#define ADSTA_CHANNEL_CH13 ADC_SR_CH13
+#define ADSTA_CHANNEL_CH14 ADC_SR_CH14
+#define ADSTA_CHANNEL_CH15 ADC_SR_CH15
+#define ADSTA_VALID ADC_SR_VALID
+#define ADSTA_OVERRUN ADC_SR_OVERRUN
+
+#define ADDR_OVERRUN ADC_CHDR_OVERRUN
+#define ADDR_VALID ADC_CHDR_VALID
+#define ADDR_DATA ADC_CHDR_DATA
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for HAL library
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for ADC of HAL library
+////////////////////////////////////////////////////////////////////////////////
+
+
+#define ADC_ExternalTrigConv_T1_CC1 ADC1_ExternalTrigConv_T1_CC1
+#define ADC_ExternalTrigConv_T1_CC2 ADC1_ExternalTrigConv_T1_CC2
+#define ADC_ExternalTrigConv_T1_CC3 ADC1_ExternalTrigConv_T1_CC3
+#define ADC_ExternalTrigConv_T2_CC2 ADC1_ExternalTrigConv_T2_CC2
+#define ADC_ExternalTrigConv_T3_TRIG ADC1_ExternalTrigConv_T3_TRIG
+#define ADC_ExternalTrigConv_T3_CC1 ADC1_ExternalTrigConv_T3_CC1
+#define ADC_ExternalTrigConv_EXTI_11 ADC1_ExternalTrigConv_EXTI_11
+#define ADC_ExternalTrigConv_T1_CC4_CC5 ADC1_ExternalTrigConv_T1_CC4_CC5
+#define ADC_ExternalTrigConv_T1_TRIG ADC1_ExternalTrigConv_T1_TRIG
+#define ADC_ExternalTrigConv_T8_CC4 ADC1_ExternalTrigConv_T8_CC4
+#define ADC_ExternalTrigConv_T8_CC4_CC5 ADC1_ExternalTrigConv_T8_CC4_CC5
+#define ADC_ExternalTrigConv_T2_CC1 ADC1_ExternalTrigConv_T2_CC1
+#define ADC_ExternalTrigConv_T3_CC4 ADC1_ExternalTrigConv_T3_CC4
+#define ADC_ExternalTrigConv_T2_TRIG ADC1_ExternalTrigConv_T2_TRIG
+#define ADC_ExternalTrigConv_T8_CC5 ADC1_ExternalTrigConv_T8_CC5
+#define ADC_ExternalTrigConv_EXTI_15 ADC1_ExternalTrigConv_EXTI_15
+#define ADC_ExternalTrigConv_T1_CC4 ADC1_ExternalTrigConv_T1_CC4
+#define ADC_ExternalTrigConv_T1_CC5 ADC1_ExternalTrigConv_T1_CC5
+
+
+
+#define ADC_SampleTime_1_5Cycles ADC_Samctl_1_5
+#define ADC_SampleTime_7_5Cycles ADC_Samctl_7_5
+#define ADC_SampleTime_13_5Cycles ADC_Samctl_13_5
+#define ADC_SampleTime_28_5Cycles ADC_Samctl_28_5
+#define ADC_SampleTime_41_5Cycles ADC_Samctl_41_5
+#define ADC_SampleTime_55_5Cycles ADC_Samctl_55_5
+#define ADC_SampleTime_71_5Cycles ADC_Samctl_71_5
+#define ADC_SampleTime_239_5Cycles ADC_Samctl_239_5
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define AES_KEYR0 AES_KEYRn ///< AES Key Register 0
+#define AES_KEYR1 AES_KEYRn ///< AES Key Register 1
+#define AES_KEYR2 AES_KEYRn ///< AES Key Register 2
+#define AES_KEYR3 AES_KEYRn ///< AES Key Register 3
+#define AES_KEYR4 AES_KEYRn ///< AES Key Register 4
+#define AES_KEYR5 AES_KEYRn ///< AES Key Register 5
+#define AES_KEYR6 AES_KEYRn ///< AES Key Register 6
+#define AES_KEYR7 AES_KEYRn ///< AES Key Register 7
+
+#define AES_IVR0 AES_IVRn ///< AES Initialization Vector Register 0
+#define AES_IVR1 AES_IVRn ///< AES Initialization Vector Register 1
+#define AES_IVR2 AES_IVRn ///< AES Initialization Vector Register 2
+#define AES_IVR3 AES_IVRn ///< AES Initialization Vector Register 3
+
+
+#define CRC_DR_DR CRC_DR_DATA
+#define CRC_IDR_IDR CRC_IDR_DATA
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_CR_SYNCOKIE CRS_CR_OKIE
+#define CRS_CR_SYNCWARNIE CRS_CR_WARNIE
+#define CRS_CR_ESYNCIE CRS_CR_EXPTIE
+#define CRS_CR_CEN CRS_CR_CNTEN
+#define CRS_CFGR_SYNCDIV CRS_CFGR_DIV
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SRC
+#define CRS_CFGR_SYNCPOL CRS_CFGR_POL
+#define CRS_ISR_SYNCOKF CRS_ISR_OKIF
+#define CRS_ISR_SYNCWARNF CRS_ISR_WARNIF
+#define CRS_ISR_ERRF CRS_ISR_ERRIF
+#define CRS_ISR_ESYNCF CRS_ISR_EXPTIF
+#define CRS_ISR_SYNCERR CRS_ISR_ERR
+#define CRS_ISR_SYNCMISS CRS_ISR_MISS
+#define CRS_ISR_TRIMOVF CRS_ISR_OVERFLOW
+#define CRS_ICR_SYNCOKC CRS_ICR_OK
+#define CRS_ICR_SYNCWARNC CRS_ICR_WARN
+#define CRS_ICR_ERRC CRS_ICR_ERR
+#define CRS_ICR_ESYNCC CRS_ICR_EXPT
+
+#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF ///< SYNC event OK
+#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF ///< SYNC warning
+#define CRS_IT_ERR CRS_CR_ERRIE ///< error
+#define CRS_IT_ESYNC CRS_ISR_ESYNCF ///< Expected SYNC
+#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF ///< Trimming overflow or underflow
+#define CRS_IT_SYNCERR CRS_ISR_SYNCERR ///< SYNC error
+#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS ///< SYNC missed
+
+#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF ///< SYNC event OK
+#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF ///< SYNC warning
+#define CRS_FLAG_ERR CRS_ISR_ERRF ///< error
+#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF ///< Expected SYNC
+#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF ///< Trimming overflow or underflow
+#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR ///< SYNC error
+#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS ///< SYNC missed
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define DIV_UNSIGN DIV_CR_USIGN ///< Unsigned enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+#define DMA_CCR_MEM2MEM DMA_CCR_M2M
+
+#define DMA_CCR1_EN DMA_CCR_EN
+#define DMA_CCR1_DIR DMA_CCR_DIR
+#define DMA_CCR1_CIRC DMA_CCR_CIRC
+#define DMA_CCR1_PINC DMA_CCR_PINC
+#define DMA_CCR1_MINC DMA_CCR_MINC
+#define DMA_CCR1_PSIZE_0 DMA_CCR_PSIZE_0
+#define DMA_CCR1_MSIZE_0 DMA_CCR_MSIZE_0
+#define DMA_CCR1_PL_0 DMA_CCR_PL_0
+#define DMA_CCR1_PSIZE_1 DMA_CCR_PSIZE_1
+#define DMA_CCR1_MSIZE_1 DMA_CCR_MSIZE_1
+#define DMA_CCR1_PL_1 DMA_CCR_PL_1
+#define DMA_CCR1_MEM2MEM DMA_CCR_M2M
+#define DMA_CCR1_TCIE DMA_CCR_TCIE
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_IMR_MR0 EXTI_IMR_0
+#define EXTI_IMR_MR1 EXTI_IMR_1
+#define EXTI_IMR_MR2 EXTI_IMR_2
+#define EXTI_IMR_MR3 EXTI_IMR_3
+#define EXTI_IMR_MR4 EXTI_IMR_4
+#define EXTI_IMR_MR5 EXTI_IMR_5
+#define EXTI_IMR_MR6 EXTI_IMR_6
+#define EXTI_IMR_MR7 EXTI_IMR_7
+#define EXTI_IMR_MR8 EXTI_IMR_8
+#define EXTI_IMR_MR9 EXTI_IMR_9
+#define EXTI_IMR_MR10 EXTI_IMR_10
+#define EXTI_IMR_MR11 EXTI_IMR_11
+#define EXTI_IMR_MR12 EXTI_IMR_12
+#define EXTI_IMR_MR13 EXTI_IMR_13
+#define EXTI_IMR_MR14 EXTI_IMR_14
+#define EXTI_IMR_MR15 EXTI_IMR_15
+#define EXTI_IMR_MR16 EXTI_IMR_16
+
+#define EXTI_EMR_MR0 EXTI_EMR_0
+#define EXTI_EMR_MR1 EXTI_EMR_1
+#define EXTI_EMR_MR2 EXTI_EMR_2
+#define EXTI_EMR_MR3 EXTI_EMR_3
+#define EXTI_EMR_MR4 EXTI_EMR_4
+#define EXTI_EMR_MR5 EXTI_EMR_5
+#define EXTI_EMR_MR6 EXTI_EMR_6
+#define EXTI_EMR_MR7 EXTI_EMR_7
+#define EXTI_EMR_MR8 EXTI_EMR_8
+#define EXTI_EMR_MR9 EXTI_EMR_9
+#define EXTI_EMR_MR10 EXTI_EMR_10
+#define EXTI_EMR_MR11 EXTI_EMR_11
+#define EXTI_EMR_MR12 EXTI_EMR_12
+#define EXTI_EMR_MR13 EXTI_EMR_13
+#define EXTI_EMR_MR14 EXTI_EMR_14
+#define EXTI_EMR_MR15 EXTI_EMR_15
+#define EXTI_EMR_MR16 EXTI_EMR_16
+
+#define EXTI_RTSR_TR0 EXTI_RTSR_0
+#define EXTI_RTSR_TR1 EXTI_RTSR_1
+#define EXTI_RTSR_TR2 EXTI_RTSR_2
+#define EXTI_RTSR_TR3 EXTI_RTSR_3
+#define EXTI_RTSR_TR4 EXTI_RTSR_4
+#define EXTI_RTSR_TR5 EXTI_RTSR_5
+#define EXTI_RTSR_TR6 EXTI_RTSR_6
+#define EXTI_RTSR_TR7 EXTI_RTSR_7
+#define EXTI_RTSR_TR8 EXTI_RTSR_8
+#define EXTI_RTSR_TR9 EXTI_RTSR_9
+#define EXTI_RTSR_TR10 EXTI_RTSR_10
+#define EXTI_RTSR_TR11 EXTI_RTSR_11
+#define EXTI_RTSR_TR12 EXTI_RTSR_12
+#define EXTI_RTSR_TR13 EXTI_RTSR_13
+#define EXTI_RTSR_TR14 EXTI_RTSR_14
+#define EXTI_RTSR_TR15 EXTI_RTSR_15
+#define EXTI_RTSR_TR16 EXTI_RTSR_16
+
+#define EXTI_FTSR_TR0 EXTI_FTSR_0
+#define EXTI_FTSR_TR1 EXTI_FTSR_1
+#define EXTI_FTSR_TR2 EXTI_FTSR_2
+#define EXTI_FTSR_TR3 EXTI_FTSR_3
+#define EXTI_FTSR_TR4 EXTI_FTSR_4
+#define EXTI_FTSR_TR5 EXTI_FTSR_5
+#define EXTI_FTSR_TR6 EXTI_FTSR_6
+#define EXTI_FTSR_TR7 EXTI_FTSR_7
+#define EXTI_FTSR_TR8 EXTI_FTSR_8
+#define EXTI_FTSR_TR9 EXTI_FTSR_9
+#define EXTI_FTSR_TR10 EXTI_FTSR_10
+#define EXTI_FTSR_TR11 EXTI_FTSR_11
+#define EXTI_FTSR_TR12 EXTI_FTSR_12
+#define EXTI_FTSR_TR13 EXTI_FTSR_13
+#define EXTI_FTSR_TR14 EXTI_FTSR_14
+#define EXTI_FTSR_TR15 EXTI_FTSR_15
+#define EXTI_FTSR_TR16 EXTI_FTSR_16
+
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_16
+
+#define EXTI_PR_PR0 EXTI_PR_0
+#define EXTI_PR_PR1 EXTI_PR_1
+#define EXTI_PR_PR2 EXTI_PR_2
+#define EXTI_PR_PR3 EXTI_PR_3
+#define EXTI_PR_PR4 EXTI_PR_4
+#define EXTI_PR_PR5 EXTI_PR_5
+#define EXTI_PR_PR6 EXTI_PR_6
+#define EXTI_PR_PR7 EXTI_PR_7
+#define EXTI_PR_PR8 EXTI_PR_8
+#define EXTI_PR_PR9 EXTI_PR_9
+#define EXTI_PR_PR10 EXTI_PR_10
+#define EXTI_PR_PR11 EXTI_PR_11
+#define EXTI_PR_PR12 EXTI_PR_12
+#define EXTI_PR_PR13 EXTI_PR_13
+#define EXTI_PR_PR14 EXTI_PR_14
+#define EXTI_PR_PR15 EXTI_PR_15
+#define EXTI_PR_PR16 EXTI_PR_16
+
+#define EXTI_IMR_MR17 EXTI_IMR_17
+
+#define EXTI_IMR_MR18 EXTI_IMR_18
+
+#define EXTI_IMR_MR19 EXTI_IMR_19
+
+#define EXTI_IMR_MR20 EXTI_IMR_20
+
+#define EXTI_IMR_MR21 EXTI_IMR_21
+
+
+#define EXTI_IMR_MR24 EXTI_IMR_24
+
+#define EXTI_EMR_MR17 EXTI_EMR_17
+
+#define EXTI_EMR_MR18 EXTI_EMR_18
+
+#define EXTI_EMR_MR19 EXTI_EMR_19
+
+#define EXTI_EMR_MR20 EXTI_EMR_20
+
+#define EXTI_EMR_MR21 EXTI_EMR_21
+
+
+#define EXTI_EMR_MR24 EXTI_EMR_24
+
+#define EXTI_RTSR_MR17 EXTI_RTSR_17
+
+#define EXTI_RTSR_MR18 EXTI_RTSR_18
+
+#define EXTI_RTSR_MR19 EXTI_RTSR_19
+
+#define EXTI_RTSR_MR20 EXTI_RTSR_20
+
+#define EXTI_RTSR_MR21 EXTI_RTSR_21
+
+
+#define EXTI_RTSR_MR24 EXTI_RTSR_24
+
+#define EXTI_FTSR_MR17 EXTI_FTSR_18
+
+#define EXTI_FTSR_MR18 EXTI_FTSR_18
+
+#define EXTI_FTSR_MR19 EXTI_FTSR_19
+
+#define EXTI_FTSR_MR20 EXTI_FTSR_20
+
+#define EXTI_FTSR_MR21 EXTI_FTSR_21
+
+
+#define EXTI_FTSR_MR24 EXTI_FTSR_24
+
+#define EXTI_SWIER_MR17 EXTI_SWIER_17
+
+#define EXTI_SWIER_MR18 EXTI_SWIER_18
+
+#define EXTI_SWIER_MR19 EXTI_SWIER_19
+
+#define EXTI_SWIER_MR20 EXTI_SWIER_20
+
+#define EXTI_SWIER_MR21 EXTI_SWIER_21
+
+
+#define EXTI_SWIER_MR24 EXTI_SWIER_24
+
+#define EXTI_PR_MR17 EXTI_PR_17
+
+#define EXTI_PR_MR18 EXTI_PR_18
+
+#define EXTI_PR_MR19 EXTI_PR_19
+
+#define EXTI_PR_MR20 EXTI_PR_20
+
+#define EXTI_PR_MR21 EXTI_PR_21
+
+
+#define EXTI_PR_MR24 EXTI_PR_24
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define GPIO_Mode_IN_FLOATING GPIO_Mode_FLOATING
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+//Bit
+#define I2C_CON_MASTER_MODE I2C_CR_MASTER
+#define I2C_CON_SPEED I2C_CR_SPEED
+#define I2C_CON_SPEED_STANDARD I2C_CR_STD
+#define I2C_CON_SPEED_FAST I2C_CR_FAST
+#define I2C_CON_10BITADDR_SLAVE I2C_CR_SLAVE10
+#define I2C_CON_10BITADDR_MASTER I2C_CR_MASTER10
+#define I2C_CON_RESTART_EN I2C_CR_REPEN
+#define I2C_CON_SLAVE_DISABLE I2C_CR_SLAVEDIS
+#define I2C_CON_STOP_DET_IFADDRESSED I2C_CR_STOPINT
+#define I2C_CON_EMPTY_CTRL I2C_CR_EMPINT
+#define I2C_CON_STOP I2C_CR_STOP
+#define I2C_CON_RESTART I2C_CR_RESTART
+
+#define I2C_TAR_TAR I2C_TAR_ADDR
+#define I2C_TAR_GC_OR_START I2C_TAR_GC
+#define I2C_SAR_SAR I2C_SAR_ADDR
+#define I2C_DATA_CMD_DAT I2C_DR_DAT
+#define I2C_DATA_CMD_CMD I2C_DR_CMD
+#define I2C_DATA_CMD_STOP I2C_DR_STOP
+#define I2C_DATA_CMD_RESTART I2C_DR_RESTART
+
+#define I2C_SS_SCL_HCNT I2C_SSHR_CNT
+#define I2C_SS_SCL_LCNT I2C_SSLR_CNT
+#define I2C_FS_SCL_HCNT I2C_FSHR_CNT
+#define I2C_FS_SCL_LCNT I2C_FSLR_CNT
+
+#define I2C_INTR_STAT_RX_UNDER I2C_ISR_RX_UNDER
+#define I2C_INTR_STAT_RX_OVER I2C_ISR_RX_OVER
+#define I2C_INTR_STAT_RX_FULL I2C_ISR_RX_FULL
+#define I2C_INTR_STAT_TX_OVER I2C_ISR_TX_OVER
+#define I2C_INTR_STAT_TX_EMPTY I2C_ISR_TX_EMPTY
+#define I2C_INTR_STAT_RX_REQ I2C_ISR_RX_REQ
+#define I2C_INTR_STAT_TX_ABRT I2C_ISR_TX_ABRT
+#define I2C_INTR_STAT_RX_DONE I2C_ISR_RX_DONE
+#define I2C_INTR_STAT_ACTIVITY I2C_ISR_ACTIV
+#define I2C_INTR_STAT_STOP_DET I2C_ISR_STOP
+#define I2C_INTR_STAT_START_DET I2C_ISR_START
+#define I2C_INTR_STAT_GEN_CALL I2C_ISR_GC
+#define I2C_INTR_STAT_RESTART_DET I2C_ISR_RESTART
+#define I2C_INTR_STAT_MST_ON_HOLD I2C_ISR_HOLD
+
+#define I2C_INTR_MASK_RX_UNDER I2C_IMR_RX_UNDER
+#define I2C_INTR_MASK_RX_OVER I2C_IMR_RX_OVER
+#define I2C_INTR_MASK_RX_FULL I2C_IMR_RX_FULL
+#define I2C_INTR_MASK_TX_OVER I2C_IMR_TX_OVER
+#define I2C_INTR_MASK_TX_EMPTY I2C_IMR_TX_EMPTY
+#define I2C_INTR_MASK_RX_REQ I2C_IMR_RX_REQ
+#define I2C_INTR_MASK_TX_ABRT I2C_IMR_TX_ABRT
+#define I2C_INTR_MASK_RX_DONE I2C_IMR_RX_DONE
+#define I2C_INTR_MASK_ACTIVITY I2C_IMR_ACTIV
+#define I2C_INTR_MASK_STOP_DET I2C_IMR_STOP
+#define I2C_INTR_MASK_START_DET I2C_IMR_START
+#define I2C_INTR_MASK_GEN_CALL I2C_IMR_GC
+#define I2C_INTR_MASK_RESTART_DET I2C_IMR_RESTART
+#define I2C_INTR_MASK_MST_ON_HOLD I2C_IMR_HOLD
+
+#define I2C_RAW_INTR_MASK_RX_UNDER I2C_RAWISR_RX_UNDER
+#define I2C_RAW_INTR_MASK_RX_OVER I2C_RAWISR_RX_OVER
+#define I2C_RAW_INTR_MASK_RX_FULL I2C_RAWISR_RX_FULL
+#define I2C_RAW_INTR_MASK_TX_OVER I2C_RAWISR_TX_OVER
+#define I2C_RAW_INTR_MASK_TX_EMPTY I2C_RAWISR_TX_EMPTY
+#define I2C_RAW_INTR_MASK_RX_REQ I2C_RAWISR_RX_REQ
+#define I2C_RAW_INTR_MASK_TX_ABRT I2C_RAWISR_TX_ABRT
+#define I2C_RAW_INTR_MASK_RX_DONE I2C_RAWISR_RX_DONE
+#define I2C_RAW_INTR_MASK_ACTIVITY I2C_RAWISR_ACTIV
+#define I2C_RAW_INTR_MASK_STOP_DET I2C_RAWISR_STOP
+#define I2C_RAW_INTR_MASK_START_DET I2C_RAWISR_START
+#define I2C_RAW_INTR_MASK_GEN_CALL I2C_RAWISR_GC
+#define I2C_RAW_INTR_MASK_RESTART_DET I2C_RAWISR_RESTART
+#define I2C_RAW_INTR_MASK_MST_ON_HOLD I2C_RAWISR_HOLD
+
+#define I2C_RX_TL I2C_RXTLR_TL
+#define I2C_TX_TL I2C_TXTLR_TL
+
+#define I2C_CLR_INTR I2C_ICR
+#define I2C_CLR_RX_UNDER I2C_RX_UNDER
+#define I2C_CLR_RX_OVER I2C_RX_OVER
+#define I2C_CLR_TX_OVER I2C_TX_OVER
+#define I2C_RX_REQ I2C_RD_REQ
+#define I2C_CLR_RX_REQ I2C_RD_REQ
+#define I2C_CLR_TX_ABRT I2C_TX_ABRT
+#define I2C_CLR_RX_DONE I2C_RX_DONE
+#define I2C_CLR_ACTIVITY I2C_ACTIV
+#define I2C_CLR_STOP_DET I2C_STOP
+#define I2C_CLR_START_DET I2C_START
+#define I2C_CLR_GEN_CALL I2C_GC
+
+#define I2C_ENABLE_ENABLE I2C_ENR_ENABLE
+#define I2C_ENABLE_ABORT I2C_ENR_ABORT
+
+#define I2C_STATUS_ACTIVITY I2C_SR_ACTIV
+#define I2C_STATUS_TFNF I2C_SR_TFNF
+#define I2C_STATUS_TFE I2C_SR_TFE
+#define I2C_STATUS_RFNE I2C_SR_RFNE
+#define I2C_STATUS_RFF I2C_SR_RFF
+#define I2C_STATUS_MST_ACTIVITY I2C_SR_MST_ACTIV
+#define I2C_STATUS_SLV_ACTIVITY I2C_SR_SLV_ACTIV
+
+#define I2C_TXFLR I2C_TXFLR_CNT
+#define I2C_RXFLR I2C_RXFLR_CNT
+
+#define I2C_SDA_TX_HOLD I2C_HOLD_TXCNT
+#define I2C_SDA_RX_HOLD I2C_HOLD_RXCNT
+#define I2C_DMA_CR_RDMAE I2C_DMA_RXEN
+#define I2C_DMA_CR_TDMAE I2C_DMA_TXEN
+#define I2C_SDA_SET_UP I2C_SETUP_CNT
+#define I2C_ACK_GENERAL_CALL I2C_GCR_GC
+
+
+#define IWDG_PR_PR IWDG_PR_PRE
+#define IWDG_PR_PR_DIV4 IWDG_PR_PRE_DIV4
+#define IWDG_PR_PR_DIV8 IWDG_PR_PRE_DIV8
+#define IWDG_PR_PR_DIV16 IWDG_PR_PRE_DIV16
+#define IWDG_PR_PR_DIV32 IWDG_PR_PRE_DIV32
+#define IWDG_PR_PR_DIV64 IWDG_PR_PRE_DIV64
+#define IWDG_PR_PR_DIV128 IWDG_PR_PRE_DIV128
+#define IWDG_PR_PR_DIV256 IWDG_PR_PRE_DIV256
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup AHB_peripheral
+/// @{
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1
+#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAM
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITF
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRC
+#define RCC_AHBPeriph_AES RCC_AHBENR_AES
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOA
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOB
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOC
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIOD
+
+
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOE
+#define RCC_AHBPeriph_HIV RCC_AHBENR_HWDIV
+#define RCC_AHBPeriph_HWDIV RCC_AHBENR_HWDIV
+
+
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup APB2_peripheral
+/// @{
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1
+#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1
+#define RCC_APB2Periph_UART1 RCC_APB2ENR_UART1
+#define RCC_APB2Periph_COMP RCC_APB2ENR_COMP
+#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCU
+
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1
+
+#define RCC_APB2Periph_ADC2 RCC_APB2ENR_ADC2
+#define RCC_APB2Periph_ADC3 RCC_APB2ENR_ADC3
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFG
+#define RCC_APB2Periph_EXTI RCC_APB2ENR_EXTI
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup APB1_peripheral
+/// @{
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4
+#define RCC_APB1Periph_UART3 RCC_APB1ENR_UART3
+#define RCC_APB1Periph_BKP RCC_APB1ENR_BKP
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DAC
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2
+#define RCC_APB1Periph_ALL 0x3AE64807
+#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN
+#define RCC_APB1Periph_CRS RCC_APB1ENR_CRS
+#define RCC_APB1Periph_UART2 RCC_APB1ENR_UART2
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDG
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWR
+
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWR
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3
+#define RCC_APB1ENR_SYSCFG RCC_APB1ENR_EXTI
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CRH_SECIE_Pos RTC_CR_SECIE_Pos
+#define RTC_CRH_SECIE RTC_CR_SECIE ///< Second Interrupt Enable
+#define RTC_CRH_ALRIE_Pos RTC_CR_ALRIE_Pos
+#define RTC_CRH_ALRIE RTC_CR_ALRIE ///< Alarm Interrupt Enable
+#define RTC_CRH_OWIE_Pos RTC_CR_OWIE_Pos
+#define RTC_CRH_OWIE RTC_CR_OWIE ///< OverfloW Interrupt Enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CRL_SECF_Pos RTC_CSR_SECF_Pos
+#define RTC_CRL_SECF RTC_CSR_SECF ///< Second Flag
+#define RTC_CRL_ALRF_Pos RTC_CSR_ALRF_Pos
+#define RTC_CRL_ALRF RTC_CSR_ALRF ///< Alarm Flag
+#define RTC_CRL_OWF_Pos RTC_CSR_OWF_Pos
+#define RTC_CRL_OWF RTC_CSR_OWF ///< OverfloW Flag
+#define RTC_CRL_RSF_Pos RTC_CSR_RSF_Pos
+#define RTC_CRL_RSF RTC_CSR_RSF ///< Registers Synchronized Flag
+#define RTC_CRL_CNF_Pos RTC_CSR_CNF_Pos
+#define RTC_CRL_CNF RTC_CSR_CNF ///< Configuration Flag
+#define RTC_CRL_RTOFF_Pos RTC_CSR_RTOFF_Pos
+#define RTC_CRL_RTOFF RTC_CSR_RTOFF ///< RTC operation OFF
+#define RTC_CRL_ALPEN_Pos RTC_CSR_ALPEN_Pos
+#define RTC_CRL_ALPEN RTC_CSR_ALPEN ///< RTC Alarm Loop Enable
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_TXREG_TXREG SPI_TDR_TXREG
+#define SPI_RXREG_RXREG SPI_RDR_RXREG
+
+#define SPI_CSTAT_TXEPT SPI_SR_TXEPT
+#define SPI_CSTAT_RXAVL SPI_SR_RXAVL
+#define SPI_CSTAT_TXFULL SPI_SR_TXFULL
+#define SPI_CSTAT_RXAVL_4BYTE SPI_SR_RXAVL_4BYTE
+#define SPI_CSTAT_TXFADDR SPI_SR_TXFADDR
+#define SPI_CSTAT_RXFADDR SPI_SR_RXFADDR
+
+#define SPI_INTSTAT_TX_INTF SPI_ISR_TX_INTF
+#define SPI_INTSTAT_RX_INTF SPI_ISR_RX_INTF
+#define SPI_INTSTAT_UNDERRUN_INTF SPI_ISR_UNDERRUN_INTF
+#define SPI_INTSTAT_RXOERR_INTF SPI_ISR_RXOERR_INTF
+#define SPI_INTSTAT_RXMATCH_INTF SPI_ISR_RXMATCH_INTF
+#define SPI_INTSTAT_RXFULL_INTF SPI_ISR_RXFULL_INTF
+#define SPI_INTSTAT_TXEPT_INTF SPI_ISR_TXEPT_INTF
+
+#define SPI_INTEN_TX_IEN SPI_IER_TX_IEN
+#define SPI_INTEN_RX_IEN SPI_IER_RX_IEN
+#define SPI_INTEN_UNDERRUN_IEN SPI_IER_UNDERRUN_IEN
+#define SPI_INTEN_RXOERR_IEN SPI_IER_RXOERR_IEN
+#define SPI_INTEN_RXMATCH_IEN SPI_IER_RXMATCH_IEN
+#define SPI_INTEN_RXFULL_IEN SPI_IER_RXFULL_IEN
+#define SPI_INTEN_TXEPT_IEN SPI_IER_TXEPT_IEN
+
+#define SPI_INTCLR_TX_ICLR SPI_ICR_TX_ICLR
+#define SPI_INTCLR_RX_ICLR SPI_ICR_RX_ICLR
+#define SPI_INTCLR_UNDERRUN_ICLR SPI_ICR_UNDERRUN_ICLR
+#define SPI_INTCLR_RXOERR_ICLR SPI_ICR_RXOERR_ICLR
+#define SPI_INTCLR_RXMATCH_ICLR SPI_ICR_RXMATCH_ICLR
+#define SPI_INTCLR_RXFULL_ICLR SPI_ICR_RXFULL_ICLR
+#define SPI_INTCLR_TXEPT_ICLR SPI_ICR_TXEPT_ICLR
+
+#define SPI_GCTL_SPIEN SPI_GCR_SPIEN
+#define SPI_GCTL_INT_EN SPI_GCR_IEN
+#define SPI_GCTL_MM SPI_GCR_MODE
+#define SPI_GCTL_TXEN SPI_GCR_TXEN
+#define SPI_GCTL_RXEN SPI_GCR_RXEN
+
+#define SPI_GCTL_RXTLF SPI_GCR_RXTLF
+#define SPI_GCTL_RXTLF_One SPI_GCR_RXTLF_One
+#define SPI_GCTL_RXTLF_Half SPI_GCR_RXTLF_Half
+
+#define SPI_GCTL_TXTLF_Pos SPI_GCR_TXTLF_Pos
+#define SPI_GCTL_TXTLF SPI_GCR_TXTLF
+#define SPI_GCTL_TXTLF_One SPI_GCR_TXTLF_One
+#define SPI_GCTL_TXTLF_Half SPI_GCR_TXTLF_Half
+#define SPI_GCTL_DMAEN SPI_GCR_DMAEN
+#define SPI_GCTL_NSS_SEL SPI_GCR_NSS
+#define SPI_GCTL_DATA_SEL SPI_GCR_DWSEL
+
+#define SPI_GCTL_NSSTOG SPI_GCR_NSSTOG
+
+#define SPI_CCTL_CPHA SPI_CCR_CPHA
+#define SPI_CCTL_CPOL SPI_CCR_CPOL
+#define SPI_CCTL_LSBFE SPI_CCR_LSBFE
+#define SPI_CCTL_SPILEN SPI_CCR_SPILEN
+#define SPI_CCTL_RXEDGE SPI_CCR_RXEDGE
+#define SPI_CCTL_TXEDGE SPI_CCR_TXEDGE
+
+#define SPI_CCTL_CPHASEL SPI_CCR_CPHASEL
+
+#define SPI_CCTL_HISPD SPI_CCR_HISPD
+
+#define SPI_SPBRG_SPBRG SPI_BRR_DIVF
+
+#define SPI_RXDNR_RXDNR SPI_RDNR_RDN
+
+#define SPI_EXTCTL_EXTLEN SPI_ECR_EXTLEN
+#define TIM_CR1_ARPE TIM_CR1_ARPEN
+
+#define TIM_SMCR_ECE TIM_SMCR_ECEN
+
+#define TIM_DIER_UIE TIM_DIER_UI
+#define TIM_DIER_CC1IE TIM_DIER_CC1I
+#define TIM_DIER_CC2IE TIM_DIER_CC2I
+#define TIM_DIER_CC3IE TIM_DIER_CC3I
+#define TIM_DIER_CC4IE TIM_DIER_CC4I
+#define TIM_DIER_COMIE TIM_DIER_COMI
+#define TIM_DIER_TIE TIM_DIER_TI
+#define TIM_DIER_BIE TIM_DIER_BI
+#define TIM_DIER_UDE TIM_DIER_UD
+#define TIM_DIER_CC1DE TIM_DIER_CC1D
+#define TIM_DIER_CC2DE TIM_DIER_CC2D
+#define TIM_DIER_CC3DE TIM_DIER_CC3D
+#define TIM_DIER_CC4DE TIM_DIER_CC4D
+#define TIM_DIER_COMDE TIM_DIER_COMD
+#define TIM_DIER_TDE TIM_DIER_TD
+
+#define TIM_DIER_UIEN TIM_DIER_UI
+#define TIM_DIER_CC1IEN TIM_DIER_CC1I
+#define TIM_DIER_CC2IEN TIM_DIER_CC2I
+#define TIM_DIER_CC3IEN TIM_DIER_CC3I
+#define TIM_DIER_CC4IEN TIM_DIER_CC4I
+#define TIM_DIER_COMIEN TIM_DIER_COMI
+#define TIM_DIER_TIEN TIM_DIER_TI
+#define TIM_DIER_BIEN TIM_DIER_BI
+#define TIM_DIER_UDEN TIM_DIER_UD
+#define TIM_DIER_CC1DEN TIM_DIER_CC1D
+#define TIM_DIER_CC2DEN TIM_DIER_CC2D
+#define TIM_DIER_CC3DEN TIM_DIER_CC3D
+#define TIM_DIER_CC4DEN TIM_DIER_CC4D
+#define TIM_DIER_COMDEN TIM_DIER_COMD
+#define TIM_DIER_TDEN TIM_DIER_TD
+
+#define TIM_DIER_CC5IE TIM_DIER_CC5I
+#define TIM_DIER_CC5DE TIM_DIER_CC5D
+
+#define TIM_SR_UIF TIM_SR_UI
+#define TIM_SR_CC1IF TIM_SR_CC1I
+#define TIM_SR_CC2IF TIM_SR_CC2I
+#define TIM_SR_CC3IF TIM_SR_CC3I
+#define TIM_SR_CC4IF TIM_SR_CC4I
+#define TIM_SR_COMIF TIM_SR_COMI
+#define TIM_SR_TIF TIM_SR_TI
+#define TIM_SR_BIF TIM_SR_BI
+#define TIM_SR_CC1OF TIM_SR_CC1O
+#define TIM_SR_CC2OF TIM_SR_CC2O
+#define TIM_SR_CC3OF TIM_SR_CC3O
+#define TIM_SR_CC4OF TIM_SR_CC4O
+
+#define TIM_SR_CC5IF TIM_SR_CC5I
+
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FEN
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PEN
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CEN
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FEN
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PEN
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CEN
+
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FEN
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PEN
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CEN
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FEN
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PEN
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CEN
+
+#define TIM_CCER_CC1E TIM_CCER_CC1EN
+#define TIM_CCER_CC1NE TIM_CCER_CC1NEN
+#define TIM_CCER_CC2E TIM_CCER_CC2EN
+#define TIM_CCER_CC2NE TIM_CCER_CC2NEN
+#define TIM_CCER_CC3E TIM_CCER_CC3EN
+#define TIM_CCER_CC3NE TIM_CCER_CC3NEN
+#define TIM_CCER_CC4E TIM_CCER_CC4EN
+
+#define TIM_CCER_CC5E TIM_CCER_CC5EN
+
+#define TIM_BDTR_BKE TIM_BDTR_BKEN
+#define TIM_BDTR_AOE TIM_BDTR_AOEN
+#define TIM_BDTR_MOE TIM_BDTR_MOEN
+
+#define TIM_BDTR_DOE TIM_BDTR_DOEN
+
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FEN
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PEN
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CEN
+#define UART_TDR_TXREG UART_TDR_DATA
+#define UART_RDR_RXREG UART_RDR_DATA
+
+#define UART_ISR_TX_INTF UART_ISR_TX
+#define UART_ISR_RX_INTF UART_ISR_RX
+#define UART_ISR_RXOERR_INTF UART_ISR_RXOERR
+#define UART_ISR_RXPERR_INTF UART_ISR_RXPERR
+#define UART_ISR_RXFERR_INTF UART_ISR_RXFERR
+#define UART_ISR_RXBRK_INTF UART_ISR_RXBRK
+
+#define UART_IER_TXIEN UART_IER_TX
+#define UART_IER_RXIEN UART_IER_RXI
+#define UART_IER_RXOERREN UART_IER_RXOERR
+#define UART_IER_RXPERREN UART_IER_RXPERR
+#define UART_IER_RXFERREN UART_IER_RXFERR
+#define UART_IER_RXBRKEN UART_IER_RXBRK
+
+#define UART_ICR_TXICLR UART_ICR_TX
+#define UART_ICR_RXICLR UART_ICR_RX
+#define UART_ICR_RXOERRCLR UART_ICR_RXOERR
+#define UART_ICR_RXPERRCLR UART_ICR_RXPERR
+#define UART_ICR_RXFERRCLR UART_ICR_RXFERR
+#define UART_ICR_RXBRKCLR UART_ICR_RXBRK
+
+#define UART_Mode_Rx UART_GCR_RX
+#define UART_Mode_Tx UART_GCR_TX
+#define UART_EN UART_GCR_UART
+#define UART_IT_RXBRK UART_IER_RXBRK
+#define UART_IT_ERR UART_IER_RXFERR
+#define UART_IT_PE UART_IER_RXPERR
+#define UART_OVER_ERR UART_IER_RXOERR
+#define UART_IT_RXIEN UART_IER_RX
+#define UART_IT_TXIEN UART_IER_TX
+
+#define UART_HardwareFlowControl_None UART_HWFlowControl_None
+
+#define UART_BRR_DIV_MANTISSA UART_BRR_MANTISSA
+#define UART_BRR_DIV_FRACTION UART_BRR_FRACTION
+
+#define UART_ISR_TXC_INTF UART_ISR_TXC
+#define UART_ISR_TXBRK_INTF UART_ISR_TXBRK
+#define UART_ISR_RXB8_INTF UART_ISR_RXB8
+
+#define UART_IT_RXB8 UART_IER_RXB8
+#define UART_IT_TXBRK UART_IER_TXBRK
+#define UART_IT_TXCIEN UART_IER_TXC
+#define UART_ICR_TXCCLR UART_ICR_TXC
+#define UART_ICR_TXBRKCLR UART_ICR_TXBRK
+#define UART_ICR_RXB8CLR UART_ICR_RXB8
+#define UART_SCR_SCAEN UART_SCR_SCARB
+#define UART_DMAReq_EN UART_GCR_DMA
+#define UART_FLAG_TXEMPTY UART_CSR_TXEPT
+#define UART_FLAG_TXFULL UART_CSR_TXFULL
+#define UART_FLAG_RXAVL UART_CSR_RXAVL
+#define UART_FLAG_TXEPT UART_CSR_TXC
+#define WWDG_CR_T WWDG_CR_CNT
+
+
+#if defined(ENABLEIP_USB_OTG)
+//USB
+
+///------------------- Bit definition for SETUP0 register --------------------
+
+//#define SETUP0 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP1 register --------------------
+//#define SETUP1 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP2 register --------------------
+//#define SETUP2 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP3 register --------------------
+//#define SETUP3 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP4 register --------------------
+//#define SETUP4 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP5 register --------------------
+//#define SETUP5 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP6 register --------------------
+//#define SETUP6 ((u16)0x00FF)
+
+///------------------- Bit definition for SETUP7 register --------------------
+//#define SETUP7 ((u16)0x00FF)
+
+
+
+#define USB_TOP_STATE_0 ((u16)0x0020)
+#define USB_TOP_STATE_1 ((u16)0x0040)
+
+///------------------- Bit definition for EP1_INT_STATE register --------------------
+#define EP1_INT_STATE_END ((u16)0x0002)
+#define EP1_INT_STATE_INNACK ((u16)0x0004)
+#define EP1_INT_STATE_INACK ((u16)0x0008)
+#define EP1_INT_STATE_INSTALL ((u16)0x0010)
+#define EP1_INT_STATE_OUTNACK ((u16)0x0020)
+#define EP1_INT_STATE_OUTACK ((u16)0x0040)
+#define EP1_INT_STATE_OUTSTALL ((u16)0x0080)
+
+///------------------- Bit definition for EP2_INT_STATE register --------------------
+#define EP2_INT_STATE_END ((u16)0x0002)
+#define EP2_INT_STATE_INNACK ((u16)0x0004)
+#define EP2_INT_STATE_INACK ((u16)0x0008)
+#define EP2_INT_STATE_INSTALL ((u16)0x0010)
+#define EP2_INT_STATE_OUTNACK ((u16)0x0020)
+#define EP2_INT_STATE_OUTACK ((u16)0x0040)
+#define EP2_INT_STATE_OUTSTALL ((u16)0x0080)
+
+///------------------- Bit definition for EP3_INT_STATE register --------------------
+#define EP3_INT_STATE_END ((u16)0x0002)
+#define EP3_INT_STATE_INNACK ((u16)0x0004)
+#define EP3_INT_STATE_INACK ((u16)0x0008)
+#define EP3_INT_STATE_INSTALL ((u16)0x0010)
+#define EP3_INT_STATE_OUTNACK ((u16)0x0020)
+#define EP3_INT_STATE_OUTACK ((u16)0x0040)
+#define EP3_INT_STATE_OUTSTALL ((u16)0x0080)
+
+///------------------- Bit definition for EP4_INT_STATE register --------------------
+#define EP4_INT_STATE_END ((u16)0x0002)
+#define EP4_INT_STATE_INNACK ((u16)0x0004)
+#define EP4_INT_STATE_INACK ((u16)0x0008)
+#define EP4_INT_STATE_INSTALL ((u16)0x0010)
+#define EP4_INT_STATE_OUTNACK ((u16)0x0020)
+#define EP4_INT_STATE_OUTACK ((u16)0x0040)
+#define EP4_INT_STATE_OUTSTALL ((u16)0x0080)
+
+
+///------------------- Bit definition for EP0_AVIL register --------------------
+#define EP0_AVIL_EPXAVIL ((u16)0x00FF)
+
+///------------------- Bit definition for EP1_AVIL register --------------------
+#define EP1_AVIL_EPXAVIL ((u16)0x00FF)
+
+///------------------- Bit definition for EP2_AVIL register --------------------
+#define EP2_AVIL_EPXAVIL ((u16)0x00FF)
+
+///------------------- Bit definition for EP3_AVIL register --------------------
+#define EP3_AVIL_EPXAVIL ((u16)0x00FF)
+
+///------------------- Bit definition for EP4_AVIL register --------------------
+#define EP4_AVIL_EPXAVIL ((u16)0x00FF)
+
+///------------------- Bit definition for EP0_CTRL register --------------------
+#define EP0_CTRL_TRANEN ((u16)0x0080)
+
+#define EP0_CTRL_TRANCOUNT ((u16)0x007F)
+#define EP0_CTRL_TRANCOUNT_0 ((u16)0x0001)
+#define EP0_CTRL_TRANCOUNT_1 ((u16)0x0002)
+#define EP0_CTRL_TRANCOUNT_2 ((u16)0x0004)
+#define EP0_CTRL_TRANCOUNT_3 ((u16)0x0008)
+#define EP0_CTRL_TRANCOUNT_4 ((u16)0x0010)
+#define EP0_CTRL_TRANCOUNT_5 ((u16)0x0020)
+#define EP0_CTRL_TRANCOUNT_6 ((u16)0x0040)
+
+///------------------- Bit definition for EP1_CTRL register --------------------
+#define EP1_CTRL_TRANEN ((u16)0x0080)
+
+#define EP1_CTRL_TRANCOUNT ((u16)0x007F)
+#define EP1_CTRL_TRANCOUNT_0 ((u16)0x0001)
+#define EP1_CTRL_TRANCOUNT_1 ((u16)0x0002)
+#define EP1_CTRL_TRANCOUNT_2 ((u16)0x0004)
+#define EP1_CTRL_TRANCOUNT_3 ((u16)0x0008)
+#define EP1_CTRL_TRANCOUNT_4 ((u16)0x0010)
+#define EP1_CTRL_TRANCOUNT_5 ((u16)0x0020)
+#define EP1_CTRL_TRANCOUNT_6 ((u16)0x0040)
+
+///------------------- Bit definition for EP2_CTRL register --------------------
+#define EP2_CTRL_TRANEN ((u16)0x0080)
+
+#define EP2_CTRL_TRANCOUNT ((u16)0x007F)
+#define EP2_CTRL_TRANCOUNT_0 ((u16)0x0001)
+#define EP2_CTRL_TRANCOUNT_1 ((u16)0x0002)
+#define EP2_CTRL_TRANCOUNT_2 ((u16)0x0004)
+#define EP2_CTRL_TRANCOUNT_3 ((u16)0x0008)
+#define EP2_CTRL_TRANCOUNT_4 ((u16)0x0010)
+#define EP2_CTRL_TRANCOUNT_5 ((u16)0x0020)
+#define EP2_CTRL_TRANCOUNT_6 ((u16)0x0040)
+
+///------------------- Bit definition for EP3_CTRL register --------------------
+#define EP3_CTRL_TRANEN ((u16)0x0080)
+
+#define EP3_CTRL_TRANCOUNT ((u16)0x007F)
+#define EP3_CTRL_TRANCOUNT_0 ((u16)0x0001)
+#define EP3_CTRL_TRANCOUNT_1 ((u16)0x0002)
+#define EP3_CTRL_TRANCOUNT_2 ((u16)0x0004)
+#define EP3_CTRL_TRANCOUNT_3 ((u16)0x0008)
+#define EP3_CTRL_TRANCOUNT_4 ((u16)0x0010)
+#define EP3_CTRL_TRANCOUNT_5 ((u16)0x0020)
+#define EP3_CTRL_TRANCOUNT_6 ((u16)0x0040)
+
+///------------------- Bit definition for EP4_CTRL register --------------------
+#define EP4_CTRL_TRANEN ((u16)0x0080)
+
+#define EP4_CTRL_TRANCOUNT ((u16)0x007F)
+#define EP4_CTRL_TRANCOUNT_0 ((u16)0x0001)
+#define EP4_CTRL_TRANCOUNT_1 ((u16)0x0002)
+#define EP4_CTRL_TRANCOUNT_2 ((u16)0x0004)
+#define EP4_CTRL_TRANCOUNT_3 ((u16)0x0008)
+#define EP4_CTRL_TRANCOUNT_4 ((u16)0x0010)
+#define EP4_CTRL_TRANCOUNT_5 ((u16)0x0020)
+#define EP4_CTRL_TRANCOUNT_6 ((u16)0x0040)
+
+
+#endif
+#endif //__MM32_REG_DEFINE_V1_H
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
new file mode 100644
index 00000000..1aab3ef1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
@@ -0,0 +1,953 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_adc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_ADC_H
+#define __REG_ADC_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) ///< Base Address: 0x40012400
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) ///< Base Address: 0x40012800
+#define ADC3_BASE (APB2PERIPH_BASE + 0x4C00) ///< Base Address: 0x40014C00
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Analog-to-Digital Converter register
+////////////////////////////////////////////////////////////////////////////////
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+
+typedef struct {
+ union {
+ __IO u32 DR; ///< ADC data register, offset: 0x00
+ __IO u32 ADDATA;
+ };
+ union {
+ __IO u32 CFGR; ///< ADC configuration register, offset: 0x04
+ __IO u32 ADCFG;
+ };
+ union {
+ __IO u32 CR; ///< ADC control register, offset: 0x08
+ __IO u32 ADCR;
+ };
+ union {
+ __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C
+ __IO u32 ADCHS;
+ };
+ union {
+ __IO u32 CMPR; ///< ADC window compare register, offset: 0x10
+ __IO u32 ADCMPR;
+ };
+ union {
+ __IO u32 SR; ///< ADC status register, offset: 0x14
+ __IO u32 ADSTA;
+ };
+ union {
+ __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18
+ __IO u32 ADDR0;
+ };
+ union {
+ __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C
+ __IO u32 ADDR1;
+ };
+ union {
+ __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20
+ __IO u32 ADDR2;
+ };
+ union {
+ __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24
+ __IO u32 ADDR3;
+ };
+ union {
+ __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28
+ __IO u32 ADDR4;
+ };
+ union {
+ __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C
+ __IO u32 ADDR5;
+ };
+ union {
+ __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30
+ __IO u32 ADDR6;
+ };
+ union {
+ __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34
+ __IO u32 ADDR7;
+ };
+ union {
+ __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38
+ __IO u32 ADDR8;
+ };
+ union {
+ __IO u32 CH9DR; ///< ADC channel9 data register, offset: 0x3C
+ __IO u32 ADDR9;
+ };
+ __IO u32 ADDR10; ///< offset: 0x40
+ __IO u32 ADDR11; ///< offset: 0x44
+ __IO u32 ADDR12; ///< offset: 0x48
+ __IO u32 ADDR13; ///< offset: 0x4C
+ union {
+ __IO u32 CH14DR; ///< ADC channel14 data register, offset: 0x50
+ __IO u32 ADDR14;
+ };
+ union {
+ __IO u32 CH15DR; ///< ADC channel15 data register, offset: 0x54
+ __IO u32 ADDR15;
+ };
+ __IO u32 SREXT; ///< ADC Extended Status Register, offset: 0x58
+ __IO u32 CHANY0; ///< ADC any Chan Select Register 0, offset: 0x5C
+ __IO u32 CHANY1; ///< ADC any Chan Select Register 1, offset: 0x60
+ __IO u32 ANYCFG; ///< ADC any Chan config Register, offset: 0x64
+ __IO u32 ANYCR; ///< ADC any Chan control Register, offset: 0x68
+ __IO u32 RESERVED0; ///< offset 0x6C
+ __IO u32 SMPR1; ///< Sampling configuration register 1 offset 0x70
+ __IO u32 SMPR2; ///< Sampling configuration register 2 offset 0x74
+ __IO u32 RESERVED1; ///< offset 0x78
+ __IO u32 JOFR0; ///< Injection channel data compensation register 0 offset 0x7C
+ __IO u32 JOFR1; ///< Injection channel data compensation register 1 offset 0x80
+ __IO u32 JOFR2; ///< Injection channel data compensation register 2 offset 0x84
+ __IO u32 JOFR3; ///< Injection channel data compensation register 3 offset 0x88
+ __IO u32 JSQR; ///< Injection sequence register offset 0x8C
+ __IO u32 JDATA; ///< Inject data register offset 0x90
+ __IO u32 RESERVED2; ///< offset 0x94
+ __IO u32 RESERVED3; ///< offset 0x98
+ __IO u32 RESERVED4; ///< offset 0x9C
+ __IO u32 RESERVED5; ///< offset 0xA0
+ __IO u32 RESERVED6; ///< offset 0xA4
+ __IO u32 RESERVED7; ///< offset 0xA8
+ __IO u32 RESERVED8; ///< offset 0xAC
+ __IO u32 JDR0; ///< Injection channel data register 0 offset 0xB0
+ __IO u32 JDR1; ///< Injection channel data register 1 offset 0xB4
+ __IO u32 JDR2; ///< Injection channel data register 2 offset 0xB8
+ __IO u32 JDR3; ///< Injection channel data register 3 offset 0xBC
+} ADC_TypeDef;
+
+#endif
+#ifdef USENNEWREGISTER
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Analog-to-Digital Converter register
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 DR; ///< ADC data register, offset: 0x00
+ __IO u32 CFGR; ///< ADC configuration register, offset: 0x04
+ __IO u32 CR; ///< ADC control register, offset: 0x08
+ __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C
+ __IO u32 CMPR; ///< ADC window compare register, offset: 0x10
+ __IO u32 SR; ///< ADC status register, offset: 0x14
+ __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18
+ __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C
+ __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20
+ __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24
+ __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28
+ __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C
+ __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30
+ __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34
+ __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38
+} ADC_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+ __IO u32 ADDATA; ///< ADC data register, offset: 0x00
+ __IO u32 ADCFG; ///< ADC configuration register, offset: 0x04
+ __IO u32 ADCR; ///< ADC control register, offset: 0x08
+ __IO u32 ADCHS; ///< ADC channel selection register, offset: 0x0C
+ __IO u32 ADCMPR; ///< ADC window compare register, offset: 0x10
+ __IO u32 ADSTA; ///< ADC status register, offset: 0x14
+ __IO u32 ADDR0; ///< ADC channel0 data register, offset: 0x18
+ __IO u32 ADDR1; ///< ADC channel1 data register, offset: 0x1C
+ __IO u32 ADDR2; ///< ADC channel2 data register, offset: 0x20
+ __IO u32 ADDR3; ///< ADC channel3 data register, offset: 0x24
+ __IO u32 ADDR4; ///< ADC channel4 data register, offset: 0x28
+ __IO u32 ADDR5; ///< ADC channel5 data register, offset: 0x2C
+ __IO u32 ADDR6; ///< ADC channel6 data register, offset: 0x30
+ __IO u32 ADDR7; ///< ADC channel7 data register, offset: 0x34
+ __IO u32 ADDR8; ///< ADC channel8 data register, offset: 0x38
+} ADC_TypeDef;
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef*) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef*) ADC3_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_DR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_DR_DATA_Pos (0)
+#define ADC_DR_DATA (0xFFFFU << ADC_DR_DATA_Pos) ///< ADC 12bit convert data
+
+#define ADC_DR_CH_Pos (16)
+#define ADC_DR_CH (0x0FU << ADC_DR_CH_Pos) ///< CHANNELSEL[19:16] (ADC current channel convert data)
+
+#define ADC_DR_CH0 (0x00U << ADC_DR_CH_Pos) ///< ADC Channel select 0
+#define ADC_DR_CH1 (0x01U << ADC_DR_CH_Pos) ///< ADC Channel select 1
+#define ADC_DR_CH2 (0x02U << ADC_DR_CH_Pos) ///< ADC Channel select 2
+#define ADC_DR_CH3 (0x03U << ADC_DR_CH_Pos) ///< ADC Channel select 3
+#define ADC_DR_CH4 (0x04U << ADC_DR_CH_Pos) ///< ADC Channel select 4
+#define ADC_DR_CH5 (0x05U << ADC_DR_CH_Pos) ///< ADC Channel select 5
+#define ADC_DR_CH6 (0x06U << ADC_DR_CH_Pos) ///< ADC Channel select 6
+#define ADC_DR_CH7 (0x07U << ADC_DR_CH_Pos) ///< ADC Channel select 7
+
+#define ADC_DR_CH8 (0x08U << ADC_DR_CH_Pos) ///< ADC Channel select 8
+
+#define ADC_DR_CH10 (0x0AU << ADC_DR_CH_Pos) ///< ADC Channel select 10
+#define ADC_DR_CH11 (0x0BU << ADC_DR_CH_Pos) ///< ADC Channel select 11
+#define ADC_DR_CH13 (0x0CU << ADC_DR_CH_Pos) ///< ADC Channel select 13
+
+#define ADC_DR_CH9 (0x09U << ADC_DR_CH_Pos) ///< ADC Channel select 9
+#define ADC_DR_CH14 (0x0EU << ADC_DR_CH_Pos) ///< ADC Channel select 14
+#define ADC_DR_CH15 (0x0FU << ADC_DR_CH_Pos) ///< ADC Channel select 15
+#define ADC_DR_OVERRUN_Pos (20)
+#define ADC_DR_OVERRUN (0x01U << ADC_DR_OVERRUN_Pos) ///< ADC data will be cover
+#define ADC_DR_VALID_Pos (21)
+#define ADC_DR_VALID (0x01U << ADC_DR_VALID_Pos) ///< ADC data[11:0] is valid
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CFGR_ADEN_Pos (0)
+#define ADC_CFGR_ADEN (0x01U << ADC_CFGR_ADEN_Pos) ///< Enable ADC convert
+#define ADC_CFGR_ADWEN_Pos (1)
+#define ADC_CFGR_ADWEN (0x01U << ADC_CFGR_ADWEN_Pos) ///< Enable ADC window compare
+
+
+#define ADC_CFGR_RSLTCTL_Pos (7)
+#define ADC_CFGR_RSLTCTL (0x07U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select
+#define ADC_CFGR_RSLTCTL_12 (0x00U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 12bit
+#define ADC_CFGR_RSLTCTL_11 (0x01U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 11bit
+#define ADC_CFGR_RSLTCTL_10 (0x02U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 10bit
+#define ADC_CFGR_RSLTCTL_9 (0x03U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 9bit
+#define ADC_CFGR_RSLTCTL_8 (0x04U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 8bit
+
+#define ADC_CFGR_TEN_Pos (2)
+#define ADC_CFGR_TEN (0x01U << ADC_CFGR_TEN_Pos) ///< Enable ADC temperature sensor
+#define ADC_CFGR_VEN_Pos (3)
+#define ADC_CFGR_VEN (0x01U << ADC_CFGR_VEN_Pos) ///< Enable ADC voltage reference
+
+
+
+
+
+#define ADC_CFGR_PRE_Pos (4)
+#define ADC_CFGR_PREL_Pos (14)
+#define ADC_CFGR_PRE ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos))
+#define ADC_CFGR_PRE_2 (0x00U << ADC_CFGR_PRE_Pos) ///< ADC preclk 2
+#define ADC_CFGR_PRE_4 (0x01U << ADC_CFGR_PRE_Pos) ///< ADC preclk 4
+#define ADC_CFGR_PRE_6 (0x02U << ADC_CFGR_PRE_Pos) ///< ADC preclk 6
+#define ADC_CFGR_PRE_8 (0x03U << ADC_CFGR_PRE_Pos) ///< ADC preclk 8
+#define ADC_CFGR_PRE_10 (0x04U << ADC_CFGR_PRE_Pos) ///< ADC preclk 10
+#define ADC_CFGR_PRE_12 (0x05U << ADC_CFGR_PRE_Pos) ///< ADC preclk 12
+#define ADC_CFGR_PRE_14 (0x06U << ADC_CFGR_PRE_Pos) ///< ADC preclk 14
+#define ADC_CFGR_PRE_16 (0x07U << ADC_CFGR_PRE_Pos) ///< ADC preclk 16
+#define ADC_CFGR_PRE_3 ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 3
+#define ADC_CFGR_PRE_5 ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 5
+#define ADC_CFGR_PRE_7 ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 7
+#define ADC_CFGR_PRE_9 ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 9
+#define ADC_CFGR_PRE_11 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 11
+#define ADC_CFGR_PRE_13 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 13
+#define ADC_CFGR_PRE_15 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 15
+#define ADC_CFGR_PRE_17 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 17
+
+#define ADC_CFGR_JADWEN_Pos (16)
+#define ADC_CFGR_JADWEN (0x01U << ADC_CFGR_JADWEN_Pos) ///< Inject ADC conversion window comparison enable
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CR_ADIE_Pos (0)
+#define ADC_CR_ADIE (0x01U << ADC_CR_ADIE_Pos) ///< ADC interrupt enable
+#define ADC_CR_ADWIE_Pos (1)
+#define ADC_CR_ADWIE (0x01U << ADC_CR_ADWIE_Pos) ///< ADC window compare interrupt enable
+#define ADC_CR_TRGEN_Pos (2)
+#define ADC_CR_TRGEN (0x01U << ADC_CR_TRGEN_Pos) ///< extranal trigger single start AD convert
+#define ADC_CR_DMAEN_Pos (3)
+#define ADC_CR_DMAEN (0x01U << ADC_CR_DMAEN_Pos) ///< ADC DMA enable
+
+#define ADC_CR_ADST_Pos (8)
+#define ADC_CR_ADST (0x01U << ADC_CR_ADST_Pos) ///< ADC start convert data
+#define ADC_CR_MODE_Pos (9)
+#define ADC_CR_MODE (0x03U << ADC_CR_MODE_Pos) ///< ADC convert mode
+#define ADC_CR_IMM (0x00U << ADC_CR_MODE_Pos) ///< ADC imm convert mode
+#define ADC_CR_SCAN (0x01U << ADC_CR_MODE_Pos) ///< ADC scan convert mode
+#define ADC_CR_CONTINUE (0x02U << ADC_CR_MODE_Pos) ///< ADC continue scan convert mode
+#define ADC_CR_ALIGN_Pos (11)
+#define ADC_CR_ALIGN (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data align
+#define ADC_CR_LEFT (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data left align
+#define ADC_CR_RIGHT (0x00U << ADC_CR_ALIGN_Pos) ///< ADC data right align
+#define ADC_CR_CMPCH_Pos (12)
+#define ADC_CR_CMPCH (0x0FU << ADC_CR_CMPCH_Pos) ///< CMPCH[15:12] ADC window compare channel0 convert data
+#define ADC_CR_CMPCH_0 (0x00U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 0 Conversion Results
+#define ADC_CR_CMPCH_1 (0x01U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 1 Conversion Results
+#define ADC_CR_CMPCH_2 (0x02U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 2 Conversion Results
+#define ADC_CR_CMPCH_4 (0x04U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 4 Conversion Results
+#define ADC_CR_CMPCH_5 (0x05U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 5 Conversion Results
+#define ADC_CR_CMPCH_6 (0x06U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 6 Conversion Results
+#define ADC_CR_CMPCH_7 (0x07U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 7 Conversion Results
+#define ADC_CR_CMPCH_8 (0x08U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 8 Conversion Results
+#define ADC_CR_CMPCH_9 (0x09U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 9 Conversion Results
+#define ADC_CR_CMPCH_10 (0x0AU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 10 Conversion Results
+#define ADC_CR_CMPCH_11 (0x0BU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 11 Conversion Results
+#define ADC_CR_CMPCH_13 (0x0DU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 13 Conversion Results
+#define ADC_CR_CMPCH_14 (0x0EU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 14 Conversion Results
+#define ADC_CR_CMPCH_ALL (0x0FU << ADC_CR_CMPCH_Pos) ///< Select Compare ALL Channel Conversion Results
+
+
+
+#define ADC_CR_SCANDIR_Pos (16)
+#define ADC_CR_SCANDIR (0x01U << ADC_CR_SCANDIR_Pos) ///< ADC scan direction
+#define ADC_CR_TRGSEL_H_Pos (17)
+#define ADC_CR_TRGSEL_L_Pos (4)
+#define ADC_CR_TRGSEL ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< TRGSEL[6:4][18:17] ADC external trigger source select
+#define ADC_CR_T1_CC1 (0x00U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC1
+#define ADC_CR_T1_CC2 (0x01U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC2
+#define ADC_CR_T1_CC3 (0x02U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC3
+#define ADC_CR_T2_CC2 (0x03U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T2_CC2
+#define ADC_CR_T3_TRIG (0x04U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_TRIG
+#define ADC_CR_T1_CC4_CC5 (0x05U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC4_CC5
+#define ADC_CR_T3_CC1 (0x06U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_CC1
+#define ADC_CR_EXTI_11 (0x07U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is EXTI_11
+#define ADC_CR_T1_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T1_TRIG
+#define ADC_CR_T8_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4
+#define ADC_CR_T8_CC4_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4_CC5
+#define ADC_CR_T2_CC1 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_CC1
+#define ADC_CR_T3_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T3_CC4
+#define ADC_CR_T2_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_TRIG
+#define ADC_CR_T8_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC5
+#define ADC_CR_EXTI_15 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is EXTI_15
+#define ADC_CR_TIM1_CC4 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC4
+#define ADC_CR_TIM1_CC5 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC5
+
+#define ADC_CR_TRGSHIFT_Pos (19)
+#define ADC_CR_TRGSHIFT (0x07U << ADC_CR_TRGSHIFT_Pos) ///< External trigger shift sample
+#define ADC_CR_TRGSHIFT_0 (0x00U << ADC_CR_TRGSHIFT_Pos) ///< No shift
+#define ADC_CR_TRGSHIFT_4 (0x01U << ADC_CR_TRGSHIFT_Pos) ///< Shift 4 period
+#define ADC_CR_TRGSHIFT_16 (0x02U << ADC_CR_TRGSHIFT_Pos) ///< Shift 16 period
+#define ADC_CR_TRGSHIFT_32 (0x03U << ADC_CR_TRGSHIFT_Pos) ///< Shift 32 period
+#define ADC_CR_TRGSHIFT_64 (0x04U << ADC_CR_TRGSHIFT_Pos) ///< Shift 64 period
+#define ADC_CR_TRGSHIFT_128 (0x05U << ADC_CR_TRGSHIFT_Pos) ///< Shift 128 period
+#define ADC_CR_TRGSHIFT_256 (0x06U << ADC_CR_TRGSHIFT_Pos) ///< Shift 256 period
+#define ADC_CR_TRGSHIFT_512 (0x07U << ADC_CR_TRGSHIFT_Pos) ///< Shift 512 period
+#define ADC_CR_CALIBEN_Pos (22)
+#define ADC_CR_CALIBEN (0x01U << ADC_CR_CALIBEN_Pos) ///< Self-calibration enable
+#define ADC_CR_CALIBSEL_Pos (23)
+#define ADC_CR_CALIBSEL (0x01U << ADC_CR_CALIBSEL_Pos) ///< Self-calibration voltage selection
+#define ADC_CR_TRG_EDGE_Pos (24)
+#define ADC_CR_TRG_EDGE (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC trig edge config
+#define ADC_CR_TRG_EDGE_DUAL (0x00U << ADC_CR_TRG_EDGE_Pos) ///< ADC dual edge trig mode
+#define ADC_CR_TRG_EDGE_DOWN (0x01U << ADC_CR_TRG_EDGE_Pos) ///< ADC down edge trig mode
+#define ADC_CR_TRG_EDGE_UP (0x02U << ADC_CR_TRG_EDGE_Pos) ///< ADC up edge trig mode
+#define ADC_CR_TRG_EDGE_MASK (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC mask edge trig mode
+
+#define ADC_CR_EOSMPIE_Pos (26)
+#define ADC_CR_EOSMPIE (0X01U << ADC_CR_EOSMPIE_Pos) ///< ADC end sampling flag interrupt enable
+#define ADC_CR_EOCIE_Pos (27)
+#define ADC_CR_EOCIE (0X01U << ADC_CR_EOCIE_Pos) ///< ADC end of conversion interrupt enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CHSR_CH0_Pos (0)
+#define ADC_CHSR_CH0 (0x01U << ADC_CHSR_CH0_Pos) ///< Enable ADC channel 0
+#define ADC_CHSR_CH1_Pos (1)
+#define ADC_CHSR_CH1 (0x01U << ADC_CHSR_CH1_Pos) ///< Enable ADC channel 1
+#define ADC_CHSR_CH2_Pos (2)
+#define ADC_CHSR_CH2 (0x01U << ADC_CHSR_CH2_Pos) ///< Enable ADC channel 2
+#define ADC_CHSR_CH3_Pos (3)
+#define ADC_CHSR_CH3 (0x01U << ADC_CHSR_CH3_Pos) ///< Enable ADC channel 3
+#define ADC_CHSR_CH4_Pos (4)
+#define ADC_CHSR_CH4 (0x01U << ADC_CHSR_CH4_Pos) ///< Enable ADC channel 4
+#define ADC_CHSR_CH5_Pos (5)
+#define ADC_CHSR_CH5 (0x01U << ADC_CHSR_CH5_Pos) ///< Enable ADC channel 5
+#define ADC_CHSR_CH6_Pos (6)
+#define ADC_CHSR_CH6 (0x01U << ADC_CHSR_CH6_Pos) ///< Enable ADC channel 6
+#define ADC_CHSR_CH7_Pos (7)
+#define ADC_CHSR_CH7 (0x01U << ADC_CHSR_CH7_Pos) ///< Enable ADC channel 7
+
+#define ADC_CHSR_CH8_Pos (8)
+#define ADC_CHSR_CH8 (0x01U << ADC_CHSR_CH8_Pos) ///< Enable ADC channel 8
+#define ADC_CHSR_CH9_Pos (9)
+#define ADC_CHSR_CH9 (0x01U << ADC_CHSR_CH9_Pos) ///< Enable ADC channel 9
+#define ADC_CHSR_CHT_Pos (14)
+#define ADC_CHSR_CHT (0x01U << ADC_CHSR_CHT_Pos) ///< Enable Temperature Sensor
+#define ADC_CHSR_CHV_Pos (15)
+#define ADC_CHSR_CHV (0x01U << ADC_CHSR_CHV_Pos) ///< Enable Voltage Sensor
+
+
+#define ADC_CHSR_CH10_Pos (10)
+#define ADC_CHSR_CH10 (0x01U << ADC_CHSR_CH10_Pos) ///< Enable ADC channel 10
+#define ADC_CHSR_CH11_Pos (11)
+#define ADC_CHSR_CH11 (0x01U << ADC_CHSR_CH11_Pos) ///< Enable ADC channel 11
+#define ADC_CHSR_CH12_Pos (12)
+#define ADC_CHSR_CH12 (0x01U << ADC_CHSR_CH12_Pos) ///< Enable ADC channel 12
+#define ADC_CHSR_CH13_Pos (13)
+#define ADC_CHSR_CH13 (0x01U << ADC_CHSR_CH13_Pos) ///< Enable ADC channel 13
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CMPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CMPR_CMPLDATA_Pos (0)
+#define ADC_CMPR_CMPLDATA (0x0FFFU << ADC_CMPR_CMPLDATA_Pos) ///< ADC 12bit window compare DOWN LEVEL DATA
+#define ADC_CMPR_CMPHDATA_Pos (16)
+#define ADC_CMPR_CMPHDATA (0x0FFFU << ADC_CMPR_CMPHDATA_Pos) ///< ADC 12bit window compare UP LEVEL DATA
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_SR_ADIF_Pos (0)
+#define ADC_SR_ADIF (0x01U << ADC_SR_ADIF_Pos) ///< ADC convert complete flag
+#define ADC_SR_ADWIF_Pos (1)
+#define ADC_SR_ADWIF (0x01U << ADC_SR_ADWIF_Pos) ///< ADC compare flag
+#define ADC_SR_BUSY_Pos (2)
+#define ADC_SR_BUSY (0x01U << ADC_SR_BUSY_Pos) ///< ADC busy flag
+#define ADC_SR_CH_Pos (4)
+#define ADC_SR_CH (0x0FU << ADC_SR_CH_Pos) ///< CHANNEL[7:4] ADC current channel
+#define ADC_SR_CH0 (0x00U << ADC_SR_CH_Pos) ///< Channel 0 is the current conversion channel
+#define ADC_SR_CH1 (0x01U << ADC_SR_CH_Pos) ///< Channel 1 is the current conversion channel
+#define ADC_SR_CH2 (0x02U << ADC_SR_CH_Pos) ///< Channel 2 is the current conversion channel
+#define ADC_SR_CH3 (0x03U << ADC_SR_CH_Pos) ///< Channel 3 is the current conversion channel
+#define ADC_SR_CH4 (0x04U << ADC_SR_CH_Pos) ///< Channel 4 is the current conversion channel
+#define ADC_SR_CH5 (0x05U << ADC_SR_CH_Pos) ///< Channel 5 is the current conversion channel
+#define ADC_SR_CH6 (0x06U << ADC_SR_CH_Pos) ///< Channel 6 is the current conversion channel
+#define ADC_SR_CH7 (0x07U << ADC_SR_CH_Pos) ///< Channel 7 is the current conversion channel
+#define ADC_SR_CH8 (0x08U << ADC_SR_CH_Pos) ///< Channel 8 is the current conversion channel
+#define ADC_SR_CH9 (0x09U << ADC_SR_CH_Pos) ///< Channel 9 is the current conversion channel
+#define ADC_SR_CH10 (0x0AU << ADC_SR_CH_Pos) ///< Channel 10 is the current conversion channel
+#define ADC_SR_CH11 (0x0BU << ADC_SR_CH_Pos) ///< Channel 11 is the current conversion channel
+#define ADC_SR_CH13 (0x0DU << ADC_SR_CH_Pos) ///< Channel 13 is the current conversion channel
+#define ADC_SR_CH14 (0x0EU << ADC_SR_CH_Pos) ///< Channel 14 is the current conversion channel
+#define ADC_SR_CH15 (0x0FU << ADC_SR_CH_Pos) ///< Channel 15 is the current conversion channel
+
+
+#define ADC_SR_VALID_Pos (8)
+#define ADC_SR_VALID (0x0FFFU << ADC_SR_VALID_Pos) ///< VALID[19:8] ADC channel 0..11 valid flag
+#define ADC_SR_OVERRUN_Pos (20)
+#define ADC_SR_OVERRUN (0x0FFFU << ADC_SR_OVERRUN_Pos) ///< OVERRUN[31:20] ADC channel 0..11 data covered flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHnDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CHDR_DATA_Pos (0)
+#define ADC_CHDR_DATA (0xFFFFU << ADC_CHDR_DATA_Pos) ///< ADC channel convert data
+#define ADC_CHDR_OVERRUN_Pos (20)
+#define ADC_CHDR_OVERRUN (0x01U << ADC_CHDR_OVERRUN_Pos) ///< ADC data covered flag
+#define ADC_CHDR_VALID_Pos (21)
+#define ADC_CHDR_VALID (0x01U << ADC_CHDR_VALID_Pos) ///< ADC data valid flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_SREXT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_SREXT_VALID_Pos (0)
+#define ADC_SREXT_VALID (0x0FU << ADC_SREXT_VALID_Pos) ///< VALID[3:0] ADC channel 12,14..15 valid flag
+#define ADC_SREXT_OVERRUN_Pos (4)
+#define ADC_SREXT_OVERRUN (0x0FU << ADC_SREXT_OVERRUN_Pos) ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag
+
+
+#define ADC_SREXT_EOSMPIF_Pos (16)
+#define ADC_SREXT_EOSMPIF (0x01U << ADC_SREXT_EOSMPIF_Pos) ///< End of sampling interrupt flag
+#define ADC_SREXT_EOCIF_Pos (17)
+#define ADC_SREXT_EOCIF (0x01U << ADC_SREXT_EOCIF_Pos) ///< End of conversion interrupt flag
+#define ADC_SREXT_JEOSMPIF_Pos (18)
+#define ADC_SREXT_JEOSMPIF (0x01U << ADC_SREXT_JEOSMPIF_Pos) /// Injected channel end of sampling interrupt flag
+#define ADC_SREXT_JEOCIF_Pos (19)
+#define ADC_SREXT_JEOCIF (0x03U << ADC_SREXT_JEOCIF_Pos) ///< Injected channel end of conversion interrupt flag
+#define ADC_SREXT_JEOSIF_Pos (20)
+#define ADC_SREXT_JEOSIF (0x03U << ADC_SREXT_JEOSIF_Pos) ///< Injected channel end of sequential conversion interrupt flag
+#define ADC_SREXT_JBUSY_Pos (21)
+#define ADC_SREXT_JBUSY (0x01U << ADC_SREXT_JBUSY_Pos) ///< Injection mode busy/idle
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY0 select Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY0_SEL0_Pos (0) ///< CHANY_SEL0 (Bit 0)
+#define ADC1_CHANY0_SEL0 (0x0FU << ADC1_CHANY0_SEL0_Pos) ///< CHANY_SEL0 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL1_Pos (4) ///< CHANY_SEL1 (Bit 4)
+#define ADC1_CHANY0_SEL1 (0x0FU << ADC1_CHANY0_SEL1_Pos) ///< CHANY_SEL1 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL2_Pos (8) ///< CHANY_SEL2 (Bit 8)
+#define ADC1_CHANY0_SEL2 (0x0FU << ADC1_CHANY0_SEL2_Pos) ///< CHANY_SEL2 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL3_Pos (12) ///< CHANY_SEL3 (Bit 12)
+#define ADC1_CHANY0_SEL3 (0x0FU << ADC1_CHANY0_SEL3_Pos) ///< CHANY_SEL3 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL4_Pos (16) ///< CHANY_SEL4 (Bit 16)
+#define ADC1_CHANY0_SEL4 (0x0FU << ADC1_CHANY0_SEL4_Pos) ///< CHANY_SEL4 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL5_Pos (20) ///< CHANY_SEL5 (Bit 20)
+#define ADC1_CHANY0_SEL5 (0x0FU << ADC1_CHANY0_SEL5_Pos) ///< CHANY_SEL5 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL6_Pos (24) ///< CHANY_SEL6 (Bit 24)
+#define ADC1_CHANY0_SEL6 (0x0FU << ADC1_CHANY0_SEL6_Pos) ///< CHANY_SEL6 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL7_Pos (28) ///< CHANY_SEL7 (Bit 28)
+#define ADC1_CHANY0_SEL7 (0x0FU << ADC1_CHANY0_SEL7_Pos) ///< CHANY_SEL7 (Bitfield-Mask: 0x0f)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY1 select Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY1_SEL8_Pos (0) ///< CHANY_SEL8 (Bit 0)
+#define ADC1_CHANY1_SEL8 (0x0FU << ADC1_CHANY1_SEL8_Pos) ///< CHANY_SEL8 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL9_Pos (4) ///< CHANY_SEL9 (Bit 4)
+#define ADC1_CHANY1_SEL9 (0x0FU << ADC1_CHANY1_SEL9_Pos) ///< CHANY_SEL9 (Bitfield-Mask: 0x0f)
+
+#define ADC1_CHANY1_SEL14_Pos (24) ///< CHANY_SEL14 (Bit 24)
+#define ADC1_CHANY1_SEL14 (0x0FU << ADC1_CHANY1_SEL14_Pos) ///< CHANY_SEL14 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL15_Pos (28) ///< CHANY_SEL15 (Bit 28)
+#define ADC1_CHANY1_SEL15 (0x0FU << ADC1_CHANY1_SEL15_Pos) ///< CHANY_SEL15 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL10_Pos (8) ///< CHANY_SEL10 (Bit 8)
+#define ADC1_CHANY1_SEL10 (0x0FU << ADC1_CHANY1_SEL10_Pos) ///< CHANY_SEL10 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL11_Pos (12) ///< CHANY_SEL11 (Bit 12)
+#define ADC1_CHANY1_SEL11 (0x0FU << ADC1_CHANY1_SEL11_Pos) ///< CHANY_SEL11 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL12_Pos (16) ///< CHANY_SEL12 (Bit 16)
+#define ADC1_CHANY1_SEL12 (0x0FU << ADC1_CHANY1_SEL12_Pos) ///< CHANY_SEL12 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL13_Pos (20) ///< CHANY_SEL13 (Bit 20)
+#define ADC1_CHANY1_SEL13 (0x0FU << ADC1_CHANY1_SEL13_Pos) ///< CHANY_SEL13 (Bitfield-Mask: 0x0f)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY config number Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY_CFG_NUM_Max (16) ///< CHANY_CFG_NUM Max Value is 16
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY_CR_MDEN_Pos (0) ///< CHANY_MDEN (Bit 0)
+#define ADC1_CHANY_CR_MDEN (0x01U << ADC1_CHANY_CR_MDEN_Pos) ///< CHANY_MDEN (Bitfield-Mask: 0x01)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_ANY_CR mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_ANY_CR_JTRGEDGE_Pos (16) ///< Injection mode triggers edge selection
+#define ADC_ANY_CR_JTRGEDGE_R_F (0x00U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Triggered along both rising and falling edges
+#define ADC_ANY_CR_JTRGEDGE_F (0x01U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Drop edge trigger
+#define ADC_ANY_CR_JTRGEDGE_R (0x02U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Rising edge trigger
+#define ADC_ANY_CR_JTRGEDGE_S (0x03U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Shield trigger
+
+#define ADC_ANY_CR_JTRGSHIFT_Pos (13) ///< Injection mode external trigger delay sampling
+#define ADC_ANY_CR_JTRGSHIFT_0 (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 0 cycle
+#define ADC_ANY_CR_JTRGSHIFT_4 (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 4 cycle
+#define ADC_ANY_CR_JTRGSHIFT_16 (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 16 cycle
+#define ADC_ANY_CR_JTRGSHIFT_32 (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 32 cycle
+#define ADC_ANY_CR_JTRGSHIFT_64 (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 64 cycle
+#define ADC_ANY_CR_JTRGSHIFT_128 (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 128 cycle
+#define ADC_ANY_CR_JTRGSHIFT_256 (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 256 cycle
+#define ADC_ANY_CR_JTRGSHIFT_512 (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 512 cycle
+
+#define ADC_ANY_CR_JTRGSEL_Pos (8) ///< External event select for injected group
+#define ADC_ANY_CR_JTRGSEL (0x07U << ADC_ANY_CR_JTRGSEL_Pos)
+#define ADC_ANY_CR_JTRGSEL_TIM1_TRGO (0x00U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 TRGO
+#define ADC_ANY_CR_JTRGSEL_TIM1_CC4 (0x01U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4
+#define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 and CC5
+#define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM2 CC1 and TIM4 CC1
+#define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM3 CC4 and TIM5 CC4
+#define ADC_ANY_CR_JTRGSEL_TIM8_CC4 (0x05U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4
+#define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 and CC5
+#define ADC_ANY_CR_JTRGSEL_EXTI12 (0x07U << ADC_ANY_CR_JTRGSEL_Pos) ///< EXTI12
+
+#define ADC_ANY_CR_JTRGEN_Pos (7)
+#define ADC_ANY_CR_JTRGEN (0x01U << ADC_ANY_CR_JTRGEN_Pos) ///< External trigger conversion mode for injected channels
+#define ADC_ANY_CR_JADST_Pos (6)
+#define ADC_ANY_CR_JADST (0x01U << ADC_ANY_CR_JADST_Pos) ///< Start conversion of injected channels
+#define ADC_ANY_CR_JAUTO_Pos (5)
+#define ADC_ANY_CR_JAUTO (0x01U << ADC_ANY_CR_JAUTO_Pos) ///© COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_BKP_H
+#define __REG_BKP_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+#define BKP_BASE (APB1PERIPH_BASE + 0x2840) ///< Base Address: 0x40002840
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#define BKP_NUMBER 20
+
+typedef struct {
+ __IO u32 RTCCR; ///< RTC clock calibration register, offset: 0x00
+ __IO u32 CR; ///< BKP control register, offset: 0x04
+ __IO u32 CSR; ///< BKP control/status register, offset: 0x08
+ __IO u32 RESERVED0; ///< Reserved, offset: 0x0C
+ __IO u32 DR1; ///< BKP data register 1, offset: 0x10
+ __IO u32 DR2; ///< BKP data register 2, offset: 0x14
+ __IO u32 DR3; ///< BKP data register 3, offset: 0x18
+ __IO u32 DR4; ///< BKP data register 4, offset: 0x1C
+ __IO u32 DR5; ///< BKP data register 5, offset: 0x20
+ __IO u32 DR6; ///< BKP data register 6, offset: 0x24
+ __IO u32 DR7; ///< BKP data register 7, offset: 0x28
+ __IO u32 DR8; ///< BKP data register 8, offset: 0x2C
+ __IO u32 DR9; ///< BKP data register 9, offset: 0x30
+ __IO u32 DR10; ///< BKP data register 10 offset: 0x34
+ __IO u32 DR11; ///< BKP data register 11, offset: 0x38
+ __IO u32 DR12; ///< BKP data register 12, offset: 0x3C
+ __IO u32 DR13; ///< BKP data register 13, offset: 0x40
+ __IO u32 DR14; ///< BKP data register 14, offset: 0x44
+ __IO u32 DR15; ///< BKP data register 15, offset: 0x48
+ __IO u32 DR16; ///< BKP data register 16, offset: 0x4C
+ __IO u32 DR17; ///< BKP data register 17, offset: 0x50
+ __IO u32 DR18; ///< BKP data register 18, offset: 0x54
+ __IO u32 DR19; ///< BKP data register 19, offset: 0x58
+ __IO u32 DR20; ///< BKP data register 20, offset: 0x5C
+} BKP_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP ((BKP_TypeDef*) BKP_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_DRn Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_DR_DATA_Pos (0)
+#define BKP_DR_DATA (0xFFFFU << BKP_DR_DATA) ///< Backup data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_RTCCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_RTCCR_CAL_Pos (0)
+#define BKP_RTCCR_CAL (0x7FU << BKP_RTCCR_CAL_Pos) ///< Calibration value
+#define BKP_RTCCR_CCO_Pos (7)
+#define BKP_RTCCR_CCO (0x01U << BKP_RTCCR_CCO_Pos) ///< Calibration Clock Output
+#define BKP_RTCCR_ASOE_Pos (8)
+#define BKP_RTCCR_ASOE (0x01U << BKP_RTCCR_ASOE_Pos) ///< Alarm or Second Output Enable
+#define BKP_RTCCR_ASOS_Pos (9)
+#define BKP_RTCCR_ASOS (0x01U << BKP_RTCCR_ASOS_Pos) ///< Alarm or Second Output Selection
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_CR_TPE_Pos (0)
+#define BKP_CR_TPE (0x01U << BKP_CR_TPE_Pos) ///< TAMPER pin enable
+#define BKP_CR_TPAL_Pos (1)
+#define BKP_CR_TPAL (0x01U << BKP_CR_TPAL_Pos) ///< TAMPER pin active level
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_CSR_CTE_Pos (0)
+#define BKP_CSR_CTE (0x01U << BKP_CSR_CTE_Pos) ///< Clear Tamper event
+#define BKP_CSR_CTI_Pos (1)
+#define BKP_CSR_CTI (0x01U << BKP_CSR_CTI_Pos) ///< Clear Tamper Interrupt
+#define BKP_CSR_TPIE_Pos (2)
+#define BKP_CSR_TPIE (0x01U << BKP_CSR_TPIE_Pos) ///< TAMPER Pin interrupt enable
+#define BKP_CSR_TEF_Pos (8)
+#define BKP_CSR_TEF (0x01U << BKP_CSR_TEF_Pos) ///< Tamper Event Flag
+#define BKP_CSR_TIF_Pos (9)
+#define BKP_CSR_TIF (0x01U << BKP_CSR_TIF_Pos) ///< Tamper Interrupt Flag
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
new file mode 100644
index 00000000..5f66bb68
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
@@ -0,0 +1,532 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_can.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_CAN_H
+#define __REG_CAN_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) ///< Base Address: 0x40006400
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN basic
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CR; ///< Control register, offset: 0x00
+ __IO u32 CMR; ///< Command register, offset: 0x04
+ __IO u32 SR; ///< © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_COMMON_H
+#define __REG_COMMON_H
+
+// Files includes
+#include
+#include
+#include "types.h"
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+#ifndef HSE_STARTUP_TIMEOUT
+#define HSE_STARTUP_TIMEOUT (0x0500U) ///< Time out for HSE start up.
+#endif
+#ifdef CUSTOM_HSE_VAL
+#ifndef HSE_VALUE
+#define HSE_VALUE (12000000U) ///< Value of the External oscillator in Hz.
+#endif
+#else
+#ifndef HSE_VALUE
+#define HSE_VALUE (8000000U) ///< Value of the External oscillator in Hz.
+#endif
+#endif
+
+
+
+#define HSI_VALUE_PLL_ON (8000000U) ///< Value of the Internal oscillator in Hz.
+#define HSI_DIV6 (8000000U) ///< Value of the Internal oscillator in Hz.
+// Value of the Internal oscillator in Hz.
+
+
+#define LSI_VALUE (40000U) ///< Value of the Internal oscillator in Hz.
+
+
+
+
+
+#ifndef HSI_VALUE
+
+#define HSI_VALUE (8000000U) ///< Value of the Internal oscillator in Hz.
+
+#endif
+
+
+
+
+
+
+
+
+#define __MPU_PRESENT (0) ///< Cortex-M3 does not provide a MPU present or not
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS (4) ///< Cortex-M3 uses 4 Bits for the Priority Levels
+//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#define __Vendor_SysTickConfig (0) ///< Set to 1 if different SysTick Config is used
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief MM32 MCU Interrupt Handle
+////////////////////////////////////////////////////////////////////////////////
+typedef enum IRQn {
+ NonMaskableInt_IRQn = -14, ///< 2 Non Maskable Interrupt
+ MemoryManagement_IRQn = -12, ///< 4 Cortex-M3 Memory Management Interrupt
+ BusFault_IRQn = -11, ///< 5 Cortex-M3 Bus Fault Interrupt
+ UsageFault_IRQn = -10, ///< 6 Cortex-M3 Usage Fault Interrupt
+ SVCall_IRQn = -5, ///< 11 Cortex-M3 SV Call Interrupt
+ DebugMonitor_IRQn = -4, ///< 12 Cortex-M3 Debug Monitor Interrupt
+ PendSV_IRQn = -2, ///< 14 Cortex-M3 Pend SV Interrupt
+ SysTick_IRQn = -1, ///< 15 Cortex-M3 System Tick Interrupt
+
+ WWDG_IWDG_IRQn = 0, ///< Watchdog interrupt
+ WWDG_IRQn = 0, ///< Watchdog interrupt
+ PVD_IRQn = 1, ///< (PVD) Interrupt
+ TAMPER_IRQn = 2, ///< Intrusion detection interrupted
+ RTC_IRQn = 3, ///< Real-time clock (RTC) global interrupt
+ FLASH_IRQn = 4, ///< Flash global interrupt
+ RCC_CRS_IRQn = 5, ///< RCC and CRS global interrupt
+ EXTI0_IRQn = 6, ///< EXTI line 0 interrupt
+ EXTI1_IRQn = 7, ///< EXTI line 1 interrupt
+ EXTI2_IRQn = 8, ///< EXTI line 2 interrupt
+ EXTI3_IRQn = 9, ///< EXTI line 3 interrupted
+ EXTI4_IRQn = 10, ///< EXTI line 4 interrupt
+ DMA1_Channel1_IRQn = 11, ///< DMA1 channel 1 global interrupt
+ DMA1_Channel2_IRQn = 12, ///< DMA1 channel 2 global interrupt
+ DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 global interrupt
+ DMA1_Channel4_IRQn = 14, ///< DMA1 channel 4 global interrupt
+ DMA1_Channel5_IRQn = 15, ///< DMA1 channel 5 global interrupt
+ DMA1_Channel6_IRQn = 16, ///< DMA1 channel 6 global interrupt
+ DMA1_Channel7_IRQn = 17, ///< DMA1 channel 7 global interrupt
+ ADC1_IRQn = 18, ///< ADC1 global interrupt
+ ADC1_2_IRQn = 18, ///< ADC1&ADC2 global interrupt
+ ADC2_IRQn = 18, ///< ADC2 global interrupt
+ FlashCache_IRQn = 19, ///< FlashCache outage
+ CAN1_RX_IRQn = 21, ///< CAN1 receive interrupt
+ CAN_IRQn = 21, ///< CAN interrupt
+ EXTI9_5_IRQn = 23, ///< EXTI line [9: 5] interrupted
+ TIM1_BRK_IRQn = 24, ///< TIM1 disconnect interrupt
+ TIM1_UP_IRQn = 25, ///< TIM1 update interrupt
+ IM1_TRG_COM_IRQn = 26, ///< TIM1 trigger and communication interrupt
+ TIM1_CC_IRQn = 27, ///< TIM1 capture compare interrupt
+ TIM2_IRQn = 28, ///< TIM2 global interrupt
+ TIM3_IRQn = 29, ///< TIM3 global interrupt
+ TIM4_IRQn = 30, ///< TIM4 global interrupt
+ I2C1_IRQn = 31, ///< I2C1 global interrupt
+ I2C2_IRQn = 33, ///< I2C2 global interrupt
+ SPI1_IRQn = 35, ///< SPI1 global interrupt
+ SPI2_IRQn = 36, ///< SPI2 global interrupt
+ UART1_IRQn = 37, ///< UART1 global interrupt
+ UART2_IRQn = 38, ///< UART2 global interrupt
+ UART3_IRQn = 39, ///< UART3 global interrupt
+ EXTI15_10_IRQn = 40, ///< EXTI line [15: 10] interrupted
+ RTCAlarm_IRQn = 41, ///< RTC alarm connected to EXTI interrupted
+ USB_WKUP_IRQn = 42, ///< Wake-up interrupt from USB connected to EXTI
+ TIM8_BRK_IRQn = 43, ///< TIM8 brake interruption
+ TIM8_UP_IRQn = 44, ///< TIM8 update interrupt
+ TIM8_TRG_COM_IRQn = 45, ///< TIM8 trigger, communication interrupt
+ TIM8_CC_IRQn = 46, ///< TIM8 capture compare interrupt
+ ADC3_IRQn = 47, ///< ADC3 global interrupt
+ SDIO_IRQn = 49, ///< SDIO global interrupt
+ TIM5_IRQn = 50, ///< TIM5 global interrupt
+ SPI3_IRQn = 51, ///< SPI3 global interrupt
+ UART4_IRQn = 52, ///< UART4 global interrupt
+ UART5_IRQn = 53, ///< UART5 global interrupt
+ TIM6_IRQn = 54, ///< TIM6 global interrupt
+ TIM7_IRQn = 55, ///< TIM7 global interrupt
+ DMA2_Channel1_IRQn = 56, ///< DMA2 channel 1 global interrupt
+ DMA2_Channel2_IRQn = 57, ///< DMA2 channel 2 global interrupt
+ DMA2_Channel3_IRQn = 58, ///< DMA2 channel 3 global interrupt
+ DMA2_Channel4_IRQn = 59, ///< DMA2 channel 4 global interrupt
+ DMA2_Channel5_IRQn = 60, ///< DMA2 channel 5 global interrupt
+ ETHERNET_MAC_IRQn = 61, ///< ETHERNET global interrupt
+ COMP1_2_IRQn = 64, ///< Comparator 1/2 interrupt connected to EXTI
+ USB_FS_IRQn = 67, ///< USB FS global interrupt
+ UART6_IRQn = 71, ///< UART6 global interrupt
+ UART7_IRQn = 82, ///< UART7 global interrupt
+ UART8_IRQn = 83, ///< UART8 global interrupt
+} IRQn_Type;
+
+
+
+
+#include
+
+
+
+#define PERIPH_BASE (0x40000000U) ///< Peripheral base address in the alias region
+
+#define EEPROM_BASE (0x08100000U) ///< EEPROM base address in the alias region
+
+
+#define SRAM_BITBAND_BASE (0x22000000U) ///< Peripheral base address in the bit-band region
+#define PERIPH_BITBAND_BASE (0x42000000U) ///< SRAM base address in the bit-band region
+
+#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x20000000)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UID type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UID_BASE (0x1FFFF7E0U) ///< Unique device ID register base address
+
+
+
+
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// @brief Nested Vectored Interrupt Controller
+///////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ISER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ISER_SETENA (0xFFFFFFFFU) ///< Interrupt set enable bits
+#define NVIC_ISER_SETENA_0 (0x00000001U) ///< bit 0
+#define NVIC_ISER_SETENA_1 (0x00000002U) ///< bit 1
+#define NVIC_ISER_SETENA_2 (0x00000004U) ///< bit 2
+#define NVIC_ISER_SETENA_3 (0x00000008U) ///< bit 3
+#define NVIC_ISER_SETENA_4 (0x00000010U) ///< bit 4
+#define NVIC_ISER_SETENA_5 (0x00000020U) ///< bit 5
+#define NVIC_ISER_SETENA_6 (0x00000040U) ///< bit 6
+#define NVIC_ISER_SETENA_7 (0x00000080U) ///< bit 7
+#define NVIC_ISER_SETENA_8 (0x00000100U) ///< bit 8
+#define NVIC_ISER_SETENA_9 (0x00000200U) ///< bit 9
+#define NVIC_ISER_SETENA_10 (0x00000400U) ///< bit 10
+#define NVIC_ISER_SETENA_11 (0x00000800U) ///< bit 11
+#define NVIC_ISER_SETENA_12 (0x00001000U) ///< bit 12
+#define NVIC_ISER_SETENA_13 (0x00002000U) ///< bit 13
+#define NVIC_ISER_SETENA_14 (0x00004000U) ///< bit 14
+#define NVIC_ISER_SETENA_15 (0x00008000U) ///< bit 15
+#define NVIC_ISER_SETENA_16 (0x00010000U) ///< bit 16
+#define NVIC_ISER_SETENA_17 (0x00020000U) ///< bit 17
+#define NVIC_ISER_SETENA_18 (0x00040000U) ///< bit 18
+#define NVIC_ISER_SETENA_19 (0x00080000U) ///< bit 19
+#define NVIC_ISER_SETENA_20 (0x00100000U) ///< bit 20
+#define NVIC_ISER_SETENA_21 (0x00200000U) ///< bit 21
+#define NVIC_ISER_SETENA_22 (0x00400000U) ///< bit 22
+#define NVIC_ISER_SETENA_23 (0x00800000U) ///< bit 23
+#define NVIC_ISER_SETENA_24 (0x01000000U) ///< bit 24
+#define NVIC_ISER_SETENA_25 (0x02000000U) ///< bit 25
+#define NVIC_ISER_SETENA_26 (0x04000000U) ///< bit 26
+#define NVIC_ISER_SETENA_27 (0x08000000U) ///< bit 27
+#define NVIC_ISER_SETENA_28 (0x10000000U) ///< bit 28
+#define NVIC_ISER_SETENA_29 (0x20000000U) ///< bit 29
+#define NVIC_ISER_SETENA_30 (0x40000000U) ///< bit 30
+#define NVIC_ISER_SETENA_31 (0x80000000U) ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ICER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ICER_CLRENA (0xFFFFFFFFU) ///< Interrupt clear-enable bits
+#define NVIC_ICER_CLRENA_0 (0x00000001U) ///< bit 0
+#define NVIC_ICER_CLRENA_1 (0x00000002U) ///< bit 1
+#define NVIC_ICER_CLRENA_2 (0x00000004U) ///< bit 2
+#define NVIC_ICER_CLRENA_3 (0x00000008U) ///< bit 3
+#define NVIC_ICER_CLRENA_4 (0x00000010U) ///< bit 4
+#define NVIC_ICER_CLRENA_5 (0x00000020U) ///< bit 5
+#define NVIC_ICER_CLRENA_6 (0x00000040U) ///< bit 6
+#define NVIC_ICER_CLRENA_7 (0x00000080U) ///< bit 7
+#define NVIC_ICER_CLRENA_8 (0x00000100U) ///< bit 8
+#define NVIC_ICER_CLRENA_9 (0x00000200U) ///< bit 9
+#define NVIC_ICER_CLRENA_10 (0x00000400U) ///< bit 10
+#define NVIC_ICER_CLRENA_11 (0x00000800U) ///< bit 11
+#define NVIC_ICER_CLRENA_12 (0x00001000U) ///< bit 12
+#define NVIC_ICER_CLRENA_13 (0x00002000U) ///< bit 13
+#define NVIC_ICER_CLRENA_14 (0x00004000U) ///< bit 14
+#define NVIC_ICER_CLRENA_15 (0x00008000U) ///< bit 15
+#define NVIC_ICER_CLRENA_16 (0x00010000U) ///< bit 16
+#define NVIC_ICER_CLRENA_17 (0x00020000U) ///< bit 17
+#define NVIC_ICER_CLRENA_18 (0x00040000U) ///< bit 18
+#define NVIC_ICER_CLRENA_19 (0x00080000U) ///< bit 19
+#define NVIC_ICER_CLRENA_20 (0x00100000U) ///< bit 20
+#define NVIC_ICER_CLRENA_21 (0x00200000U) ///< bit 21
+#define NVIC_ICER_CLRENA_22 (0x00400000U) ///< bit 22
+#define NVIC_ICER_CLRENA_23 (0x00800000U) ///< bit 23
+#define NVIC_ICER_CLRENA_24 (0x01000000U) ///< bit 24
+#define NVIC_ICER_CLRENA_25 (0x02000000U) ///< bit 25
+#define NVIC_ICER_CLRENA_26 (0x04000000U) ///< bit 26
+#define NVIC_ICER_CLRENA_27 (0x08000000U) ///< bit 27
+#define NVIC_ICER_CLRENA_28 (0x10000000U) ///< bit 28
+#define NVIC_ICER_CLRENA_29 (0x20000000U) ///< bit 29
+#define NVIC_ICER_CLRENA_30 (0x40000000U) ///< bit 30
+#define NVIC_ICER_CLRENA_31 (0x80000000U) ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ISPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ISPR_SETPEND (0xFFFFFFFFU) ///< Interrupt set-pending bits
+#define NVIC_ISPR_SETPEND_0 (0x00000001U) ///< bit 0
+#define NVIC_ISPR_SETPEND_1 (0x00000002U) ///< bit 1
+#define NVIC_ISPR_SETPEND_2 (0x00000004U) ///< bit 2
+#define NVIC_ISPR_SETPEND_3 (0x00000008U) ///< bit 3
+#define NVIC_ISPR_SETPEND_4 (0x00000010U) ///< bit 4
+#define NVIC_ISPR_SETPEND_5 (0x00000020U) ///< bit 5
+#define NVIC_ISPR_SETPEND_6 (0x00000040U) ///< bit 6
+#define NVIC_ISPR_SETPEND_7 (0x00000080U) ///< bit 7
+#define NVIC_ISPR_SETPEND_8 (0x00000100U) ///< bit 8
+#define NVIC_ISPR_SETPEND_9 (0x00000200U) ///< bit 9
+#define NVIC_ISPR_SETPEND_10 (0x00000400U) ///< bit 10
+#define NVIC_ISPR_SETPEND_11 (0x00000800U) ///< bit 11
+#define NVIC_ISPR_SETPEND_12 (0x00001000U) ///< bit 12
+#define NVIC_ISPR_SETPEND_13 (0x00002000U) ///< bit 13
+#define NVIC_ISPR_SETPEND_14 (0x00004000U) ///< bit 14
+#define NVIC_ISPR_SETPEND_15 (0x00008000U) ///< bit 15
+#define NVIC_ISPR_SETPEND_16 (0x00010000U) ///< bit 16
+#define NVIC_ISPR_SETPEND_17 (0x00020000U) ///< bit 17
+#define NVIC_ISPR_SETPEND_18 (0x00040000U) ///< bit 18
+#define NVIC_ISPR_SETPEND_19 (0x00080000U) ///< bit 19
+#define NVIC_ISPR_SETPEND_20 (0x00100000U) ///< bit 20
+#define NVIC_ISPR_SETPEND_21 (0x00200000U) ///< bit 21
+#define NVIC_ISPR_SETPEND_22 (0x00400000U) ///< bit 22
+#define NVIC_ISPR_SETPEND_23 (0x00800000U) ///< bit 23
+#define NVIC_ISPR_SETPEND_24 (0x01000000U) ///< bit 24
+#define NVIC_ISPR_SETPEND_25 (0x02000000U) ///< bit 25
+#define NVIC_ISPR_SETPEND_26 (0x04000000U) ///< bit 26
+#define NVIC_ISPR_SETPEND_27 (0x08000000U) ///< bit 27
+#define NVIC_ISPR_SETPEND_28 (0x10000000U) ///< bit 28
+#define NVIC_ISPR_SETPEND_29 (0x20000000U) ///< bit 29
+#define NVIC_ISPR_SETPEND_30 (0x40000000U) ///< bit 30
+#define NVIC_ISPR_SETPEND_31 (0x80000000U) ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ICPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ICPR_CLRPEND (0xFFFFFFFFU) ///< Interrupt clear-pending bits
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U) ///< bit 0
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U) ///< bit 1
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U) ///< bit 2
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U) ///< bit 3
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U) ///< bit 4
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U) ///< bit 5
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U) ///< bit 6
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U) ///< bit 7
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U) ///< bit 8
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U) ///< bit 9
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U) ///< bit 10
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U) ///< bit 11
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U) ///< bit 12
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U) ///< bit 13
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U) ///< bit 14
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U) ///< bit 15
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U) ///< bit 16
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U) ///< bit 17
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U) ///< bit 18
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U) ///< bit 19
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U) ///< bit 20
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U) ///< bit 21
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U) ///< bit 22
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U) ///< bit 23
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U) ///< bit 24
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U) ///< bit 25
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U) ///< bit 26
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U) ///< bit 27
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U) ///< bit 28
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U) ///< bit 29
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U) ///< bit 30
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U) ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_IABR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IABR_ACTIVE (0xFFFFFFFFU) ///< Interrupt active flags
+#define NVIC_IABR_ACTIVE_0 (0x00000001U) ///< bit 0
+#define NVIC_IABR_ACTIVE_1 (0x00000002U) ///< bit 1
+#define NVIC_IABR_ACTIVE_2 (0x00000004U) ///< bit 2
+#define NVIC_IABR_ACTIVE_3 (0x00000008U) ///< bit 3
+#define NVIC_IABR_ACTIVE_4 (0x00000010U) ///< bit 4
+#define NVIC_IABR_ACTIVE_5 (0x00000020U) ///< bit 5
+#define NVIC_IABR_ACTIVE_6 (0x00000040U) ///< bit 6
+#define NVIC_IABR_ACTIVE_7 (0x00000080U) ///< bit 7
+#define NVIC_IABR_ACTIVE_8 (0x00000100U) ///< bit 8
+#define NVIC_IABR_ACTIVE_9 (0x00000200U) ///< bit 9
+#define NVIC_IABR_ACTIVE_10 (0x00000400U) ///< bit 10
+#define NVIC_IABR_ACTIVE_11 (0x00000800U) ///< bit 11
+#define NVIC_IABR_ACTIVE_12 (0x00001000U) ///< bit 12
+#define NVIC_IABR_ACTIVE_13 (0x00002000U) ///< bit 13
+#define NVIC_IABR_ACTIVE_14 (0x00004000U) ///< bit 14
+#define NVIC_IABR_ACTIVE_15 (0x00008000U) ///< bit 15
+#define NVIC_IABR_ACTIVE_16 (0x00010000U) ///< bit 16
+#define NVIC_IABR_ACTIVE_17 (0x00020000U) ///< bit 17
+#define NVIC_IABR_ACTIVE_18 (0x00040000U) ///< bit 18
+#define NVIC_IABR_ACTIVE_19 (0x00080000U) ///< bit 19
+#define NVIC_IABR_ACTIVE_20 (0x00100000U) ///< bit 20
+#define NVIC_IABR_ACTIVE_21 (0x00200000U) ///< bit 21
+#define NVIC_IABR_ACTIVE_22 (0x00400000U) ///< bit 22
+#define NVIC_IABR_ACTIVE_23 (0x00800000U) ///< bit 23
+#define NVIC_IABR_ACTIVE_24 (0x01000000U) ///< bit 24
+#define NVIC_IABR_ACTIVE_25 (0x02000000U) ///< bit 25
+#define NVIC_IABR_ACTIVE_26 (0x04000000U) ///< bit 26
+#define NVIC_IABR_ACTIVE_27 (0x08000000U) ///< bit 27
+#define NVIC_IABR_ACTIVE_28 (0x10000000U) ///< bit 28
+#define NVIC_IABR_ACTIVE_29 (0x20000000U) ///< bit 29
+#define NVIC_IABR_ACTIVE_30 (0x40000000U) ///< bit 30
+#define NVIC_IABR_ACTIVE_31 (0x80000000U) ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI0 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR0_PRI_0 (0x000000FFU) ///< Priority of interrupt 0
+#define NVIC_IPR0_PRI_1 (0x0000FF00U) ///< Priority of interrupt 1
+#define NVIC_IPR0_PRI_2 (0x00FF0000U) ///< Priority of interrupt 2
+#define NVIC_IPR0_PRI_3 (0xFF000000U) ///< Priority of interrupt 3
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR1_PRI_4 (0x000000FFU) ///< Priority of interrupt 4
+#define NVIC_IPR1_PRI_5 (0x0000FF00U) ///< Priority of interrupt 5
+#define NVIC_IPR1_PRI_6 (0x00FF0000U) ///< Priority of interrupt 6
+#define NVIC_IPR1_PRI_7 (0xFF000000U) ///< Priority of interrupt 7
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR2_PRI_8 (0x000000FFU) ///< Priority of interrupt 8
+#define NVIC_IPR2_PRI_9 (0x0000FF00U) ///< Priority of interrupt 9
+#define NVIC_IPR2_PRI_10 (0x00FF0000U) ///< Priority of interrupt 10
+#define NVIC_IPR2_PRI_11 (0xFF000000U) ///< Priority of interrupt 11
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR3_PRI_12 (0x000000FFU) ///< Priority of interrupt 12
+#define NVIC_IPR3_PRI_13 (0x0000FF00U) ///< Priority of interrupt 13
+#define NVIC_IPR3_PRI_14 (0x00FF0000U) ///< Priority of interrupt 14
+#define NVIC_IPR3_PRI_15 (0xFF000000U) ///< Priority of interrupt 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR4_PRI_16 (0x000000FFU) ///< Priority of interrupt 16
+#define NVIC_IPR4_PRI_17 (0x0000FF00U) ///< Priority of interrupt 17
+#define NVIC_IPR4_PRI_18 (0x00FF0000U) ///< Priority of interrupt 18
+#define NVIC_IPR4_PRI_19 (0xFF000000U) ///< Priority of interrupt 19
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI5 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR5_PRI_20 (0x000000FFU) ///< Priority of interrupt 20
+#define NVIC_IPR5_PRI_21 (0x0000FF00U) ///< Priority of interrupt 21
+#define NVIC_IPR5_PRI_22 (0x00FF0000U) ///< Priority of interrupt 22
+#define NVIC_IPR5_PRI_23 (0xFF000000U) ///< Priority of interrupt 23
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI6 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR6_PRI_24 (0x000000FFU) ///< Priority of interrupt 24
+#define NVIC_IPR6_PRI_25 (0x0000FF00U) ///< Priority of interrupt 25
+#define NVIC_IPR6_PRI_26 (0x00FF0000U) ///< Priority of interrupt 26
+#define NVIC_IPR6_PRI_27 (0xFF000000U) ///< Priority of interrupt 27
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI7 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_28 (0x000000FFU) ///< Priority of interrupt 28
+#define NVIC_IPR7_PRI_29 (0x0000FF00U) ///< Priority of interrupt 29
+#define NVIC_IPR7_PRI_30 (0x00FF0000U) ///< Priority of interrupt 30
+#define NVIC_IPR7_PRI_31 (0xFF000000U) ///< Priority of interrupt 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI8 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_32 (0x000000FFU) ///< Priority of interrupt 32
+#define NVIC_IPR7_PRI_33 (0x0000FF00U) ///< Priority of interrupt 33
+#define NVIC_IPR7_PRI_34 (0x00FF0000U) ///< Priority of interrupt 34
+#define NVIC_IPR7_PRI_35 (0xFF000000U) ///< Priority of interrupt 35
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI9 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_36 (0x000000FFU) ///< Priority of interrupt 36
+#define NVIC_IPR7_PRI_37 (0x0000FF00U) ///< Priority of interrupt 37
+#define NVIC_IPR7_PRI_38 (0x00FF0000U) ///< Priority of interrupt 38
+#define NVIC_IPR7_PRI_39 (0xFF000000U) ///< Priority of interrupt 39
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI10 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_40 (0x000000FFU) ///< Priority of interrupt 40
+#define NVIC_IPR7_PRI_41 (0x0000FF00U) ///< Priority of interrupt 41
+#define NVIC_IPR7_PRI_42 (0x00FF0000U) ///< Priority of interrupt 42
+#define NVIC_IPR7_PRI_43 (0xFF000000U) ///< Priority of interrupt 43
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI11 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_44 (0x000000FFU) ///< Priority of interrupt 44
+#define NVIC_IPR7_PRI_45 (0x0000FF00U) ///< Priority of interrupt 45
+#define NVIC_IPR7_PRI_46 (0x00FF0000U) ///< Priority of interrupt 46
+#define NVIC_IPR7_PRI_47 (0xFF000000U) ///< Priority of interrupt 47
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_CPUID Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_CPUID_REVISION (0x0000000FU) ///< Implementation defined revision number
+#define SCB_CPUID_PARTNO (0x0000FFF0U) ///< Number of processor within family
+#define SCB_CPUID_Constant (0x000F0000U) ///< Reads as 0x0F
+#define SCB_CPUID_VARIANT (0x00F00000U) ///< Implementation defined variant number
+#define SCB_CPUID_IMPLEMENTER (0xFF000000U) ///< Implementer code. ARM is 0x41
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_ICSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_ICSR_VECTACTIVE (0x000001FFU) ///< Active ISR number field
+#define SCB_ICSR_RETTOBASE (0x00000800U) ///< All active exceptions minus the IPSR_current_exception yields the empty set
+#define SCB_ICSR_VECTPENDING (0x003FF000U) ///< Pending ISR number field
+#define SCB_ICSR_ISRPENDING (0x00400000U) ///< Interrupt pending flag
+#define SCB_ICSR_ISRPREEMPT (0x00800000U) ///< It indicates that a pending interrupt becomes active in the next running cycle
+#define SCB_ICSR_PENDSTCLR (0x02000000U) ///< Clear pending SysTick bit
+#define SCB_ICSR_PENDSTSET (0x04000000U) ///< Set pending SysTick bit
+#define SCB_ICSR_PENDSVCLR (0x08000000U) ///< Clear pending pendSV bit
+#define SCB_ICSR_PENDSVSET (0x10000000U) ///< Set pending pendSV bit
+#define SCB_ICSR_NMIPENDSET (0x80000000U) ///< Set pending NMI bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_VTOR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_VTOR_TBLOFF (0x1FFFFF80U) ///< Vector table base offset field
+#define SCB_VTOR_TBLBASE (0x20000000U) ///< Table base in code(0) or RAM(1)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_AIRCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_AIRCR_VECTRESET (0x00000001U) ///< System Reset bit
+#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) ///< Clear active vector bit
+#define SCB_AIRCR_SYSRESETREQ (0x00000004U) ///< Requests chip control logic to generate a reset
+#define SCB_AIRCR_PRIGROUP (0x00000700U) ///< PRIGROUP[2:0] bits (Priority group)
+#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) ///< Bit 0
+#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) ///< Bit 1
+#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) ///< Bit 2
+
+#define SCB_AIRCR_PRIGROUP0 (0x00000000U) ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
+#define SCB_AIRCR_PRIGROUP1 (0x00000100U) ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP2 (0x00000200U) ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP3 (0x00000300U) ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP4 (0x00000400U) ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP5 (0x00000500U) ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP6 (0x00000600U) ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP7 (0x00000700U) ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority)
+
+#define SCB_AIRCR_ENDIANESS (0x00008000U) ///< Data endianness bit
+#define SCB_AIRCR_VECTKEY (0xFFFF0000U) ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_SCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_SCR_SLEEPONEXIT (0x02U) ///< Sleep on exit bit
+#define SCB_SCR_SLEEPDEEP (0x04U) ///< Sleep deep bit
+#define SCB_SCR_SEVONPEND (0x10U) ///< Wake up from WFE
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_CCR_NONBASETHRDENA (0x0001U) ///< Thread mode can be entered from any level in Handler mode by controlled return value
+#define SCB_CCR_USERSETMPEND (0x0002U) ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
+#define SCB_CCR_UNALIGN_TRP (0x0008U) ///< Trap for unaligned access
+#define SCB_CCR_DIV_0_TRP (0x0010U) ///< Trap on Divide by 0
+#define SCB_CCR_BFHFNMIGN (0x0100U) ///< Handlers running at priority -1 and -2
+#define SCB_CCR_STKALIGN (0x0200U) ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_SHPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_SHPR_PRI_N (0x000000FFU) ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
+#define SCB_SHPR_PRI_N1 (0x0000FF00U) ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
+#define SCB_SHPR_PRI_N2 (0x00FF0000U) ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
+#define SCB_SHPR_PRI_N3 (0xFF000000U) ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_SHCSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_SHCSR_MEMFAULTACT (0x00000001U) ///< MemManage is active
+#define SCB_SHCSR_BUSFAULTACT (0x00000002U) ///< BusFault is active
+#define SCB_SHCSR_USGFAULTACT (0x00000008U) ///< UsageFault is active
+#define SCB_SHCSR_SVCALLACT (0x00000080U) ///< SVCall is active
+#define SCB_SHCSR_MONITORACT (0x00000100U) ///< Monitor is active
+#define SCB_SHCSR_PENDSVACT (0x00000400U) ///< PendSV is active
+#define SCB_SHCSR_SYSTICKACT (0x00000800U) ///< SysTick is active
+#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) ///< Usage Fault is pended
+#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) ///< MemManage is pended
+#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) ///< Bus Fault is pended
+#define SCB_SHCSR_SVCALLPENDED (0x00008000U) ///< SVCall is pended
+#define SCB_SHCSR_MEMFAULTENA (0x00010000U) ///< MemManage enable
+#define SCB_SHCSR_BUSFAULTENA (0x00020000U) ///< Bus Fault enable
+#define SCB_SHCSR_USGFAULTENA (0x00040000U) ///< UsageFault enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_CFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+///< MFSR
+#define SCB_CFSR_IACCVIOL (0x00000001U) ///< Instruction access violation
+#define SCB_CFSR_DACCVIOL (0x00000002U) ///< Data access violation
+#define SCB_CFSR_MUNSTKERR (0x00000008U) ///< Unstacking error
+#define SCB_CFSR_MSTKERR (0x00000010U) ///< Stacking error
+#define SCB_CFSR_MMARVALID (0x00000080U) ///< Memory Manage Address Register address valid flag
+///< BFSR
+#define SCB_CFSR_IBUSERR (0x00000100U) ///< Instruction bus error flag
+#define SCB_CFSR_PRECISERR (0x00000200U) ///< Precise data bus error
+#define SCB_CFSR_IMPRECISERR (0x00000400U) ///< Imprecise data bus error
+#define SCB_CFSR_UNSTKERR (0x00000800U) ///< Unstacking error
+#define SCB_CFSR_STKERR (0x00001000U) ///< Stacking error
+#define SCB_CFSR_BFARVALID (0x00008000U) ///< Bus Fault Address Register address valid flag
+///< UFSR
+#define SCB_CFSR_UNDEFINSTR (0x00010000U) ///< The processor attempt to excecute an undefined instruction
+#define SCB_CFSR_INVSTATE (0x00020000U) ///< Invalid combination of EPSR and instruction
+#define SCB_CFSR_INVPC (0x00040000U) ///< Attempt to load EXC_RETURN into pc illegally
+#define SCB_CFSR_NOCP (0x00080000U) ///< Attempt to use a coprocessor instruction
+#define SCB_CFSR_UNALIGNED (0x01000000U) ///< Fault occurs when there is an attempt to make an unaligned memory access
+#define SCB_CFSR_DIVBYZERO (0x02000000U) ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_HFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_HFSR_VECTTBL (0x00000002U) ///< Fault occures because of vector table read on exception processing
+#define SCB_HFSR_FORCED (0x40000000U) ///< Hard Fault activated when a configurable Fault was received and cannot activate
+#define SCB_HFSR_DEBUGEVT (0x80000000U) ///< Fault related to debug
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_DFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_DFSR_HALTED (0x01U) ///< Halt request flag
+#define SCB_DFSR_BKPT (0x02U) ///< BKPT flag
+#define SCB_DFSR_DWTTRAP (0x04U) ///< Data Watchpoint and Trace (DWT) flag
+#define SCB_DFSR_VCATCH (0x08U) ///< Vector catch flag
+#define SCB_DFSR_EXTERNAL (0x10U) ///< External debug request flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_MMFAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_MMFAR_ADDRESS (0xFFFFFFFFU) ///< Mem Manage fault address field
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_BFAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_BFAR_ADDRESS (0xFFFFFFFFU) ///< Bus fault address field
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_AFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_AFSR_IMPDEF (0xFFFFFFFFU) ///< Implementation defined
+
+
+
+#endif
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
new file mode 100644
index 00000000..71297819
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
@@ -0,0 +1,228 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_comp.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_COMP_H
+#define __REG_COMP_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_BASE (APB2PERIPH_BASE + 0x4000) ///< Base Address: 0x40014000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Comparators Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+
+
+
+ __IO u32 RESERVED1; ///< offset: 0x00
+ __IO u32 RESERVED2; ///< offset: 0x04
+ __IO u32 RESERVED3; ///< offset: 0x08
+ union {
+ __IO u32 CSR1; ///< COMP1 Control Status Register offset: 0x0C
+ __IO u32 COMP1_CSR;
+ };
+ union {
+ __IO u32 CSR2; ///< COMP2 Control Status Register offset: 0x10
+ __IO u32 COMP2_CSR;
+ };
+ __IO u32 RESERVED4; ///< offset: 0x14
+ union {
+ __IO u32 CRV; ///< COMP external reference voltage register offset: 0x18
+ __IO u32 COMP_CRV;
+ };
+ union {
+ __IO u32 POLL1; ///< COMP1 polling register offset: 0x1C
+ __IO u32 COMP1_POLL;
+ };
+ union {
+ __IO u32 POLL2; ///< COMP2 polling register offset: 0x20
+ __IO u32 COMP2_POLL;
+ };
+} COMP_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP ((COMP_TypeDef*) COMP_BASE)
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_CSR_EN_Pos (0)
+#define COMP_CSR_EN (0x01U << COMP_CSR_EN_Pos) ///< Comparator enable
+#define COMP_CSR_MODE_Pos (2)
+#define COMP_CSR_MODE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator mode
+#define COMP_CSR_MODE_LOWESTPOWER (0x00U << COMP_CSR_MODE_Pos) ///< Comparator lowest power mode
+#define COMP_CSR_MODE_LOWPOWER (0x01U << COMP_CSR_MODE_Pos) ///< Comparator low power mode
+#define COMP_CSR_MODE_MEDIUMRATE (0x02U << COMP_CSR_MODE_Pos) ///< Comparator medium rate mode
+#define COMP_CSR_MODE_HIGHRATE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator high rate mode
+
+#define COMP_CSR_INM_Pos (4)
+#define COMP_CSR_INM (0x03U << COMP_CSR_INM_Pos) ///< Comparator inverting input selection
+#define COMP_CSR_INM_0 (0x00U << COMP_CSR_INM_Pos) ///< INM0 as COMP inverting input
+#define COMP_CSR_INM_1 (0x01U << COMP_CSR_INM_Pos) ///< INM1 as COMP inverting input
+#define COMP_CSR_INM_2 (0x02U << COMP_CSR_INM_Pos) ///< INM2 as COMP inverting input
+#define COMP_CSR_INM_3 (0x03U << COMP_CSR_INM_Pos) ///< INM3 as COMP inverting input
+
+#define COMP_CSR_INP_Pos (7)
+#define COMP_CSR_INP (0x03U << COMP_CSR_INP_Pos) ///< Comparator non-inverting input selection
+#define COMP_CSR_INP_INP0 (0x00U << COMP_CSR_INP_Pos) ///< INP0 as COMP non-inverting input
+#define COMP_CSR_INP_INP1 (0x01U << COMP_CSR_INP_Pos) ///< INP1 as COMP non-inverting input
+#define COMP_CSR_INP_INP2 (0x02U << COMP_CSR_INP_Pos) ///< INP2 as COMP non-inverting input
+#define COMP_CSR_INP_INP3 (0x03U << COMP_CSR_INP_Pos) ///< INP3 as COMP non-inverting input
+
+#define COMP_CSR_OUT_Pos (10)
+#define COMP_CSR_OUT (0x0FU << COMP_CSR_OUT_Pos) ///< Comparator output selection
+#define COMP_CSR_OUT_TIM1_BRAKE (0x02U << COMP_CSR_OUT_Pos) ///< Timer1 brake input
+#define COMP_CSR_OUT_TIM8_BRAKE (0x03U << COMP_CSR_OUT_Pos) ///< Timer8 brake input
+#define COMP_CSR_OUT_TIM1_OCREFCLR (0x06U << COMP_CSR_OUT_Pos) ///< Timer1 ocrefclear input
+#define COMP_CSR_OUT_TIM1_CAPTURE1 (0x07U << COMP_CSR_OUT_Pos) ///< Timer1 input capture 1
+#define COMP_CSR_OUT_TIM2_CAPTURE4 (0x08U << COMP_CSR_OUT_Pos) ///< Timer2 input capture 4
+#define COMP_CSR_OUT_TIM2_OCREFCLR (0x09U << COMP_CSR_OUT_Pos) ///< Timer2 ocrefclear input
+#define COMP_CSR_OUT_TIM3_CAPTURE1 (0x0AU << COMP_CSR_OUT_Pos) ///< Timer3 input capture 1
+#define COMP_CSR_OUT_TIM3_OCREFCLR (0x0BU << COMP_CSR_OUT_Pos) ///< Timer3 ocrefclear input
+#define COMP_CSR_OUT_TIM8_OCREFCLR (0x0FU << COMP_CSR_OUT_Pos) ///< Timer8 ocrefclear input
+
+#define COMP_CSR_POL_Pos (15)
+#define COMP_CSR_POL (0x01U << COMP_CSR_POL_Pos) ///< Comparator output polarity
+#define COMP_CSR_HYST_Pos (16)
+#define COMP_CSR_HYST (0x03U << COMP_CSR_HYST_Pos) ///< Comparator hysteresis
+#define COMP_CSR_HYST_0 (0x00U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 0mV
+#define COMP_CSR_HYST_15 (0x01U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 15mV
+#define COMP_CSR_HYST_30 (0x02U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 30mV
+#define COMP_CSR_HYST_90 (0x03U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 90mV
+
+#define COMP_CSR_OFLT_Pos (18)
+#define COMP_CSR_OFLT (0x07U << COMP_CSR_OFLT_Pos) ///< Comparator output filter
+#define COMP_CSR_OFLT_0 (0x00U << COMP_CSR_OFLT_Pos) ///< 0 clock cycle
+#define COMP_CSR_OFLT_1 (0x01U << COMP_CSR_OFLT_Pos) ///< 2 clock cycle
+#define COMP_CSR_OFLT_2 (0x02U << COMP_CSR_OFLT_Pos) ///< 4 clock cycle
+#define COMP_CSR_OFLT_3 (0x03U << COMP_CSR_OFLT_Pos) ///< 8 clock cycle
+#define COMP_CSR_OFLT_4 (0x04U << COMP_CSR_OFLT_Pos) ///< 16 clock cycle
+#define COMP_CSR_OFLT_5 (0x05U << COMP_CSR_OFLT_Pos) ///< 32 clock cycle
+#define COMP_CSR_OFLT_6 (0x06U << COMP_CSR_OFLT_Pos) ///< 64 clock cycle
+#define COMP_CSR_OFLT_7 (0x07U << COMP_CSR_OFLT_Pos) ///< 128 clock cycle
+
+#define COMP_CSR_STA_Pos (30)
+#define COMP_CSR_STA (0x01U << COMP_CSR_STA_Pos) ///< Comparator output status
+#define COMP_CSR_LOCK_Pos (31)
+#define COMP_CSR_LOCK (0x01U << COMP_CSR_LOCK_Pos) ///< Comparator lock
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_CRV Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_CRV_Pos (0)
+#define COMP_CRV_MASK (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_1_20 (0x00U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_2_20 (0x01U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_3_20 (0x02U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_4_20 (0x03U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_5_20 (0x04U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_6_20 (0x05U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_7_20 (0x06U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_8_20 (0x07U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_9_20 (0x08U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_10_20 (0x09U << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_11_20 (0x0AU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_12_20 (0x0BU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_13_20 (0x0CU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_14_20 (0x0DU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_15_20 (0x0EU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+#define COMP_CRV_16_20 (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select
+
+#define COMP_CRV_EN_Pos (4)
+#define COMP_CRV_EN (0x01U << COMP_CRV_EN_Pos) ///< Comparator external reference voltage enable
+#define COMP_CRV_EN_DISABLE (0x00U << COMP_CRV_EN_Pos) ///< Disable comparator external reference voltage
+#define COMP_CRV_EN_ENABLE (0x01U << COMP_CRV_EN_Pos) ///< Enable comparator external reference voltage
+#define COMP_CRV_SRC_Pos (5)
+#define COMP_CRV_SRC (0x01U << COMP_CRV_SRC_Pos) ///< Comparator external reference voltage source select
+#define COMP_CRV_SRC_VREF (0x00U << COMP_CRV_SRC_Pos) ///< Select VREF
+#define COMP_CRV_SRC_AVDD (0x01U << COMP_CRV_SRC_Pos) ///< Select AVDD
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_POL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_POLL_EN_Pos (0)
+#define COMP_POLL_EN (0x01U << COMP_POLL_EN_Pos) ///< Comparator polling enable
+#define COMP_POLL_EN_DISABLE (0x00U << COMP_POLL_EN_Pos) ///< Disable comparator polling mode
+#define COMP_POLL_EN_ENABLE (0x01U << COMP_POLL_EN_Pos) ///< Enable comparator polling mode
+#define COMP_POLL_CH_Pos (1)
+#define COMP_POLL_CH (0x01U << COMP_POLL_CH_Pos) ///< Comparator polling channel
+#define COMP_POLL_CH_1_2 (0x00U << COMP_POLL_CH_Pos) ///< Polling channel 1/2
+#define COMP_POLL_CH_1_2_3 (0x01U << COMP_POLL_CH_Pos) ///< Polling channel 1/2/3
+#define COMP_POLL_FIXN_Pos (2)
+#define COMP_POLL_FIXN (0x01U << COMP_POLL_FIXN_Pos) ///< Polling inverting input fix
+#define COMP_POLL_FIXN_NOTFIXED (0x00U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input is not fixed
+#define COMP_POLL_FIXN_FIXED (0x01U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input fixed
+#define COMP_POLL_PERIOD_Pos (4)
+#define COMP_POLL_PERIOD (0x07U << COMP_POLL_PERIOD_Pos) ///< polling wait cycle
+#define COMP_POLL_PERIOD_1 (0x00U << COMP_POLL_PERIOD_Pos) ///< 1 clock cycle
+#define COMP_POLL_PERIOD_2 (0x01U << COMP_POLL_PERIOD_Pos) ///< 2 clock cycle
+#define COMP_POLL_PERIOD_4 (0x02U << COMP_POLL_PERIOD_Pos) ///< 4 clock cycle
+#define COMP_POLL_PERIOD_8 (0x03U << COMP_POLL_PERIOD_Pos) ///< 8 clock cycle
+#define COMP_POLL_PERIOD_16 (0x04U << COMP_POLL_PERIOD_Pos) ///< 16 clock cycle
+#define COMP_POLL_PERIOD_32 (0x05U << COMP_POLL_PERIOD_Pos) ///< 32 clock cycle
+#define COMP_POLL_PERIOD_64 (0x06U << COMP_POLL_PERIOD_Pos) ///< 64 clock cycle
+#define COMP_POLL_PERIOD_128 (0x07U << COMP_POLL_PERIOD_Pos) ///< 128 clock cycle
+#define COMP_POLL_POUT_Pos (8)
+#define COMP_POLL_POUT (0x07U << COMP_POLL_POUT_Pos) ///< Polling output
+#define COMP_POLL_POUT_Low (0x00U << COMP_POLL_POUT_Pos) ///< Non-inverting input is lower than inverting input
+#define COMP_POLL_POUT_High (0x01U << COMP_POLL_POUT_Pos) ///< Non-inverting input is higher than inverting input
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
new file mode 100644
index 00000000..9bb28e56
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
@@ -0,0 +1,102 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_crc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_CRC_H
+#define __REG_CRC_H
+
+// Files includes
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000) ///< Base Address: 0x40023000
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 DR; ///< CRC data register, offset: 0x00
+ __IO u32 IDR; ///< CRC independent data register, offset: 0x04
+ __IO u32 CR; ///< CRC control register, offset: 0x08
+ __IO u32 MIR; ///< Middle data register, offset: 0x08
+} CRC_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC ((CRC_TypeDef*) CRC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_DR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_DR_DATA_Pos (0)
+#define CRC_DR_DATA (0xFFFFFFFFU << CRC_DR_DATA_Pos) ///< Data register bits
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_IDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_IDR_DATA_Pos (0)
+#define CRC_IDR_DATA (0xFFU << CRC_IDR_DATA_Pos) ///< General-purpose 8-bit data register bits
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_CTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_CR_RESET_Pos (0)
+#define CRC_CR_RESET (0x01U << CRC_CR_RESET_Pos) ///< RESET bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_MIR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_MIR_Pos (0)
+#define CRC_MIR (0xFFFFFFFFU << CRC_MIR_Pos) ///< Middle data register
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
new file mode 100644
index 00000000..a8beece9
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
@@ -0,0 +1,152 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_crs.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_CRS_H
+#define __REG_CRS_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_BASE (APB1PERIPH_BASE + 0x6C00) ///< Base Address: 0x40006C00
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CR; ///< Control Register offset: 0x00
+ __IO u32 CFGR; ///< Configuration Register offset: 0x04
+ __IO u32 ISR; ///< Interrupt and Status Register offset: 0x08
+ __IO u32 ICR; ///< Interrupt Flag Clear Register offset: 0x0C
+} CRS_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS ((CRS_TypeDef*) CRS_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_CR_OKIE_Pos (0)
+#define CRS_CR_OKIE (0x01U << CRS_CR_OKIE_Pos) ///< SYNC event OK interrupt enable
+#define CRS_CR_WARNIE_Pos (1)
+#define CRS_CR_WARNIE (0x01U << CRS_CR_WARNIE_Pos) ///< SYNC warning interrupt enable
+#define CRS_CR_ERRIE_Pos (2)
+#define CRS_CR_ERRIE (0x01U << CRS_CR_ERRIE_Pos) ///< Synchronization or trimming error interrupt enable
+#define CRS_CR_EXPTIE_Pos (3)
+#define CRS_CR_EXPTIE (0x01U << CRS_CR_EXPTIE_Pos) ///< Expected SYNC interrupt enable
+#define CRS_CR_CNTEN_Pos (5)
+#define CRS_CR_CNTEN (0x01U << CRS_CR_CNTEN_Pos) ///< Frequency error counter enable
+#define CRS_CR_AUTOTRIMEN_Pos (6)
+#define CRS_CR_AUTOTRIMEN (0x01U << CRS_CR_AUTOTRIMEN_Pos) ///< Automatic trimming enable
+#define CRS_CR_SWSYNC_Pos (7)
+#define CRS_CR_SWSYNC (0x01U << CRS_CR_SWSYNC_Pos) ///< Generate software SYNC event
+#define CRS_CR_TRIM_Pos (8)
+#define CRS_CR_TRIM (0x3FFU << CRS_CR_TRIM_Pos) ///< HSI 48 oscillator smooth trimming
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_CFGR_RELOAD_Pos (0)
+#define CRS_CFGR_RELOAD (0xFFFFU << CRS_CFGR_RELOAD_Pos) ///< Counter reload value
+#define CRS_CFGR_FELIM_Pos (16)
+#define CRS_CFGR_FELIM (0xFFU << CRS_CFGR_FELIM_Pos) ///< Frequency error limit
+#define CRS_CFGR_DIV_Pos (24)
+#define CRS_CFGR_DIV (0x07U << CRS_CFGR_DIV_Pos) ///< SYNC divider
+#define CRS_CFGR_SRC_Pos (28)
+#define CRS_CFGR_SRC (0x03U << CRS_CFGR_SRC_Pos) ///< SYNC signal source selection
+#define CRS_CFGR_SRC_MCO (0x00U << CRS_CFGR_SRC_Pos)
+#define CRS_CFGR_SRC_USBSOF (0x02U << CRS_CFGR_SRC_Pos)
+#define CRS_CFGR_POL_Pos (31)
+#define CRS_CFGR_POL (0x01U << CRS_CFGR_POL_Pos) ///< SYNC polarity selection
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_ISR_OKIF_Pos (0)
+#define CRS_ISR_OKIF (0x01U << CRS_ISR_OKIF_Pos) ///< SYNC event OK flag
+#define CRS_ISR_WARNIF_Pos (1)
+#define CRS_ISR_WARNIF (0x01U << CRS_ISR_WARNIF_Pos) ///< SYNC warning flag
+#define CRS_ISR_ERRIF_Pos (2)
+#define CRS_ISR_ERRIF (0x01U << CRS_ISR_ERRIF_Pos) ///< Error flag
+#define CRS_ISR_EXPTIF_Pos (3)
+#define CRS_ISR_EXPTIF (0x01U << CRS_ISR_EXPTIF_Pos) ///< Expected SYNC flag
+#define CRS_ISR_ERR_Pos (8)
+#define CRS_ISR_ERR (0x01U << CRS_ISR_ERR_Pos) ///< SYNC error
+#define CRS_ISR_MISS_Pos (9)
+#define CRS_ISR_MISS (0x01U << CRS_ISR_MISS_Pos) ///< SYNC missed
+#define CRS_ISR_OVERFLOW_Pos (10)
+#define CRS_ISR_OVERFLOW (0x01U << CRS_ISR_OVERFLOW_Pos) ///< Trimming overflow or underflow
+#define CRS_ISR_FEDIR_Pos (15)
+#define CRS_ISR_FEDIR (0x01U << CRS_ISR_FEDIR_Pos) ///< Frequency error direction
+#define CRS_ISR_FECAP_Pos (16)
+#define CRS_ISR_FECAP (0xFFFFU << CRS_ISR_FECAP_Pos) ///< Frequency error capture
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_ICR_OK_Pos (0)
+#define CRS_ICR_OK (0x01U << CRS_ICR_OK_Pos) ///< SYNC event OK clear flag
+#define CRS_ICR_WARN_Pos (1)
+#define CRS_ICR_WARN (0x01U << CRS_ICR_WARN_Pos) ///< SYNC warning clear flag
+#define CRS_ICR_ERR_Pos (2)
+#define CRS_ICR_ERR (0x01U << CRS_ICR_ERR_Pos) ///< Error clear flag
+#define CRS_ICR_EXPT_Pos (3)
+#define CRS_ICR_EXPT (0x01U << CRS_ICR_EXPT_Pos) ///< Expected SYNC clear flag
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
new file mode 100644
index 00000000..2e8d1883
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
@@ -0,0 +1,247 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_dac.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_DAC_H
+#define __REG_DAC_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400) ///< Base Address: 0x40007400
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Digital to analog converter register
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CR; ///< DAC control register, offset: 0x00
+ __IO u32 SWTRIGR; ///< DAC software trigger register, offset: 0x04
+ __IO u32 DHR12R1; ///< Channel 1 12-bit right align data register, offset: 0x08
+ __IO u32 DHR12L1; ///< Channel 1 12-bit left align data register, offset: 0x0C
+ __IO u32 DHR8R1; ///< Channel 1 8-bit right align data register, offset: 0x10
+ __IO u32 DHR12R2; ///< Channel 2 12-bit right align data register, offset: 0x14
+ __IO u32 DHR12L2; ///< Channel 2 12-bit left align data register, offset: 0x18
+ __IO u32 DHR8R2; ///< Channel 2 8-bit right align data register, offset: 0x1C
+ __IO u32 DHR12RD; ///< Dual channel 12-bit right align data register,offset: 0x20
+ __IO u32 DHR12LD; ///< Dual channel 12-bit left align data register, offset: 0x24
+ __IO u32 DHR8RD; ///< Dual channel 8-bit right align data register, offset: 0x28
+ __IO u32 DOR1; ///< Channel 1 output register, offset: 0x2C
+ __IO u32 DOR2; ///< Channel 2 output register, offset: 0x30
+} DAC_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC ((DAC_TypeDef*) DAC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_CR_EN1_Pos (0)
+#define DAC_CR_EN1 (0x01U << DAC_CR_EN1_Pos) ///< DAC channel1 enable
+#define DAC_CR_BOFF1_Pos (1)
+#define DAC_CR_BOFF1 (0x01U << DAC_CR_BOFF1_Pos) ///< DAC channel1 output buffer disable
+#define DAC_CR_TEN1_Pos (2)
+#define DAC_CR_TEN1 (0x01U << DAC_CR_TEN1_Pos) ///< DAC channel1 Trigger enable
+#define DAC_CR_TSEL1_Pos (3)
+#define DAC_CR_TSEL1 (0x07U << DAC_CR_TSEL1_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection)
+#define DAC_CR_TSEL1_TIM1_TRIG (0x00U << DAC_CR_TSEL1_Pos) ///< TIM1_TRIG trigger
+#define DAC_CR_TSEL1_TIM3_TRIG (0x01U << DAC_CR_TSEL1_Pos) ///< TIM3_TRIG trigger
+#define DAC_CR_TSEL1_TIM2_TRIG (0x04U << DAC_CR_TSEL1_Pos) ///< TIM2_TRIG trigger
+#define DAC_CR_TSEL1_TIM4_TRIG (0x05U << DAC_CR_TSEL1_Pos) ///< TIM4_TRIG trigger
+#define DAC_CR_TSEL1_EXTI9 (0x06U << DAC_CR_TSEL1_Pos) ///< External interrupt line 9 trigger
+#define DAC_CR_TSEL1_SOFTWARE (0x07U << DAC_CR_TSEL1_Pos) ///< Software trigger
+#define DAC_CR_WAVE1_Pos (6)
+#define DAC_CR_WAVE1 (0x03U << DAC_CR_WAVE1_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
+#define DAC_CR_WAVE1_NONE (0x00U << DAC_CR_WAVE1_Pos) ///< Turn off waveform generation
+#define DAC_CR_WAVE1_NOISE (0x01U << DAC_CR_WAVE1_Pos) ///< Noise waveform generation
+#define DAC_CR_WAVE1_TRIANGLE (0x02U << DAC_CR_WAVE1_Pos) ///< Triangle wave generation
+#define DAC_CR_MAMP1_Pos (8)
+#define DAC_CR_MAMP1 (0x0FU << DAC_CR_MAMP1_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
+#define DAC_CR_MAMP1_1 (0x00U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1
+#define DAC_CR_MAMP1_3 (0x01U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 3
+#define DAC_CR_MAMP1_7 (0x02U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 7
+#define DAC_CR_MAMP1_15 (0x03U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 15
+#define DAC_CR_MAMP1_31 (0x04U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 31
+#define DAC_CR_MAMP1_63 (0x05U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 63
+#define DAC_CR_MAMP1_127 (0x06U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 127
+#define DAC_CR_MAMP1_255 (0x07U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 255
+#define DAC_CR_MAMP1_511 (0x08U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 511
+#define DAC_CR_MAMP1_1023 (0x09U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1023
+#define DAC_CR_MAMP1_2047 (0x0AU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 2047
+#define DAC_CR_MAMP1_4095 (0x0BU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 4095
+#define DAC_CR_DMAEN1_Pos (12)
+#define DAC_CR_DMAEN1 (0x01U << DAC_CR_DMAEN1_Pos) ///< DAC channel1 DMA enable
+#define DAC_CR_EN2_Pos (16)
+#define DAC_CR_EN2 (0x01U << DAC_CR_EN2_Pos) ///< DAC channel2 enable
+#define DAC_CR_BOFF2_Pos (17)
+#define DAC_CR_BOFF2 (0x01U << DAC_CR_BOFF2_Pos) ///< DAC channel2 output buffer disable
+#define DAC_CR_TEN2_Pos (18)
+#define DAC_CR_TEN2 (0x01U << DAC_CR_TEN2_Pos) ///< DAC channel2 Trigger enable
+#define DAC_CR_TSEL2_Pos (19)
+#define DAC_CR_TSEL2 (0x07U << DAC_CR_TSEL2_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection)
+#define DAC_CR_TSEL2_TIM1_TRIG (0x00U << DAC_CR_TSEL2_Pos) ///< TIM1_TRIG trigger
+#define DAC_CR_TSEL2_TIM3_TRIG (0x01U << DAC_CR_TSEL2_Pos) ///< TIM3_TRIG trigger
+#define DAC_CR_TSEL2_TIM2_TRIG (0x04U << DAC_CR_TSEL2_Pos) ///< TIM2_TRIG trigger
+#define DAC_CR_TSEL2_TIM4_TRIG (0x05U << DAC_CR_TSEL2_Pos) ///< TIM4_TRIG trigger
+#define DAC_CR_TSEL2_EXTI9 (0x06U << DAC_CR_TSEL2_Pos) ///< External interrupt line 9 trigger
+#define DAC_CR_TSEL2_SOFTWARE (0x07U << DAC_CR_TSEL2_Pos) ///< Software trigger
+#define DAC_CR_WAVE2_Pos (22)
+#define DAC_CR_WAVE2 (0x03U << DAC_CR_WAVE2_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
+#define DAC_CR_WAVE2_NONE (0x00U << DAC_CR_WAVE2_Pos) ///< Turn off waveform generation
+#define DAC_CR_WAVE2_NOISE (0x01U << DAC_CR_WAVE2_Pos) ///< Noise waveform generation
+#define DAC_CR_WAVE2_TRIANGLE (0x02U << DAC_CR_WAVE2_Pos) ///< Triangle wave generation
+#define DAC_CR_MAMP2_Pos (24)
+#define DAC_CR_MAMP2 (0x0FU << DAC_CR_MAMP2_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
+#define DAC_CR_MAMP2_1 (0x00U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1
+#define DAC_CR_MAMP2_3 (0x01U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 3
+#define DAC_CR_MAMP2_7 (0x02U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 7
+#define DAC_CR_MAMP2_15 (0x03U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 15
+#define DAC_CR_MAMP2_31 (0x04U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 31
+#define DAC_CR_MAMP2_63 (0x05U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 63
+#define DAC_CR_MAMP2_127 (0x06U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 127
+#define DAC_CR_MAMP2_255 (0x07U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 255
+#define DAC_CR_MAMP2_511 (0x08U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 511
+#define DAC_CR_MAMP2_1023 (0x09U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1023
+#define DAC_CR_MAMP2_2047 (0x0AU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 2047
+#define DAC_CR_MAMP2_4095 (0x0BU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 4095
+#define DAC_CR_DMAEN2_Pos (28)
+#define DAC_CR_DMAEN2 (0x01U << DAC_CR_DMAEN2_Pos) ///< DAC channel2 DMA enabled
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_SWTRIGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_SWTRIGR_SWTRIG1_Pos (0)
+#define DAC_SWTRIGR_SWTRIG1 (0x01U << DAC_SWTRIGR_SWTRIG1_Pos) ///< DAC channel1 software trigger
+#define DAC_SWTRIGR_SWTRIG2_Pos (1)
+#define DAC_SWTRIGR_SWTRIG2 (0x01U << DAC_SWTRIGR_SWTRIG2_Pos) ///< DAC channel2 software trigger
+#define DAC_SWTRIGR_DACPRE_Pos (8)
+#define DAC_SWTRIGR_DACPRE (0x7FU << DAC_SWTRIGR_DACPRE_Pos) ///< DAC prescale
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12R1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12R1_DACC1DHR_Pos (0)
+#define DAC_DHR12R1_DACC1DHR (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12L1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12L1_DACC1DHR_Pos (4)
+#define DAC_DHR12L1_DACC1DHR (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) ///< DAC channel1 12-bit Left align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR8R1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR8R1_DACC1DHR_Pos (0)
+#define DAC_DHR8R1_DACC1DHR (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12R2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12R2_DACC2DHR_Pos (0)
+#define DAC_DHR12R2_DACC2DHR (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12L2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12L2_DACC2DHR_Pos (4)
+#define DAC_DHR12L2_DACC2DHR (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) ///< DAC channel2 12-bit Left align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR8R2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR8R2_DACC2DHR_Pos (0)
+#define DAC_DHR8R2_DACC2DHR (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12RD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12RD_DACC1DHR_Pos (0)
+#define DAC_DHR12RD_DACC1DHR (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data
+#define DAC_DHR12RD_DACC2DHR_Pos (16)
+#define DAC_DHR12RD_DACC2DHR (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12LD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12LD_DACC1DHR_Pos (4)
+#define DAC_DHR12LD_DACC1DHR (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data
+#define DAC_DHR12LD_DACC2DHR_Pos (20)
+#define DAC_DHR12LD_DACC2DHR (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR8RD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR8RD_DACC1DHR_Pos (0)
+#define DAC_DHR8RD_DACC1DHR (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data
+#define DAC_DHR8RD_DACC2DHR_Pos (8)
+#define DAC_DHR8RD_DACC2DHR (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DOR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DOR1_DACC1DOR_Pos (0)
+#define DAC_DOR1_DACC1DOR (0xFFFU << DAC_DOR1_DACC1DOR_Pos) ///< DAC channel1 data output
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DOR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DOR2_DACC2DOR_Pos (0)
+#define DAC_DOR2_DACC2DOR (0xFFFU << DAC_DOR2_DACC2DOR_Pos) ///< DAC channel2 data output #endif
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
new file mode 100644
index 00000000..5e378753
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_dbg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_DBG_H
+#define __REG_DBG_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define DBG_BASE (0x40007080UL) ///< Base Address: 0x40007080
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DEBUG Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 IDCODE; ///< Code ID offset: 0x00
+ __IO u32 CR; ///< Control Register offset: 0x04
+} DBGMCU_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBGMCU type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DBGMCU ((DBGMCU_TypeDef*) DBG_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBGMCU_IDCODE Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DBGMCU_IDCODE_DEV_ID_Pos (0)
+#define DBGMCU_IDCODE_DEV_ID (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos) ///< Device identifier
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBGMCU_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DBGMCU_CR_SLEEP_Pos (0)
+#define DBGMCU_CR_SLEEP (0x01U << DBGMCU_CR_SLEEP_Pos) ///< Debug Sleep mode
+#define DBGMCU_CR_STOP_Pos (1)
+#define DBGMCU_CR_STOP (0x01U << DBGMCU_CR_STOP_Pos) ///< Debug Stop mode
+#define DBGMCU_CR_STANDBY_Pos (2)
+#define DBGMCU_CR_STANDBY (0x01U << DBGMCU_CR_STANDBY_Pos) ///< Debug Standby mode
+#define DBGMCU_CR_TRACE_IOEN_Pos (5)
+#define DBGMCU_CR_TRACE_IOEN (0x01U << DBGMCU_CR_TRACE_IOEN_Pos) ///< Trace pin assignment
+#define DBGMCU_CR_TRACE_MODE_Pos (6)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x03U << DBGMCU_CR_TRACE_MODE_Pos) ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control)
+#define DBGMCU_CR_TRACE_MODE_0 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 0
+#define DBGMCU_CR_TRACE_MODE_1 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 1
+#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00U << DBGMCU_CR_TRACE_MODE_Pos) ///< Tracking pin uses asynchronous mode
+#define DBGMCU_CR_TRACE_MODE_SYNC1 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 1
+#define DBGMCU_CR_TRACE_MODE_SYNC2 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 2
+
+#define DBGMCU_CR_IWDG_STOP_Pos (8)
+#define DBGMCU_CR_IWDG_STOP (0x01U << DBGMCU_CR_IWDG_STOP_Pos) ///< Debug independent watchdog stopped when core is halted
+#define DBGMCU_CR_WWDG_STOP_Pos (9)
+#define DBGMCU_CR_WWDG_STOP (0x01U << DBGMCU_CR_WWDG_STOP_Pos) ///< Debug window watchdog stopped when core is halted
+#define DBGMCU_CR_TIM_STOP_Pos (10)
+#define DBGMCU_CR_TIM1_STOP (0x01U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM1 counter stopped when core is halted
+#define DBGMCU_CR_TIM2_STOP (0x02U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM2 counter stopped when core is halted
+#define DBGMCU_CR_TIM3_STOP (0x04U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM3 counter stopped when core is halted
+#define DBGMCU_CR_TIM4_STOP (0x08U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM4 counter stopped when core is halted
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
new file mode 100644
index 00000000..ffcba565
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
@@ -0,0 +1,325 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_dma.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_DMA_H
+#define __REG_DMA_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) ///< Base Address: 0x40020000
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) ///< Base Address: 0x40020008
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) ///< Base Address: 0x4002001C
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) ///< Base Address: 0x40020030
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ///< Base Address: 0x40020044
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) ///< Base Address: 0x40020058
+
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) ///< Base Address: 0x4002006C
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) ///< Base Address: 0x40020080
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) ///< Base Address: 0x40020400
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) ///< Base Address: 0x40020408
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) ///< Base Address: 0x4002041C
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) ///< Base Address: 0x40020430
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) ///< Base Address: 0x40020444
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ///< Base Address: 0x40020458
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CCR; ///< DMA channel x configuration register offset: 0x00
+ __IO u32 CNDTR; ///< DMA channel x number of data register offset: 0x04
+ __IO u32 CPAR; ///< DMA channel x peripheral address register offset: 0x08
+ __IO u32 CMAR; ///< DMA channel x memory address register offset: 0x0C
+} DMA_Channel_TypeDef;
+
+typedef struct {
+ __IO u32 ISR; ///< Interrupt Status Register offset: 0x00
+ __IO u32 IFCR; ///< Interrupt Flag Clear Register offset: 0x04
+ __IO u32 CCRx; ///< Channel X configures registers offset: 0x08
+ __IO u32 CNDTRx; ///< Channel X transfer quantity register offset: 0x0C
+ __IO u32 CPARx; ///< Channel X peripheral address register offset: 0x10
+ __IO u32 CMARx; ///< Channel X memory address register offset: 0x14
+} DMA_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA1 ((DMA_TypeDef*) DMA1_BASE)
+#define DMA1_ch1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
+#define DMA1_ch2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
+#define DMA1_ch3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
+#define DMA1_ch4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
+#define DMA1_ch5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
+
+#define DMA1_Channel1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
+
+
+#define DMA1_ch6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
+#define DMA1_ch7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
+
+#define DMA1_Channel6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
+
+#define DMA2 ((DMA_TypeDef*) DMA2_BASE)
+#define DMA2_ch1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
+#define DMA2_ch2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
+#define DMA2_ch3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
+#define DMA2_ch4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
+#define DMA2_ch5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_ISR_GIF1_Pos (0)
+#define DMA_ISR_GIF1 (0x01U << DMA_ISR_GIF1_Pos) ///< Channel 1 Global interrupt flag
+#define DMA_ISR_TCIF1_Pos (1)
+#define DMA_ISR_TCIF1 (0x01U << DMA_ISR_TCIF1_Pos) ///< Channel 1 Transfer Complete flag
+#define DMA_ISR_HTIF1_Pos (2)
+#define DMA_ISR_HTIF1 (0x01U << DMA_ISR_HTIF1_Pos) ///< Channel 1 Half Transfer flag
+#define DMA_ISR_TEIF1_Pos (3)
+#define DMA_ISR_TEIF1 (0x01U << DMA_ISR_TEIF1_Pos) ///< Channel 1 Transfer Error flag
+#define DMA_ISR_GIF2_Pos (4)
+#define DMA_ISR_GIF2 (0x01U << DMA_ISR_GIF2_Pos) ///< Channel 2 Global interrupt flag
+#define DMA_ISR_TCIF2_Pos (5)
+#define DMA_ISR_TCIF2 (0x01U << DMA_ISR_TCIF2_Pos) ///< Channel 2 Transfer Complete flag
+#define DMA_ISR_HTIF2_Pos (6)
+#define DMA_ISR_HTIF2 (0x01U << DMA_ISR_HTIF2_Pos) ///< Channel 2 Half Transfer flag
+#define DMA_ISR_TEIF2_Pos (7)
+#define DMA_ISR_TEIF2 (0x01U << DMA_ISR_TEIF2_Pos) ///< Channel 2 Transfer Error flag
+#define DMA_ISR_GIF3_Pos (8)
+#define DMA_ISR_GIF3 (0x01U << DMA_ISR_GIF3_Pos) ///< Channel 3 Global interrupt flag
+#define DMA_ISR_TCIF3_Pos (9)
+#define DMA_ISR_TCIF3 (0x01U << DMA_ISR_TCIF3_Pos) ///< Channel 3 Transfer Complete flag
+#define DMA_ISR_HTIF3_Pos (10)
+#define DMA_ISR_HTIF3 (0x01U << DMA_ISR_HTIF3_Pos) ///< Channel 3 Half Transfer flag
+#define DMA_ISR_TEIF3_Pos (11)
+#define DMA_ISR_TEIF3 (0x01U << DMA_ISR_TEIF3_Pos) ///< Channel 3 Transfer Error flag
+#define DMA_ISR_GIF4_Pos (12)
+#define DMA_ISR_GIF4 (0x01U << DMA_ISR_GIF4_Pos) ///< Channel 4 Global interrupt flag
+#define DMA_ISR_TCIF4_Pos (13)
+#define DMA_ISR_TCIF4 (0x01U << DMA_ISR_TCIF4_Pos) ///< Channel 4 Transfer Complete flag
+#define DMA_ISR_HTIF4_Pos (14)
+#define DMA_ISR_HTIF4 (0x01U << DMA_ISR_HTIF4_Pos) ///< Channel 4 Half Transfer flag
+#define DMA_ISR_TEIF4_Pos (15)
+#define DMA_ISR_TEIF4 (0x01U << DMA_ISR_TEIF4_Pos) ///< Channel 4 Transfer Error flag
+#define DMA_ISR_GIF5_Pos (16)
+#define DMA_ISR_GIF5 (0x01U << DMA_ISR_GIF5_Pos) ///< Channel 5 Global interrupt flag
+#define DMA_ISR_TCIF5_Pos (17)
+#define DMA_ISR_TCIF5 (0x01U << DMA_ISR_TCIF5_Pos) ///< Channel 5 Transfer Complete flag
+#define DMA_ISR_HTIF5_Pos (18)
+#define DMA_ISR_HTIF5 (0x01U << DMA_ISR_HTIF5_Pos) ///< Channel 5 Half Transfer flag
+#define DMA_ISR_TEIF5_Pos (19)
+#define DMA_ISR_TEIF5 (0x01U << DMA_ISR_TEIF5_Pos) ///< Channel 5 Transfer Error flag
+
+#define DMA_ISR_GIF6_Pos (20)
+#define DMA_ISR_GIF6 (0x01U << DMA_ISR_GIF6_Pos) ///< Channel 6 Global interrupt flag
+#define DMA_ISR_TCIF6_Pos (21)
+#define DMA_ISR_TCIF6 (0x01U << DMA_ISR_TCIF6_Pos) ///< Channel 6 Transfer Complete flag
+#define DMA_ISR_HTIF6_Pos (22)
+#define DMA_ISR_HTIF6 (0x01U << DMA_ISR_HTIF6_Pos) ///< Channel 6 Half Transfer flag
+#define DMA_ISR_TEIF6_Pos (23)
+#define DMA_ISR_TEIF6 (0x01U << DMA_ISR_TEIF6_Pos) ///< Channel 6 Transfer Error flag
+#define DMA_ISR_GIF7_Pos (24)
+#define DMA_ISR_GIF7 (0x01U << DMA_ISR_GIF7_Pos) ///< Channel 7 Global interrupt flag
+#define DMA_ISR_TCIF7_Pos (25)
+#define DMA_ISR_TCIF7 (0x01U << DMA_ISR_TCIF7_Pos) ///< Channel 7 Transfer Complete flag
+#define DMA_ISR_HTIF7_Pos (26)
+#define DMA_ISR_HTIF7 (0x01U << DMA_ISR_HTIF7_Pos) ///< Channel 7 Half Transfer flag
+#define DMA_ISR_TEIF7_Pos (27)
+#define DMA_ISR_TEIF7 (0x01U << DMA_ISR_TEIF7_Pos) ///< Channel 7 Transfer Error flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_IFCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_IFCR_CGIF1_Pos (0)
+#define DMA_IFCR_CGIF1 (0x01U << DMA_IFCR_CGIF1_Pos) ///< Channel 1 Global interrupt clearr
+#define DMA_IFCR_CTCIF1_Pos (1)
+#define DMA_IFCR_CTCIF1 (0x01U << DMA_IFCR_CTCIF1_Pos) ///< Channel 1 Transfer Complete clear
+#define DMA_IFCR_CHTIF1_Pos (2)
+#define DMA_IFCR_CHTIF1 (0x01U << DMA_IFCR_CHTIF1_Pos) ///< Channel 1 Half Transfer clear
+#define DMA_IFCR_CTEIF1_Pos (3)
+#define DMA_IFCR_CTEIF1 (0x01U << DMA_IFCR_CTEIF1_Pos) ///< Channel 1 Transfer Error clear
+#define DMA_IFCR_CGIF2_Pos (4)
+#define DMA_IFCR_CGIF2 (0x01U << DMA_IFCR_CGIF2_Pos) ///< Channel 2 Global interrupt clear
+#define DMA_IFCR_CTCIF2_Pos (5)
+#define DMA_IFCR_CTCIF2 (0x01U << DMA_IFCR_CTCIF2_Pos) ///< Channel 2 Transfer Complete clear
+#define DMA_IFCR_CHTIF2_Pos (6)
+#define DMA_IFCR_CHTIF2 (0x01U << DMA_IFCR_CHTIF2_Pos) ///< Channel 2 Half Transfer clear
+#define DMA_IFCR_CTEIF2_Pos (7)
+#define DMA_IFCR_CTEIF2 (0x01U << DMA_IFCR_CTEIF2_Pos) ///< Channel 2 Transfer Error clear
+#define DMA_IFCR_CGIF3_Pos (8)
+#define DMA_IFCR_CGIF3 (0x01U << DMA_IFCR_CGIF3_Pos) ///< Channel 3 Global interrupt clear
+#define DMA_IFCR_CTCIF3_Pos (9)
+#define DMA_IFCR_CTCIF3 (0x01U << DMA_IFCR_CTCIF3_Pos) ///< Channel 3 Transfer Complete clear
+#define DMA_IFCR_CHTIF3_Pos (10)
+#define DMA_IFCR_CHTIF3 (0x01U << DMA_IFCR_CHTIF3_Pos) ///< Channel 3 Half Transfer clear
+#define DMA_IFCR_CTEIF3_Pos (11)
+#define DMA_IFCR_CTEIF3 (0x01U << DMA_IFCR_CTEIF3_Pos) ///< Channel 3 Transfer Error clear
+#define DMA_IFCR_CGIF4_Pos (12)
+#define DMA_IFCR_CGIF4 (0x01U << DMA_IFCR_CGIF4_Pos) ///< Channel 4 Global interrupt clear
+#define DMA_IFCR_CTCIF4_Pos (13)
+#define DMA_IFCR_CTCIF4 (0x01U << DMA_IFCR_CTCIF4_Pos) ///< Channel 4 Transfer Complete clear
+#define DMA_IFCR_CHTIF4_Pos (14)
+#define DMA_IFCR_CHTIF4 (0x01U << DMA_IFCR_CHTIF4_Pos) ///< Channel 4 Half Transfer clear
+#define DMA_IFCR_CTEIF4_Pos (15)
+#define DMA_IFCR_CTEIF4 (0x01U << DMA_IFCR_CTEIF4_Pos) ///< Channel 4 Transfer Error clear
+#define DMA_IFCR_CGIF5_Pos (16)
+#define DMA_IFCR_CGIF5 (0x01U << DMA_IFCR_CGIF5_Pos) ///< Channel 5 Global interrupt clear
+#define DMA_IFCR_CTCIF5_Pos (17)
+#define DMA_IFCR_CTCIF5 (0x01U << DMA_IFCR_CTCIF5_Pos) ///< Channel 5 Transfer Complete clear
+#define DMA_IFCR_CHTIF5_Pos (18)
+#define DMA_IFCR_CHTIF5 (0x01U << DMA_IFCR_CHTIF5_Pos) ///< Channel 5 Half Transfer clear
+#define DMA_IFCR_CTEIF5_Pos (19)
+#define DMA_IFCR_CTEIF5 (0x01U << DMA_IFCR_CTEIF5_Pos) ///< Channel 5 Transfer Error clear
+
+#define DMA_IFCR_CGIF6_Pos (20)
+#define DMA_IFCR_CGIF6 (0x01U << DMA_IFCR_CGIF6_Pos) ///< Channel 6 Global interrupt clear
+#define DMA_IFCR_CTCIF6_Pos (21)
+#define DMA_IFCR_CTCIF6 (0x01U << DMA_IFCR_CTCIF6_Pos) ///< Channel 6 Transfer Complete clear
+#define DMA_IFCR_CHTIF6_Pos (22)
+#define DMA_IFCR_CHTIF6 (0x01U << DMA_IFCR_CHTIF6_Pos) ///< Channel 6 Half Transfer clear
+#define DMA_IFCR_CTEIF6_Pos (23)
+#define DMA_IFCR_CTEIF6 (0x01U << DMA_IFCR_CTEIF6_Pos) ///< Channel 6 Transfer Error clear
+#define DMA_IFCR_CGIF7_Pos (24)
+#define DMA_IFCR_CGIF7 (0x01U << DMA_IFCR_CGIF7_Pos) ///< Channel 7 Global interrupt clear
+#define DMA_IFCR_CTCIF7_Pos (25)
+#define DMA_IFCR_CTCIF7 (0x01U << DMA_IFCR_CTCIF7_Pos) ///< Channel 7 Transfer Complete clear
+#define DMA_IFCR_CHTIF7_Pos (26)
+#define DMA_IFCR_CHTIF7 (0x01U << DMA_IFCR_CHTIF7_Pos) ///< Channel 7 Half Transfer clear
+#define DMA_IFCR_CTEIF7_Pos (27)
+#define DMA_IFCR_CTEIF7 (0x01U << DMA_IFCR_CTEIF7_Pos) ///< Channel 7 Transfer Error clear
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CCR_EN_Pos (0)
+#define DMA_CCR_EN (0x01U << DMA_CCR_EN_Pos) ///< Channel enabl
+#define DMA_CCR_TCIE_Pos (1)
+#define DMA_CCR_TCIE (0x01U << DMA_CCR_TCIE_Pos) ///< Transfer complete interrupt enable
+#define DMA_CCR_HTIE_Pos (2)
+#define DMA_CCR_HTIE (0x01U << DMA_CCR_HTIE_Pos) ///< Half Transfer interrupt enable
+#define DMA_CCR_TEIE_Pos (3)
+#define DMA_CCR_TEIE (0x01U << DMA_CCR_TEIE_Pos) ///< Transfer error interrupt enable
+#define DMA_CCR_DIR_Pos (4)
+#define DMA_CCR_DIR (0x01U << DMA_CCR_DIR_Pos) ///< Data transfer direction
+#define DMA_CCR_CIRC_Pos (5)
+#define DMA_CCR_CIRC (0x01U << DMA_CCR_CIRC_Pos) ///< Circular mode
+#define DMA_CCR_PINC_Pos (6)
+#define DMA_CCR_PINC (0x01U << DMA_CCR_PINC_Pos) ///< Peripheral increment mode
+#define DMA_CCR_MINC_Pos (7)
+#define DMA_CCR_MINC (0x01U << DMA_CCR_MINC_Pos) ///< Memory increment mode
+
+#define DMA_CCR_PSIZE_Pos (8)
+#define DMA_CCR_PSIZE (0x03U << DMA_CCR_PSIZE_Pos) ///< PSIZE[1:0] bits (Peripheral size)
+#define DMA_CCR_PSIZE_0 (0x01U << DMA_CCR_PSIZE_Pos) ///< Bit0
+#define DMA_CCR_PSIZE_1 (0x02U << DMA_CCR_PSIZE_Pos) ///< Bit1
+
+#define DMA_CCR_PSIZE_BYTE (0x00U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Byte
+#define DMA_CCR_PSIZE_HALFWORD (0x01U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size HalfWord
+#define DMA_CCR_PSIZE_WORD (0x02U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Word
+
+#define DMA_CCR_MSIZE_Pos (10)
+#define DMA_CCR_MSIZE (0x03U << DMA_CCR_MSIZE_Pos) ///< MSIZE[1:0] bits (Memory size)
+#define DMA_CCR_MSIZE_0 (0x01U << DMA_CCR_MSIZE_Pos) ///< Bit0
+#define DMA_CCR_MSIZE_1 (0x02U << DMA_CCR_MSIZE_Pos) ///< Bit1
+
+#define DMA_CCR_MSIZE_BYTE (0x00U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Byte
+#define DMA_CCR_MSIZE_HALFWORD (0x01U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size HalfWord
+#define DMA_CCR_MSIZE_WORD (0x02U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Word
+
+#define DMA_CCR_PL_Pos (12)
+#define DMA_CCR_PL (0x03U << DMA_CCR_PL_Pos) ///< PL[1:0] bits(Channel Priority level)
+#define DMA_CCR_PL_0 (0x01U << DMA_CCR_PL_Pos) ///< Bit0
+#define DMA_CCR_PL_1 (0x02U << DMA_CCR_PL_Pos) ///< Bit1
+
+#define DMA_CCR_PL_Low (0x00U << DMA_CCR_PL_Pos) ///< DMA Priority Low
+#define DMA_CCR_PL_Medium (0x01U << DMA_CCR_PL_Pos) ///< DMA Priority Medium
+#define DMA_CCR_PL_High (0x02U << DMA_CCR_PL_Pos) ///< DMA Priority High
+#define DMA_CCR_PL_VeryHigh (0x03U << DMA_CCR_PL_Pos) ///< DMA Priority VeryHigh
+#define DMA_CCR_M2M_Pos (14)
+#define DMA_CCR_M2M (0x01U << DMA_CCR_M2M_Pos) ///< Memory to memory mode
+
+#define DMA_CCR_ARE_Pos (15)
+#define DMA_CCR_ARE (0x01U << DMA_CCR_ARE_Pos) ///< Auto-Reload Enable bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CNDTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CNDTR_NDT_Pos (0)
+#define DMA_CNDTR_NDT (0xFFFFU << DMA_CNDTR_NDT_Pos) ///< Number of data to Transfer
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CPAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CPAR_PA_Pos (0)
+#define DMA_CPAR_PA (0xFFFFFFFFU << DMA_CPAR_PA_Pos) ///< Peripheral Address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CMAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CMAR_MA_Pos (0)
+#define DMA_CMAR_MA (0xFFFFFFFFU << DMA_CMAR_MA_Pos) ///< Peripheral Address
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
new file mode 100644
index 00000000..61a0d25c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
@@ -0,0 +1,730 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_iwdg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_ETH_H
+#define __REG_ETH_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+#include "reg_common.h"
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000) ///< Base Address: 0x40028000
+
+
+#define ETH ((ETH_TypeDef*) ETH_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 MACCR; ///< configuration register offset 0x0000
+ __IO u32 MACFFR; ///< frame filter register offset 0x0004
+ __IO u32 MACHTHR; ///< Hash list high register offset 0x0008
+ __IO u32 MACHTLR; ///< Hash list low register offset 0x000C
+ __IO u32 MACMIIAR; ///< MII address register offset 0x0010
+ __IO u32 MACMIIDR; ///< MII data register offset 0x0014
+ __IO u32 MACFCR; ///< flow control register offset 0x0018
+ __IO u32 MACVLANTR; ///< VLAN label register offset 0x001C
+ __IO u32 RESERVEDX0020[2]; /// 0x0020 ~ 0x0024
+ __IO u32 MACRWUFFR; /// 0x0028
+ __IO u32 MACPMTCSR; /// 0x002C
+ __IO u32 RESERVEDX0030[4]; /// 0x0030 ~ 0x003C
+ __IO u32 MACA0HR; ///< address 0 high register offset 0x0040
+ __IO u32 MACA0LR; ///< address 0 low register offset 0x0044
+ __IO u32 MACA1HR; ///< address 1 high register offset 0x0048
+ __IO u32 MACA1LR; ///< address 1 low register offset 0x004C
+ __IO u32 MACA2HR; ///< address 2 high register offset 0x0050
+ __IO u32 MACA2LR; ///< address 2 low register offset 0x0054
+ __IO u32 MACA3HR; ///< address 3 high register offset 0x0058
+ __IO u32 MACA3LR; ///< address 3 low register offset 0x005C
+ __IO u32 MACA4HR; ///< address 4 high register offset 0x0060
+ __IO u32 MACA4LR; ///< address 4 low register offset 0x0064
+ __IO u32 MACA5HR; ///< address 5 high register offset 0x0068
+ __IO u32 MACA5LR; ///< address 5 low register offset 0x006C
+ __IO u32 MACA6HR; ///< address 6 high register offset 0x0070
+ __IO u32 MACA6LR; ///< address 6 low register offset 0x0074
+ __IO u32 MACA7HR; ///< address 7 high register offset 0x0078
+ __IO u32 MACA7LR; ///< address 7 low register offset 0x007C
+ __IO u32 MACA8HR; ///< address 8 high register offset 0x0080
+ __IO u32 MACA8LR; ///< address 8 low register offset 0x0084
+ __IO u32 MACA9HR; ///< address 9 high register offset 0x0088
+ __IO u32 MACA9LR; ///< address 9 low register offset 0x008C
+ __IO u32 MACA10HR; ///< address 10 high register offset 0x0090
+ __IO u32 MACA10LR; ///< address 10 low register offset 0x0094
+ __IO u32 MACA11HR; ///< address 11 high register offset 0x0098
+ __IO u32 MACA11LR; ///< address 11 low register offset 0x009C
+ __IO u32 MACA12HR; ///< address 12 high register offset 0x00A0
+ __IO u32 MACA12LR; ///< address 12 low register offset 0x00A4
+ __IO u32 MACA13HR; ///< address 13 high register offset 0x00A8
+ __IO u32 MACA13LR; ///< address 13 low register offset 0x00AC
+ __IO u32 MACA14HR; ///< address 14 high register offset 0x00B0
+ __IO u32 MACA14LR; ///< address 14 low register offset 0x00B4
+ __IO u32 MACA15HR; ///< address 15 high register offset 0x00B8
+ __IO u32 MACA15LR; ///< address 15 low register offset 0x00BC
+ __IO u32 MACANCR; ///< Automatic negotiation control register offset 0x00C0
+ __IO u32 MACANSR; ///< Automatic negotiation of the status register offset 0x00C4
+ __IO u32 MACANAR; ///< Automatic negotiation of broadcast registers offset 0x00C8
+ __IO u32 MACANLPAR; ///< Automatic negotiation of link partner capability register offset 0x00CC
+ __IO u32 MACANER; ///< Automatic negotiation of extension registers offset 0x00D0
+ __IO u32 MACTBIER; ///< Ten - place interface extension register offset 0x00D4
+ __IO u32 MACMIISR; ///< MII status register offset 0x00D8
+ __IO u32 RESERVEDX00DC[9]; ///< offset 0x00DC ~ 0x00FC
+ __IO u32 MMCCR; ///< MMC controls registers offset 0x0100
+ __IO u32 MMCRIR; ///< The MMC receives the interrupt register offset 0x0104
+ __IO u32 MMCTIR; ///< The MMC sends the interrupt register offset 0x0108
+ __IO u32 MMCRIMR; ///< The MMC receives the interrupt mask register offset 0x010C
+ __IO u32 MMCTIMR; ///< MMC sends interrupt masking registers offset 0x0110
+ __IO u32 RESERVEDX0114[14]; ///< offset 0x0114 ~ 0x0148
+ __IO u32 MMCTGFSCCR; ///< A good frame counter register that MMC sends after a single conflict offset 0x014C
+ __IO u32 MMCTGFMSCCR; ///< A good frame counter register that MMC sends after multiple collisions offset 0x0150
+ __IO u32 RESERVEDX0154[5]; ///< offset 0x0154 ~ 0x0164
+ __IO u32 MMCTGFCR; ///< Good frame counter register sent by MMC offset 0x0168
+ __IO u32 RESERVEDX016C[10]; ///< offset 0x016C ~ 0x0190
+ __IO u32 MMCRFCECR; ///< Ethernet MMC with CRC error counter register receives frame register offset 0x0194
+ __IO u32 MMCRFAECR; ///< Ethernet MMC receives frames with alignment error counter registers offset 0x0198
+ __IO u32 RESERVEDX019C[10]; ///< offset 0x019C ~ 0x01C0
+ __IO u32 MMCRGUFCR; ///< Good unicast frame counter register received by MMC offset 0x01C4
+ __IO u32 RESERVEDx01C8[910]; ///< offset 0x01C8 ~ 0x0FFC
+ __IO u32 DMABMR; ///< Bus mode register offset 0x1000
+ __IO u32 DMATPDR; ///< DMA sends the polling request register offset 0x1004
+ __IO u32 DMARPDR; ///< DMA receives the polling request register offset 0x1008
+ __IO u32 DMARDLAR; ///< DMA receives a list of descriptor addresses offset 0x100C
+ __IO u32 DMATDLAR; ///< DMA sends the descriptor list address offset 0x1010
+ __IO u32 DMASR; ///< DMA status register offset 0x1014
+ __IO u32 DMAOMR; ///< DMA working mode register offset 0x1018
+ __IO u32 DMAIER; ///< DMA interrupt enablement register offset 0x101C
+ __IO u32 DMAMFBOCR; ///< DMA lost frames and cache overflow counter registers offset 0x1020
+ __IO u32 DMARSWTR; /// 0x1024
+ __IO u32 RESERVEDX1028[8]; /// 0x1028 ~ 0x1044
+ __IO u32 DMACHTDR; /// 0x1048
+ __IO u32 DMACHRDR; /// 0x104C
+ __IO u32 DMACHTBAR; ///< DMA is currently sending the cache address register offset 0x1050
+ __IO u32 DMACHRBAR; ///< DMA currently receives the cache address register offset 0x1054
+} ETH_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACCR_WD_Pos (23)
+#define ETH_MACCR_WD (0x01U << ETH_MACCR_WD_Pos) ///< Watchdog disable
+#define ETH_MACCR_JD_Pos (22)
+#define ETH_MACCR_JD (0x01U << ETH_MACCR_JD_Pos) ///< Jabber disable
+#define ETH_MACCR_FBE_Pos (21)
+#define ETH_MACCR_FBE (0x01U << ETH_MACCR_FBE_Pos) ///< Frame Burst Enable
+#define ETH_MACCR_JE_Pos (20)
+#define ETH_MACCR_JE (0x01U << ETH_MACCR_JE_Pos) ///< Jumbo Frame Enable
+#define ETH_MACCR_IFG_Pos (17) ///< Inter-frame gap
+#define ETH_MACCR_IFG_96Bit (0x00U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 96Bit
+#define ETH_MACCR_IFG_88Bit (0x01U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 88Bit
+#define ETH_MACCR_IFG_80Bit (0x02U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 80Bit
+#define ETH_MACCR_IFG_72Bit (0x03U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 72Bit
+#define ETH_MACCR_IFG_64Bit (0x04U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 64Bit
+#define ETH_MACCR_IFG_56Bit (0x05U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 56Bit
+#define ETH_MACCR_IFG_48Bit (0x06U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 48Bit
+#define ETH_MACCR_IFG_40Bit (0x07U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 40Bit
+#define ETH_MACCR_FES_Pos (14)
+#define ETH_MACCR_FES (0x01U << ETH_MACCR_FES_Pos) ///< Fast ethernet speed
+#define ETH_MACCR_ROD_Pos (13)
+#define ETH_MACCR_ROD (0x01U << ETH_MACCR_ROD_Pos) ///< Receive own disable
+#define ETH_MACCR_LM_Pos (12)
+#define ETH_MACCR_LM (0x01U << ETH_MACCR_LM_Pos) ///< loopback mode
+#define ETH_MACCR_DM_Pos (11)
+#define ETH_MACCR_DM (0x01U << ETH_MACCR_DM_Pos) ///< Duplex mode
+#define ETH_MACCR_IPCO_Pos (10)
+#define ETH_MACCR_IPCO (0x01U << ETH_MACCR_IPCO_Pos) ///< IP Checksum offload
+#define ETH_MACCR_RD_Pos (9)
+#define ETH_MACCR_RD (0x01U << ETH_MACCR_RD_Pos) ///< Retry disable
+#define ETH_MACCR_APCS_Pos (8)
+#define ETH_MACCR_APCS (0x01U << ETH_MACCR_APCS_Pos) ///< Automatic Pad/CRC stripping
+#define ETH_MACCR_BL_Pos (5) ///< Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k
+#define ETH_MACCR_BL_10 (0x00U << ETH_MACCR_BL_Pos) ///< k = min (n, 10)
+#define ETH_MACCR_BL_8 (0x01U << ETH_MACCR_BL_Pos) ///< k = min (n, 8)
+#define ETH_MACCR_BL_4 (0x02U << ETH_MACCR_BL_Pos) ///< k = min (n, 4)
+#define ETH_MACCR_BL_1 (0x03U << ETH_MACCR_BL_Pos) ///< k = min (n, 1)
+#define ETH_MACCR_DC_Pos (4)
+#define ETH_MACCR_DC (0x01U << ETH_MACCR_DC_Pos) ///< Defferal check
+#define ETH_MACCR_TE_Pos (3)
+#define ETH_MACCR_TE (0x01U << ETH_MACCR_TE_Pos) ///< Transmitter enable
+#define ETH_MACCR_RE_Pos (2)
+#define ETH_MACCR_RE (0x01U << ETH_MACCR_RE_Pos) ///< Receiver enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACFFR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACFFR_RA_Pos (31)
+#define ETH_MACFFR_RA (0x01U << ETH_MACFFR_RA_Pos) ///< Receive all
+
+#define ETH_MACFFR_SAF_Pos (9)
+#define ETH_MACFFR_SAF (0x01U << ETH_MACFFR_SAF_Pos) ///< Source address filter enable
+#define ETH_MACFFR_SAIF_Pos (8)
+#define ETH_MACFFR_SAIF (0x01U << ETH_MACFFR_SAIF_Pos) ///< SA inverse filtering
+#define ETH_MACFFR_PCF_Pos (6)
+#define ETH_MACFFR_PCF (0x03U << ETH_MACFFR_PCF_Pos) ///< Pass control frames: 3 cases
+#define ETH_MACFFR_PCF_BlockAll (0x01U << ETH_MACFFR_PCF_Pos) ///< MAC filters all control frames from reaching the application
+#define ETH_MACFFR_PCF_ForwardAll (0x02U << ETH_MACFFR_PCF_Pos) ///< MAC forwards all control frames to application even if they fail the Address Filter
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter (0x03U << ETH_MACFFR_PCF_Pos) ///< MAC forwards control frames that pass the Address Filter.
+#define ETH_MACFFR_BFD_Pos (5)
+#define ETH_MACFFR_BFD (0x01U << ETH_MACFFR_BFD_Pos) ///< Broadcast frame disable
+#define ETH_MACFFR_PAM_Pos (4)
+#define ETH_MACFFR_PAM (0x01U << ETH_MACFFR_PAM_Pos) ///< Pass all mutlicast
+#define ETH_MACFFR_DAIF_Pos (3)
+#define ETH_MACFFR_DAIF (0x01U << ETH_MACFFR_DAIF_Pos) ///< DA Inverse filtering
+#define ETH_MACFFR_HM_Pos (2)
+#define ETH_MACFFR_HM (0x01U << ETH_MACFFR_HM_Pos) ///< Hash multicast
+#define ETH_MACFFR_HU_Pos (1)
+#define ETH_MACFFR_HU (0x01U << ETH_MACFFR_HU_Pos) ///< Hash unicast
+#define ETH_MACFFR_PM_Pos (0)
+#define ETH_MACFFR_PM (0x01U << ETH_MACFFR_PM_Pos) ///< Promiscuous mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACHTHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACHTHR_HTH (0xFFFFFFFFU) ///< Hash table high
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACHTLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACHTLR_HTL (0xFFFFFFFFU) ///< Hash table low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACMIIAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACMIIAR_PA_Pos (11)
+#define ETH_MACMIIAR_PA (0x1FU << ETH_MACMIIAR_PA_Pos) ///< Physical layer address
+#define ETH_MACMIIAR_MR_Pos (6)
+#define ETH_MACMIIAR_MR (0x1FU << ETH_MACMIIAR_MR_Pos) ///< MII register in the selected PHY
+#define ETH_MACMIIAR_CR_Pos (2)
+#define ETH_MACMIIAR_CR (0x07U << ETH_MACMIIAR_CR_Pos) ///< CR clock range: 6 cases
+#define ETH_MACMIIAR_CR_Div42 (0x00U << ETH_MACMIIAR_CR_Pos) ///< HCLK:60-100 MHz; MDC clock= HCLK/42
+#define ETH_MACMIIAR_CR_Div62 (0x01U << ETH_MACMIIAR_CR_Pos) ///< HCLK:100-150 MHz; MDC clock= HCLK/62
+#define ETH_MACMIIAR_CR_Div16 (0x02U << ETH_MACMIIAR_CR_Pos) ///< HCLK:20-35 MHz; MDC clock= HCLK/16
+#define ETH_MACMIIAR_CR_Div26 (0x03U << ETH_MACMIIAR_CR_Pos) ///< HCLK:35-60 MHz; MDC clock= HCLK/26
+#define ETH_MACMIIAR_CR_Div102 (0x04U << ETH_MACMIIAR_CR_Pos) ///< HCLK:150-168 MHz; MDC clock= HCLK/102
+#define ETH_MACMIIAR_MW_Pos (1)
+#define ETH_MACMIIAR_MW (0x01U << ETH_MACMIIAR_MW_Pos) ///< MII write
+#define ETH_MACMIIAR_MB_Pos (0)
+#define ETH_MACMIIAR_MB (0x01U << ETH_MACMIIAR_MB_Pos) ///< MII busy
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACMIIDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACMIIDR_MD (0x0000FFFFU) ///< MII data: read/write data from/to PHY
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACFCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACFCR_PT_Pos (16)
+#define ETH_MACFCR_PT ((u32)0xFFFF << ETH_MACFCR_PT_Pos) ///< Pause time
+#define ETH_MACFCR_PLT_Pos (4)
+#define ETH_MACFCR_PLT (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause low threshold: 4 cases
+#define ETH_MACFCR_PLT_Minus4 (0x00U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 4 slot times
+#define ETH_MACFCR_PLT_Minus28 (0x01U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 28 slot times
+#define ETH_MACFCR_PLT_Minus144 (0x02U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 144 slot times
+#define ETH_MACFCR_PLT_Minus256 (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 256 slot times
+#define ETH_MACFCR_UPFD_Pos (3)
+#define ETH_MACFCR_UPFD (0x01U << ETH_MACFCR_UPFD_Pos) ///< Unicast pause frame detect
+#define ETH_MACFCR_RFCE_Pos (2)
+#define ETH_MACFCR_RFCE (0x01U << ETH_MACFCR_RFCE_Pos) ///< Receive flow control enable
+#define ETH_MACFCR_TFCE_Pos (1)
+#define ETH_MACFCR_TFCE (0x01U << ETH_MACFCR_TFCE_Pos) ///< Transmit flow control enable
+#define ETH_MACFCR_FCBBPA_Pos (0)
+#define ETH_MACFCR_FCBBPA (0x01U << ETH_MACFCR_FCBBPA_Pos) ///< Flow control busy/backpressure activate
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACVLANTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACVLANTR_VLANTI (0x0000FFFFU) ///< VLAN tag identifier (for receive frames)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACRWUFFR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACRWUFFR_D (0xFFFFFFFFU) ///< Wake-up frame filter register data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACPMTCSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACPMTCSR_WFFRPR_Pos (31) ///< Wake-Up Frame Filter Register Pointer Reset
+#define ETH_MACPMTCSR_WFFRPR (0x01U << ETH_MACPMTCSR_WFFRPR_Pos) ///< Wake-Up Frame Filter Register Pointer Reset
+#define ETH_MACPMTCSR_GU_Pos (9)
+#define ETH_MACPMTCSR_GU (0x01U << ETH_MACPMTCSR_GU_Pos) ///< Global Unicast
+#define ETH_MACPMTCSR_WFR_Pos (6)
+#define ETH_MACPMTCSR_WFR (0x01U << ETH_MACPMTCSR_WFR_Pos) ///< Wake-Up Frame Received
+#define ETH_MACPMTCSR_MPR_Pos (5)
+#define ETH_MACPMTCSR_MPR (0x01U << ETH_MACPMTCSR_MPR_Pos) ///< Magic Packet Received
+#define ETH_MACPMTCSR_WFE_Pos (2)
+#define ETH_MACPMTCSR_WFE (0x01U << ETH_MACPMTCSR_WFE_Pos) ///< Wake-Up Frame Enable
+#define ETH_MACPMTCSR_MPE_Pos (1)
+#define ETH_MACPMTCSR_MPE (0x01U << ETH_MACPMTCSR_MPE_Pos) ///< Magic Packet Enable
+#define ETH_MACPMTCSR_PD_Pos (0)
+#define ETH_MACPMTCSR_PD (0x01U << ETH_MACPMTCSR_PD_Pos) ///< Power Down
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA0HR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) ///< MAC address0 high
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA0LR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) ///< MAC address0 low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA1HR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA1HR_AE_Pos (31)
+#define ETH_MACA1HR_AE (0x01U << ETH_MACA1HR_AE_Pos) ///< Address enable
+#define ETH_MACA1HR_SA_Pos (30)
+#define ETH_MACA1HR_SA (0x01U << ETH_MACA1HR_SA_Pos) ///< Source address
+#define ETH_MACA1HR_MBC_Pos (24)
+#define ETH_MACA1HR_MBC (0x3FU << ETH_MACA1HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes
+#define ETH_MACA1HR_MBC_HBits15_8 (0x20U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8]
+#define ETH_MACA1HR_MBC_HBits7_0 (0x10U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0]
+#define ETH_MACA1HR_MBC_LBits31_24 (0x08U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24]
+#define ETH_MACA1HR_MBC_LBits23_16 (0x04U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16]
+#define ETH_MACA1HR_MBC_LBits15_8 (0x02U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8]
+#define ETH_MACA1HR_MBC_LBits7_0 (0x00U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0]
+#define ETH_MACA1HR_MACA1H_Pos (0)
+#define ETH_MACA1HR_MACA1H (0x0000FFFFU << ETH_MACA1HR_MACA1H_Pos) ///< MAC address1 high
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA1LR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA1LR_MACA1L (0xFFFFFFFFU) ///< MAC address1 low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA2HR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA2HR_AE_Pos (31)
+#define ETH_MACA2HR_AE (0x01U << ETH_MACA2HR_AE_Pos) ///< Address enable
+#define ETH_MACA2HR_SA_Pos (30)
+#define ETH_MACA2HR_SA (0x01U << ETH_MACA2HR_SA_Pos) ///< Source address
+#define ETH_MACA2HR_MBC_Pos (24)
+#define ETH_MACA2HR_MBC (0x3FU << ETH_MACA2HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes
+#define ETH_MACA2HR_MBC_HBits15_8 (0x20U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8]
+#define ETH_MACA2HR_MBC_HBits7_0 (0x10U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0]
+#define ETH_MACA2HR_MBC_LBits31_24 (0x08U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24]
+#define ETH_MACA2HR_MBC_LBits23_16 (0x04U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16]
+#define ETH_MACA2HR_MBC_LBits15_8 (0x02U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8]
+#define ETH_MACA2HR_MBC_LBits7_0 (0x00U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0]
+#define ETH_MACA2HR_MACA2H_Pos (0)
+#define ETH_MACA2HR_MACA2H (0x0000FFFFU << ETH_MACA2HR_MACA2H_Pos) ///< MAC address2 high
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA2LR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA2LR_MACA2L (0xFFFFFFFFU) ///< MAC address2 low
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANCR_LR_Pos (17)
+#define ETH_MACANCR_LR (0x01U << ETH_MACANCR_LR_Pos) ///< Lock to Reference
+#define ETH_MACANCR_ECD_Pos (16)
+#define ETH_MACANCR_ECD (0x01U << ETH_MACANCR_ECD_Pos) ///< Enable Comma Detect
+#define ETH_MACANCR_ELE_Pos (14)
+#define ETH_MACANCR_ELE (0x01U << ETH_MACANCR_ELE_Pos) ///< External Loopback Enable
+#define ETH_MACANCR_ANE_Pos (12)
+#define ETH_MACANCR_ANE (0x01U << ETH_MACANCR_ANE_Pos) ///< Auto-Negotiation Enable
+#define ETH_MACANCR_RAN_Pos (9)
+#define ETH_MACANCR_RAN (0x01U << ETH_MACANCR_RAN_Pos) ///< Restart Auto-Negotiation
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANSR_ES_Pos (8)
+#define ETH_MACANSR_ES (0x01U << ETH_MACANSR_ES_Pos) ///< Extended Status
+#define ETH_MACANSR_ANC_Pos (5)
+#define ETH_MACANSR_ANC (0x01U << ETH_MACANSR_ANC_Pos) ///< Auto-Negotiation Complete
+#define ETH_MACANSR_ANA_Pos (3)
+#define ETH_MACANSR_ANA (0x01U << ETH_MACANSR_ANA_Pos) ///< Auto-Negotiation Ability
+#define ETH_MACANSR_LS_Pos (2)
+#define ETH_MACANSR_LS (0x01U << ETH_MACANSR_LS_Pos) ///< Link Status
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANAR_NP_Pos (15)
+#define ETH_MACANAR_NP (0x01U << ETH_MACANAR_NP_Pos) ///< Next Page Support
+#define ETH_MACANAR_RFE_Pos (12)
+#define ETH_MACANAR_RFE (0x01U << ETH_MACANAR_RFE_Pos) ///< Remote Fault Encoding
+#define ETH_MACANAR_PSE_Pos (7)
+#define ETH_MACANAR_PSE (0x01U << ETH_MACANAR_PSE_Pos) ///< Pause Encoding
+#define ETH_MACANAR_HD_Pos (6)
+#define ETH_MACANAR_HD (0x01U << ETH_MACANAR_HD_Pos) ///< support Half-Duplex
+#define ETH_MACANAR_FD_Pos (5)
+#define ETH_MACANAR_FD (0x01U << ETH_MACANAR_FD_Pos) ///< support Full-Durplex
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANLPAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANLPAR_NP_Pos (15)
+#define ETH_MACANLPAR_NP (0x01U << ETH_MACANLPAR_NP_Pos) ///< Next Page Support
+#define ETH_MACANLPAR_ACK_Pos (14)
+#define ETH_MACANLPAR_ACK (0x01U << ETH_MACANLPAR_ACK_Pos) ///< Acknowledge
+#define ETH_MACANLPAR_RFE_Pos (12)
+#define ETH_MACANLPAR_RFE (0x01U << ETH_MACANLPAR_RFE_Pos) ///< Remote Fault Encoding
+#define ETH_MACANLPAR_PSE_Pos (7)
+#define ETH_MACANLPAR_PSE (0x01U << ETH_MACANLPAR_PSE_Pos) ///< Pause Encoding
+#define ETH_MACANLPAR_HD_Pos (6)
+#define ETH_MACANLPAR_HD (0x01U << ETH_MACANLPAR_HD_Pos) ///< support Half-Duplex
+#define ETH_MACANLPAR_FD_Pos (5)
+#define ETH_MACANLPAR_FD (0x01U << ETH_MACANLPAR_FD_Pos) ///< support Full-Durplex
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANER_NPA_Pos (2)
+#define ETH_MACANER_NPA (0x01U << ETH_MACANER_NPA_Pos) ///< Next Page Ability
+#define ETH_MACANER_NPR_Pos (1)
+#define ETH_MACANER_NPR (0x01U << ETH_MACANER_NPR_Pos) ///< New Page Received
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACTBIER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACTBIER_GFD_Pos (15)
+#define ETH_MACTBIER_GFD (0x01U << ETH_MACTBIER_GFD_Pos) ///< 1000BASE-X Full-Duplex Capable
+#define ETH_MACTBIER_GHD_Pos (14)
+#define ETH_MACTBIER_GHD (0x01U << ETH_MACTBIER_GHD_Pos) ///< 1000BASE-X Half-Duplex Capable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACMIISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACMIISR_LS_Pos (3)
+#define ETH_MACMIISR_LS (0x01U << ETH_MACMIISR_LS_Pos) ///< Link Status
+#define ETH_MACMIISR_LSP_Pos (1)
+#define ETH_MACMIISR_LSP_2_5 (0x00U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 2.5 MHz
+#define ETH_MACMIISR_LSP_25 (0x01U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 25 MHz
+#define ETH_MACMIISR_LSP_125 (0x02U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 125 MHz
+#define ETH_MACMIISR_LM_Pos (0)
+#define ETH_MACMIISR_LM (0x01U << ETH_MACMIISR_LM_Pos) ///< Link Mode : Full-Duplex Capable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCCR_MCFHP ((u32)0x00000020) ///< MMC counter Full-Half preset
+#define ETH_MMCCR_MCP ((u32)0x00000010) ///< MMC counter preset
+#define ETH_MMCCR_MCF ((u32)0x00000008) ///< MMC Counter Freeze
+#define ETH_MMCCR_ROR_Pos (2)
+#define ETH_MMCCR_ROR (0x01U << ETH_MMCCR_ROR_Pos) ///< Reset on Read
+#define ETH_MMCCR_CSR_Pos (1)
+#define ETH_MMCCR_CSR (0x01U << ETH_MMCCR_CSR_Pos) ///< Counter Stop Rollover
+#define ETH_MMCCR_CR_Pos (0)
+#define ETH_MMCCR_CR (0x01U << ETH_MMCCR_CR_Pos) ///< Counters Reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRIR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRIR_RGUF_Pos (17)
+#define ETH_MMCRIR_RGUFS (0x01U << ETH_MMCRIR_RGUF_Pos) ///< Set when Rx good unicast frames counter reaches half the maximum value
+#define ETH_MMCRIR_RFAES_Pos (6)
+#define ETH_MMCRIR_RFAES (0x01U << ETH_MMCRIR_RFAES_Pos) ///< Set when Rx alignment error counter reaches half the maximum value
+#define ETH_MMCRIR_RFCES_Pos (5)
+#define ETH_MMCRIR_RFCES (0x01U << ETH_MMCRIR_RFCES_Pos) ///< Set when Rx crc error counter reaches half the maximum value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTIR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTIR_TGFS_Pos (21)
+#define ETH_MMCTIR_TGFS (0x01U << ETH_MMCTIR_TGFS_Pos) ///< Set when Tx good frame count counter reaches half the maximum value
+#define ETH_MMCTIR_TGFMSCS_Pos (15)
+#define ETH_MMCTIR_TGFMSCS (0x01U << ETH_MMCTIR_TGFMSCS_Pos) ///< Set when Tx good multi col counter reaches half the maximum value
+#define ETH_MMCTIR_TGFSCS_Pos (14)
+#define ETH_MMCTIR_TGFSCS (0x01U << ETH_MMCTIR_TGFSCS_Pos) ///< Set when Tx good single col counter reaches half the maximum value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRIMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRIMR_RGUFM_Pos (17)
+#define ETH_MMCRIMR_RGUFM (0x01U << ETH_MMCRIMR_RGUFM_Pos) ///< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value
+#define ETH_MMCRIMR_RFAEM_Pos (6)
+#define ETH_MMCRIMR_RFAEM (0x01U << ETH_MMCRIMR_RFAEM_Pos) ///< Mask the interrupt when when Rx alignment error counter reaches half the maximum value
+#define ETH_MMCRIMR_RFCEM_Pos (5)
+#define ETH_MMCRIMR_RFCEM (0x01U << ETH_MMCRIMR_RFCEM_Pos) ///< Mask the interrupt when Rx crc error counter reaches half the maximum value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTIMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTIMR_TGFM_Pos (21)
+#define ETH_MMCTIMR_TGFM (0x01U << ETH_MMCTIMR_TGFM_Pos) ///< Mask the interrupt when Tx good frame count counter reaches half the maximum value
+#define ETH_MMCTIMR_TGFMSCM_Pos (15)
+#define ETH_MMCTIMR_TGFMSCM (0x01U << ETH_MMCTIMR_TGFMSCM_Pos) ///< Mask the interrupt when Tx good multi col counter reaches half the maximum value
+#define ETH_MMCTIMR_TGFSCM_Pos (14)
+#define ETH_MMCTIMR_TGFSCM (0x01U << ETH_MMCTIMR_TGFSCM_Pos) ///< Mask the interrupt when Tx good single col counter reaches half the maximum value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTGFSCCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTGFSCCR_TGFSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after a single collision in Half-duplex mode.
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTGFMSCCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTGFMSCCR_TGFMSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after more than a single collision in Half-duplex mode.
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTGFCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTGFCR_TGFC (0xFFFFFFFFU) ///< Number of good frames transmitted.
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRFCECR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRFCECR_RFCEC (0xFFFFFFFFU) ///< Number of frames received with CRC error.
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRFAECR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRFAECR_RFAEC (0xFFFFFFFFU) ///< Number of frames received with alignment (dribble) error
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRGUFCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRGUFCR_RGUFC (0xFFFFFFFFU) ///< Number of good unicast frames received.
+/// @brief ETH_DMABMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMABMR_FB_Pos (16)
+#define ETH_DMABMR_FB (0x01U << ETH_DMABMR_FB_Pos) ///< Fixed Burst
+#define ETH_DMABMR_RTPR_Pos (14)
+#define ETH_DMABMR_RTPR (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
+#define ETH_DMABMR_RTPR_1_1 (0x00U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
+#define ETH_DMABMR_RTPR_2_1 (0x01U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
+#define ETH_DMABMR_RTPR_3_1 (0x02U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
+#define ETH_DMABMR_RTPR_4_1 (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
+#define ETH_DMABMR_PBL_Pos (8)
+#define ETH_DMABMR_PBL (0x3FU<< ETH_DMABMR_PBL_Pos) //< Programmable burst length
+#define ETH_DMABMR_PBL_1Beat (0x01U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
+#define ETH_DMABMR_PBL_2Beat (0x02U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
+#define ETH_DMABMR_PBL_4Beat (0x04U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
+#define ETH_DMABMR_PBL_8Beat (0x08U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
+#define ETH_DMABMR_PBL_16Beat (0x10U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
+#define ETH_DMABMR_PBL_32Beat (0x20U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
+#define ETH_DMABMR_PBL_4xPBL_4Beat (0x10001U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
+#define ETH_DMABMR_PBL_4xPBL_8Beat (0x10002U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
+#define ETH_DMABMR_PBL_4xPBL_16Beat (0x10004U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
+#define ETH_DMABMR_PBL_4xPBL_32Beat (0x10008U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
+#define ETH_DMABMR_PBL_4xPBL_64Beat (0x10010U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
+#define ETH_DMABMR_PBL_4xPBL_128Beat (0x10020U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
+
+#define ETH_DMABMR_DSL_Pos (2)
+#define ETH_DMABMR_DSL (0x01U << ETH_DMABMR_DSL_Pos) ///< Descriptor Skip Length
+#define ETH_DMABMR_DA_Pos (1)
+#define ETH_DMABMR_DA (0x1FU << ETH_DMABMR_DA_Pos) ///< DMA arbitration scheme
+#define ETH_DMABMR_SR_Pos (0)
+#define ETH_DMABMR_SR (0x01U << ETH_DMABMR_SR_Pos) ///< Software reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMATPDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMATPDR_TPD (0xFFFFFFFFU) ///< Transmit poll demand
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMARPDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMARPDR_RPD (0xFFFFFFFFU) ///< Receive poll demand
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMARDLAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMARDLAR_SRL (0xFFFFFFFFU) ///< Start of receive list
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMATDLAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMATDLAR_STL (0xFFFFFFFFU) ///< Start of transmit list
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMASR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMASR_PMTS_Pos (28)
+#define ETH_DMASR_PMTS (0x01U << ETH_DMASR_PMTS_Pos) ///< PMT status
+#define ETH_DMASR_MMCS_Pos (27)
+#define ETH_DMASR_MMCS (0x01U << ETH_DMASR_MMCS_Pos) ///< MMC status
+#define ETH_DMASR_LIS_Pos (26)
+#define ETH_DMASR_LIS (0x01U << ETH_DMASR_LIS_Pos) ///< GMAC Line interface Status
+
+#define ETH_DMASR_EBS_Pos (23)
+#define ETH_DMASR_EBS (0x07U << ETH_DMASR_EBS_Pos) ///< Error bits status
+#define ETH_DMASR_EBS_DescAccess (0x04U << ETH_DMASR_EBS_Pos) ///< Error bits 0-data buffer, 1-desc. access
+#define ETH_DMASR_EBS_ReadTransf (0x02U << ETH_DMASR_EBS_Pos) ///< Error bits 0-write trnsf, 1-read transfr
+#define ETH_DMASR_EBS_DataTransfTx (0x01U << ETH_DMASR_EBS_Pos) ///< Error bits 0-Rx DMA, 1-Tx DMA
+#define ETH_DMASR_TPS_Pos (20)
+#define ETH_DMASR_TPS (0x007U << ETH_DMASR_TPS_Pos) ///< Transmit process state
+#define ETH_DMASR_TPS_Stopped (0x000U << ETH_DMASR_TPS_Pos) ///< Stopped - Reset or Stop Tx Command issued
+#define ETH_DMASR_TPS_Fetching (0x001U << ETH_DMASR_TPS_Pos) ///< Running - fetching the Tx descriptor
+#define ETH_DMASR_TPS_Waiting (0x002U << ETH_DMASR_TPS_Pos) ///< Running - waiting for status
+#define ETH_DMASR_TPS_Reading (0x003U << ETH_DMASR_TPS_Pos) ///< Running - reading the data from host memory
+#define ETH_DMASR_TPS_Suspended (0x006U << ETH_DMASR_TPS_Pos) ///< Suspended - Tx Descriptor unavailabe
+#define ETH_DMASR_TPS_Closing (0x007U << ETH_DMASR_TPS_Pos) ///< Running - closing Rx descriptor
+#define ETH_DMASR_RPS_Pos (17)
+#define ETH_DMASR_RPS (0x07U << ETH_DMASR_RPS_Pos) ///< Receive process state
+#define ETH_DMASR_RPS_Stopped (0x00U << ETH_DMASR_RPS_Pos) ///< Stopped - Reset or Stop Rx Command issued
+#define ETH_DMASR_RPS_Fetching (0x01U << ETH_DMASR_RPS_Pos) ///< Running - fetching the Rx descriptor
+#define ETH_DMASR_RPS_Waiting (0x03U << ETH_DMASR_RPS_Pos) ///< Running - waiting for packet
+#define ETH_DMASR_RPS_Suspended (0x04U << ETH_DMASR_RPS_Pos) ///< Suspended - Rx Descriptor unavailable
+#define ETH_DMASR_RPS_Closing (0x05U << ETH_DMASR_RPS_Pos) ///< Running - closing descriptor
+#define ETH_DMASR_RPS_Queuing (0x07U << ETH_DMASR_RPS_Pos) ///< Running - queuing the recieve frame into host memory
+#define ETH_DMASR_NIS_Pos (16)
+#define ETH_DMASR_NIS (0x01U << ETH_DMASR_NIS_Pos ) ///< Normal interrupt summary
+#define ETH_DMASR_AIS_Pos (15)
+#define ETH_DMASR_AIS (0x01U << ETH_DMASR_AIS_Pos ) ///< Abnormal interrupt summary
+#define ETH_DMASR_ERS_Pos (14)
+#define ETH_DMASR_ERS (0x01U << ETH_DMASR_ERS_Pos ) ///< Early receive status
+#define ETH_DMASR_FBES_Pos (13)
+#define ETH_DMASR_FBES (0x01U << ETH_DMASR_FBES_Pos) ///< Fatal bus error status
+#define ETH_DMASR_ETS_Pos (10)
+#define ETH_DMASR_ETS (0x01U << ETH_DMASR_ETS_Pos ) ///< Early transmit status
+#define ETH_DMASR_RWTS_Pos (9)
+#define ETH_DMASR_RWTS (0x01U << ETH_DMASR_RWTS_Pos) ///< Receive watchdog timeout status
+#define ETH_DMASR_RPSS_Pos (8)
+#define ETH_DMASR_RPSS (0x01U << ETH_DMASR_RPSS_Pos) ///< Receive process stopped status
+#define ETH_DMASR_RBUS_Pos (7)
+#define ETH_DMASR_RBUS (0x01U << ETH_DMASR_RBUS_Pos) ///< Receive buffer unavailable status
+#define ETH_DMASR_RS_Pos (6)
+#define ETH_DMASR_RS (0x01U << ETH_DMASR_RS_Pos ) ///< Receive status
+#define ETH_DMASR_TUS_Pos (5)
+#define ETH_DMASR_TUS (0x01U << ETH_DMASR_TUS_Pos ) ///< Transmit underflow status
+#define ETH_DMASR_ROS_Pos (4)
+#define ETH_DMASR_ROS (0x01U << ETH_DMASR_ROS_Pos ) ///< Receive overflow status
+#define ETH_DMASR_TJTS_Pos (3)
+#define ETH_DMASR_TJTS (0x01U << ETH_DMASR_TJTS_Pos) ///< Transmit jabber timeout status
+#define ETH_DMASR_TBUS_Pos (2)
+#define ETH_DMASR_TBUS (0x01U << ETH_DMASR_TBUS_Pos) ///< Transmit buffer unavailable status
+#define ETH_DMASR_TPSS_Pos (1)
+#define ETH_DMASR_TPSS (0x01U << ETH_DMASR_TPSS_Pos) ///< Transmit process stopped status
+#define ETH_DMASR_TS_Pos (0)
+#define ETH_DMASR_TS (0x01U << ETH_DMASR_TS_Pos ) ///< Transmit status
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMAOMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define ETH_DMAOMR_TSF_Pos (21)
+#define ETH_DMAOMR_TSF (0x01U << ETH_DMAOMR_TSF_Pos) ///< Transmit store and forward
+#define ETH_DMAOMR_FTF_Pos (20)
+#define ETH_DMAOMR_FTF (0x01U << ETH_DMAOMR_FTF_Pos) ///< Flush transmit FIFO
+#define ETH_DMAOMR_TTC_Pos (14)
+#define ETH_DMAOMR_TTC (0x07U << ETH_DMAOMR_TTC_Pos) ///< Transmit threshold control
+#define ETH_DMAOMR_TTC_64Bytes (0x00U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 64 Bytes
+#define ETH_DMAOMR_TTC_128Bytes (0x01U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 128 Bytes
+#define ETH_DMAOMR_TTC_192Bytes (0x02U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 192 Bytes
+#define ETH_DMAOMR_TTC_256Bytes (0x03U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 256 Bytes
+#define ETH_DMAOMR_TTC_40Bytes (0x04U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 40 Bytes
+#define ETH_DMAOMR_TTC_32Bytes (0x05U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 32 Bytes
+#define ETH_DMAOMR_TTC_24Bytes (0x06U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 24 Bytes
+#define ETH_DMAOMR_TTC_16Bytes (0x07U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 16 Bytes
+#define ETH_DMAOMR_ST_Pos (13)
+#define ETH_DMAOMR_ST (0x01U << ETH_DMAOMR_ST_Pos ) ///< Start/stop transmission command
+#define ETH_DMAOMR_RFD_Pos (11)
+#define ETH_DMAOMR_RFD1 (0x00U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 1 byte
+#define ETH_DMAOMR_RFD2 (0x01U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 2 byte
+#define ETH_DMAOMR_RFD3 (0x02U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 3 byte
+#define ETH_DMAOMR_RFD4 (0x03U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 4 byte
+#define ETH_DMAOMR_RFA_Pos (9)
+#define ETH_DMAOMR_RFA1 (0x00U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 1 byte
+#define ETH_DMAOMR_RFA2 (0x01U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 2 byte
+#define ETH_DMAOMR_RFA3 (0x02U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 3 byte
+#define ETH_DMAOMR_RFA4 (0x03U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 4 byte
+
+#define ETH_DMAOMR_EFC_Pos (8)
+#define ETH_DMAOMR_EFC (0x01U << ETH_DMAOMR_EFC_Pos ) ///< Enable HW Flow Control
+#define ETH_DMAOMR_FEF_Pos (7)
+#define ETH_DMAOMR_FEF (0x01U << ETH_DMAOMR_FEF_Pos ) ///< Forward error frames
+#define ETH_DMAOMR_FUGF_Pos (6)
+#define ETH_DMAOMR_FUGF (0x01U << ETH_DMAOMR_FUGF_Pos) ///< Forward undersized good frames
+#define ETH_DMAOMR_RTC_Pos (3)
+#define ETH_DMAOMR_RTC (0x03U << ETH_DMAOMR_RTC_Pos) ///< receive threshold control
+#define ETH_DMAOMR_RTC_64Bytes (0x00U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 64 Bytes
+#define ETH_DMAOMR_RTC_32Bytes (0x01U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 32 Bytes
+#define ETH_DMAOMR_RTC_96Bytes (0x02U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 96 Bytes
+#define ETH_DMAOMR_RTC_128Bytes (0x03U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 128 Bytes
+#define ETH_DMAOMR_OSF_Pos (2)
+#define ETH_DMAOMR_OSF (0x01U << ETH_DMAOMR_OSF_Pos) ///< operate on second frame
+#define ETH_DMAOMR_SR_Pos (1)
+#define ETH_DMAOMR_SR (0x01U << ETH_DMAOMR_SR_Pos ) ///< Start/stop receive
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMAIER Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMAIER_NISE_Pos (16)
+#define ETH_DMAIER_NISE (0x01U << ETH_DMAIER_NISE_Pos ) ///< Normal interrupt summary enable
+#define ETH_DMAIER_AISE_Pos (15)
+#define ETH_DMAIER_AISE (0x01U << ETH_DMAIER_AISE_Pos ) ///< Abnormal interrupt summary enable
+#define ETH_DMAIER_ERIE_Pos (14)
+#define ETH_DMAIER_ERIE (0x01U << ETH_DMAIER_ERIE_Pos ) ///< Early receive interrupt enable
+#define ETH_DMAIER_FBEIE_Pos (13)
+#define ETH_DMAIER_FBEIE (0x01U << ETH_DMAIER_FBEIE_Pos) ///< Fatal bus error interrupt enable
+#define ETH_DMAIER_ETIE_Pos (10)
+#define ETH_DMAIER_ETIE (0x01U << ETH_DMAIER_ETIE_Pos ) ///< Early transmit interrupt enable
+#define ETH_DMAIER_RWTIE_Pos (9)
+#define ETH_DMAIER_RWTIE (0x01U << ETH_DMAIER_RWTIE_Pos) ///< Receive watchdog timeout interrupt enable
+#define ETH_DMAIER_RPSIE_Pos (8)
+#define ETH_DMAIER_RPSIE (0x01U << ETH_DMAIER_RPSIE_Pos) ///< Receive process stopped interrupt enable
+#define ETH_DMAIER_RBUIE_Pos (7)
+#define ETH_DMAIER_RBUIE (0x01U << ETH_DMAIER_RBUIE_Pos) ///< Receive buffer unavailable interrupt enable
+#define ETH_DMAIER_RIE_Pos (6)
+#define ETH_DMAIER_RIE (0x01U << ETH_DMAIER_RIE_Pos ) ///< Receive interrupt enable
+#define ETH_DMAIER_TUIE_Pos (5)
+#define ETH_DMAIER_TUIE (0x01U << ETH_DMAIER_TUIE_Pos ) ///< Transmit Underflow interrupt enable
+#define ETH_DMAIER_ROIE_Pos (4)
+#define ETH_DMAIER_ROIE (0x01U << ETH_DMAIER_ROIE_Pos ) ///< Receive Overflow interrupt enable
+#define ETH_DMAIER_TJTIE_Pos (3)
+#define ETH_DMAIER_TJTIE (0x01U << ETH_DMAIER_TJTIE_Pos) ///< Transmit jabber timeout interrupt enable
+#define ETH_DMAIER_TBUIE_Pos (2)
+#define ETH_DMAIER_TBUIE (0x01U << ETH_DMAIER_TBUIE_Pos) ///< Transmit buffer unavailable interrupt enable
+#define ETH_DMAIER_TPSIE_Pos (1)
+#define ETH_DMAIER_TPSIE (0x01U << ETH_DMAIER_TPSIE_Pos) ///< Transmit process stopped interrupt enable
+#define ETH_DMAIER_TIE_Pos (0)
+#define ETH_DMAIER_TIE (0x01U << ETH_DMAIER_TIE_Pos ) ///< Transmit interrupt enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMAMFBOCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMAMFBOCR_OFOC_Pos (28)
+#define ETH_DMAMFBOCR_OFOC (0x01U << ETH_DMAMFBOCR_OFOC_Pos) ///< Overflow bit for FIFO overflow counter
+
+#define ETH_DMAMFBOCR_MFA_Pos (17)
+#define ETH_DMAMFBOCR_MFA (0x7FFU << ETH_DMAMFBOCR_MFA_Pos ) ///< Number of frames missed by the application
+
+#define ETH_DMAMFBOCR_OMFC_Pos (16)
+#define ETH_DMAMFBOCR_OMFC (0x01U << ETH_DMAMFBOCR_OMFC_Pos) ///< Overflow bit for missed frame counter
+
+#define ETH_DMAMFBOCR_MFC_Pos (0)
+#define ETH_DMAMFBOCR_MFC (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos ) ///< Number of frames missed by the controller
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHTDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHTDR_HTDAP (0xFFFFFFFFU) ///< Host transmit descriptor address pointer
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHRDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHRDR_HRDAP (0xFFFFFFFFU) ///< Host receive descriptor address pointer
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHTBAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHTBAR_HTBAP (0xFFFFFFFFU) ///< Host transmit buffer address pointer
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHRBAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHRBAR_HRBAP (0xFFFFFFFFU) ///< Host receive buffer address pointer
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
new file mode 100644
index 00000000..608c12bc
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
@@ -0,0 +1,544 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_exti.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_EXTI_H
+#define __REG_EXTI_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CFGR; ///< configuration register, offset: 0x00
+ u32 Reserved; ///< Reserved offset: 0x04
+ __IO u32 CR[4]; ///< External interrupt configuration register, offset: 0x08 - 0x14
+ __IO u32 CFGR2; ///< configuration register offset: 0x18
+ __IO u32 PDETCSR; ///< Power detection configuration status register offset: 0x1C
+ __IO u32 VOSDLY; ///< VOS delay time offset: 0x20
+ u32 Reserved1[0x100 - 0x09]; ///< Reserved space
+ __IO u32 IMR; ///< Interrupt Mask Register offset: 0x00 + 0x400
+ __IO u32 EMR; ///< Event Mask Register offset: 0x04 + 0x400
+ __IO u32 RTSR; ///< Rising Trigger Status Register offset: 0x08 + 0x400
+ __IO u32 FTSR; ///< Falling Trigger Status Register offset: 0x0C + 0x400
+ __IO u32 SWIER; ///< Software Interrupt Enable Register offset: 0x10 + 0x400
+ __IO u32 PR; ///< Pending Register offset: 0x14 + 0x400
+} EXTI_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI ((EXTI_TypeDef*) EXTI_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CFGR_MEMMODE_Pos (0)
+#define EXTI_CFGR_MEMMODE (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config
+#define EXTI_CFGR_MEMMODE_0 (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 0
+#define EXTI_CFGR_MEMMODE_1 (0x02U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 1
+#define EXTI_CFGR_FLASH_MEMORY (0x00U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 0
+#define EXTI_CFGR_SYSTEM_MEMORY (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 1
+#define EXTI_CFGR_SRAM_MEMORY (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 3
+
+
+#define EXTI_CFGR_FC_SYNCEN_Pos (27)
+#define EXTI_CFGR_FC_SYNCEN (0x01U << EXTI_CFGR_FC_SYNCEN_Pos) ///< FSMC synchronization enable
+#define EXTI_CFGR_FC_ODATAEN_Pos (28)
+#define EXTI_CFGR_FC_ODATAEN (0x01U << EXTI_CFGR_FC_ODATAEN_Pos) ///< FSMC Only used as data pin
+#define EXTI_CFGR_MODESEL_Pos (29) ///< FSMC mode selection
+#define EXTI_CFGR_MODESEL0 (0x00U << EXTI_CFGR_MODESEL0_Pos) ///< Compatible with 8080 protocol interface
+#define EXTI_CFGR_MODESEL1 (0x01U << EXTI_CFGR_MODESEL1_Pos) ///< Compatible with NOR FLASH protocol interface
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR1_EXTI0_Pos (0)
+#define EXTI_CR1_EXTI0 (0x0FU << EXTI_CR1_EXTI0_Pos) ///< EXTI 0 configuration
+#define EXTI_CR1_EXTI0_PA (0x00U << EXTI_CR1_EXTI0_Pos) ///< PA[0] pin
+#define EXTI_CR1_EXTI0_PB (0x01U << EXTI_CR1_EXTI0_Pos) ///< PB[0] pin
+#define EXTI_CR1_EXTI0_PC (0x02U << EXTI_CR1_EXTI0_Pos) ///< PC[0] pin
+#define EXTI_CR1_EXTI0_PD (0x03U << EXTI_CR1_EXTI0_Pos) ///< PD[0] pin
+
+#define EXTI_CR1_EXTI1_Pos (4)
+#define EXTI_CR1_EXTI1 (0x0FU << EXTI_CR1_EXTI1_Pos) ///< EXTI 1 configuration
+#define EXTI_CR1_EXTI1_PA (0x00U << EXTI_CR1_EXTI1_Pos) ///< PA[1] pin
+#define EXTI_CR1_EXTI1_PB (0x01U << EXTI_CR1_EXTI1_Pos) ///< PB[1] pin
+#define EXTI_CR1_EXTI1_PC (0x02U << EXTI_CR1_EXTI1_Pos) ///< PC[1] pin
+#define EXTI_CR1_EXTI1_PD (0x03U << EXTI_CR1_EXTI1_Pos) ///< PD[1] pin
+
+#define EXTI_CR1_EXTI2_Pos (8)
+#define EXTI_CR1_EXTI2 (0x0FU << EXTI_CR1_EXTI2_Pos) ///< EXTI 2 configuration
+#define EXTI_CR1_EXTI2_PA (0x00U << EXTI_CR1_EXTI2_Pos) ///< PA[2] pin
+#define EXTI_CR1_EXTI2_PB (0x01U << EXTI_CR1_EXTI2_Pos) ///< PB[2] pin
+#define EXTI_CR1_EXTI2_PC (0x02U << EXTI_CR1_EXTI2_Pos) ///< PC[2] pin
+#define EXTI_CR1_EXTI2_PD (0x03U << EXTI_CR1_EXTI2_Pos) ///< PD[2] pin
+
+#define EXTI_CR1_EXTI3_Pos (12)
+#define EXTI_CR1_EXTI3 (0x0FU << EXTI_CR1_EXTI3_Pos) ///< EXTI 3 configuration
+#define EXTI_CR1_EXTI3_PA (0x00U << EXTI_CR1_EXTI3_Pos) ///< PA[3] pin
+#define EXTI_CR1_EXTI3_PB (0x01U << EXTI_CR1_EXTI3_Pos) ///< PB[3] pin
+#define EXTI_CR1_EXTI3_PC (0x02U << EXTI_CR1_EXTI3_Pos) ///< PC[3] pin
+#define EXTI_CR1_EXTI3_PD (0x03U << EXTI_CR1_EXTI3_Pos) ///< PD[3] pin
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR2_EXTI4_Pos (0)
+#define EXTI_CR2_EXTI4 (0x0FU << EXTI_CR2_EXTI4_Pos) ///< EXTI 4 configuration
+#define EXTI_CR2_EXTI4_PA (0x00U << EXTI_CR2_EXTI4_Pos) ///< PA[4] pin
+#define EXTI_CR2_EXTI4_PB (0x01U << EXTI_CR2_EXTI4_Pos) ///< PB[4] pin
+#define EXTI_CR2_EXTI4_PC (0x02U << EXTI_CR2_EXTI4_Pos) ///< PC[4] pin
+#define EXTI_CR2_EXTI4_PD (0x03U << EXTI_CR2_EXTI4_Pos) ///< PD[4] pin
+
+#define EXTI_CR2_EXTI5_Pos (4)
+#define EXTI_CR2_EXTI5 (0x0FU << EXTI_CR2_EXTI5_Pos) ///< EXTI 5 configuration
+#define EXTI_CR2_EXTI5_PA (0x00U << EXTI_CR2_EXTI5_Pos) ///< PA[5] pin
+#define EXTI_CR2_EXTI5_PB (0x01U << EXTI_CR2_EXTI5_Pos) ///< PB[5] pin
+#define EXTI_CR2_EXTI5_PC (0x02U << EXTI_CR2_EXTI5_Pos) ///< PC[5] pin
+#define EXTI_CR2_EXTI5_PD (0x03U << EXTI_CR2_EXTI5_Pos) ///< PD[5] pin
+
+#define EXTI_CR2_EXTI6_Pos (8)
+#define EXTI_CR2_EXTI6 (0x0FU << EXTI_CR2_EXTI6_Pos) ///< EXTI 6 configuration
+#define EXTI_CR2_EXTI6_PA (0x00U << EXTI_CR2_EXTI6_Pos) ///< PA[6] pin
+#define EXTI_CR2_EXTI6_PB (0x01U << EXTI_CR2_EXTI6_Pos) ///< PB[6] pin
+#define EXTI_CR2_EXTI6_PC (0x02U << EXTI_CR2_EXTI6_Pos) ///< PC[6] pin
+#define EXTI_CR2_EXTI6_PD (0x03U << EXTI_CR2_EXTI6_Pos) ///< PD[6] pin
+
+#define EXTI_CR2_EXTI7_Pos (12)
+#define EXTI_CR2_EXTI7 (0x0FU << EXTI_CR2_EXTI7_Pos) ///< EXTI 7 configuration
+#define EXTI_CR2_EXTI7_PA (0x00U << EXTI_CR2_EXTI7_Pos) ///< PA[7] pin
+#define EXTI_CR2_EXTI7_PB (0x01U << EXTI_CR2_EXTI7_Pos) ///< PB[7] pin
+#define EXTI_CR2_EXTI7_PC (0x02U << EXTI_CR2_EXTI7_Pos) ///< PC[7] pin
+#define EXTI_CR2_EXTI7_PD (0x03U << EXTI_CR2_EXTI7_Pos) ///< PD[7] pin
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR3_EXTI8_Pos (0)
+#define EXTI_CR3_EXTI8 (0x0FU << EXTI_CR3_EXTI8_Pos) ///< EXTI 8 configuration
+#define EXTI_CR3_EXTI8_PA (0x00U << EXTI_CR3_EXTI8_Pos) ///< PA[8] pin
+#define EXTI_CR3_EXTI8_PB (0x01U << EXTI_CR3_EXTI8_Pos) ///< PB[8] pin
+#define EXTI_CR3_EXTI8_PC (0x02U << EXTI_CR3_EXTI8_Pos) ///< PC[8] pin
+#define EXTI_CR3_EXTI8_PD (0x03U << EXTI_CR3_EXTI8_Pos) ///< PD[8] pin
+
+#define EXTI_CR3_EXTI9_Pos (4)
+#define EXTI_CR3_EXTI9 (0x0FU << EXTI_CR3_EXTI9_Pos) ///< EXTI 9 configuration
+#define EXTI_CR3_EXTI9_PA (0x00U << EXTI_CR3_EXTI9_Pos) ///< PA[9] pin
+#define EXTI_CR3_EXTI9_PB (0x01U << EXTI_CR3_EXTI9_Pos) ///< PB[9] pin
+#define EXTI_CR3_EXTI9_PC (0x02U << EXTI_CR3_EXTI9_Pos) ///< PC[9] pin
+#define EXTI_CR3_EXTI9_PD (0x03U << EXTI_CR3_EXTI9_Pos) ///< PD[9] pin
+
+#define EXTI_CR3_EXTI10_Pos (8)
+#define EXTI_CR3_EXTI10 (0x0FU << EXTI_CR3_EXTI10_Pos) ///< EXTI 10 configuration
+#define EXTI_CR3_EXTI10_PA (0x00U << EXTI_CR3_EXTI10_Pos) ///< PA[10] pin
+#define EXTI_CR3_EXTI10_PB (0x01U << EXTI_CR3_EXTI10_Pos) ///< PB[10] pin
+#define EXTI_CR3_EXTI10_PC (0x02U << EXTI_CR3_EXTI10_Pos) ///< PC[10] pin
+#define EXTI_CR3_EXTI10_PD (0x03U << EXTI_CR3_EXTI10_Pos) ///< PD[10] pin
+
+#define EXTI_CR3_EXTI11_Pos (12)
+#define EXTI_CR3_EXTI11 (0x0FU << EXTI_CR3_EXTI11_Pos) ///< EXTI 11 configuration
+#define EXTI_CR3_EXTI11_PA (0x00U << EXTI_CR3_EXTI11_Pos) ///< PA[11] pin
+#define EXTI_CR3_EXTI11_PB (0x01U << EXTI_CR3_EXTI11_Pos) ///< PB[11] pin
+#define EXTI_CR3_EXTI11_PC (0x02U << EXTI_CR3_EXTI11_Pos) ///< PC[11] pin
+#define EXTI_CR3_EXTI11_PD (0x03U << EXTI_CR3_EXTI11_Pos) ///< PD[11] pin
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR4_EXTI12_Pos (0)
+#define EXTI_CR4_EXTI12 (0x0FU << EXTI_CR4_EXTI12_Pos) ///< EXTI 12 configuration
+#define EXTI_CR4_EXTI12_PA (0x00U << EXTI_CR4_EXTI12_Pos) ///< PA[12] pin
+#define EXTI_CR4_EXTI12_PB (0x01U << EXTI_CR4_EXTI12_Pos) ///< PB[12] pin
+#define EXTI_CR4_EXTI12_PC (0x02U << EXTI_CR4_EXTI12_Pos) ///< PC[12] pin
+#define EXTI_CR4_EXTI12_PD (0x03U << EXTI_CR4_EXTI12_Pos) ///< PD[12] pin
+
+#define EXTI_CR4_EXTI13_Pos (4)
+#define EXTI_CR4_EXTI13 (0x0FU << EXTI_CR4_EXTI13_Pos) ///< EXTI 13 configuration
+#define EXTI_CR4_EXTI13_PA (0x00U << EXTI_CR4_EXTI13_Pos) ///< PA[13] pin
+#define EXTI_CR4_EXTI13_PB (0x01U << EXTI_CR4_EXTI13_Pos) ///< PB[13] pin
+#define EXTI_CR4_EXTI13_PC (0x02U << EXTI_CR4_EXTI13_Pos) ///< PC[13] pin
+#define EXTI_CR4_EXTI13_PD (0x03U << EXTI_CR4_EXTI13_Pos) ///< PD[13] pin
+
+#define EXTI_CR4_EXTI14_Pos (8)
+#define EXTI_CR4_EXTI14 (0x0FU << EXTI_CR4_EXTI14_Pos) ///< EXTI 14 configuration
+#define EXTI_CR4_EXTI14_PA (0x00U << EXTI_CR4_EXTI14_Pos) ///< PA[14] pin
+#define EXTI_CR4_EXTI14_PB (0x01U << EXTI_CR4_EXTI14_Pos) ///< PB[14] pin
+#define EXTI_CR4_EXTI14_PC (0x02U << EXTI_CR4_EXTI14_Pos) ///< PC[14] pin
+#define EXTI_CR4_EXTI14_PD (0x03U << EXTI_CR4_EXTI14_Pos) ///< PD[14] pin
+
+#define EXTI_CR4_EXTI15_Pos (12)
+#define EXTI_CR4_EXTI15 (0x0FU << EXTI_CR4_EXTI15_Pos) ///< EXTI 15 configuration
+#define EXTI_CR4_EXTI15_PA (0x00U << EXTI_CR4_EXTI15_Pos) ///< PA[15] pin
+#define EXTI_CR4_EXTI15_PB (0x01U << EXTI_CR4_EXTI15_Pos) ///< PB[15] pin
+#define EXTI_CR4_EXTI15_PC (0x02U << EXTI_CR4_EXTI15_Pos) ///< PC[15] pin
+#define EXTI_CR4_EXTI15_PD (0x03U << EXTI_CR4_EXTI15_Pos) ///< PD[15] pin
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CFGR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CFGR2_I2C1_Pos (16)
+#define EXTI_CFGR2_I2C1_OD (0x00U << EXTI_CFGR2_I2C1_Pos) ///< Select open drain mode
+#define EXTI_CFGR2_I2C1_PP (0x01U << EXTI_CFGR2_I2C1_Pos) ///< Select Push-pull mode
+#define EXTI_CFGR2_I2C2_Pos (17)
+#define EXTI_CFGR2_I2C2_OD (0x00U << EXTI_CFGR2_I2C2_Pos) ///< Select open drain mode
+#define EXTI_CFGR2_I2C2_PP (0x01U << EXTI_CFGR2_I2C2_Pos) ///< Select Push-pull mode
+#define EXTI_CFGR2_ETPHY_Pos (20)
+#define EXTI_CFGR2_ETPHY_MII (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MII port
+#define EXTI_CFGR2_ETPHY_RMII (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select RMII port
+#define EXTI_CFGR2_MAC_SPD_Pos (20)
+#define EXTI_CFGR2_MAC_SPD_10 (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 10 Mbps
+#define EXTI_CFGR2_MAC_SPD_100 (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 100 Mbps
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_PDETCSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_PDETCSR_PVDE_Pos (0)
+#define EXTI_PDETCSR_PVDE (0x01U << EXTI_PDETCSR_PVDE_Pos) ///< PVD Enable
+#define EXTI_PDETCSR_PLS_Pos (1)
+#define EXTI_PDETCSR_PLS_1_7 (0x00U << EXTI_PDETCSR_PLS_Pos) ///< PVD 1.7mV
+#define EXTI_PDETCSR_PLS_2_0 (0x01U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.0mV
+#define EXTI_PDETCSR_PLS_2_3 (0x02U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.3mV
+#define EXTI_PDETCSR_PLS_2_6 (0x03U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.6mV
+#define EXTI_PDETCSR_PLS_2_9 (0x04U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.9mV
+#define EXTI_PDETCSR_PLS_3_2 (0x05U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.2mV
+#define EXTI_PDETCSR_PLS_3_5 (0x06U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.5mV
+#define EXTI_PDETCSR_PLS_3_8 (0x07U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.8mV
+#define EXTI_PDETCSR_PLS_4_1 (0x08U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.1mV
+#define EXTI_PDETCSR_PLS_4_4 (0x09U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.4mV
+#define EXTI_PDETCSR_PLS_4_7 (0x0AU << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.7mV
+#define EXTI_PDETCSR_PVDO_Pos (5)
+#define EXTI_PDETCSR_PVDO (0x01U << EXTI_PDETCSR_PVDO_Pos) ///< PVD Output state
+#define EXTI_PDETCSR_VDTO_Pos (6)
+#define EXTI_PDETCSR_VDTO (0x01U << EXTI_PDETCSR_VDTO_Pos) ///< VDTO Output state
+#define EXTI_PDETCSR_VDTE_Pos (8)
+#define EXTI_PDETCSR_VDTE (0x01U << EXTI_PDETCSR_VDTE_Pos) ///< VDT Enable
+#define EXTI_PDETCSR_VDTLS_Pos (9)
+#define EXTI_PDETCSR_VDTLS0 (0x00U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 0.9V
+#define EXTI_PDETCSR_VDTLS1 (0x01U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.0V
+#define EXTI_PDETCSR_VDTLS2 (0x02U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.1V
+#define EXTI_PDETCSR_VDTLS3 (0x03U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.2V
+#define EXTI_PDETCSR_VBATDIV3_Pos (11)
+#define EXTI_PDETCSR_VBATDIV3 (0x01U << EXTI_PDETCSR_VBATDIV3_Pos) ///< PVD Enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_VOSDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_EXTI_VOSDLY (0x3FFU) ///< VOS delay time
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_IMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_IMR_0_Pos (0)
+#define EXTI_IMR_0 (0x01U << EXTI_IMR_0_Pos) ///< Interrupt Mask on line 0
+#define EXTI_IMR_1_Pos (1)
+#define EXTI_IMR_1 (0x01U << EXTI_IMR_1_Pos) ///< Interrupt Mask on line 1
+#define EXTI_IMR_2_Pos (2)
+#define EXTI_IMR_2 (0x01U << EXTI_IMR_2_Pos) ///< Interrupt Mask on line 2
+#define EXTI_IMR_3_Pos (3)
+#define EXTI_IMR_3 (0x01U << EXTI_IMR_3_Pos) ///< Interrupt Mask on line 3
+#define EXTI_IMR_4_Pos (4)
+#define EXTI_IMR_4 (0x01U << EXTI_IMR_4_Pos) ///< Interrupt Mask on line 4
+#define EXTI_IMR_5_Pos (5)
+#define EXTI_IMR_5 (0x01U << EXTI_IMR_5_Pos) ///< Interrupt Mask on line 5
+#define EXTI_IMR_6_Pos (6)
+#define EXTI_IMR_6 (0x01U << EXTI_IMR_6_Pos) ///< Interrupt Mask on line 6
+#define EXTI_IMR_7_Pos (7)
+#define EXTI_IMR_7 (0x01U << EXTI_IMR_7_Pos) ///< Interrupt Mask on line 7
+#define EXTI_IMR_8_Pos (8)
+#define EXTI_IMR_8 (0x01U << EXTI_IMR_8_Pos) ///< Interrupt Mask on line 8
+#define EXTI_IMR_9_Pos (9)
+#define EXTI_IMR_9 (0x01U << EXTI_IMR_9_Pos) ///< Interrupt Mask on line 9
+#define EXTI_IMR_10_Pos (10)
+#define EXTI_IMR_10 (0x01U << EXTI_IMR_10_Pos) ///< Interrupt Mask on line 10
+#define EXTI_IMR_11_Pos (11)
+#define EXTI_IMR_11 (0x01U << EXTI_IMR_11_Pos) ///< Interrupt Mask on line 11
+#define EXTI_IMR_12_Pos (12)
+#define EXTI_IMR_12 (0x01U << EXTI_IMR_12_Pos) ///< Interrupt Mask on line 12
+#define EXTI_IMR_13_Pos (13)
+#define EXTI_IMR_13 (0x01U << EXTI_IMR_13_Pos) ///< Interrupt Mask on line 13
+#define EXTI_IMR_14_Pos (14)
+#define EXTI_IMR_14 (0x01U << EXTI_IMR_14_Pos) ///< Interrupt Mask on line 14
+#define EXTI_IMR_15_Pos (15)
+#define EXTI_IMR_15 (0x01U << EXTI_IMR_15_Pos) ///< Interrupt Mask on line 15
+#define EXTI_IMR_16_Pos (16)
+#define EXTI_IMR_16 (0x01U << EXTI_IMR_16_Pos) ///< Interrupt Mask on line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_EMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_EMR_0_Pos (0)
+#define EXTI_EMR_0 (0x01U << EXTI_EMR_0_Pos) ///< Event Mask on line 0
+#define EXTI_EMR_1_Pos (1)
+#define EXTI_EMR_1 (0x01U << EXTI_EMR_1_Pos) ///< Event Mask on line 1
+#define EXTI_EMR_2_Pos (2)
+#define EXTI_EMR_2 (0x01U << EXTI_EMR_2_Pos) ///< Event Mask on line 2
+#define EXTI_EMR_3_Pos (3)
+#define EXTI_EMR_3 (0x01U << EXTI_EMR_3_Pos) ///< Event Mask on line 3
+#define EXTI_EMR_4_Pos (4)
+#define EXTI_EMR_4 (0x01U << EXTI_EMR_4_Pos) ///< Event Mask on line 4
+#define EXTI_EMR_5_Pos (5)
+#define EXTI_EMR_5 (0x01U << EXTI_EMR_5_Pos) ///< Event Mask on line 5
+#define EXTI_EMR_6_Pos (6)
+#define EXTI_EMR_6 (0x01U << EXTI_EMR_6_Pos) ///< Event Mask on line 6
+#define EXTI_EMR_7_Pos (7)
+#define EXTI_EMR_7 (0x01U << EXTI_EMR_7_Pos) ///< Event Mask on line 7
+#define EXTI_EMR_8_Pos (8)
+#define EXTI_EMR_8 (0x01U << EXTI_EMR_8_Pos) ///< Event Mask on line 8
+#define EXTI_EMR_9_Pos (9)
+#define EXTI_EMR_9 (0x01U << EXTI_EMR_9_Pos) ///< Event Mask on line 9
+#define EXTI_EMR_10_Pos (10)
+#define EXTI_EMR_10 (0x01U << EXTI_EMR_10_Pos) ///< Event Mask on line 10
+#define EXTI_EMR_11_Pos (11)
+#define EXTI_EMR_11 (0x01U << EXTI_EMR_11_Pos) ///< Event Mask on line 11
+#define EXTI_EMR_12_Pos (12)
+#define EXTI_EMR_12 (0x01U << EXTI_EMR_12_Pos) ///< Event Mask on line 12
+#define EXTI_EMR_13_Pos (13)
+#define EXTI_EMR_13 (0x01U << EXTI_EMR_13_Pos) ///< Event Mask on line 13
+#define EXTI_EMR_14_Pos (14)
+#define EXTI_EMR_14 (0x01U << EXTI_EMR_14_Pos) ///< Event Mask on line 14
+#define EXTI_EMR_15_Pos (15)
+#define EXTI_EMR_15 (0x01U << EXTI_EMR_15_Pos) ///< Event Mask on line 15
+#define EXTI_EMR_16_Pos (16)
+#define EXTI_EMR_16 (0x01U << EXTI_EMR_16_Pos) ///< Event Mask on line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_RTSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_RTSR_0_Pos (0)
+#define EXTI_RTSR_0 (0x01U << EXTI_RTSR_0_Pos) ///< Rising trigger event configuration bit of line 0
+#define EXTI_RTSR_1_Pos (1)
+#define EXTI_RTSR_1 (0x01U << EXTI_RTSR_1_Pos) ///< Rising trigger event configuration bit of line 1
+#define EXTI_RTSR_2_Pos (2)
+#define EXTI_RTSR_2 (0x01U << EXTI_RTSR_2_Pos) ///< Rising trigger event configuration bit of line 2
+#define EXTI_RTSR_3_Pos (3)
+#define EXTI_RTSR_3 (0x01U << EXTI_RTSR_3_Pos) ///< Rising trigger event configuration bit of line 3
+#define EXTI_RTSR_4_Pos (4)
+#define EXTI_RTSR_4 (0x01U << EXTI_RTSR_4_Pos) ///< Rising trigger event configuration bit of line 4
+#define EXTI_RTSR_5_Pos (5)
+#define EXTI_RTSR_5 (0x01U << EXTI_RTSR_5_Pos) ///< Rising trigger event configuration bit of line 5
+#define EXTI_RTSR_6_Pos (6)
+#define EXTI_RTSR_6 (0x01U << EXTI_RTSR_6_Pos) ///< Rising trigger event configuration bit of line 6
+#define EXTI_RTSR_7_Pos (7)
+#define EXTI_RTSR_7 (0x01U << EXTI_RTSR_7_Pos) ///< Rising trigger event configuration bit of line 7
+#define EXTI_RTSR_8_Pos (8)
+#define EXTI_RTSR_8 (0x01U << EXTI_RTSR_8_Pos) ///< Rising trigger event configuration bit of line 8
+#define EXTI_RTSR_9_Pos (9)
+#define EXTI_RTSR_9 (0x01U << EXTI_RTSR_9_Pos) ///< Rising trigger event configuration bit of line 9
+#define EXTI_RTSR_10_Pos (10)
+#define EXTI_RTSR_10 (0x01U << EXTI_RTSR_10_Pos) ///< Rising trigger event configuration bit of line 10
+#define EXTI_RTSR_11_Pos (11)
+#define EXTI_RTSR_11 (0x01U << EXTI_RTSR_11_Pos) ///< Rising trigger event configuration bit of line 11
+#define EXTI_RTSR_12_Pos (12)
+#define EXTI_RTSR_12 (0x01U << EXTI_RTSR_12_Pos) ///< Rising trigger event configuration bit of line 12
+#define EXTI_RTSR_13_Pos (13)
+#define EXTI_RTSR_13 (0x01U << EXTI_RTSR_13_Pos) ///< Rising trigger event configuration bit of line 13
+#define EXTI_RTSR_14_Pos (14)
+#define EXTI_RTSR_14 (0x01U << EXTI_RTSR_14_Pos) ///< Rising trigger event configuration bit of line 14
+#define EXTI_RTSR_15_Pos (15)
+#define EXTI_RTSR_15 (0x01U << EXTI_RTSR_15_Pos) ///< Rising trigger event configuration bit of line 15
+#define EXTI_RTSR_16_Pos (16)
+#define EXTI_RTSR_16 (0x01U << EXTI_RTSR_16_Pos) ///< Rising trigger event configuration bit of line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_FTSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_FTSR_0_Pos (0)
+#define EXTI_FTSR_0 (0x01U << EXTI_FTSR_0_Pos) ///< Falling trigger event configuration bit of line 0
+#define EXTI_FTSR_1_Pos (1)
+#define EXTI_FTSR_1 (0x01U << EXTI_FTSR_1_Pos) ///< Falling trigger event configuration bit of line 1
+#define EXTI_FTSR_2_Pos (2)
+#define EXTI_FTSR_2 (0x01U << EXTI_FTSR_2_Pos) ///< Falling trigger event configuration bit of line 2
+#define EXTI_FTSR_3_Pos (3)
+#define EXTI_FTSR_3 (0x01U << EXTI_FTSR_3_Pos) ///< Falling trigger event configuration bit of line 3
+#define EXTI_FTSR_4_Pos (4)
+#define EXTI_FTSR_4 (0x01U << EXTI_FTSR_4_Pos) ///< Falling trigger event configuration bit of line 4
+#define EXTI_FTSR_5_Pos (5)
+#define EXTI_FTSR_5 (0x01U << EXTI_FTSR_5_Pos) ///< Falling trigger event configuration bit of line 5
+#define EXTI_FTSR_6_Pos (6)
+#define EXTI_FTSR_6 (0x01U << EXTI_FTSR_6_Pos) ///< Falling trigger event configuration bit of line 6
+#define EXTI_FTSR_7_Pos (7)
+#define EXTI_FTSR_7 (0x01U << EXTI_FTSR_7_Pos) ///< Falling trigger event configuration bit of line 7
+#define EXTI_FTSR_8_Pos (8)
+#define EXTI_FTSR_8 (0x01U << EXTI_FTSR_8_Pos) ///< Falling trigger event configuration bit of line 8
+#define EXTI_FTSR_9_Pos (9)
+#define EXTI_FTSR_9 (0x01U << EXTI_FTSR_9_Pos) ///< Falling trigger event configuration bit of line 9
+#define EXTI_FTSR_10_Pos (10)
+#define EXTI_FTSR_10 (0x01U << EXTI_FTSR_10_Pos) ///< Falling trigger event configuration bit of line 10
+#define EXTI_FTSR_11_Pos (11)
+#define EXTI_FTSR_11 (0x01U << EXTI_FTSR_11_Pos) ///< Falling trigger event configuration bit of line 11
+#define EXTI_FTSR_12_Pos (12)
+#define EXTI_FTSR_12 (0x01U << EXTI_FTSR_12_Pos) ///< Falling trigger event configuration bit of line 12
+#define EXTI_FTSR_13_Pos (13)
+#define EXTI_FTSR_13 (0x01U << EXTI_FTSR_13_Pos) ///< Falling trigger event configuration bit of line 13
+#define EXTI_FTSR_14_Pos (14)
+#define EXTI_FTSR_14 (0x01U << EXTI_FTSR_14_Pos) ///< Falling trigger event configuration bit of line 14
+#define EXTI_FTSR_15_Pos (15)
+#define EXTI_FTSR_15 (0x01U << EXTI_FTSR_15_Pos) ///< Falling trigger event configuration bit of line 15
+#define EXTI_FTSR_16_Pos (16)
+#define EXTI_FTSR_16 (0x01U << EXTI_FTSR_16_Pos) ///< Falling trigger event configuration bit of line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_SWIER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_SWIER_0_Pos (0)
+#define EXTI_SWIER_0 (0x01U << EXTI_SWIER_0_Pos) ///< Software Interrupt on line 0
+#define EXTI_SWIER_1_Pos (1)
+#define EXTI_SWIER_1 (0x01U << EXTI_SWIER_1_Pos) ///< Software Interrupt on line 1
+#define EXTI_SWIER_2_Pos (2)
+#define EXTI_SWIER_2 (0x01U << EXTI_SWIER_2_Pos) ///< Software Interrupt on line 2
+#define EXTI_SWIER_3_Pos (3)
+#define EXTI_SWIER_3 (0x01U << EXTI_SWIER_3_Pos) ///< Software Interrupt on line 3
+#define EXTI_SWIER_4_Pos (4)
+#define EXTI_SWIER_4 (0x01U << EXTI_SWIER_4_Pos) ///< Software Interrupt on line 4
+#define EXTI_SWIER_5_Pos (5)
+#define EXTI_SWIER_5 (0x01U << EXTI_SWIER_5_Pos) ///< Software Interrupt on line 5
+#define EXTI_SWIER_6_Pos (6)
+#define EXTI_SWIER_6 (0x01U << EXTI_SWIER_6_Pos) ///< Software Interrupt on line 6
+#define EXTI_SWIER_7_Pos (7)
+#define EXTI_SWIER_7 (0x01U << EXTI_SWIER_7_Pos) ///< Software Interrupt on line 7
+#define EXTI_SWIER_8_Pos (8)
+#define EXTI_SWIER_8 (0x01U << EXTI_SWIER_8_Pos) ///< Software Interrupt on line 8
+#define EXTI_SWIER_9_Pos (9)
+#define EXTI_SWIER_9 (0x01U << EXTI_SWIER_9_Pos) ///< Software Interrupt on line 9
+#define EXTI_SWIER_10_Pos (10)
+#define EXTI_SWIER_10 (0x01U << EXTI_SWIER_10_Pos) ///< Software Interrupt on line 10
+#define EXTI_SWIER_11_Pos (11)
+#define EXTI_SWIER_11 (0x01U << EXTI_SWIER_11_Pos) ///< Software Interrupt on line 11
+#define EXTI_SWIER_12_Pos (12)
+#define EXTI_SWIER_12 (0x01U << EXTI_SWIER_12_Pos) ///< Software Interrupt on line 12
+#define EXTI_SWIER_13_Pos (13)
+#define EXTI_SWIER_13 (0x01U << EXTI_SWIER_13_Pos) ///< Software Interrupt on line 13
+#define EXTI_SWIER_14_Pos (14)
+#define EXTI_SWIER_14 (0x01U << EXTI_SWIER_14_Pos) ///< Software Interrupt on line 14
+#define EXTI_SWIER_15_Pos (15)
+#define EXTI_SWIER_15 (0x01U << EXTI_SWIER_15_Pos) ///< Software Interrupt on line 15
+#define EXTI_SWIER_16_Pos (16)
+#define EXTI_SWIER_16 (0x01U << EXTI_SWIER_16_Pos) ///< Software Interrupt on line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_PR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_PR_0_Pos (0)
+#define EXTI_PR_0 (0x01U << EXTI_PR_0_Pos) ///< Pending bit 0
+#define EXTI_PR_1_Pos (1)
+#define EXTI_PR_1 (0x01U << EXTI_PR_1_Pos) ///< Pending bit 1
+#define EXTI_PR_2_Pos (2)
+#define EXTI_PR_2 (0x01U << EXTI_PR_2_Pos) ///< Pending bit 2
+#define EXTI_PR_3_Pos (3)
+#define EXTI_PR_3 (0x01U << EXTI_PR_3_Pos) ///< Pending bit 3
+#define EXTI_PR_4_Pos (4)
+#define EXTI_PR_4 (0x01U << EXTI_PR_4_Pos) ///< Pending bit 4
+#define EXTI_PR_5_Pos (5)
+#define EXTI_PR_5 (0x01U << EXTI_PR_5_Pos) ///< Pending bit 5
+#define EXTI_PR_6_Pos (6)
+#define EXTI_PR_6 (0x01U << EXTI_PR_6_Pos) ///< Pending bit 6
+#define EXTI_PR_7_Pos (7)
+#define EXTI_PR_7 (0x01U << EXTI_PR_7_Pos) ///< Pending bit 7
+#define EXTI_PR_8_Pos (8)
+#define EXTI_PR_8 (0x01U << EXTI_PR_8_Pos) ///< Pending bit 8
+#define EXTI_PR_9_Pos (9)
+#define EXTI_PR_9 (0x01U << EXTI_PR_9_Pos) ///< Pending bit 9
+#define EXTI_PR_10_Pos (10)
+#define EXTI_PR_10 (0x01U << EXTI_PR_10_Pos) ///< Pending bit 10
+#define EXTI_PR_11_Pos (11)
+#define EXTI_PR_11 (0x01U << EXTI_PR_11_Pos) ///< Pending bit 11
+#define EXTI_PR_12_Pos (12)
+#define EXTI_PR_12 (0x01U << EXTI_PR_12_Pos) ///< Pending bit 12
+#define EXTI_PR_13_Pos (13)
+#define EXTI_PR_13 (0x01U << EXTI_PR_13_Pos) ///< Pending bit 13
+#define EXTI_PR_14_Pos (14)
+#define EXTI_PR_14 (0x01U << EXTI_PR_14_Pos) ///< Pending bit 14
+#define EXTI_PR_15_Pos (15)
+#define EXTI_PR_15 (0x01U << EXTI_PR_15_Pos) ///< Pending bit 15
+#define EXTI_PR_16_Pos (16)
+#define EXTI_PR_16 (0x01U << EXTI_PR_16_Pos) ///< Pending bit 16
+
+
+
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
new file mode 100644
index 00000000..b95acef6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
@@ -0,0 +1,290 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_flash.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_FLASH_H
+#define __REG_FLASH_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief MM32 MCU Memory/Peripherals mapping
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_BASE (0x08000000U) ///< FLASH base address in the alias region
+#define SRAM_BASE (0x20000000U) ///< SRAM base address in the alias region
+
+#define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000) ///< Base Address: 0x40022000
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OPTB Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OB_BASE (0x1FFFF800U) ///< Flash Option Bytes base address
+#define PROTECT_BASE (0x1FFE0000U) ///< Flash Protect Bytes base address
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 ACR; ///< Access control Register offset: 0x00
+ __IO u32 KEYR; ///< Key Register offset: 0x04
+ __IO u32 OPTKEYR; ///< Option byte key Register offset: 0x08
+ __IO u32 SR; ///< State Register offset: 0x0C
+ __IO u32 CR; ///< Control Register offset: 0x10
+ __IO u32 AR; ///< Address Register offset: 0x14
+ __IO u32 RESERVED;
+ __IO u32 OBR; ///< Option bytes Register offset: 0x1C
+ __IO u32 WRPR; ///< Write protect Register offset: 0x20
+} FLASH_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OPT Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u16 RDP; ///< Read Protect, offset: 0x00
+ __IO u16 USER; ///< User option byte, offset: 0x02
+ __IO u16 Data0; ///< User data 0, offset: 0x04
+ __IO u16 Data1; ///< User data 1, offset: 0x06
+ __IO u16 WRP0; ///< Flash write protection option byte 0, offset: 0x08
+ __IO u16 WRP1; ///< Flash write protection option byte 1, offset: 0x0A
+ __IO u16 WRP2; ///< Flash write protection option byte 2, offset: 0x0C
+ __IO u16 WRP3; ///< Flash write protection option byte 3, offset: 0x0E
+} OB_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PROTECT BYTES Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u16 PROTECT_LEN0; ///< The length of Protect byte 0, offset: 0x00
+ __IO u16 PROTECT_ADDR0; ///< Data of Protect byte 0, offset: 0x02
+ __IO u16 PROTECT_LEN1; ///< The length of Protect byte 1, offset: 0x04
+ __IO u16 PROTECT_ADDR1; ///< Data of Protect byte 1, offset: 0x06
+ __IO u16 PROTECT_LEN2; ///< The length of Protect byte 2, offset: 0x08
+ __IO u16 PROTECT_ADDR2; ///< Data of Protect byte 2, offset: 0x0A
+ __IO u16 PROTECT_LEN3; ///< The length of Protect byte 3, offset: 0x0C
+ __IO u16 PROTECT_ADDR3; ///< Data of Protect byte 3, offset: 0x0E
+} PROTECT_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE BYTES Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ __IO u32 CCR; ///< Configuration and control register offset: 0x00
+ __IO u32 SR; ///< Status register offset: 0x04
+ __IO u32 IMR; ///< Interrupt mask register offset: 0x08
+ __IO u32 ISR; ///< Interrupt status register offset: 0x0C
+ __IO u32 RESERVED0; ///< offset: 0x10
+ __IO u32 CSHR; ///< Hit Statistics Register offset: 0x14
+ __IO u32 CSMR; ///< Lost Statistics Register offset: 0x18
+} CACHE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH ((FLASH_TypeDef*) FLASH_REG_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OPTB type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OB ((OB_TypeDef*) OB_BASE)
+#define PROTECT ((PROTECT_TypeDef*) PROTECT_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE ((CACHE_TypeDef*) CACHE_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_ACR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_ACR_LATENCY_Pos (0)
+#define FLASH_ACR_LATENCY (0x07U << FLASH_ACR_LATENCY_Pos) ///< LATENCY[2:0] bits (Latency)
+#define FLASH_ACR_LATENCY_0 (0x00U << FLASH_ACR_LATENCY_Pos) ///< 0 waiting state
+#define FLASH_ACR_LATENCY_1 (0x01U << FLASH_ACR_LATENCY_Pos) ///< 1 waiting state
+#define FLASH_ACR_LATENCY_2 (0x02U << FLASH_ACR_LATENCY_Pos) ///< 2 waiting state
+#define FLASH_ACR_LATENCY_3 (0x03U << FLASH_ACR_LATENCY_Pos) ///< 3 waiting state
+#define FLASH_ACR_HLFCYA_Pos (3)
+#define FLASH_ACR_HLFCYA (0x01U << FLASH_ACR_HLFCYA_Pos) ///< Flash Half Cycle Access Enable
+#define FLASH_ACR_PRFTBE_Pos (4)
+#define FLASH_ACR_PRFTBE (0x01U << FLASH_ACR_PRFTBE_Pos) ///< Prefetch Buffer Enable
+#define FLASH_ACR_PRFTBS_Pos (5)
+#define FLASH_ACR_PRFTBS (0x01U << FLASH_ACR_PRFTBS_Pos) ///< Prefetch Buffer Status
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_KEYR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_KEYR_FKEY_Pos (0)
+#define FLASH_KEYR_FKEY (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos) ///< FLASH Key
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_OPTKEYR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_OPTKEYR_OPTKEY_Pos (0)
+#define FLASH_OPTKEYR_OPTKEY (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos) ///< Option Byte Key
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_SR_BUSY_Pos (0)
+#define FLASH_SR_BUSY (0x01U << FLASH_SR_BUSY_Pos) ///< Busy
+#define FLASH_SR_PGERR_Pos (2)
+#define FLASH_SR_PGERR (0x01U << FLASH_SR_PGERR_Pos) ///< Programming Error
+#define FLASH_SR_WRPRTERR_Pos (4)
+#define FLASH_SR_WRPRTERR (0x01U << FLASH_SR_WRPRTERR_Pos) ///< Write Protection Error
+#define FLASH_SR_EOP_Pos (5)
+#define FLASH_SR_EOP (0x01U << FLASH_SR_EOP_Pos) ///< End of operation
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_CR_PG_Pos (0)
+#define FLASH_CR_PG (0x01U << FLASH_CR_PG_Pos) ///< Programming
+#define FLASH_CR_PER_Pos (1)
+#define FLASH_CR_PER (0x01U << FLASH_CR_PER_Pos) ///< Page Erase
+#define FLASH_CR_MER_Pos (2)
+#define FLASH_CR_MER (0x01U << FLASH_CR_MER_Pos) ///< Mass Erase
+#define FLASH_CR_OPTPG_Pos (4)
+#define FLASH_CR_OPTPG (0x01U << FLASH_CR_OPTPG_Pos) ///< Option Byte Programming
+#define FLASH_CR_OPTER_Pos (5)
+#define FLASH_CR_OPTER (0x01U << FLASH_CR_OPTER_Pos) ///< Option Byte Erase
+#define FLASH_CR_STRT_Pos (6)
+#define FLASH_CR_STRT (0x01U << FLASH_CR_STRT_Pos) ///< Start
+#define FLASH_CR_LOCK_Pos (7)
+#define FLASH_CR_LOCK (0x01U << FLASH_CR_LOCK_Pos) ///< Lock
+#define FLASH_CR_OPTWRE_Pos (9)
+#define FLASH_CR_OPTWRE (0x01U << FLASH_CR_OPTWRE_Pos) ///< Option Bytes Write Enable
+#define FLASH_CR_ERRIE_Pos (10)
+#define FLASH_CR_ERRIE (0x01U << FLASH_CR_ERRIE_Pos) ///< Error Interrupt Enable
+#define FLASH_CR_EOPIE_Pos (12)
+#define FLASH_CR_EOPIE (0x01U << FLASH_CR_EOPIE_Pos) ///< End of operation interrupt enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_AR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_AR_FAR_Pos (0)
+#define FLASH_AR_FAR (0xFFFFFFFFU << FLASH_AR_FAR_Pos) ///< Flash Address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_OBR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_OBR_OPTERR_Pos (0)
+#define FLASH_OBR_OPTERR (0x01U << FLASH_OBR_OPTERR_Pos) ///< Option Byte Error
+#define FLASH_OBR_RDPRT_Pos (1)
+#define FLASH_OBR_RDPRT (0x01U << FLASH_OBR_RDPRT_Pos) ///< Read protection level status
+#define FLASH_OBR_USER_Pos (2)
+#define FLASH_OBR_USER (0xFFU << FLASH_OBR_USER_Pos) ///< User Option Bytes
+
+#define FLASH_OBR_WDG_SW (0x01U << FLASH_OBR_USER_Pos) ///< WDG_SW
+#define FLASH_OBR_RST_STOP (0x02U << FLASH_OBR_USER_Pos) ///< nRST_STOP
+#define FLASH_OBR_RST_STDBY (0x04U << FLASH_OBR_USER_Pos) ///< nRST_STDBY
+
+
+#define FLASH_OBR_Data0_Pos (10)
+#define FLASH_OBR_Data0 (0xFFU << FLASH_OBR_Data0_Pos) ///< User data storage option byte
+#define FLASH_OBR_Data1_Pos (18)
+#define FLASH_OBR_Data1 (0xFFU << FLASH_OBR_Data1_Pos) ///< User data storage option byte
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_WRPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_WRPR_WRP_Pos (0)
+#define FLASH_WRPR_WRP (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) ///< Write Protect
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_CCR_EN_Pos (0)
+#define CACHE_CCR_EN (0x01U << CACHE_CCR_EN_Pos) ///< Cache Enable
+#define CACHE_CCR_INV_Pos (1)
+#define CACHE_CCR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Manually invalidate the request
+#define CACHE_CCR_POW_Pos (2)
+#define CACHE_CCR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< Manual SRAM power request
+#define CACHE_CCR_MAN_POW_Pos (3)
+#define CACHE_CCR_MAN_POW (0x01U << CACHE_CCR_MAN_POW_Pos) ///< Set manual or automatic SRAM power request
+#define CACHE_CCR_MAN_INV_Pos (4)
+#define CACHE_CCR_MAN_INV (0x01U << CACHE_CCR_MAN_INV_Pos) ///< Manually or automatically disable it
+#define CACHE_CCR_PREFETCH_Pos (5)
+#define CACHE_CCR_PREFETCH (0x01U << CACHE_CCR_PREFETCH_Pos) ///< Prefetch function
+#define CACHE_CCR_STATISTIC_Pos (6)
+#define CACHE_CCR_STATISTIC (0x01U << CACHE_CCR_STATISTIC_Pos) ///< Statistics enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_SR_CS_Pos (0)
+#define CACHE_SR_CS0 (0x00U << CACHE_CCR_CS_Pos) ///< Cache is disabled
+#define CACHE_SR_CS1 (0x01U << CACHE_CCR_CS_Pos) ///< Cache is being enabled
+#define CACHE_SR_CS2 (0x02U << CACHE_CCR_CS_Pos) ///< Cache is enabled
+#define CACHE_SR_CS3 (0x03U << CACHE_CCR_CS_Pos) ///< Cache is being disabled
+#define CACHE_SR_INV_Pos (2)
+#define CACHE_SR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Invalidation status
+#define CACHE_SR_POW_Pos (4)
+#define CACHE_SR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< SRAM power response
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_IMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_IMR_MAN_INV_Pos (0)
+#define CACHE_IMR_MAN_INV (0x01U << CACHE_IMR_MAN_INV_Pos) ///< Mask the interrupt request of manual invalidation error
+#define CACHE_IMR_POW_Pos (1)
+#define CACHE_IMR_POW (0x01U << CACHE_IMR_POW_Pos) ///< Mask the interrupt request of power supply error
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_ISR_MAN_INV_Pos (0)
+#define CACHE_ISR_MAN_INV (0x01U << CACHE_ISR_MAN_INV_Pos) ///< Manual invalidation of error flags
+#define CACHE_ISR_POW_Pos (1)
+#define CACHE_ISR_POW (0x01U << CACHE_ISR_POW_Pos) ///< SRAM power error flags
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_CSHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_CSHR (0xFFFFU ) ///< Cache Hits
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_CSHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_CSMR (0xFFFFU ) ///< Cache Lost times
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
new file mode 100644
index 00000000..77870dd1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
@@ -0,0 +1,194 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_fsmc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_FSMC_H
+#define __REG_FSMC_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define FSMC_BANK1_ADDR (0x60000000UL )
+#define FSMC_BANK2_ADDR (0x60000000UL + 0x4000000 )
+#define FSMC_BANK3_ADDR (0x60000000UL + 0x8000000 )
+#define FSMC_BANK4_ADDR (0x60000000UL + 0xc000000 )
+#define FSMC_BASE (0x60000000UL + 0x40000000) ///< Base Address: 0xA0000000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ __IO u32 Reservedoffset0x00; ///< Reserved Register offset: 0x00
+ __IO u32 Reservedoffset0x04; ///< Reserved Register offset: 0x04
+ __IO u32 Reservedoffset0x08; ///< Reserved Register offset: 0x08
+ __IO u32 Reservedoffset0x0c; ///< Reserved Register offset: 0x0c
+ __IO u32 Reservedoffset0x10; ///< Reserved Register offset: 0x10
+ __IO u32 Reservedoffset0x14; ///< Reserved Register offset: 0x14
+ __IO u32 Reservedoffset0x18; ///< Reserved Register offset: 0x18
+ __IO u32 Reservedoffset0x1c; ///< Reserved Register offset: 0x1c
+ __IO u32 Reservedoffset0x20; ///< Reserved Register offset: 0x20
+ __IO u32 Reservedoffset0x24; ///< Reserved Register offset: 0x24
+ __IO u32 Reservedoffset0x28; ///< Reserved Register offset: 0x28
+ __IO u32 Reservedoffset0x2c; ///< Reserved Register offset: 0x2c
+ __IO u32 Reservedoffset0x30; ///< Reserved Register offset: 0x30
+ __IO u32 Reservedoffset0x34; ///< Reserved Register offset: 0x34
+ __IO u32 Reservedoffset0x38; ///< Reserved Register offset: 0x38
+ __IO u32 Reservedoffset0x3c; ///< Reserved Register offset: 0x3c
+ __IO u32 Reservedoffset0x40; ///< Reserved Register offset: 0x40
+ __IO u32 Reservedoffset0x44; ///< Reserved Register offset: 0x44
+ __IO u32 Reservedoffset0x48; ///< Reserved Register offset: 0x48
+ __IO u32 Reservedoffset0x4c; ///< Reserved Register offset: 0x4c
+ __IO u32 Reservedoffset0x50; ///< Reserved Register offset: 0x50
+ __IO u32 SMSKR; ///< SMSKR control Register offset: 0x54
+ __IO u32 Reservedoffset0x58; ///< Reserved Register offset: 0x58
+ __IO u32 Reservedoffset0x5c; ///< Reserved Register offset: 0x5c
+ __IO u32 Reservedoffset0x60; ///< Reserved Register offset: 0x60
+ __IO u32 Reservedoffset0x64; ///< Reserved Register offset: 0x64
+ __IO u32 Reservedoffset0x68; ///< Reserved Register offset: 0x68
+ __IO u32 Reservedoffset0x6c; ///< Reserved Register offset: 0x6c
+ __IO u32 Reservedoffset0x70; ///< Reserved Register offset: 0x70
+ __IO u32 Reservedoffset0x74; ///< Reserved Register offset: 0x74
+ __IO u32 Reservedoffset0x78; ///< Reserved Register offset: 0x78
+ __IO u32 Reservedoffset0x7c; ///< Reserved Register offset: 0x7c
+ __IO u32 Reservedoffset0x80; ///< Reserved Register offset: 0x80
+ __IO u32 Reservedoffset0x84; ///< Reserved Register offset: 0x84
+ __IO u32 Reservedoffset0x88; ///< Reserved Register offset: 0x88
+ __IO u32 Reservedoffset0x8c; ///< Reserved Register offset: 0x8c
+ __IO u32 Reservedoffset0x90; ///< Reserved Register offset: 0x90
+ __IO u32 SMTMGR_SET0; ///< SMTMGR_SET Register 0 offset: 0x94
+ __IO u32 SMTMGR_SET1; ///< SMTMGR_SET Register 1 offset: 0x98
+ __IO u32 SMTMGR_SET2; ///< SMTMGR_SET Register 2 offset: 0x9c
+ __IO u32 Reservedoffset0xA0; ///< Reserved Register offset: 0xa0
+ __IO u32 SMCTLR; ///< Reserved Register offset: 0xa4
+ __IO u32 Reservedoffset0xA8; ///< Reserved Register offset: 0xa8
+ __IO u32 Reservedoffset0xAC; ///< Reserved Register offset: 0xac
+} FSMC_TypeDef;
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC ((FSMC_TypeDef*) FSMC_BASE)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_SMSKR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC_SMSKR_REG_SELECT_Pos (8)
+#define FSMC_SMSKR_REG_SELECT0 (0x00U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 0
+#define FSMC_SMSKR_REG_SELECT1 (0x01U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 1
+#define FSMC_SMSKR_REG_SELECT2 (0x02U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 2
+#define FSMC_SMSKR_MEM_TYPE_Pos (5)
+#define FSMC_SMSKR_MEM_TYPE0 (0x00U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SDRAM
+#define FSMC_SMSKR_MEM_TYPE1 (0x01U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SRAM
+#define FSMC_SMSKR_MEM_TYPE2 (0x02U << FSMC_SMSKR_MEM_TYPE_Pos) ///< FLASH
+#define FSMC_SMSKR_MEM_SIZE_Pos (0)
+#define FSMC_SMSKR_MEM_SIZE_64K (0x01U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64KB
+#define FSMC_SMSKR_MEM_SIZE_128K (0x02U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128KB
+#define FSMC_SMSKR_MEM_SIZE_256K (0x03U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256KB
+#define FSMC_SMSKR_MEM_SIZE_512K (0x04U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512KB
+#define FSMC_SMSKR_MEM_SIZE_1M (0x05U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1MB
+#define FSMC_SMSKR_MEM_SIZE_2M (0x06U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2MB
+#define FSMC_SMSKR_MEM_SIZE_4M (0x07U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4MB
+#define FSMC_SMSKR_MEM_SIZE_8M (0x08U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 8MB
+#define FSMC_SMSKR_MEM_SIZE_16M (0x09U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 16MB
+#define FSMC_SMSKR_MEM_SIZE_32M (0x10U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 32MB
+#define FSMC_SMSKR_MEM_SIZE_64M (0x11U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64MB
+#define FSMC_SMSKR_MEM_SIZE_128M (0x12U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128MB
+#define FSMC_SMSKR_MEM_SIZE_256M (0x13U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256MB
+#define FSMC_SMSKR_MEM_SIZE_512M (0x14U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512MB
+#define FSMC_SMSKR_MEM_SIZE_1G (0x15U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1GB
+#define FSMC_SMSKR_MEM_SIZE_2G (0x16U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2GB
+#define FSMC_SMSKR_MEM_SIZE_4G (0x17U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4GB
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos (28)
+#define FSMC_SMTMGR_SET_SM_READ_PIPE (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) ///< The period of the latched read data
+#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos (27)
+#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos) ///< Access low frequency synchronization devices
+#define FSMC_SMTMGR_SET_READ_MODE_Pos (26)
+#define FSMC_SMTMGR_SET_READ_MODE (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos) ///< The Hready_RESP signal is from an external DEVICE
+#define FSMC_SMTMGR_SET_T_WP_Pos (10)
+#define FSMC_SMTMGR_SET_T_WP (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos) ///< Write pulse width 64 clock cycles
+#define FSMC_SMTMGR_SET_T_WR_Pos (8)
+#define FSMC_SMTMGR_SET_T_WR (0x03U << FSMC_SMTMGR_SET_T_WR_Pos) ///< Address/data retention time for write operations is 3 clock cycles
+#define FSMC_SMTMGR_SET_T_AS_Pos (6)
+#define FSMC_SMTMGR_SET_T_AS (0x03U << FSMC_SMTMGR_SET_T_AS_Pos) ///< The address establishment time of write operation is 3 clock cycles
+#define FSMC_SMTMGR_SET_T_RC_Pos (0)
+#define FSMC_SMTMGR_SET_T_RC (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos) ///< Read operation cycle 64 clock cycles
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_SMCTLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos (13)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 16 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 32 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 64 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 128 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 8 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos (10)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 16 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 32 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 64 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 128 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 8 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos (7)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 16 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 32 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 64 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 128 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 8 bits
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__REG_FSMC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
new file mode 100644
index 00000000..44e043ba
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
@@ -0,0 +1,706 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_gpio.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_GPIO_H
+#define __REG_GPIO_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x0020000) ///< Base Address: 0x40040000
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x0020400) ///< Base Address: 0x40040400
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x0020800) ///< Base Address: 0x40040800
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x0020C00) ///< Base Address: 0x40040C00
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x0021000) ///< Base Address: 0x40041000
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x0021400) ///< Base Address: 0x40041400
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x0021800) ///< Base Address: 0x40041800
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x0021C00) ///< Base Address: 0x40041C00
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CRL; ///< Control Register Low, offset: 0x00
+ __IO u32 CRH; ///< Control Register High, offset: 0x04
+ __IO u32 IDR; ///< Input Data Register, offset: 0x08
+ __IO u32 ODR; ///< Output Data Register, offset: 0x0C
+ __IO u32 BSRR; ///< Bit Set or Reset Register, offset: 0x10
+ __IO u32 BRR; ///< Bit Reset Register, offset: 0x14
+ __IO u32 LCKR; ///< Lock Register, offset: 0x18
+ __IO u32 DCR; ///< Pin Output Open Drain Config Register, offset: 0x1C
+ __IO u32 AFRL; ///< Port Multiplexing Function Low Register, offset: 0x20
+ __IO u32 AFRH; ///< Port Multiplexing Function High Register, offset: 0x24
+} GPIO_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef*) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef*) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef*) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef*) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef*) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef*) GPIOH_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Common Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+#define GPIO_CNF_MODE_AIN 0x00UL //0b0000, ///< Analog input
+#define GPIO_CNF_MODE_FLOATING 0x04UL //0b0100, ///< Floating input
+#define GPIO_CNF_MODE_INPUPD 0x08UL //0b1000, ///< Pull up and down input
+#define GPIO_CNF_MODE_INRESEVED 0x0CUL //0b1100, ///< Reseved input mode
+#define GPIO_CNF_MODE_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output default
+#define GPIO_CNF_MODE_OUT_OD 0x05UL //0b0101, ///< Universal open drain output default
+#define GPIO_CNF_MODE_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output default
+#define GPIO_CNF_MODE_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output default
+#define GPIO_CNF_MODE_50MHZ_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output 50MHZ
+#define GPIO_CNF_MODE_50MHZ_OUT_OD 0x05UL //0b0101, ///< Universal open drain output 50MHZ
+#define GPIO_CNF_MODE_50MHZ_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output 50MHZ
+#define GPIO_CNF_MODE_50MHZ_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output 50MHZ
+#define GPIO_CNF_MODE_20MHZ_OUT_PP 0x02UL //0b0010, ///< Universal push-pull output 20MHZ
+#define GPIO_CNF_MODE_20MHZ_OUT_OD 0x06UL //0b0110, ///< Universal open drain output 20MHZ
+#define GPIO_CNF_MODE_20MHZ_AF_PP 0x0AUL //0b1010, ///< Multiplex push-pull output 20MHZ
+#define GPIO_CNF_MODE_20MHZ_AF_OD 0x0EUL //0b1110 ///< Multiplex open drain output 20MHZ
+#define GPIO_CNF_MODE_10MHZ_OUT_PP 0x03UL //0b0011, ///< Universal push-pull output 10MHZ
+#define GPIO_CNF_MODE_10MHZ_OUT_OD 0x07UL //0b0111, ///< Universal open drain output 10MHZ
+#define GPIO_CNF_MODE_10MHZ_AF_PP 0x0BUL //0b1011, ///< Multiplex push-pull output 10MHZ
+#define GPIO_CNF_MODE_10MHZ_AF_OD 0x0FUL //0b1111 ///< Multiplex open drain output 10MHZ
+#define GPIO_CNF_MODE_MASK 0x0FUL //0b1111
+
+#define GPIO_CRL_CNF_MODE_0_Pos (0) // ///< Analog input
+#define GPIO_CRL_CNF_MODE_1_Pos (4) // ///< Floating input
+#define GPIO_CRL_CNF_MODE_2_Pos (8) // ///< Pull up and down input
+#define GPIO_CRL_CNF_MODE_3_Pos (12) // ///< Reseved input mode
+#define GPIO_CRL_CNF_MODE_4_Pos (16) // ///< Universal push-pull output default
+#define GPIO_CRL_CNF_MODE_5_Pos (20) // ///< Universal open drain output default
+#define GPIO_CRL_CNF_MODE_6_Pos (24) // ///< Multiplex push-pull output default
+#define GPIO_CRL_CNF_MODE_7_Pos (28) // ///< Multiplex open drain output default
+#define GPIO_CRH_CNF_MODE_8_Pos (0) // ///< Universal push-pull output 50MHZ
+#define GPIO_CRH_CNF_MODE_9_Pos (4) // ///< Universal open drain output 50MHZ
+#define GPIO_CRH_CNF_MODE_10_Pos (8) // ///< Multiplex push-pull output 50MHZ
+#define GPIO_CRH_CNF_MODE_11_Pos (12) // ///< Multiplex open drain output 50MHZ
+#define GPIO_CRH_CNF_MODE_12_Pos (16) // ///< Universal push-pull output 20MHZ
+#define GPIO_CRH_CNF_MODE_13_Pos (20) // ///< Universal open drain output 20MHZ
+#define GPIO_CRH_CNF_MODE_14_Pos (24) // ///< Multiplex push-pull output 20MHZ
+#define GPIO_CRH_CNF_MODE_15_Pos (28) // ///< Multiplex open drain output 20MHZ
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_CRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_CRL_MODE ((u32)0x33333333) ///< Port x mode bits
+
+#define GPIO_CRL_MODE0_Pos (0)
+#define GPIO_CRL_MODE0 (0x03U << GPIO_CRL_MODE0_Pos) ///< MODE0[1:0] bits (portx mode bits, pin 0)
+#define GPIO_CRL_MODE0_0 (0x01U << GPIO_CRL_MODE0_Pos) ///< Bit 0
+#define GPIO_CRL_MODE0_1 (0x02U << GPIO_CRL_MODE0_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF0_Pos (2)
+#define GPIO_CRL_CNF0 (0x03U << GPIO_CRL_CNF0_Pos) ///< CNF0[1:0] bits (portx configuration bits, pin 0)
+#define GPIO_CRL_CNF0_0 (0x01U << GPIO_CRL_CNF0_Pos) ///< Bit 0
+#define GPIO_CRL_CNF0_1 (0x02U << GPIO_CRL_CNF0_Pos) ///< Bit 1
+
+#define GPIO_CRL_MODE1_Pos (4)
+#define GPIO_CRL_MODE1 (0x03U << GPIO_CRL_MODE1_Pos) ///< MODE1[1:0] bits (portx mode bits, pin 1)
+#define GPIO_CRL_MODE1_0 (0x01U << GPIO_CRL_MODE1_Pos) ///< Bit 0
+#define GPIO_CRL_MODE1_1 (0x02U << GPIO_CRL_MODE1_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF1_Pos (6)
+#define GPIO_CRL_CNF1 (0x03U << GPIO_CRL_CNF1_Pos) ///< CNF1[1:0] bits (portx configuration bits, pin 1)
+#define GPIO_CRL_CNF1_0 (0x01U << GPIO_CRL_CNF1_Pos) ///< Bit 0
+#define GPIO_CRL_CNF1_1 (0x02U << GPIO_CRL_CNF1_Pos) ///< Bit 1
+
+#define GPIO_CRL_MODE2_Pos (8)
+#define GPIO_CRL_MODE2 (0x03U << GPIO_CRL_MODE2_Pos) ///< MODE2[1:0] bits (portx mode bits, pin 2)
+#define GPIO_CRL_MODE2_0 (0x01U << GPIO_CRL_MODE2_Pos) ///< Bit 0
+#define GPIO_CRL_MODE2_1 (0x02U << GPIO_CRL_MODE2_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF2_Pos (10)
+#define GPIO_CRL_CNF2 (0x03U << GPIO_CRL_CNF2_Pos) ///< CNF2[1:0] bits (portx configuration bits, pin 2)
+#define GPIO_CRL_CNF2_0 (0x01U << GPIO_CRL_CNF2_Pos) ///< Bit 0
+#define GPIO_CRL_CNF2_1 (0x02U << GPIO_CRL_CNF2_Pos) ///< Bit 1
+
+#define GPIO_CRL_MODE3_Pos (12)
+#define GPIO_CRL_MODE3 (0x03U << GPIO_CRL_MODE3_Pos) ///< MODE3[1:0] bits (portx mode bits, pin 3)
+#define GPIO_CRL_MODE3_0 (0x01U << GPIO_CRL_MODE3_Pos) ///< Bit 0
+#define GPIO_CRL_MODE3_1 (0x02U << GPIO_CRL_MODE3_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF3_Pos (14)
+#define GPIO_CRL_CNF3 (0x03U << GPIO_CRL_CNF3_Pos) ///< CNF3[1:0] bits (portx configuration bits, pin 3)
+#define GPIO_CRL_CNF3_0 (0x01U << GPIO_CRL_CNF3_Pos) ///< Bit 0
+#define GPIO_CRL_CNF3_1 (0x02U << GPIO_CRL_CNF3_Pos) ///< Bit 1
+
+
+#define GPIO_CRL_MODE4_Pos (16)
+#define GPIO_CRL_MODE4 (0x03U << GPIO_CRL_MODE4_Pos) ///< MODE4[1:0] bits (portx mode bits, pin 4)
+#define GPIO_CRL_MODE4_0 (0x01U << GPIO_CRL_MODE4_Pos) ///< Bit 0
+#define GPIO_CRL_MODE4_1 (0x02U << GPIO_CRL_MODE4_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF4_Pos (18)
+#define GPIO_CRL_CNF4 (0x03U << GPIO_CRL_CNF4_Pos) ///< CNF4[1:0] bits (portx configuration bits, pin 4)
+#define GPIO_CRL_CNF4_0 (0x01U << GPIO_CRL_CNF4_Pos) ///< Bit 0
+#define GPIO_CRL_CNF4_1 (0x02U << GPIO_CRL_CNF4_Pos) ///< Bit 1
+
+#define GPIO_CRL_MODE5_Pos (20)
+#define GPIO_CRL_MODE5 (0x03U << GPIO_CRL_MODE5_Pos) ///< MODE5[1:0] bits (portx mode bits, pin 5)
+#define GPIO_CRL_MODE5_0 (0x01U << GPIO_CRL_MODE5_Pos) ///< Bit 0
+#define GPIO_CRL_MODE5_1 (0x02U << GPIO_CRL_MODE5_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF5_Pos (22)
+#define GPIO_CRL_CNF5 (0x03U << GPIO_CRL_CNF5_Pos) ///< CNF5[1:0] bits (portx configuration bits, pin 5)
+#define GPIO_CRL_CNF5_0 (0x01U << GPIO_CRL_CNF5_Pos) ///< Bit 0
+#define GPIO_CRL_CNF5_1 (0x02U << GPIO_CRL_CNF5_Pos) ///< Bit 1
+
+#define GPIO_CRL_MODE6_Pos (24)
+#define GPIO_CRL_MODE6 (0x03U << GPIO_CRL_MODE6_Pos) ///< MODE6[1:0] bits (portx mode bits, pin 6)
+#define GPIO_CRL_MODE6_0 (0x01U << GPIO_CRL_MODE6_Pos) ///< Bit 0
+#define GPIO_CRL_MODE6_1 (0x02U << GPIO_CRL_MODE6_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF6_Pos (26)
+#define GPIO_CRL_CNF6 (0x03U << GPIO_CRL_CNF6_Pos) ///< CNF6[1:0] bits (portx configuration bits, pin 6)
+#define GPIO_CRL_CNF6_0 (0x01U << GPIO_CRL_CNF6_Pos) ///< Bit 0
+#define GPIO_CRL_CNF6_1 (0x02U << GPIO_CRL_CNF6_Pos) ///< Bit 1
+
+#define GPIO_CRL_MODE7_Pos (28)
+#define GPIO_CRL_MODE7 (0x03U << GPIO_CRL_MODE7_Pos) ///< MODE7[1:0] bits (portx mode bits, pin 7)
+#define GPIO_CRL_MODE7_0 (0x01U << GPIO_CRL_MODE7_Pos) ///< Bit 0
+#define GPIO_CRL_MODE7_1 (0x02U << GPIO_CRL_MODE7_Pos) ///< Bit 1
+
+#define GPIO_CRL_CNF7_Pos (30)
+#define GPIO_CRL_CNF7 (0x03U << GPIO_CRL_CNF7_Pos) ///< CNF7[1:0] bits (portx configuration bits, pin 7)
+#define GPIO_CRL_CNF7_0 (0x01U << GPIO_CRL_CNF7_Pos) ///< Bit 0
+#define GPIO_CRL_CNF7_1 (0x02U << GPIO_CRL_CNF7_Pos) ///< Bit 1
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_CRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_CRH_MODE ((u32)0x33333333) ///< Port x mode bits
+
+#define GPIO_CRH_MODE8_Pos (0)
+#define GPIO_CRH_MODE8 (0x03U << GPIO_CRH_MODE8_Pos) ///< MODE8[1:0] bits (portx mode bits, pin 0)
+#define GPIO_CRH_MODE8_0 (0x01U << GPIO_CRH_MODE8_Pos) ///< Bit 0
+#define GPIO_CRH_MODE8_1 (0x02U << GPIO_CRH_MODE8_Pos) ///< Bit 1
+#define GPIO_CRH_CNF8_Pos (2)
+#define GPIO_CRH_CNF8 (0x03U << GPIO_CRH_CNF8_Pos) ///< CNF8[1:0] bits (portx configuration bits, pin 0)
+#define GPIO_CRH_CNF8_0 (0x01U << GPIO_CRH_CNF8_Pos) ///< Bit 0
+#define GPIO_CRH_CNF8_1 (0x02U << GPIO_CRH_CNF8_Pos) ///< Bit 1
+#define GPIO_CRH_MODE9_Pos (4)
+#define GPIO_CRH_MODE9 (0x03U << GPIO_CRH_MODE9_Pos) ///< MODE9[1:0] bits (portx mode bits, pin 1)
+#define GPIO_CRH_MODE9_0 (0x01U << GPIO_CRH_MODE9_Pos) ///< Bit 0
+#define GPIO_CRH_MODE9_1 (0x02U << GPIO_CRH_MODE9_Pos) ///< Bit 1
+#define GPIO_CRH_CNF9_Pos (6)
+#define GPIO_CRH_CNF9 (0x03U << GPIO_CRH_CNF9_Pos) ///< CNF9[1:0] bits (portx configuration bits, pin 1)
+#define GPIO_CRH_CNF9_0 (0x01U << GPIO_CRH_CNF9_Pos) ///< Bit 0
+#define GPIO_CRH_CNF9_1 (0x02U << GPIO_CRH_CNF9_Pos) ///< Bit 1
+#define GPIO_CRH_MODE10_Pos (8)
+#define GPIO_CRH_MODE10 (0x03U << GPIO_CRH_MODE10_Pos) ///< MODE10[1:0] bits (portx mode bits, pin 2)
+#define GPIO_CRH_MODE10_0 (0x01U << GPIO_CRH_MODE10_Pos) ///< Bit 0
+#define GPIO_CRH_MODE10_1 (0x02U << GPIO_CRH_MODE10_Pos) ///< Bit 1
+#define GPIO_CRH_CNF10_Pos (10)
+#define GPIO_CRH_CNF10 (0x03U << GPIO_CRH_CNF10_Pos) ///< CNF10[1:0] bits (portx configuration bits, pin 2)
+#define GPIO_CRH_CNF10_0 (0x01U << GPIO_CRH_CNF10_Pos) ///< Bit 0
+#define GPIO_CRH_CNF10_1 (0x02U << GPIO_CRH_CNF10_Pos) ///< Bit 1
+#define GPIO_CRH_MODE11_Pos (12)
+#define GPIO_CRH_MODE11 (0x03U << GPIO_CRH_MODE11_Pos) ///< MODE11[1:0] bits (portx mode bits, pin 3)
+#define GPIO_CRH_MODE11_0 (0x01U << GPIO_CRH_MODE11_Pos) ///< Bit 0
+#define GPIO_CRH_MODE11_1 (0x02U << GPIO_CRH_MODE11_Pos) ///< Bit 1
+#define GPIO_CRH_CNF11_Pos (14)
+#define GPIO_CRH_CNF11 (0x03U << GPIO_CRH_CNF11_Pos) ///< CNF11[1:0] bits (portx configuration bits, pin 3)
+#define GPIO_CRH_CNF11_0 (0x01U << GPIO_CRH_CNF11_Pos) ///< Bit 0
+#define GPIO_CRH_CNF11_1 (0x02U << GPIO_CRH_CNF11_Pos) ///< Bit 1
+#define GPIO_CRH_MODE12_Pos (16)
+#define GPIO_CRH_MODE12 (0x03U << GPIO_CRH_MODE12_Pos) ///< MODE12[1:0] bits (portx mode bits, pin 4)
+#define GPIO_CRH_MODE12_0 (0x01U << GPIO_CRH_MODE12_Pos) ///< Bit 0
+#define GPIO_CRH_MODE12_1 (0x02U << GPIO_CRH_MODE12_Pos) ///< Bit 1
+#define GPIO_CRH_CNF12_Pos (18)
+#define GPIO_CRH_CNF12 (0x03U << GPIO_CRH_CNF12_Pos) ///< CNF12[1:0] bits (portx configuration bits, pin 4)
+#define GPIO_CRH_CNF12_0 (0x01U << GPIO_CRH_CNF12_Pos) ///< Bit 0
+#define GPIO_CRH_CNF12_1 (0x02U << GPIO_CRH_CNF12_Pos) ///< Bit 1
+#define GPIO_CRH_MODE13_Pos (20)
+#define GPIO_CRH_MODE13 (0x03U << GPIO_CRH_MODE13_Pos) ///< MODE13[1:0] bits (portx mode bits, pin 5)
+#define GPIO_CRH_MODE13_0 (0x01U << GPIO_CRH_MODE13_Pos) ///< Bit 0
+#define GPIO_CRH_MODE13_1 (0x02U << GPIO_CRH_MODE13_Pos) ///< Bit 1
+#define GPIO_CRH_CNF13_Pos (22)
+#define GPIO_CRH_CNF13 (0x03U << GPIO_CRH_CNF13_Pos) ///< CNF13[1:0] bits (portx configuration bits, pin 5)
+#define GPIO_CRH_CNF13_0 (0x01U << GPIO_CRH_CNF13_Pos) ///< Bit 0
+#define GPIO_CRH_CNF13_1 (0x02U << GPIO_CRH_CNF13_Pos) ///< Bit 1
+#define GPIO_CRH_MODE14_Pos (24)
+#define GPIO_CRH_MODE14 (0x03U << GPIO_CRH_MODE14_Pos) ///< MODE14[1:0] bits (portx mode bits, pin 6)
+#define GPIO_CRH_MODE14_0 (0x01U << GPIO_CRH_MODE14_Pos) ///< Bit 0
+#define GPIO_CRH_MODE14_1 (0x02U << GPIO_CRH_MODE14_Pos) ///< Bit 1
+#define GPIO_CRH_CNF14_Pos (26)
+#define GPIO_CRH_CNF14 (0x03U << GPIO_CRH_CNF14_Pos) ///< CNF14[1:0] bits (portx configuration bits, pin 6)
+#define GPIO_CRH_CNF14_0 (0x01U << GPIO_CRH_CNF14_Pos) ///< Bit 0
+#define GPIO_CRH_CNF14_1 (0x02U << GPIO_CRH_CNF14_Pos) ///< Bit 1
+#define GPIO_CRH_MODE15_Pos (28)
+#define GPIO_CRH_MODE15 (0x03U << GPIO_CRH_MODE15_Pos) ///< MODE15[1:0] bits (portx mode bits, pin 7)
+#define GPIO_CRH_MODE15_0 (0x01U << GPIO_CRH_MODE15_Pos) ///< Bit 0
+#define GPIO_CRH_MODE15_1 (0x02U << GPIO_CRH_MODE15_Pos) ///< Bit 1
+#define GPIO_CRH_CNF15_Pos (30)
+#define GPIO_CRH_CNF15 (0x03U << GPIO_CRH_CNF15_Pos) ///< CNF15[1:0] bits (portx configuration bits, pin 7)
+#define GPIO_CRH_CNF15_0 (0x01U << GPIO_CRH_CNF15_Pos) ///< Bit 0
+#define GPIO_CRH_CNF15_1 (0x02U << GPIO_CRH_CNF15_Pos) ///< Bit 1
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_IDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_IDR_DATA_Pos (0)
+#define GPIO_IDR_DATA (0xFFFFU << GPIO_IDR_DATA_Pos) ///< Port input data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_IDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_IDR_IDR0_Pos (0)
+#define GPIO_IDR_IDR0 (0x01U << GPIO_IDR_IDR0_Pos) ///< Portx Set bit 0
+#define GPIO_IDR_IDR1_Pos (1)
+#define GPIO_IDR_IDR1 (0x01U << GPIO_IDR_IDR1_Pos) ///< Portx Set bit 1
+#define GPIO_IDR_IDR2_Pos (2)
+#define GPIO_IDR_IDR2 (0x01U << GPIO_IDR_IDR2_Pos) ///< Portx Set bit 2
+#define GPIO_IDR_IDR3_Pos (3)
+#define GPIO_IDR_IDR3 (0x01U << GPIO_IDR_IDR3_Pos) ///< Portx Set bit 3
+#define GPIO_IDR_IDR4_Pos (4)
+#define GPIO_IDR_IDR4 (0x01U << GPIO_IDR_IDR4_Pos) ///< Portx Set bit 4
+#define GPIO_IDR_IDR5_Pos (5)
+#define GPIO_IDR_IDR5 (0x01U << GPIO_IDR_IDR5_Pos) ///< Portx Set bit 5
+#define GPIO_IDR_IDR6_Pos (6)
+#define GPIO_IDR_IDR6 (0x01U << GPIO_IDR_IDR6_Pos) ///< Portx Set bit 6
+#define GPIO_IDR_IDR7_Pos (7)
+#define GPIO_IDR_IDR7 (0x01U << GPIO_IDR_IDR7_Pos) ///< Portx Set bit 7
+#define GPIO_IDR_IDR8_Pos (8)
+#define GPIO_IDR_IDR8 (0x01U << GPIO_IDR_IDR8_Pos) ///< Portx Set bit 8
+#define GPIO_IDR_IDR9_Pos (9)
+#define GPIO_IDR_IDR9 (0x01U << GPIO_IDR_IDR9_Pos) ///< Portx Set bit 9
+#define GPIO_IDR_IDR10_Pos (10)
+#define GPIO_IDR_IDR10 (0x01U << GPIO_IDR_IDR10_Pos) ///< Portx Set bit 10
+#define GPIO_IDR_IDR11_Pos (11)
+#define GPIO_IDR_IDR11 (0x01U << GPIO_IDR_IDR11_Pos) ///< Portx Set bit 11
+#define GPIO_IDR_IDR12_Pos (12)
+#define GPIO_IDR_IDR12 (0x01U << GPIO_IDR_IDR12_Pos) ///< Portx Set bit 12
+#define GPIO_IDR_IDR13_Pos (13)
+#define GPIO_IDR_IDR13 (0x01U << GPIO_IDR_IDR13_Pos) ///< Portx Set bit 13
+#define GPIO_IDR_IDR14_Pos (14)
+#define GPIO_IDR_IDR14 (0x01U << GPIO_IDR_IDR14_Pos) ///< Portx Set bit 14
+#define GPIO_IDR_IDR15_Pos (15)
+#define GPIO_IDR_IDR15 (0x01U << GPIO_IDR_IDR15_Pos) ///< Portx Set bit 15
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_ODR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_ODR_DATA_Pos (0)
+#define GPIO_ODR_DATA (0xFFFF << GPIO_ODR_DATA_Pos) ///< Port output data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_ODR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_ODR_ODR0_Pos (0)
+#define GPIO_ODR_ODR0 (0x01U << GPIO_ODR_ODR0_Pos) ///< Portx Set bit 0
+#define GPIO_ODR_ODR1_Pos (1)
+#define GPIO_ODR_ODR1 (0x01U << GPIO_ODR_ODR1_Pos) ///< Portx Set bit 1
+#define GPIO_ODR_ODR2_Pos (2)
+#define GPIO_ODR_ODR2 (0x01U << GPIO_ODR_ODR2_Pos) ///< Portx Set bit 2
+#define GPIO_ODR_ODR3_Pos (3)
+#define GPIO_ODR_ODR3 (0x01U << GPIO_ODR_ODR3_Pos) ///< Portx Set bit 3
+#define GPIO_ODR_ODR4_Pos (4)
+#define GPIO_ODR_ODR4 (0x01U << GPIO_ODR_ODR4_Pos) ///< Portx Set bit 4
+#define GPIO_ODR_ODR5_Pos (5)
+#define GPIO_ODR_ODR5 (0x01U << GPIO_ODR_ODR5_Pos) ///< Portx Set bit 5
+#define GPIO_ODR_ODR6_Pos (6)
+#define GPIO_ODR_ODR6 (0x01U << GPIO_ODR_ODR6_Pos) ///< Portx Set bit 6
+#define GPIO_ODR_ODR7_Pos (7)
+#define GPIO_ODR_ODR7 (0x01U << GPIO_ODR_ODR7_Pos) ///< Portx Set bit 7
+#define GPIO_ODR_ODR8_Pos (8)
+#define GPIO_ODR_ODR8 (0x01U << GPIO_ODR_ODR8_Pos) ///< Portx Set bit 8
+#define GPIO_ODR_ODR9_Pos (9)
+#define GPIO_ODR_ODR9 (0x01U << GPIO_ODR_ODR9_Pos) ///< Portx Set bit 9
+#define GPIO_ODR_ODR10_Pos (10)
+#define GPIO_ODR_ODR10 (0x01U << GPIO_ODR_ODR10_Pos) ///< Portx Set bit 10
+#define GPIO_ODR_ODR11_Pos (11)
+#define GPIO_ODR_ODR11 (0x01U << GPIO_ODR_ODR11_Pos) ///< Portx Set bit 11
+#define GPIO_ODR_ODR12_Pos (12)
+#define GPIO_ODR_ODR12 (0x01U << GPIO_ODR_ODR12_Pos) ///< Portx Set bit 12
+#define GPIO_ODR_ODR13_Pos (13)
+#define GPIO_ODR_ODR13 (0x01U << GPIO_ODR_ODR13_Pos) ///< Portx Set bit 13
+#define GPIO_ODR_ODR14_Pos (14)
+#define GPIO_ODR_ODR14 (0x01U << GPIO_ODR_ODR14_Pos) ///< Portx Set bit 14
+#define GPIO_ODR_ODR15_Pos (15)
+#define GPIO_ODR_ODR15 (0x01U << GPIO_ODR_ODR15_Pos) ///< Portx Set bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BSRR_BS_Pos (0)
+#define GPIO_BSRR_BS (0xFFFFU << GPIO_BSRR_BS_Pos) ///< Portx Reset
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BSRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BSRR_BS0_Pos (0)
+#define GPIO_BSRR_BS0 (0x01U << GPIO_BSRR_BS0_Pos) ///< Portx Set bit 0
+#define GPIO_BSRR_BS1_Pos (1)
+#define GPIO_BSRR_BS1 (0x01U << GPIO_BSRR_BS1_Pos) ///< Portx Set bit 1
+#define GPIO_BSRR_BS2_Pos (2)
+#define GPIO_BSRR_BS2 (0x01U << GPIO_BSRR_BS2_Pos) ///< Portx Set bit 2
+#define GPIO_BSRR_BS3_Pos (3)
+#define GPIO_BSRR_BS3 (0x01U << GPIO_BSRR_BS3_Pos) ///< Portx Set bit 3
+#define GPIO_BSRR_BS4_Pos (4)
+#define GPIO_BSRR_BS4 (0x01U << GPIO_BSRR_BS4_Pos) ///< Portx Set bit 4
+#define GPIO_BSRR_BS5_Pos (5)
+#define GPIO_BSRR_BS5 (0x01U << GPIO_BSRR_BS5_Pos) ///< Portx Set bit 5
+#define GPIO_BSRR_BS6_Pos (6)
+#define GPIO_BSRR_BS6 (0x01U << GPIO_BSRR_BS6_Pos) ///< Portx Set bit 6
+#define GPIO_BSRR_BS7_Pos (7)
+#define GPIO_BSRR_BS7 (0x01U << GPIO_BSRR_BS7_Pos) ///< Portx Set bit 7
+#define GPIO_BSRR_BS8_Pos (8)
+#define GPIO_BSRR_BS8 (0x01U << GPIO_BSRR_BS8_Pos) ///< Portx Set bit 8
+#define GPIO_BSRR_BS9_Pos (9)
+#define GPIO_BSRR_BS9 (0x01U << GPIO_BSRR_BS9_Pos) ///< Portx Set bit 9
+#define GPIO_BSRR_BS10_Pos (10)
+#define GPIO_BSRR_BS10 (0x01U << GPIO_BSRR_BS10_Pos) ///< Portx Set bit 10
+#define GPIO_BSRR_BS11_Pos (11)
+#define GPIO_BSRR_BS11 (0x01U << GPIO_BSRR_BS11_Pos) ///< Portx Set bit 11
+#define GPIO_BSRR_BS12_Pos (12)
+#define GPIO_BSRR_BS12 (0x01U << GPIO_BSRR_BS12_Pos) ///< Portx Set bit 12
+#define GPIO_BSRR_BS13_Pos (13)
+#define GPIO_BSRR_BS13 (0x01U << GPIO_BSRR_BS13_Pos) ///< Portx Set bit 13
+#define GPIO_BSRR_BS14_Pos (14)
+#define GPIO_BSRR_BS14 (0x01U << GPIO_BSRR_BS14_Pos) ///< Portx Set bit 14
+#define GPIO_BSRR_BS15_Pos (15)
+#define GPIO_BSRR_BS15 (0x01U << GPIO_BSRR_BS15_Pos) ///< Portx Set bit 15
+
+#define GPIO_BSRR_BR0_Pos (16)
+#define GPIO_BSRR_BR0 (0x01U << GPIO_BSRR_BR0_Pos) ///< Portx Reset bit 0
+#define GPIO_BSRR_BR1_Pos (17)
+#define GPIO_BSRR_BR1 (0x01U << GPIO_BSRR_BR1_Pos) ///< Portx Reset bit 1
+#define GPIO_BSRR_BR2_Pos (18)
+#define GPIO_BSRR_BR2 (0x01U << GPIO_BSRR_BR2_Pos) ///< Portx Reset bit 2
+#define GPIO_BSRR_BR3_Pos (19)
+#define GPIO_BSRR_BR3 (0x01U << GPIO_BSRR_BR3_Pos) ///< Portx Reset bit 3
+#define GPIO_BSRR_BR4_Pos (20)
+#define GPIO_BSRR_BR4 (0x01U << GPIO_BSRR_BR4_Pos) ///< Portx Reset bit 4
+#define GPIO_BSRR_BR5_Pos (21)
+#define GPIO_BSRR_BR5 (0x01U << GPIO_BSRR_BR5_Pos) ///< Portx Reset bit 5
+#define GPIO_BSRR_BR6_Pos (22)
+#define GPIO_BSRR_BR6 (0x01U << GPIO_BSRR_BR6_Pos) ///< Portx Reset bit 6
+#define GPIO_BSRR_BR7_Pos (23)
+#define GPIO_BSRR_BR7 (0x01U << GPIO_BSRR_BR7_Pos) ///< Portx Reset bit 7
+#define GPIO_BSRR_BR8_Pos (24)
+#define GPIO_BSRR_BR8 (0x01U << GPIO_BSRR_BR8_Pos) ///< Portx Reset bit 8
+#define GPIO_BSRR_BR9_Pos (25)
+#define GPIO_BSRR_BR9 (0x01U << GPIO_BSRR_BR9_Pos) ///< Portx Reset bit 9
+#define GPIO_BSRR_BR10_Pos (26)
+#define GPIO_BSRR_BR10 (0x01U << GPIO_BSRR_BR10_Pos) ///< Portx Reset bit 10
+#define GPIO_BSRR_BR11_Pos (27)
+#define GPIO_BSRR_BR11 (0x01U << GPIO_BSRR_BR11_Pos) ///< Portx Reset bit 11
+#define GPIO_BSRR_BR12_Pos (28)
+#define GPIO_BSRR_BR12 (0x01U << GPIO_BSRR_BR12_Pos) ///< Portx Reset bit 12
+#define GPIO_BSRR_BR13_Pos (29)
+#define GPIO_BSRR_BR13 (0x01U << GPIO_BSRR_BR13_Pos) ///< Portx Reset bit 13
+#define GPIO_BSRR_BR14_Pos (30)
+#define GPIO_BSRR_BR14 (0x01U << GPIO_BSRR_BR14_Pos) ///< Portx Reset bit 14
+#define GPIO_BSRR_BR15_Pos (31)
+#define GPIO_BSRR_BR15 (0x01U << GPIO_BSRR_BR15_Pos) ///< Portx Reset bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BRR_BR_Pos (0)
+#define GPIO_BRR_BR (0xFFFFU << GPIO_BRR_BR_Pos) ///< Portx Reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BRR_BR0_Pos (0)
+#define GPIO_BRR_BR0 (0x01U << GPIO_BRR_BR0_Pos) ///< Portx Set bit 0
+#define GPIO_BRR_BR1_Pos (1)
+#define GPIO_BRR_BR1 (0x01U << GPIO_BRR_BR1_Pos) ///< Portx Set bit 1
+#define GPIO_BRR_BR2_Pos (2)
+#define GPIO_BRR_BR2 (0x01U << GPIO_BRR_BR2_Pos) ///< Portx Set bit 2
+#define GPIO_BRR_BR3_Pos (3)
+#define GPIO_BRR_BR3 (0x01U << GPIO_BRR_BR3_Pos) ///< Portx Set bit 3
+#define GPIO_BRR_BR4_Pos (4)
+#define GPIO_BRR_BR4 (0x01U << GPIO_BRR_BR4_Pos) ///< Portx Set bit 4
+#define GPIO_BRR_BR5_Pos (5)
+#define GPIO_BRR_BR5 (0x01U << GPIO_BRR_BR5_Pos) ///< Portx Set bit 5
+#define GPIO_BRR_BR6_Pos (6)
+#define GPIO_BRR_BR6 (0x01U << GPIO_BRR_BR6_Pos) ///< Portx Set bit 6
+#define GPIO_BRR_BR7_Pos (7)
+#define GPIO_BRR_BR7 (0x01U << GPIO_BRR_BR7_Pos) ///< Portx Set bit 7
+#define GPIO_BRR_BR8_Pos (8)
+#define GPIO_BRR_BR8 (0x01U << GPIO_BRR_BR8_Pos) ///< Portx Set bit 8
+#define GPIO_BRR_BR9_Pos (9)
+#define GPIO_BRR_BR9 (0x01U << GPIO_BRR_BR9_Pos) ///< Portx Set bit 9
+#define GPIO_BRR_BR10_Pos (10)
+#define GPIO_BRR_BR10 (0x01U << GPIO_BRR_BR10_Pos) ///< Portx Set bit 10
+#define GPIO_BRR_BR11_Pos (11)
+#define GPIO_BRR_BR11 (0x01U << GPIO_BRR_BR11_Pos) ///< Portx Set bit 11
+#define GPIO_BRR_BR12_Pos (12)
+#define GPIO_BRR_BR12 (0x01U << GPIO_BRR_BR12_Pos) ///< Portx Set bit 12
+#define GPIO_BRR_BR13_Pos (13)
+#define GPIO_BRR_BR13 (0x01U << GPIO_BRR_BR13_Pos) ///< Portx Set bit 13
+#define GPIO_BRR_BR14_Pos (14)
+#define GPIO_BRR_BR14 (0x01U << GPIO_BRR_BR14_Pos) ///< Portx Set bit 14
+#define GPIO_BRR_BR15_Pos (15)
+#define GPIO_BRR_BR15 (0x01U << GPIO_BRR_BR15_Pos) ///< Portx Set bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_LCKR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_LCKR_LCK_Pos (0)
+#define GPIO_LCKR_LCK (0xFFFFU << GPIO_LCKR_LCK_Pos) ///< Portx Lock
+#define GPIO_LCKR_LCKK_Pos (16)
+#define GPIO_LCKR_LCKK (0x01U << GPIO_LCKR_LCKK_Pos) ///< Lock key
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_LCKR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_LCKR_LCK0_Pos (0)
+#define GPIO_LCKR_LCK0 (0x01U << GPIO_LCKR_LCK0_Pos) ///< Portx Set bit 0
+#define GPIO_LCKR_LCK1_Pos (1)
+#define GPIO_LCKR_LCK1 (0x01U << GPIO_LCKR_LCK1_Pos) ///< Portx Set bit 1
+#define GPIO_LCKR_LCK2_Pos (2)
+#define GPIO_LCKR_LCK2 (0x01U << GPIO_LCKR_LCK2_Pos) ///< Portx Set bit 2
+#define GPIO_LCKR_LCK3_Pos (3)
+#define GPIO_LCKR_LCK3 (0x01U << GPIO_LCKR_LCK3_Pos) ///< Portx Set bit 3
+#define GPIO_LCKR_LCK4_Pos (4)
+#define GPIO_LCKR_LCK4 (0x01U << GPIO_LCKR_LCK4_Pos) ///< Portx Set bit 4
+#define GPIO_LCKR_LCK5_Pos (5)
+#define GPIO_LCKR_LCK5 (0x01U << GPIO_LCKR_LCK5_Pos) ///< Portx Set bit 5
+#define GPIO_LCKR_LCK6_Pos (6)
+#define GPIO_LCKR_LCK6 (0x01U << GPIO_LCKR_LCK6_Pos) ///< Portx Set bit 6
+#define GPIO_LCKR_LCK7_Pos (7)
+#define GPIO_LCKR_LCK7 (0x01U << GPIO_LCKR_LCK7_Pos) ///< Portx Set bit 7
+#define GPIO_LCKR_LCK8_Pos (8)
+#define GPIO_LCKR_LCK8 (0x01U << GPIO_LCKR_LCK8_Pos) ///< Portx Set bit 8
+#define GPIO_LCKR_LCK9_Pos (9)
+#define GPIO_LCKR_LCK9 (0x01U << GPIO_LCKR_LCK9_Pos) ///< Portx Set bit 9
+#define GPIO_LCKR_LCK10_Pos (10)
+#define GPIO_LCKR_LCK10 (0x01U << GPIO_LCKR_LCK10_Pos) ///< Portx Set bit 10
+#define GPIO_LCKR_LCK11_Pos (11)
+#define GPIO_LCKR_LCK11 (0x01U << GPIO_LCKR_LCK11_Pos) ///< Portx Set bit 11
+#define GPIO_LCKR_LCK12_Pos (12)
+#define GPIO_LCKR_LCK12 (0x01U << GPIO_LCKR_LCK12_Pos) ///< Portx Set bit 12
+#define GPIO_LCKR_LCK13_Pos (13)
+#define GPIO_LCKR_LCK13 (0x01U << GPIO_LCKR_LCK13_Pos) ///< Portx Set bit 13
+#define GPIO_LCKR_LCK14_Pos (14)
+#define GPIO_LCKR_LCK14 (0x01U << GPIO_LCKR_LCK14_Pos) ///< Portx Set bit 14
+#define GPIO_LCKR_LCK15_Pos (15)
+#define GPIO_LCKR_LCK15 (0x01U << GPIO_LCKR_LCK15_Pos) ///< Portx Set bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_DCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_DCR_PX0_Pos (0)
+#define GPIO_DCR_PX0 (0x03U << GPIO_DCR_PX0_Pos) ///< PX0[1:0] bits (pinx configuration bits, pin 0)
+#define GPIO_DCR_PX0_MODE0 (0x00U << GPIO_DCR_PX0_Pos) ///< Mode = 0
+#define GPIO_DCR_PX0_MODE1 (0x01U << GPIO_DCR_PX0_Pos) ///< Mode = 1
+#define GPIO_DCR_PX0_MODE2 (0x02U << GPIO_DCR_PX0_Pos) ///< Mode = 2
+#define GPIO_DCR_PX0_MODE3 (0x03U << GPIO_DCR_PX0_Pos) ///< Mode = 3
+#define GPIO_DCR_PX1_Pos (2)
+#define GPIO_DCR_PX1 (0x03U << GPIO_DCR_PX1_Pos) ///< PX1[1:0] bits (pinx configuration bits, pin 1)
+#define GPIO_DCR_PX1_MODE0 (0x00U << GPIO_DCR_PX1_Pos) ///< Mode = 0
+#define GPIO_DCR_PX1_MODE1 (0x01U << GPIO_DCR_PX1_Pos) ///< Mode = 1
+#define GPIO_DCR_PX1_MODE2 (0x02U << GPIO_DCR_PX1_Pos) ///< Mode = 2
+#define GPIO_DCR_PX1_MODE3 (0x03U << GPIO_DCR_PX1_Pos) ///< Mode = 3
+#define GPIO_DCR_PX2_Pos (4)
+#define GPIO_DCR_PX2 (0x03U << GPIO_DCR_PX2_Pos) ///< PX2[1:0] bits (pinx configuration bits, pin 2)
+#define GPIO_DCR_PX2_MODE0 (0x00U << GPIO_DCR_PX2_Pos) ///< Mode = 0
+#define GPIO_DCR_PX2_MODE1 (0x01U << GPIO_DCR_PX2_Pos) ///< Mode = 1
+#define GPIO_DCR_PX2_MODE2 (0x02U << GPIO_DCR_PX2_Pos) ///< Mode = 2
+#define GPIO_DCR_PX2_MODE3 (0x03U << GPIO_DCR_PX2_Pos) ///< Mode = 3
+#define GPIO_DCR_PX3_Pos (6)
+#define GPIO_DCR_PX3 (0x03U << GPIO_DCR_PX3_Pos) ///< PX3[1:0] bits (pinx configuration bits, pin 3)
+#define GPIO_DCR_PX3_MODE0 (0x00U << GPIO_DCR_PX3_Pos) ///< Mode = 0
+#define GPIO_DCR_PX3_MODE1 (0x01U << GPIO_DCR_PX3_Pos) ///< Mode = 1
+#define GPIO_DCR_PX3_MODE2 (0x02U << GPIO_DCR_PX3_Pos) ///< Mode = 2
+#define GPIO_DCR_PX3_MODE3 (0x03U << GPIO_DCR_PX3_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX4_Pos (8)
+#define GPIO_DCR_PX4 (0x03U << GPIO_DCR_PX4_Pos) ///< PX4[1:0] bits (pinx configuration bits, pin 4)
+#define GPIO_DCR_PX4_MODE0 (0x00U << GPIO_DCR_PX4_Pos) ///< Mode = 0
+#define GPIO_DCR_PX4_MODE1 (0x01U << GPIO_DCR_PX4_Pos) ///< Mode = 1
+#define GPIO_DCR_PX4_MODE2 (0x02U << GPIO_DCR_PX4_Pos) ///< Mode = 2
+#define GPIO_DCR_PX4_MODE3 (0x03U << GPIO_DCR_PX4_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX5_Pos (10)
+#define GPIO_DCR_PX5 (0x03U << GPIO_DCR_PX5_Pos) ///< PX5[1:0] bits (pinx configuration bits, pin 5)
+#define GPIO_DCR_PX5_MODE0 (0x00U << GPIO_DCR_PX5_Pos) ///< Mode = 0
+#define GPIO_DCR_PX5_MODE1 (0x01U << GPIO_DCR_PX5_Pos) ///< Mode = 1
+#define GPIO_DCR_PX5_MODE2 (0x02U << GPIO_DCR_PX5_Pos) ///< Mode = 2
+#define GPIO_DCR_PX5_MODE3 (0x03U << GPIO_DCR_PX5_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX6_Pos (12)
+#define GPIO_DCR_PX6 (0x03U << GPIO_DCR_PX6_Pos) ///< PX6[1:0] bits (pinx configuration bits, pin 6)
+#define GPIO_DCR_PX6_MODE0 (0x00U << GPIO_DCR_PX6_Pos) ///< Mode = 0
+#define GPIO_DCR_PX6_MODE1 (0x01U << GPIO_DCR_PX6_Pos) ///< Mode = 1
+#define GPIO_DCR_PX6_MODE2 (0x02U << GPIO_DCR_PX6_Pos) ///< Mode = 2
+#define GPIO_DCR_PX6_MODE3 (0x03U << GPIO_DCR_PX6_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX7_Pos (14)
+#define GPIO_DCR_PX7 (0x03U << GPIO_DCR_PX7_Pos) ///< PX7[1:0] bits (pinx configuration bits, pin 7)
+#define GPIO_DCR_PX7_MODE0 (0x00U << GPIO_DCR_PX7_Pos) ///< Mode = 0
+#define GPIO_DCR_PX7_MODE1 (0x01U << GPIO_DCR_PX7_Pos) ///< Mode = 1
+#define GPIO_DCR_PX7_MODE2 (0x02U << GPIO_DCR_PX7_Pos) ///< Mode = 2
+#define GPIO_DCR_PX7_MODE3 (0x03U << GPIO_DCR_PX7_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX8_Pos (16)
+#define GPIO_DCR_PX8 (0x03U << GPIO_DCR_PX8_Pos) ///< PX8[1:0] bits (pinx configuration bits, pin 8)
+#define GPIO_DCR_PX8_MODE0 (0x00U << GPIO_DCR_PX8_Pos) ///< Mode = 0
+#define GPIO_DCR_PX8_MODE1 (0x01U << GPIO_DCR_PX8_Pos) ///< Mode = 1
+#define GPIO_DCR_PX8_MODE2 (0x02U << GPIO_DCR_PX8_Pos) ///< Mode = 2
+#define GPIO_DCR_PX8_MODE3 (0x03U << GPIO_DCR_PX8_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX9_Pos (18)
+#define GPIO_DCR_PX9 (0x03U << GPIO_DCR_PX9_Pos) ///< PX9[1:0] bits (pinx configuration bits, pin 9)
+#define GPIO_DCR_PX9_MODE0 (0x00U << GPIO_DCR_PX9_Pos) ///< Mode = 0
+#define GPIO_DCR_PX9_MODE1 (0x01U << GPIO_DCR_PX9_Pos) ///< Mode = 1
+#define GPIO_DCR_PX9_MODE2 (0x02U << GPIO_DCR_PX9_Pos) ///< Mode = 2
+#define GPIO_DCR_PX9_MODE3 (0x03U << GPIO_DCR_PX9_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX10_Pos (20)
+#define GPIO_DCR_PX10 (0x03U << GPIO_DCR_PX10_Pos) ///< PX10[1:0] bits (pinx configuration bits, pin 10)
+#define GPIO_DCR_PX10_MODE0 (0x00U << GPIO_DCR_PX10_Pos) ///< Mode = 0
+#define GPIO_DCR_PX10_MODE1 (0x01U << GPIO_DCR_PX10_Pos) ///< Mode = 1
+#define GPIO_DCR_PX10_MODE2 (0x02U << GPIO_DCR_PX10_Pos) ///< Mode = 2
+#define GPIO_DCR_PX10_MODE3 (0x03U << GPIO_DCR_PX10_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX11_Pos (22)
+#define GPIO_DCR_PX11 (0x03U << GPIO_DCR_PX11_Pos) ///< PX11[1:0] bits (pinx configuration bits, pin 11)
+#define GPIO_DCR_PX11_MODE0 (0x00U << GPIO_DCR_PX11_Pos) ///< Mode = 0
+#define GPIO_DCR_PX11_MODE1 (0x01U << GPIO_DCR_PX11_Pos) ///< Mode = 1
+#define GPIO_DCR_PX11_MODE2 (0x02U << GPIO_DCR_PX11_Pos) ///< Mode = 2
+#define GPIO_DCR_PX11_MODE3 (0x03U << GPIO_DCR_PX11_Pos) ///< Mode = 3
+#define GPIO_DCR_PX12_Pos (24)
+#define GPIO_DCR_PX12 (0x03U << GPIO_DCR_PX12_Pos) ///< PX12[1:0] bits (pinx configuration bits, pin 12)
+#define GPIO_DCR_PX12_MODE0 (0x00U << GPIO_DCR_PX12_Pos) ///< Mode = 0
+#define GPIO_DCR_PX12_MODE1 (0x01U << GPIO_DCR_PX12_Pos) ///< Mode = 1
+#define GPIO_DCR_PX12_MODE2 (0x02U << GPIO_DCR_PX12_Pos) ///< Mode = 2
+#define GPIO_DCR_PX12_MODE3 (0x03U << GPIO_DCR_PX12_Pos) ///< Mode = 3
+#define GPIO_DCR_PX13_Pos (26)
+#define GPIO_DCR_PX13 (0x03U << GPIO_DCR_PX13_Pos) ///< PX13[1:0] bits (pinx configuration bits, pin 13)
+#define GPIO_DCR_PX13_MODE0 (0x00U << GPIO_DCR_PX13_Pos) ///< Mode = 0
+#define GPIO_DCR_PX13_MODE1 (0x01U << GPIO_DCR_PX13_Pos) ///< Mode = 1
+#define GPIO_DCR_PX13_MODE2 (0x02U << GPIO_DCR_PX13_Pos) ///< Mode = 2
+#define GPIO_DCR_PX13_MODE3 (0x03U << GPIO_DCR_PX13_Pos) ///< Mode = 3
+
+#define GPIO_DCR_PX14_Pos (28)
+#define GPIO_DCR_PX14 (0x03U << GPIO_DCR_PX14_Pos) ///< PX14[1:0] bits (pinx configuration bits, pin 14)
+#define GPIO_DCR_PX14_MODE0 (0x00U << GPIO_DCR_PX14_Pos) ///< Mode = 0
+#define GPIO_DCR_PX14_MODE1 (0x01U << GPIO_DCR_PX14_Pos) ///< Mode = 1
+#define GPIO_DCR_PX14_MODE2 (0x02U << GPIO_DCR_PX14_Pos) ///< Mode = 2
+#define GPIO_DCR_PX14_MODE3 (0x03U << GPIO_DCR_PX14_Pos) ///< Mode = 3
+#define GPIO_DCR_PX15_Pos (30)
+#define GPIO_DCR_PX15 (0x03U << GPIO_DCR_PX15_Pos) ///< PX15[1:0] bits (pinx configuration bits, pin 15)
+#define GPIO_DCR_PX15_MODE0 (0x00U << GPIO_DCR_PX15_Pos) ///< Mode = 0
+#define GPIO_DCR_PX15_MODE1 (0x01U << GPIO_DCR_PX15_Pos) ///< Mode = 1
+#define GPIO_DCR_PX15_MODE2 (0x02U << GPIO_DCR_PX15_Pos) ///< Mode = 2
+#define GPIO_DCR_PX15_MODE3 (0x03U << GPIO_DCR_PX15_Pos) ///< Mode = 3
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_AFRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_AFRL_AFR0_Pos (0)
+#define GPIO_AFRL_AFR0 (0x0FU << GPIO_AFRL_AFR0_Pos) ///< Multiplexing function selection for bit 0 of portx
+#define GPIO_AFRL_AFR1_Pos (4)
+#define GPIO_AFRL_AFR1 (0x0FU << GPIO_AFRL_AFR1_Pos) ///< Multiplexing function selection for bit 1 of portx
+#define GPIO_AFRL_AFR2_Pos (8)
+#define GPIO_AFRL_AFR2 (0x0FU << GPIO_AFRL_AFR2_Pos) ///< Multiplexing function selection for bit 2 of portx
+#define GPIO_AFRL_AFR3_Pos (12)
+#define GPIO_AFRL_AFR3 (0x0FU << GPIO_AFRL_AFR3_Pos) ///< Multiplexing function selection for bit 3 of portx
+#define GPIO_AFRL_AFR4_Pos (16)
+#define GPIO_AFRL_AFR4 (0x0FU << GPIO_AFRL_AFR4_Pos) ///< Multiplexing function selection for bit 4 of portx
+#define GPIO_AFRL_AFR5_Pos (20)
+#define GPIO_AFRL_AFR5 (0x0FU << GPIO_AFRL_AFR5_Pos) ///< Multiplexing function selection for bit 5 of portx
+#define GPIO_AFRL_AFR6_Pos (24)
+#define GPIO_AFRL_AFR6 (0x0FU << GPIO_AFRL_AFR6_Pos) ///< Multiplexing function selection for bit 6 of portx
+#define GPIO_AFRL_AFR7_Pos (28)
+#define GPIO_AFRL_AFR7 (0x0FU << GPIO_AFRL_AFR7_Pos) ///< Multiplexing function selection for bit 7 of portx
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_AFRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_AFRH_AFR8_Pos (0)
+#define GPIO_AFRH_AFR8 (0x0FU << GPIO_AFRH_AFR8_Pos) ///< Multiplexing function selection for bit 8 of portx
+#define GPIO_AFRH_AFR9_Pos (4)
+#define GPIO_AFRH_AFR9 (0x0FU << GPIO_AFRH_AFR9_Pos) ///< Multiplexing function selection for bit 9 of portx
+#define GPIO_AFRH_AFR10_Pos (8)
+#define GPIO_AFRH_AFR10 (0x0FU << GPIO_AFRH_AFR10_Pos) ///< Multiplexing function selection for bit 10 of portx
+#define GPIO_AFRH_AFR11_Pos (12)
+#define GPIO_AFRH_AFR11 (0x0FU << GPIO_AFRH_AFR11_Pos) ///< Multiplexing function selection for bit 11 of portx
+#define GPIO_AFRH_AFR12_Pos (16)
+#define GPIO_AFRH_AFR12 (0x0FU << GPIO_AFRH_AFR12_Pos) ///< Multiplexing function selection for bit 12 of portx
+#define GPIO_AFRH_AFR13_Pos (20)
+#define GPIO_AFRH_AFR13 (0x0FU << GPIO_AFRH_AFR13_Pos) ///< Multiplexing function selection for bit 13 of portx
+#define GPIO_AFRH_AFR14_Pos (24)
+#define GPIO_AFRH_AFR14 (0x0FU << GPIO_AFRH_AFR14_Pos) ///< Multiplexing function selection for bit 14 of portx
+#define GPIO_AFRH_AFR15_Pos (28)
+#define GPIO_AFRH_AFR15 (0x0FU << GPIO_AFRH_AFR15_Pos) ///< Multiplexing function selection for bit 15 of portx
+#define GPIO_AF_MODEMASK (0x0FU) ///< Mode = 0
+#define GPIO_AF_MODE0 (0x00U) ///< Mode = 0
+#define GPIO_AF_MODE1 (0x01U) ///< Mode = 1
+#define GPIO_AF_MODE2 (0x02U) ///< Mode = 2
+#define GPIO_AF_MODE3 (0x03U) ///< Mode = 3
+#define GPIO_AF_MODE4 (0x04U) ///< Mode = 4
+#define GPIO_AF_MODE5 (0x05U) ///< Mode = 5
+#define GPIO_AF_MODE6 (0x06U) ///< Mode = 6
+#define GPIO_AF_MODE7 (0x07U) ///< Mode = 7
+#define GPIO_AF_MODE8 (0x08U) ///< Mode = 8
+#define GPIO_AF_MODE9 (0x09U) ///< Mode = 9
+#define GPIO_AF_MODE10 (0x0AU) ///< Mode = 10
+#define GPIO_AF_MODE11 (0x0BU) ///< Mode = 11
+#define GPIO_AF_MODE12 (0x0CU) ///< Mode = 12
+#define GPIO_AF_MODE13 (0x0DU) ///< Mode = 13
+#define GPIO_AF_MODE14 (0x0EU) ///< Mode = 14
+#define GPIO_AF_MODE15 (0x0FU) ///< Mode = 15
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
new file mode 100644
index 00000000..e12f107e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
@@ -0,0 +1,635 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_i2c.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_I2C_H
+#define __REG_I2C_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) ///< Base Address: 0x40005400
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) ///< Base Address: 0x40005800
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+#undef USENCOMBINEREGISTER
+#undef USENNEWREGISTER
+#undef USENOLDREGISTER
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+typedef struct {
+ union {
+ __IO u32 CR; ///< Control Register offset: 0x00
+ __IO u32 IC_CON;
+ };
+ union {
+ __IO u32 TAR; ///< Target Address Register offset: 0x04
+ __IO u32 IC_TAR;
+ };
+ union {
+ __IO u32 SAR; ///< Slave Address Register offset: 0x08
+ __IO u32 IC_SAR;
+ };
+ __IO u32 IC_HS_MADDR_RESERVED; ///< Reserved Register offset: 0x0C
+ union {
+ __IO u32 DR; ///< Data Command Register offset: 0x10
+ __IO u32 IC_DATA_CMD;
+ };
+ union {
+ __IO u32 SSHR; ///< SCL High Period Count for Std. Speed Register offset: 0x14
+ __IO u32 IC_SS_SCL_HCNT;
+ };
+ union {
+ __IO u32 SSLR; ///< SCL Low Period Count for Std. Speed Register offset: 0x18
+ __IO u32 IC_SS_SCL_LCNT;
+ };
+ union {
+ __IO u32 FSHR; ///< SCL High Period Count for Fast Speed Register offset: 0x1C
+ __IO u32 IC_FS_SCL_HCNT;
+ };
+ union {
+ __IO u32 FSLR; ///< SCL Low Period Count for Fast Speed Register offset: 0x20
+ __IO u32 IC_FS_SCL_LCNT;
+ };
+ __IO u32 IC_HS_SCL_HCNT_RESERVED; ///< Reserved Register offset: 0x24
+ __IO u32 IC_HS_SCL_LCNT_RESERVED; ///< Reserved Register offset: 0x28
+ union {
+ __IO u32 ISR; ///< Interrupt Status Register offset: 0x2C
+ __IO u32 IC_INTR_STAT;
+ };
+ union {
+ __IO u32 IMR; ///< Interrupt Mask Register offset: 0x30
+ __IO u32 IC_INTR_MASK;
+ };
+ union {
+ __IO u32 RAWISR; ///< RAW Interrupt Status Register offset: 0x34
+ __IO u32 IC_RAW_INTR_STAT;
+ };
+ union {
+ __IO u32 RXTLR; ///< Receive FIFO Threshold Level Register offset: 0x38
+ __IO u32 IC_RX_TL;
+ };
+ union {
+ __IO u32 TXTLR; ///< Transmit FIFO Threshold Level Register offset: 0x3C
+ __IO u32 IC_TX_TL;
+ };
+ union {
+ __IO u32 ICR; ///< Clear All Interrupt Register offset: 0x40
+ __IO u32 IC_CLR_INTR;
+ };
+ union {
+ __IO u32 RX_UNDER; ///< Clear RX_UNDER Interrupt Register offset: 0x44
+ __IO u32 IC_CLR_RX_UNDER;
+ };
+ union {
+ __IO u32 RX_OVER; ///< Clear RX_OVER Interrupt Register offset: 0x48
+ __IO u32 IC_CLR_RX_OVER;
+ };
+ union {
+ __IO u32 TX_OVER; ///< Clear TX_OVER Interrupt Register offset: 0x4C
+ __IO u32 IC_CLR_TX_OVER;
+ };
+ union {
+ __IO u32 RD_REQ; ///< Clear RD_REQ Interrupt Register offset: 0x50
+ __IO u32 IC_CLR_RD_REQ;
+ };
+ union {
+ __IO u32 TX_ABRT; ///< Clear TX_ABRT Interrupt Register offset: 0x54
+ __IO u32 IC_CLR_TX_ABRT;
+ };
+ union {
+ __IO u32 RX_DONE; ///< Clear RX_DONE Interrupt Register offset: 0x58
+ __IO u32 IC_CLR_RX_DONE;
+ };
+ union {
+ __IO u32 ACTIV; ///< Clear ACTIVITY Interrupt Register offset: 0x5C
+ __IO u32 IC_CLR_ACTIVITY;
+ };
+ union {
+ __IO u32 STOP; ///< Clear STOP_DET Interrupt Register offset: 0x60
+ __IO u32 IC_CLR_STOP_DET;
+ };
+ union {
+ __IO u32 START; ///< Clear START_DET Interrupt Register offset: 0x64
+ __IO u32 IC_CLR_START_DET;
+ };
+ union {
+ __IO u32 GC; ///< Clear GEN_CALL Interrupt Register offset: 0x68
+ __IO u32 IC_CLR_GEN_CALL;
+ };
+ union {
+ __IO u32 ENR; ///< Enable Register offset: 0x6C
+ __IO u32 IC_ENABLE;
+ };
+ union {
+ __IO u32 SR; ///< Status Register offset: 0x70
+ __IO u32 IC_STATUS;
+ };
+ union {
+ __IO u32 TXFLR; ///< Transmit FIFO Level Register offset: 0x74
+ __IO u32 IC_TXFLR;
+ };
+ union {
+ __IO u32 RXFLR; ///< Receive FIFO Level Register offset: 0x78
+ __IO u32 IC_RXFLR;
+ };
+ union {
+ __IO u32 HOLD; ///< SDA Hold Time Register offset: 0x7C
+ __IO u32 IC_SDA_HOLD;
+ };
+ __IO u32 RESERVED28; ///IC_TX_ABRT_SOURCE_RESERVED;
+ __IO u32 RESERVED29; ///IC_SLV_DATA_NACK_ONLY_RESERVED;
+
+ union {
+ __IO u32 DMA; ///< DMA Control Register offset: 0x88
+ __IO u32 IC_DMA_CR;
+ };
+ __IO u32 RESERVED30; ///IC_DMA_TDLR_RESERVED;
+ __IO u32 RESERVED31; ///IC_DMA_RDLR_RESERVED;
+ union {
+ __IO u32 SETUP; ///< SDA Setup Time Register offset: 0x94
+ __IO u32 IC_SDA_SETUP;
+ };
+ union {
+ __IO u32 GCR; ///< ACK General Call Register offset: 0x98
+ __IO u32 IC_ACK_GENERAL_CALL;
+ };
+ __IO u32 RESERVED32a; ///_RESERVED; offset:Â 0x9C
+ __IO u32 RESERVED33; ///_RESERVED; offset:Â 0xA0
+ __IO u32 RESERVED34; ///_RESERVED; offset:Â 0xA4
+ __IO u32 RESERVED35; ///_RESERVED; offset:Â 0xA8
+ __IO u32 RESERVED36; ///_RESERVED; offset:Â 0xACÂ Â Â Â
+ __IO u32 SLVMASK; ///© COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_IWDG_H
+#define __REG_IWDG_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) ///< Base Address: 0x40003000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 KR; ///< Key Register offset: 0x00
+ __IO u32 PR; ///< Prescaler Register offset: 0x04
+ __IO u32 RLR; ///< Reload Register offset: 0x08
+ __IO u32 SR; ///< Status Register offset: 0x0C
+ __IO u32 CR; ///< Control Register offset: 0x10
+ __IO u32 IGEN; ///< Interrupt Generator Register offset: 0x14
+ __IO u32 CNT; ///< Interrupt Generator count Register offset: 0x18
+ __IO u32 PS; ///< Prescaler count Register offset: 0x1C
+} IWDG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG ((IWDG_TypeDef*) IWDG_BASE)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_KR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_KEYR_KEY_Pos (0)
+#define IWDG_KEYR_KEY (0xFFFFU << IWDG_KEYR_KEY_Pos) ///< Key Value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_PR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_PR_PRE_Pos (0)
+#define IWDG_PR_PRE (0x07U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4
+#define IWDG_PR_PRE_DIV4 (0x00U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4
+#define IWDG_PR_PRE_DIV8 (0x01U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 8
+#define IWDG_PR_PRE_DIV16 (0x02U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 16
+#define IWDG_PR_PRE_DIV32 (0x03U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 32
+#define IWDG_PR_PRE_DIV64 (0x04U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 64
+#define IWDG_PR_PRE_DIV128 (0x05U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 128
+#define IWDG_PR_PRE_DIV256 (0x06U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 256
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_RLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_RLR_RL_Pos (0)
+#define IWDG_RLR_RL (0x0FFFU << IWDG_RLR_RL_Pos) ///< Watchdog counter reload value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_SR_PVU_Pos (0)
+#define IWDG_SR_PVU (0x01U << IWDG_SR_PVU_Pos) ///< Watchdog prescaler value update
+#define IWDG_SR_RVU_Pos (1)
+#define IWDG_SR_RVU (0x01U << IWDG_SR_RVU_Pos) ///< Watchdog counter reload value update
+
+#define IWDG_SR_IVU_Pos (2)
+#define IWDG_SR_IVU (0x01U << IWDG_SR_IVU_Pos)
+
+#define IWDG_SR_UPDATE_Pos (3)
+#define IWDG_SR_UPDATE (0x01U << IWDG_SR_UPDATE_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_CR_IRQSEL_Pos (0)
+#define IWDG_CR_IRQSEL (0x01U << IWDG_CR_IRQSEL_Pos) ///< IWDG overflow operation selection
+#define IWDG_CR_IRQCLR_Pos (1)
+#define IWDG_CR_IRQCLR (0x01U << IWDG_CR_IRQCLR_Pos) ///< IWDG interrupt clear
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_IGRN Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_IGEN_IGEN_Pos (0)
+#define IWDG_IGEN_IGEN (0xFFFU << IWDG_CR_IRQSEL_Pos) ///< IWDG Interrupt Generate value
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
new file mode 100644
index 00000000..aa360552
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_pwm.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_PWM_H
+#define __REG_PWM_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWM Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWM Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
new file mode 100644
index 00000000..99f52322
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
@@ -0,0 +1,219 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_pwr.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_PWR_H
+#define __REG_PWR_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000) ///< Base Address: 0x40007000
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ union {
+ __IO u32 CR; ///< Control register, offset: 0x00
+ __IO u32 CR1;
+ };
+ union {
+ __IO u32 CSR; ///< Control Status register offset: 0x04
+ __IO u32 CSR1;
+ };
+ __IO u32 CR2; ///< Control register 2 offset: 0x08
+ __IO u32 CR3; ///< Control register 3 offset: 0x0C
+ __IO u32 CR4; ///< Control register 4 offset: 0x10
+ __IO u32 CR5; ///< Control register 5 offset: 0x14
+ __IO u32 CR6; ///< Control register 6 offset: 0x18
+ __IO u32 SR; ///< Status register offset: 0x1C
+ __IO u32 SCR; ///< clear status register offset: 0x20
+ __IO u32 CFGR; ///< Configuration register offset: 0x24
+} PWR_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR ((PWR_TypeDef*) PWR_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR_LDPS_Pos (0)
+#define PWR_CR_LDPS (0x01U << PWR_CR_LDPS_Pos) ///< Domain Write Protction
+
+#define PWR_CR_PDDS_Pos (1)
+#define PWR_CR_PDDS (0x01U << PWR_CR_PDDS_Pos) ///< Power Down Deepsleep
+#define PWR_CR_CSBF_Pos (3)
+#define PWR_CR_CSBF (0x01U << PWR_CR_CSBF_Pos) ///< Clear Standby Flag
+#define PWR_CR_LPR_Pos (13)
+#define PWR_CR_LPR (0x01U << PWR_CR_LPR_Pos) ///< Low power run
+#define PWR_CR_VOS_Pos (14)
+#define PWR_CR_VOS0 (0x00U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.80V
+#define PWR_CR_VOS1 (0x01U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.70V
+#define PWR_CR_VOS2 (0x02U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.60V
+#define PWR_CR_VOS3 (0x03U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.55V
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CSR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CSR_SBF_Pos (1)
+#define PWR_CSR_SBF (0x01U << PWR_CSR_SBF_Pos) ///< Standby Flag
+#define PWR_CSR_VOSRDY_Pos (14)
+#define PWR_CSR_VOSRDY (0x01U << PWR_CR_VOSRDY_Pos) ///< Voltage Modulator Output Selection Ready
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR2 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR2_EWUP1_Pos (0)
+#define PWR_CR2_EWUP1 (0x01U << PWR_CR2_EWUP1_Pos) ///< Enable WKUP1 wake-up pin
+#define PWR_CR2_EWUP2_Pos (1)
+#define PWR_CR2_EWUP2 (0x01U << PWR_CR2_EWUP2_Pos) ///< Enable WKUP2 wake-up pin
+#define PWR_CR2_EWUP3_Pos (2)
+#define PWR_CR2_EWUP3 (0x01U << PWR_CR2_EWUP3_Pos) ///< Enable WKUP3 wake-up pin
+#define PWR_CR2_EWUP4_Pos (3)
+#define PWR_CR2_EWUP4 (0x01U << PWR_CR2_EWUP4_Pos) ///< Enable WKUP4 wake-up pin
+#define PWR_CR2_EWUP5_Pos (4)
+#define PWR_CR2_EWUP5 (0x01U << PWR_CR2_EWUP5_Pos) ///< Enable WKUP5 wake-up pin
+#define PWR_CR2_EWUP6_Pos (5)
+#define PWR_CR2_EWUP6 (0x01U << PWR_CR2_EWUP6_Pos) ///< Enable WKUP6 wake-up pin
+#define PWR_CR2_ENWU_Pos (15)
+#define PWR_CR2_ENWU (0x01U << PWR_CR2_ENWU_Pos) ///< Enable wakeup module
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR3 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR3_WP1_Pos (0)
+#define PWR_CR3_WP1 (0x01U << PWR_CR3_WP1_Pos) ///< WKUP1 used for event polarity detection
+#define PWR_CR3_WP2_Pos (1)
+#define PWR_CR3_WP2 (0x01U << PWR_CR3_WP2_Pos) ///< WKUP2 used for event polarity detection
+#define PWR_CR3_WP3_Pos (2)
+#define PWR_CR3_WP3 (0x01U << PWR_CR3_WP3_Pos) ///< WKUP3 used for event polarity detection
+#define PWR_CR3_WP4_Pos (3)
+#define PWR_CR3_WP4 (0x01U << PWR_CR3_WP4_Pos) ///< WKUP4 used for event polarity detection
+#define PWR_CR3_WP5_Pos (4)
+#define PWR_CR3_WP5 (0x01U << PWR_CR3_WP5_Pos) ///< WKUP5 used for event polarity detection
+#define PWR_CR3_WP6_Pos (5)
+#define PWR_CR3_WP6 (0x01U << PWR_CR3_WP6_Pos) ///< WKUP6 used for event polarity detection
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR4 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR4_FILTSEL0_Pos (0)
+#define PWR_CR4_FILTSEL0 (0x01U << PWR_CR4_FILTSEL0_Pos) ///< selection wake-up source
+#define PWR_CR4_FILTE0_Pos (2)
+#define PWR_CR4_FILTE0 (0x01U << PWR_CR4_FILTE0_Pos) ///< enable Filter 0
+#define PWR_CR4_FILTF0_Pos (4)
+#define PWR_CR4_FILTF0 (0x01U << PWR_CR4_FILTF0_Pos) ///< Whether the wake source passes through filter 0
+#define PWR_CR4_FILTCNT0_Pos (8)
+#define PWR_CR4_FILTCNT0 (0xFFU << PWR_CR4_FILTCNT0_Pos) ///< Filter 0 counter
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR5 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR5_FILTSEL1_Pos (0)
+#define PWR_CR5_FILTSEL1 (0x01U << PWR_CR5_FILTSEL1_Pos) ///< selection wake-up source
+#define PWR_CR5_FILTE1_Pos (2)
+#define PWR_CR5_FILTE1 (0x01U << PWR_CR5_FILTE1_Pos) ///< enable Filter 1
+#define PWR_CR5_FILTF1_Pos (4)
+#define PWR_CR5_FILTF1 (0x01U << PWR_CR5_FILTF1_Pos) ///< Whether the wake source passes through filter 1
+#define PWR_CR5_FILTCNT1_Pos (8)
+#define PWR_CR5_FILTCNT1 (0xFFU << PWR_CR5_FILTCNT1_Pos) ///< Filter 1 counter
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR6 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR6_STDBY_FS_W_Pos (0)
+#define PWR_CR6_STDBY_FS_W1 (0x00U << PWR_CR6_STDBY_FS_W_Pos) ///< 1 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W2 (0x01U << PWR_CR6_STDBY_FS_W_Pos) ///< 2 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W3 (0x02U << PWR_CR6_STDBY_FS_W_Pos) ///< 3 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W4 (0x03U << PWR_CR6_STDBY_FS_W_Pos) ///< 4 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W5 (0x04U << PWR_CR6_STDBY_FS_W_Pos) ///< 5 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W6 (0x05U << PWR_CR6_STDBY_FS_W_Pos) ///< 6 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W7 (0x06U << PWR_CR6_STDBY_FS_W_Pos) ///< 7 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W8 (0x07U << PWR_CR6_STDBY_FS_W_Pos) ///< 8 LSI cycle wake
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_SR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_SR_WUF1_Pos (0)
+#define PWR_SR_WUF1 (0x01U << PWR_SR_WUF1_Pos) ///< wake-up flag 1
+#define PWR_SR_WUF2_Pos (1)
+#define PWR_SR_WUF2 (0x01U << PWR_SR_WUF2_Pos) ///< wake-up flag 2
+#define PWR_SR_WUF3_Pos (2)
+#define PWR_SR_WUF3 (0x01U << PWR_SR_WUF3_Pos) ///< wake-up flag 3
+#define PWR_SR_WUF4_Pos (3)
+#define PWR_SR_WUF4 (0x01U << PWR_SR_WUF4_Pos) ///< wake-up flag 4
+#define PWR_SR_WUF5_Pos (4)
+#define PWR_SR_WUF5 (0x01U << PWR_SR_WUF5_Pos) ///< wake-up flag 5
+#define PWR_SR_WUF6_Pos (5)
+#define PWR_SR_WUF6 (0x01U << PWR_SR_WUF6_Pos) ///< wake-up flag 6
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_SCR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_SCR_CWUF1_Pos (0)
+#define PWR_SCR_CWUF1 (0x01U << PWR_SCR_CWUF1_Pos) ///< clear wake-up flag 1
+#define PWR_SCR_CWUF2_Pos (1)
+#define PWR_SCR_CWUF2 (0x01U << PWR_SCR_CWUF2_Pos) ///< clear wake-up flag 2
+#define PWR_SCR_CWUF3_Pos (2)
+#define PWR_SCR_CWUF3 (0x01U << PWR_SCR_CWUF3_Pos) ///< clear wake-up flag 3
+#define PWR_SCR_CWUF4_Pos (3)
+#define PWR_SCR_CWUF4 (0x01U << PWR_SCR_CWUF4_Pos) ///< clear wake-up flag 4
+#define PWR_SCR_CWUF5_Pos (4)
+#define PWR_SCR_CWUF5 (0x01U << PWR_SCR_CWUF5_Pos) ///< clear wake-up flag 5
+#define PWR_SCR_CWUF6_Pos (5)
+#define PWR_SCR_CWUF6 (0x01U << PWR_SCR_CWUF6_Pos) ///< clear wake-up flag 6
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CFGR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CFGR_LSICALSEL_Pos (0)
+#define PWR_CFGR_LSICALSEL (0x1FU << PWR_CFGR_LSICALSEL_Pos) ///< Enable internal clock calibration
+#define PWR_CFGR_LSICAL_Pos (5)
+#define PWR_CFGR_LSICAL (0x1FU << PWR_CFGR_LSICAL_Pos) ///< Internal high-speed clock calibration
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
new file mode 100644
index 00000000..d378371f
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
@@ -0,0 +1,654 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_rcc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_RCC_H
+#define __REG_RCC_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000) ///< Base Address: 0x40021000
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CR; ///< Control Register offset: 0x00
+ __IO u32 CFGR; ///< Configuration Register offset: 0x04
+ __IO u32 CIR; ///< Clock Interrupt Register offset: 0x08
+ __IO u32 AHB3RSTR; ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C
+ __IO u32 AHB2RSTR; ///< Advanced High Performance Bus 2 Reset Register offset: 0x10
+ __IO u32 AHBRSTR; ///< Advanced High Performance Bus 1 Reset Register offset: 0x14
+ __IO u32 APB2RSTR; ///< Advanced Peripheral Bus 2 Reset Register offset: 0x18
+ __IO u32 APB1RSTR; ///< Advanced Peripheral Bus 1 Reset Register offset: 0x1C
+ __IO u32 AHB3ENR; ///< Advanced High Performance Bus 3 Enable Register offset: 0x20
+ __IO u32 AHB2ENR; ///< Advanced High Performance Bus 2 Enable Register offset: 0x24
+ union {
+ __IO u32 AHBENR; ///< Advanced High Performance Bus 1 Enable Register offset: 0x28
+ __IO u32 AHB1ENR;
+ };
+
+ __IO u32 APB2ENR; ///< Advanced Peripheral Bus 2 Enable Register offset: 0x2C
+ __IO u32 APB1ENR; ///< Advanced Peripheral Bus 1 Enable Register offset: 0x30
+
+
+ __IO u32 BDCR; ///< Backup Domain Control Register offset: 0x34
+ __IO u32 CSR; ///< Control Status Register offset: 0x38
+ __IO u32 SYSCFGR; ///< System Configuration Register offset: 0x3C
+ __IO u32 CFGR2; ///< System Configuration Register offset: 0x40
+ __IO u32 ICSCR; ///< Internal clock source calibration register offset: 0x44
+ __IO u32 PLLCFGR; ///< PLL configures registers offset: 0x48
+ u32 Reserved1[13]; ///< Reserved space
+ __IO u32 HSIDLY; ///< HSI delay register offset: 0x80
+ __IO u32 HSEDLY; ///< HSE delay register offset: 0x84
+ __IO u32 PLLDLY; ///< PLL delay register offset: 0x88
+} RCC_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC ((RCC_TypeDef*) RCC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CR_HSION_Pos (0)
+#define RCC_CR_HSION (0x01U << RCC_CR_HSION_Pos) ///< Internal High Speed clock enable
+
+#define RCC_CR_HSIRDY_Pos (1)
+#define RCC_CR_HSIRDY (0x01U << RCC_CR_HSIRDY_Pos) ///< Internal High Speed clock ready flag
+
+
+
+#define RCC_CR_HSIDIV_Pos (11)
+#define RCC_CR_HSIDIV_0 (0x00U << RCC_CR_HSIDIV_Pos) ///< HSI regardless of frequency
+#define RCC_CR_HSIDIV_2 (0x01U << RCC_CR_HSIDIV_Pos) ///< HSI 2 frequency division
+#define RCC_CR_HSIDIV_4 (0x02U << RCC_CR_HSIDIV_Pos) ///< HSI 4 frequency division
+#define RCC_CR_HSIDIV_8 (0x03U << RCC_CR_HSIDIV_Pos) ///< HSI eight points and frequency
+#define RCC_CR_HSIDIV_16 (0x04U << RCC_CR_HSIDIV_Pos) ///< HSI 16 points and frequency
+#define RCC_CR_HSIDIV_32 (0x05U << RCC_CR_HSIDIV_Pos) ///< HSI 32 points and frequency
+#define RCC_CR_HSIDIV_64 (0x06U << RCC_CR_HSIDIV_Pos) ///< HSI 64 frequency division
+#define RCC_CR_HSIDIV_128 (0x07U << RCC_CR_HSIDIV_Pos) ///< HSI 128 frequency division
+#define RCC_CR_HSEON_Pos (16)
+#define RCC_CR_HSEON (0x01U << RCC_CR_HSEON_Pos) ///< External High Speed clock enable
+#define RCC_CR_HSERDY_Pos (17)
+#define RCC_CR_HSERDY (0x01U << RCC_CR_HSERDY_Pos) ///< External High Speed clock ready flag
+#define RCC_CR_HSEBYP_Pos (18)
+#define RCC_CR_HSEBYP (0x01U << RCC_CR_HSEBYP_Pos) ///< External High Speed clock Bypass
+#define RCC_CR_CSSON_Pos (19)
+#define RCC_CR_CSSON (0x01U << RCC_CR_CSSON_Pos) ///< Clock Security System enable
+
+
+#define RCC_CR_PLLON_Pos (24)
+#define RCC_CR_PLLON (0x01U << RCC_CR_PLLON_Pos) ///< PLL enable
+#define RCC_CR_PLLRDY_Pos (25)
+#define RCC_CR_PLLRDY (0x01U << RCC_CR_PLLRDY_Pos) ///< PLL clock ready flag
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CFGR_SW_Pos (0)
+#define RCC_CFGR_SW (0x03U << RCC_CFGR_SW_Pos) ///< SW[1:0] bits (System clock Switch)
+#define RCC_CFGR_SW_HSI_DIV6 (0x00U << RCC_CFGR_SW_Pos) ///< HSI/6 selected as system clock
+#define RCC_CFGR_SW_HSE (0x01U << RCC_CFGR_SW_Pos) ///< HSE selected as system clock
+#define RCC_CFGR_SW_PLL (0x02U << RCC_CFGR_SW_Pos) ///< PLL selected as system clock
+#define RCC_CFGR_SW_LSI (0x03U << RCC_CFGR_SW_Pos) ///< LSI selected as system clock
+
+#define RCC_CFGR_SWS_Pos (2)
+#define RCC_CFGR_SWS (0x03U << RCC_CFGR_SWS_Pos) ///< SWS[1:0] bits (System Clock Switch Status)
+#define RCC_CFGR_SWS_HSI_DIV6 (0x00U << RCC_CFGR_SWS_Pos) ///< HSI/6 oscillator used as system clock
+#define RCC_CFGR_SWS_HSE (0x01U << RCC_CFGR_SWS_Pos) ///< HSE oscillator used as system clock
+#define RCC_CFGR_SWS_PLL (0x02U << RCC_CFGR_SWS_Pos) ///< PLL used as system clock
+#define RCC_CFGR_SWS_LSI (0x03U << RCC_CFGR_SWS_Pos) ///< LSI used as system clock
+
+#define RCC_CFGR_HPRE_Pos (4)
+#define RCC_CFGR_HPRE (0x0FU << RCC_CFGR_HPRE_Pos) ///< HPRE[3:0] bits (AHB prescaler)
+#define RCC_CFGR_PPRE_0 (0x01U << RCC_CFGR_HPRE_Pos) ///< Bit 0
+#define RCC_CFGR_PPRE_1 (0x02U << RCC_CFGR_HPRE_Pos) ///< Bit 1
+#define RCC_CFGR_PPRE_2 (0x04U << RCC_CFGR_HPRE_Pos) ///< Bit 2
+#define RCC_CFGR_PPRE_3 (0x08U << RCC_CFGR_HPRE_Pos) ///< Bit 3
+
+#define RCC_CFGR_HPRE_DIV1 (0x00U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK not divided
+#define RCC_CFGR_HPRE_DIV2 (0x08U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 2
+#define RCC_CFGR_HPRE_DIV4 (0x09U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 4
+#define RCC_CFGR_HPRE_DIV8 (0x0AU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 8
+#define RCC_CFGR_HPRE_DIV16 (0x0BU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 16
+#define RCC_CFGR_HPRE_DIV64 (0x0CU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 64
+#define RCC_CFGR_HPRE_DIV128 (0x0DU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 128
+#define RCC_CFGR_HPRE_DIV256 (0x0EU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 256
+#define RCC_CFGR_HPRE_DIV512 (0x0FU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 512
+
+#define RCC_CFGR_PPRE1_Pos (8)
+#define RCC_CFGR_PPRE1 (0x07U << RCC_CFGR_PPRE1_Pos) ///< PRE1[2:0] bits (APB1 prescaler)
+#define RCC_CFGR_PPRE1_0 (0x01U << RCC_CFGR_PPRE1_Pos) ///< Bit 0
+#define RCC_CFGR_PPRE1_1 (0x02U << RCC_CFGR_PPRE1_Pos) ///< Bit 1
+#define RCC_CFGR_PPRE1_2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< Bit 2
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK not divided
+#define RCC_CFGR_PPRE1_DIV2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 2
+#define RCC_CFGR_PPRE1_DIV4 (0x05U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 4
+#define RCC_CFGR_PPRE1_DIV8 (0x06U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 8
+#define RCC_CFGR_PPRE1_DIV16 (0x07U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 16
+
+#define RCC_CFGR_PPRE2_Pos (11)
+#define RCC_CFGR_PPRE2 (0x07U << RCC_CFGR_PPRE2_Pos) ///< PRE2[2:0] bits (APB2 prescaler)
+#define RCC_CFGR_PPRE2_0 (0x01U << RCC_CFGR_PPRE2_Pos) ///< Bit 0
+#define RCC_CFGR_PPRE2_1 (0x02U << RCC_CFGR_PPRE2_Pos) ///< Bit 1
+#define RCC_CFGR_PPRE2_2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< Bit 2
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK not divided
+#define RCC_CFGR_PPRE2_DIV2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 2
+#define RCC_CFGR_PPRE2_DIV4 (0x05U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 4
+#define RCC_CFGR_PPRE2_DIV8 (0x06U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 8
+#define RCC_CFGR_PPRE2_DIV16 (0x07U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 16
+
+
+#define RCC_CFGR_USBPRE_Pos (22)
+#define RCC_CFGR_USBPRE (0x03U << RCC_CFGR_USBPRE_Pos) ///< USB prescaler BIT[1:0]
+
+#define RCC_CFGR_MCO_Pos (24)
+#define RCC_CFGR_MCO (0x07U << RCC_CFGR_MCO_Pos) ///< MCO[2:0] bits (Microcontroller Clock Output)
+#define RCC_CFGR_MCO_NOCLOCK (0x00U << RCC_CFGR_MCO_Pos) ///< No clock
+#define RCC_CFGR_MCO_LSI (0x02U << RCC_CFGR_MCO_Pos) ///< LSI clock
+#define RCC_CFGR_MCO_LSE (0x03U << RCC_CFGR_MCO_Pos) ///< LSE clock
+#define RCC_CFGR_MCO_SYSCLK (0x04U << RCC_CFGR_MCO_Pos) ///< System clock selected
+#define RCC_CFGR_MCO_HSI (0x05U << RCC_CFGR_MCO_Pos) ///< Internal 48 MHz RC oscillator clock selected
+#define RCC_CFGR_MCO_HSE (0x06U << RCC_CFGR_MCO_Pos) ///< External 1-25 MHz oscillator clock selected
+#define RCC_CFGR_MCO_PLL (0x07U << RCC_CFGR_MCO_Pos) ///< PLL clock divided by 2 selected
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CIR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CIR_LSIRDYF_Pos (0)
+#define RCC_CIR_LSIRDYF (0x01U << RCC_CIR_LSIRDYF_Pos) ///< LSI Ready Interrupt flag
+
+#define RCC_CIR_LSERDYF_Pos (1)
+#define RCC_CIR_LSERDYF (0x01U << RCC_CIR_LSERDYF_Pos) ///< LSE Ready Interrupt flag
+
+#define RCC_CIR_HSIRDYF_Pos (2)
+#define RCC_CIR_HSIRDYF (0x01U << RCC_CIR_HSIRDYF_Pos) ///< HSI Ready Interrupt flag
+#define RCC_CIR_HSERDYF_Pos (3)
+#define RCC_CIR_HSERDYF (0x01U << RCC_CIR_HSERDYF_Pos) ///< HSE Ready Interrupt flag
+
+#define RCC_CIR_PLLRDYF_Pos (4)
+#define RCC_CIR_PLLRDYF (0x01U << RCC_CIR_PLLRDYF_Pos) ///< PLL Ready Interrupt flag
+
+#define RCC_CIR_CSSF_Pos (7)
+#define RCC_CIR_CSSF (0x01U << RCC_CIR_CSSF_Pos) ///< Clock Security System Interrupt flag
+#define RCC_CIR_LSIRDYIE_Pos (8)
+#define RCC_CIR_LSIRDYIE (0x01U << RCC_CIR_LSIRDYIE_Pos) ///< LSI Ready Interrupt Enable
+
+#define RCC_CIR_LSERDYIE_Pos (9)
+#define RCC_CIR_LSERDYIE (0x01U << RCC_CIR_LSERDYIE_Pos) ///< LSE Ready Interrupt Enable
+
+#define RCC_CIR_HSIRDYIE_Pos (10)
+#define RCC_CIR_HSIRDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSI Ready Interrupt Enable
+#define RCC_CIR_HSERDYIE_Pos (11)
+#define RCC_CIR_HSERDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSE Ready Interrupt Enable
+
+#define RCC_CIR_PLLRDYIE_Pos (12)
+#define RCC_CIR_PLLRDYIE (0x01U << RCC_CIR_PLLRDYIE_Pos) ///< PLL Ready Interrupt Enable
+
+#define RCC_CIR_LSIRDYC_Pos (16)
+#define RCC_CIR_LSIRDYC (0x01U << RCC_CIR_LSIRDYC_Pos) ///< LSI Ready Interrupt Clear
+
+#define RCC_CIR_LSERDYC_Pos (17)
+#define RCC_CIR_LSERDYC (0x01U << RCC_CIR_LSERDYC_Pos) ///< LSE Ready Interrupt Clear
+
+#define RCC_CIR_HSIRDYC_Pos (18)
+#define RCC_CIR_HSIRDYC (0x01U << RCC_CIR_HSIRDYC_Pos) ///< HSI Ready Interrupt Clear
+#define RCC_CIR_HSERDYC_Pos (19)
+#define RCC_CIR_HSERDYC (0x01U << RCC_CIR_HSERDYC_Pos) ///< HSE Ready Interrupt Clear
+
+#define RCC_CIR_PLLRDYC_Pos (20)
+#define RCC_CIR_PLLRDYC (0x01U << RCC_CIR_PLLRDYC_Pos) ///< PLL Ready Interrupt Clear
+
+#define RCC_CIR_CSSC_Pos (23)
+#define RCC_CIR_CSSC (0x01U << RCC_CIR_CSSC_Pos) ///< Clock Security System Interrupt Clear
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB2RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB2RSTR_TIM1_Pos (0)
+#define RCC_APB2RSTR_TIM1 (0x01U << RCC_APB2RSTR_TIM1_Pos) ///< TIM1 reset
+#define RCC_APB2RSTR_TIM8_Pos (1)
+#define RCC_APB2RSTR_TIM8 (0x01U << RCC_APB2RSTR_TIM8_Pos) ///< TIM8 reset
+#define RCC_APB2RSTR_UART1_Pos (4)
+#define RCC_APB2RSTR_UART1 (0x01U << RCC_APB2RSTR_UART1_Pos) ///< UART1 reset
+#define RCC_APB2RSTR_UART6_Pos (5)
+#define RCC_APB2RSTR_UART6 (0x01U << RCC_APB2RSTR_UART6_Pos) ///< UART6 reset
+#define RCC_APB2RSTR_ADC1_Pos (8)
+#define RCC_APB2RSTR_ADC1 (0x01U << RCC_APB2RSTR_ADC1_Pos) ///< ADC1 reset
+#define RCC_APB2RSTR_ADC2_Pos (9)
+#define RCC_APB2RSTR_ADC2 (0x01U << RCC_APB2RSTR_ADC2_Pos) ///< ADC2 reset
+#define RCC_APB2RSTR_ADC3_Pos (10)
+#define RCC_APB2RSTR_ADC3 (0x01U << RCC_APB2RSTR_ADC3_Pos) ///< ADC3 reset
+#define RCC_APB2RSTR_SPI1_Pos (12)
+#define RCC_APB2RSTR_SPI1 (0x01U << RCC_APB2RSTR_SPI1_Pos) ///< SPI1 reset
+#define RCC_APB2RSTR_SYSCFG_Pos (14)
+#define RCC_APB2RSTR_SYSCFG (0x01U << RCC_APB2RSTR_SYSCFG_Pos) ///< SYSCFG reset
+#define RCC_APB2RSTR_COMP_Pos (15)
+#define RCC_APB2RSTR_COMP (0x01U << RCC_APB2RSTR_COMP_Pos) ///< COMP reset
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB3RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB3RSTR_FSMC_Pos (0)
+#define RCC_AHB3RSTR_FSMC (0x01U << RCC_AHB3RSTR_FSMC_Pos) ///< FSMC reset
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB1RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB1RSTR_TIM2_Pos (0)
+#define RCC_APB1RSTR_TIM2 (0x01U << RCC_APB1RSTR_TIM2_Pos) ///< Timer 2 reset
+#define RCC_APB1RSTR_TIM3_Pos (1)
+#define RCC_APB1RSTR_TIM3 (0x01U << RCC_APB1RSTR_TIM3_Pos) ///< Timer 3 reset
+
+#define RCC_APB1RSTR_TIM4_Pos (2)
+#define RCC_APB1RSTR_TIM4 (0x01U << RCC_APB1RSTR_TIM4_Pos) ///< Timer 4 reset
+#define RCC_APB1RSTR_TIM5_Pos (3)
+#define RCC_APB1RSTR_TIM5 (0x01U << RCC_APB1RSTR_TIM5_Pos) ///< Timer 5 reset
+#define RCC_APB1RSTR_TIM6_Pos (4)
+#define RCC_APB1RSTR_TIM6 (0x01U << RCC_APB1RSTR_TIM6_Pos) ///< Timer 6 reset
+#define RCC_APB1RSTR_TIM7_Pos (5)
+#define RCC_APB1RSTR_TIM7 (0x01U << RCC_APB1RSTR_TIM7_Pos) ///< Timer 7 reset
+
+#define RCC_APB1RSTR_WWDG_Pos (11)
+#define RCC_APB1RSTR_WWDG (0x01U << RCC_APB1RSTR_WWDG_Pos) ///< Window Watchdog reset
+#define RCC_APB1RSTR_SPI2_Pos (14)
+#define RCC_APB1RSTR_SPI2 (0x01U << RCC_APB1RSTR_SPI2_Pos) ///< SPI 2 reset
+#define RCC_APB1RSTR_SPI3_Pos (15)
+#define RCC_APB1RSTR_SPI3 (0x01U << RCC_APB1RSTR_SPI3_Pos) ///< SPI 3 reset
+
+#define RCC_APB1RSTR_UART2_Pos (17)
+#define RCC_APB1RSTR_UART2 (0x01U << RCC_APB1RSTR_UART2_Pos) ///< UART 2 reset
+#define RCC_APB1RSTR_UART3_Pos (18)
+#define RCC_APB1RSTR_UART3 (0x01U << RCC_APB1RSTR_UART3_Pos) ///< UART 3 reset
+#define RCC_APB1RSTR_UART4_Pos (19)
+#define RCC_APB1RSTR_UART4 (0x01U << RCC_APB1RSTR_UART4_Pos) ///< UART 4 reset
+#define RCC_APB1RSTR_UART5_Pos (20)
+#define RCC_APB1RSTR_UART5 (0x01U << RCC_APB1RSTR_UART5_Pos) ///< UART 5 reset
+#define RCC_APB1RSTR_I2C1_Pos (21)
+#define RCC_APB1RSTR_I2C1 (0x01U << RCC_APB1RSTR_I2C1_Pos) ///< I2C 1 reset
+#define RCC_APB1RSTR_I2C2_Pos (22)
+#define RCC_APB1RSTR_I2C2 (0x01U << RCC_APB1RSTR_I2C2_Pos) ///< I2C 2 reset
+
+#define RCC_APB1RSTR_CRS_Pos (24)
+#define RCC_APB1RSTR_CRS (0x01U << RCC_APB1RSTR_CRS_Pos) ///< CRS reset
+#define RCC_APB1RSTR_CAN_Pos (25)
+#define RCC_APB1RSTR_CAN (0x01U << RCC_APB1RSTR_CAN_Pos) ///< CAN reset
+
+#define RCC_APB1RSTR_BKP_Pos (27)
+#define RCC_APB1RSTR_BKP (0x01U << RCC_APB1RSTR_BKP_Pos) ///< Backup interface reset
+
+#define RCC_APB1RSTR_PWR_Pos (28)
+#define RCC_APB1RSTR_PWR (0x01U << RCC_APB1RSTR_PWR_Pos) ///< Power interface reset
+#define RCC_APB1RSTR_DAC_Pos (29)
+#define RCC_APB1RSTR_DAC (0x01U << RCC_APB1RSTR_DAC_Pos) ///< DAC interface reset
+
+
+#define RCC_APB1RSTR_UART7_Pos (30)
+#define RCC_APB1RSTR_UART7 (0x01U << RCC_APB1RSTR_UART7_Pos) ///< UART7 reset
+#define RCC_APB1RSTR_UART8_Pos (31)
+#define RCC_APB1RSTR_UART8 (0x01U << RCC_APB1RSTR_UART8_Pos) ///< UART8 reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB2RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB2RSTR_USBFS_Pos (7)
+#define RCC_AHB2RSTR_USBFS (0x01U << RCC_AHB2RSTR_USBFS_Pos) ///< USBFS reset
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB3ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB3ENR_FSMC_Pos (0)
+#define RCC_AHB3ENR_FSMC (0x01U << RCC_AHB3ENR_FSMC_Pos) ///< FSMC reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB2ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB2ENR_USBFS_Pos (7)
+#define RCC_AHB2ENR_USBFS (0x01U << RCC_AHB2ENR_USBFS_Pos) ///< USBFS reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHBENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#define RCC_AHBENR_GPIOA_Pos (0)
+#define RCC_AHBENR_GPIOA (0x01U << RCC_AHBENR_GPIOA_Pos) ///< GPIOA clock enable
+#define RCC_AHBENR_GPIOB_Pos (1)
+#define RCC_AHBENR_GPIOB (0x01U << RCC_AHBENR_GPIOB_Pos) ///< GPIOB clock enable
+#define RCC_AHBENR_GPIOC_Pos (2)
+#define RCC_AHBENR_GPIOC (0x01U << RCC_AHBENR_GPIOC_Pos) ///< GPIOC clock enable
+#define RCC_AHBENR_GPIOD_Pos (3)
+#define RCC_AHBENR_GPIOD (0x01U << RCC_AHBENR_GPIOD_Pos) ///< GPIOD clock enable
+#define RCC_AHBENR_GPIOE_Pos (4)
+#define RCC_AHBENR_GPIOE (0x01U << RCC_AHBENR_GPIOE_Pos) ///< GPIOE clock enable
+#define RCC_AHBENR_GPIOF_Pos (5)
+#define RCC_AHBENR_GPIOF (0x01U << RCC_AHBENR_GPIOF_Pos) ///< GPIOF clock enable
+#define RCC_AHBENR_GPIOG_Pos (6)
+#define RCC_AHBENR_GPIOG (0x01U << RCC_AHBENR_GPIOG_Pos) ///< GPIOG clock enable
+#define RCC_AHBENR_GPIOH_Pos (7)
+#define RCC_AHBENR_GPIOH (0x01U << RCC_AHBENR_GPIOH_Pos) ///< GPIOH clock enable
+#define RCC_AHBENR_SDIO_Pos (10)
+#define RCC_AHBENR_SDIO (0x01U << RCC_AHBENR_SDIO_Pos) ///< SDIO clock enable
+#define RCC_AHBENR_CRC_Pos (12)
+#define RCC_AHBENR_CRC (0x01U << RCC_AHBENR_CRC_Pos) ///< CRC clock enable
+#define RCC_AHBENR_FLASH_Pos (13)
+#define RCC_AHBENR_FLASH (0x01U << RCC_AHBENR_FLASH_Pos) ///< FLASH clock enable
+#define RCC_AHBENR_SRAM_Pos (14)
+#define RCC_AHBENR_SRAM (0x01U << RCC_AHBENR_SRAM_Pos) ///< SRAM clock enable
+#define RCC_AHBENR_DMA1_Pos (21)
+#define RCC_AHBENR_DMA1 (0x01U << RCC_AHBENR_DMA1_Pos) ///< DMA1 clock enable
+#define RCC_AHBENR_DMA2_Pos (22)
+#define RCC_AHBENR_DMA2 (0x01U << RCC_AHBENR_DMA2_Pos) ///< DMA2 clock enable
+#define RCC_AHBENR_ETHMAC_Pos (25)
+#define RCC_AHBENR_ETHMAC (0x01U << RCC_AHBENR_ETHMAC_Pos) ///< ETHMAC clock enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB2ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB2ENR_TIM1_Pos (0)
+#define RCC_APB2ENR_TIM1 (0x01U << RCC_APB2ENR_TIM1_Pos) ///< TIM1 enable
+#define RCC_APB2ENR_TIM8_Pos (1)
+#define RCC_APB2ENR_TIM8 (0x01U << RCC_APB2ENR_TIM8_Pos) ///< TIM8 enable
+#define RCC_APB2ENR_UART1_Pos (4)
+#define RCC_APB2ENR_UART1 (0x01U << RCC_APB2ENR_UART1_Pos) ///< UART1 enable
+#define RCC_APB2ENR_UART6_Pos (5)
+#define RCC_APB2ENR_UART6 (0x01U << RCC_APB2ENR_UART6_Pos) ///< UART6 enable
+#define RCC_APB2ENR_ADC1_Pos (8)
+#define RCC_APB2ENR_ADC1 (0x01U << RCC_APB2ENR_ADC1_Pos) ///< ADC1 enable
+#define RCC_APB2ENR_ADC2_Pos (9)
+#define RCC_APB2ENR_ADC2 (0x01U << RCC_APB2ENR_ADC2_Pos) ///< ADC2 enable
+#define RCC_APB2ENR_ADC3_Pos (10)
+#define RCC_APB2ENR_ADC3 (0x01U << RCC_APB2ENR_ADC3_Pos) ///< ADC3 enable
+#define RCC_APB2ENR_SPI1_Pos (12)
+#define RCC_APB2ENR_SPI1 (0x01U << RCC_APB2ENR_SPI1_Pos) ///< SPI1 enable
+#define RCC_APB2ENR_EXTI_Pos (14)
+#define RCC_APB2ENR_EXTI (0x01U << RCC_APB2ENR_EXTI_Pos) ///< EXTI Block enable
+#define RCC_APB2ENR_SYSCFG_Pos (14)
+#define RCC_APB2ENR_SYSCFG (0x01U << RCC_APB2ENR_SYSCFG_Pos) ///< SYSCFG enable
+#define RCC_APB2ENR_COMP_Pos (15)
+#define RCC_APB2ENR_COMP (0x01U << RCC_APB2ENR_COMP_Pos) ///< COMP enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB1ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB1ENR_TIM2_Pos (0)
+#define RCC_APB1ENR_TIM2 (0x01U << RCC_APB1ENR_TIM2_Pos) ///< Timer 2 clock enable
+
+#define RCC_APB1ENR_TIM3_Pos (1)
+#define RCC_APB1ENR_TIM3 (0x01U << RCC_APB1ENR_TIM3_Pos) ///< Timer 3 clock enabled
+
+#define RCC_APB1ENR_TIM4_Pos (2)
+#define RCC_APB1ENR_TIM4 (0x01U << RCC_APB1ENR_TIM4_Pos) ///< Timer 4 clock enable
+
+
+#define RCC_APB1ENR_TIM5_Pos (3)
+#define RCC_APB1ENR_TIM5 (0x01U << RCC_APB1ENR_TIM5_Pos) ///< TIM5 Timer clock enable
+#define RCC_APB1ENR_TIM6_Pos (4)
+#define RCC_APB1ENR_TIM6 (0x01U << RCC_APB1ENR_TIM6_Pos) ///< TIM6 Timer clock enable
+#define RCC_APB1ENR_TIM7_Pos (5)
+#define RCC_APB1ENR_TIM7 (0x01U << RCC_APB1ENR_TIM7_Pos) ///< TIM7 Timer clock enable
+
+#define RCC_APB1ENR_WWDG_Pos (11)
+#define RCC_APB1ENR_WWDG (0x01U << RCC_APB1ENR_WWDG_Pos) ///< Window Watchdog clock enable
+
+
+#define RCC_APB1ENR_SPI2_Pos (14)
+#define RCC_APB1ENR_SPI2 (0x01U << RCC_APB1ENR_SPI2_Pos) ///< SPI 2 clock enable
+#define RCC_APB1ENR_SPI3_Pos (15)
+#define RCC_APB1ENR_SPI3 (0x01U << RCC_APB1ENR_SPI3_Pos) ///< SPI 3 clock enable
+
+#define RCC_APB1ENR_UART2_Pos (17)
+#define RCC_APB1ENR_UART2 (0x01U << RCC_APB1ENR_UART2_Pos) ///< UART 2 clock enable
+#define RCC_APB1ENR_UART3_Pos (18)
+#define RCC_APB1ENR_UART3 (0x01U << RCC_APB1ENR_UART3_Pos) ///< UART 3 clock enable
+#define RCC_APB1ENR_UART4_Pos (19)
+#define RCC_APB1ENR_UART4 (0x01U << RCC_APB1ENR_UART4_Pos) ///< UART 4 clock enable
+#define RCC_APB1ENR_UART5_Pos (20)
+#define RCC_APB1ENR_UART5 (0x01U << RCC_APB1ENR_UART5_Pos) ///< UART 5 clock enable
+#define RCC_APB1ENR_I2C1_Pos (21)
+#define RCC_APB1ENR_I2C1 (0x01U << RCC_APB1ENR_I2C1_Pos) ///< I2C 1 clock enable
+#define RCC_APB1ENR_I2C2_Pos (22)
+#define RCC_APB1ENR_I2C2 (0x01U << RCC_APB1ENR_I2C2_Pos) ///< I2C 2 clock enable
+#define RCC_APB1ENR_CRS_Pos (24)
+#define RCC_APB1ENR_CRS (0x01U << RCC_APB1ENR_CRS_Pos) ///< CRS 4 clock enable
+#define RCC_APB1ENR_CAN_Pos (25)
+#define RCC_APB1ENR_CAN (0x01U << RCC_APB1ENR_CAN_Pos) ///< CAN 5 clock enable
+
+
+
+#define RCC_APB1ENR_BKP_Pos (27)
+#define RCC_APB1ENR_BKP (0x01U << RCC_APB1ENR_BKP_Pos) ///< Backup interface clock enable
+
+#define RCC_APB1ENR_PWR_Pos (28)
+#define RCC_APB1ENR_PWR (0x01U << RCC_APB1ENR_PWR_Pos) ///< Power interface clock enable
+
+#define RCC_APB1ENR_DBGMCU_Pos (28)
+#define RCC_APB1ENR_DBGMCU (0x01U << RCC_APB1ENR_DBGMCU_Pos) ///< DBGMCU clock enable
+
+
+#define RCC_APB1ENR_DAC_Pos (29)
+#define RCC_APB1ENR_DAC (0x01U << RCC_APB1ENR_DAC_Pos) ///< DAC interface clock enable
+#define RCC_APB1ENR_UART7_Pos (30)
+#define RCC_APB1ENR_UART7 (0x01U << RCC_APB1ENR_UART7_Pos) ///< UART7 interface clock enable
+#define RCC_APB1ENR_UART8_Pos (31)
+#define RCC_APB1ENR_UART8 (0x01U << RCC_APB1ENR_UART8_Pos) ///< UART8 interface clock enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_BDCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_BDCR_LSEON_Pos (0)
+#define RCC_BDCR_LSEON (0x01U << RCC_BDCR_LSEON_Pos) ///< External Low Speed oscillator enable
+#define RCC_BDCR_LSERDY_Pos (1)
+#define RCC_BDCR_LSERDY (0x01U << RCC_BDCR_LSERDY_Pos) ///< External Low Speed oscillator Ready
+#define RCC_BDCR_LSEBYP_Pos (2)
+#define RCC_BDCR_LSEBYP (0x01U << RCC_BDCR_LSEBYP_Pos) ///< External Low Speed oscillator Bypass
+
+#define RCC_BDCR_RTCSEL_Pos (8)
+#define RCC_BDCR_RTCSEL (0x03U << RCC_BDCR_RTCSEL_Pos) ///< RTCSEL[1:0] bits (RTC clock source selection)
+#define RCC_BDCR_RTCSEL_LSE (0x01U << RCC_BDCR_RTCSEL_Pos) ///< LSE oscillator clock used as RTC clock
+#define RCC_BDCR_RTCSEL_LSI (0x02U << RCC_BDCR_RTCSEL_Pos) ///< LSI oscillator clock used as RTC clock
+#define RCC_BDCR_RTCSEL_HSE (0x03U << RCC_BDCR_RTCSEL_Pos) ///< HSE oscillator clock divided by 128 used as RTC clock
+
+#define RCC_BDCR_RTCEN_Pos (15)
+#define RCC_BDCR_RTCEN (0x01U << RCC_BDCR_RTCEN_Pos) ///< RTC clock enable
+#define RCC_BDCR_BDRST_Pos (16)
+#define RCC_BDCR_BDRST (0x01U << RCC_BDCR_BDRST_Pos) ///< Backup domain software reset
+#define RCC_BDCR_DBP_Pos (24)
+#define RCC_BDCR_DBP (0x01U << RCC_BDCR_DBP_Pos) ///< DBP clock enable
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CSR_LSION_Pos (0)
+#define RCC_CSR_LSION (0x01U << RCC_CSR_LSION_Pos) ///< Internal Low Speed oscillator enable
+#define RCC_CSR_LSIRDY_Pos (1)
+#define RCC_CSR_LSIRDY (0x01U << RCC_CSR_LSIRDY_Pos) ///< Internal Low Speed oscillator Ready
+#define RCC_CSR_LSIOENLV_Pos (5)
+#define RCC_CSR_LSIOENLV (0x01U << RCC_CSR_LSIOENLV_Pos) ///< LSI output enable lower voltage
+#define RCC_CSR_PVDRSTEN_Pos (6)
+#define RCC_CSR_PVDRSTEN (0x01U << RCC_CSR_PVDRSTEN_Pos) ///< PVD reset enable
+#define RCC_CSR_LOCKUPEN_Pos (7)
+#define RCC_CSR_LOCKUPEN (0x01U << RCC_CSR_LOCKUPEN_Pos) ///< CPU lockup reset enable
+#define RCC_CSR_VDTRSTNEN_Pos (8)
+#define RCC_CSR_VDTRSTNEN (0x01U << RCC_CSR_VDTRSTNEN_Pos) ///< Voltage detect reset enable
+#define RCC_CSR_VDTRSTF_Pos (21)
+#define RCC_CSR_VDTRSTF (0x01U << RCC_CSR_VDTRSTF_Pos) ///< Voltage detect reset flag
+#define RCC_CSR_PVDRSTF_Pos (22)
+#define RCC_CSR_PVDRSTF (0x01U << RCC_CSR_PVDRSTF_Pos) ///< PVD reset flag
+#define RCC_CSR_LOCKUPF_Pos (23)
+#define RCC_CSR_LOCKUPF (0x01U << RCC_CSR_LOCKUPF_Pos) ///< CPU lockup reset flag
+
+#define RCC_CSR_RMVF_Pos (24)
+#define RCC_CSR_RMVF (0x01U << RCC_CSR_RMVF_Pos) ///< Remove reset flag
+#define RCC_CSR_PINRSTF_Pos (26)
+#define RCC_CSR_PINRSTF (0x01U << RCC_CSR_PINRSTF_Pos) ///< PIN reset flag
+
+#define RCC_CSR_PORRSTF_Pos (27)
+#define RCC_CSR_PORRSTF (0x01U << RCC_CSR_PORRSTF_Pos) ///< POR/PDR reset flag
+
+#define RCC_CSR_SFTRSTF_Pos (28)
+#define RCC_CSR_SFTRSTF (0x01U << RCC_CSR_SFTRSTF_Pos) ///< Software Reset flag
+
+#define RCC_CSR_IWDGRSTF_Pos (29)
+#define RCC_CSR_IWDGRSTF (0x01U << RCC_CSR_IWDGRSTF_Pos) ///< Independent Watchdog reset flag
+
+#define RCC_CSR_WWDGRSTF_Pos (30)
+#define RCC_CSR_WWDGRSTF (0x01U << RCC_CSR_WWDGRSTF_Pos) ///< Window watchdog reset flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHBRSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHBRSTR_GPIOA_Pos (0)
+#define RCC_AHBRSTR_GPIOA (0x01U << RCC_AHBRSTR_GPIOA_Pos) ///< GPIOA clock reset
+#define RCC_AHBRSTR_GPIOB_Pos (1)
+#define RCC_AHBRSTR_GPIOB (0x01U << RCC_AHBRSTR_GPIOB_Pos) ///< GPIOB clock reset
+#define RCC_AHBRSTR_GPIOC_Pos (2)
+#define RCC_AHBRSTR_GPIOC (0x01U << RCC_AHBRSTR_GPIOC_Pos) ///< GPIOC clock reset
+#define RCC_AHBRSTR_GPIOD_Pos (3)
+#define RCC_AHBRSTR_GPIOD (0x01U << RCC_AHBRSTR_GPIOD_Pos) ///< GPIOD clock reset
+#define RCC_AHBRSTR_GPIOE_Pos (4)
+#define RCC_AHBRSTR_GPIOE (0x01U << RCC_AHBRSTR_GPIOE_Pos) ///< GPIOE clock reset
+#define RCC_AHBRSTR_GPIOF_Pos (5)
+#define RCC_AHBRSTR_GPIOF (0x01U << RCC_AHBRSTR_GPIOF_Pos) ///< GPIOF clock reset
+#define RCC_AHBRSTR_GPIOG_Pos (6)
+#define RCC_AHBRSTR_GPIOG (0x01U << RCC_AHBRSTR_GPIOG_Pos) ///< GPIOG clock reset
+#define RCC_AHBRSTR_GPIOH_Pos (7)
+#define RCC_AHBRSTR_GPIOH (0x01U << RCC_AHBRSTR_GPIOH_Pos) ///< GPIOH clock reset
+#define RCC_AHBRSTR_SDIO_Pos (10)
+#define RCC_AHBRSTR_SDIO (0x01U << RCC_AHBRSTR_SDIO_Pos) ///< SDIO clock reset
+#define RCC_AHBRSTR_CRC_Pos (12)
+#define RCC_AHBRSTR_CRC (0x01U << RCC_AHBRSTR_CRC_Pos) ///< CRC clock reset
+#define RCC_AHBRSTR_DMA1_Pos (21)
+#define RCC_AHBRSTR_DMA1 (0x01U << RCC_AHBRSTR_DMA1_Pos) ///< DMA1 clock reset
+#define RCC_AHBRSTR_DMA2_Pos (22)
+#define RCC_AHBRSTR_DMA2 (0x01U << RCC_AHBRSTR_DMA2_Pos) ///< DMA2 clock reset
+#define RCC_AHBRSTR_ETHMAC_Pos (25)
+#define RCC_AHBRSTR_ETHMAC (0x01U << RCC_AHBRSTR_ETHMAC_Pos) ///< ETHMAC clock reset
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_SYSCFG Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define RCC_SYSCFG_PROGCHECKEN_Pos (0)
+#define RCC_SYSCFG_PROGCHECKEN (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos) ///< Whether to check the number in Flash when writing to Flash
+#define RCC_SYSCFG_SECTOR1KCFG_Pos (1)
+#define RCC_SYSCFG_SECTOR1KCFG (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos) ///< The size of the Flash page when erased.
+#define RCC_SYSCFG_DATAPREFETCH_Pos (2)
+#define RCC_SYSCFG_DATAPREFETCH (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit
+#define RCC_SYSCFG_PAD_OSC_TRIM_Pos (8)
+#define RCC_SYSCFG_PAD_OSC_TRIM (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration
+#define RCC_SYSCFG_OSC_LPFEN_Pos (14)
+#define RCC_SYSCFG_OSC_LPFEN (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos) ///< External crystal oscillator low pass filtering enables
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CFGR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CFGR2_TIMADVCKSEL_Pos (1)
+#define RCC_CFGR2_TIMADVCKSEL (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos) ///< TIMADV_CKSEL
+#define RCC_CFGR2_TIMADV_PRE_Pos (1) ///<
+#define RCC_CFGR2_TIMADV_PRE (0x07U << RCC_CFGR2_TIMADV_PRE_Pos) ///< SYSCLK's advance points are controlled by the software Frequency coefficient
+#define RCC_CFGR2_FSMC_PRE_Pos (8)
+#define RCC_CFGR2_FSMC_PRE (0x1FU << RCC_CFGR2_FSMC_PRE_Pos) ///< FSMC Output clock frequency division factor
+#define RCC_CFGR2_APB1_CLK_HV_PRE_Pos (16)
+#define RCC_CFGR2_APB1_CLK_HV_PRE (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_ICSCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_ICSCR_TIME_CRS_SEL_Pos (0)
+#define RCC_ICSCR_TIME_CRS_SEL (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source
+#define RCC_ICSCR_HSI_CAL_SEL_Pos (11) ///<
+#define RCC_ICSCR_HSI_CAL_SEL (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos) ///< Select the internal high speed clock calibration value
+#define RCC_ICSCR_HSI_CAL_SFT_Pos (16)
+#define RCC_ICSCR_HSI_CAL_SFT (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos) ///< Internal high-speed clock calibration
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_PLLCFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_PLLCFGR_PLLSRC_Pos (0)
+#define RCC_PLLCFGR_PLLSRC (0x01U << RCC_PLLCFGR_PLLSRC_Pos) ///< PLL entry clock source
+#define RCC_PLLCFGR_PLLXTPRE_Pos (1) ///<
+#define RCC_PLLCFGR_PLLXTPRE (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos) ///< HSE divider for PLL entry
+#define RCC_PLLCFGR_PLL_ICTRL_Pos (2)
+#define RCC_PLLCFGR_PLL_ICTRL (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos) ///< PLL CP current control signals
+#define RCC_PLLCFGR_PLL_LDS_Pos (4)
+#define RCC_PLLCFGR_PLL_LDS (0x03U << RCC_PLLCFGR_PLL_LDS_Pos) ///< PLL lock detector accuracy select
+#define RCC_PLLCFGR_PLL_DP_Pos (8) ///<
+#define RCC_PLLCFGR_PLL_DP (0x07U << RCC_PLLCFGR_PLL_DP_Pos) ///< PLL divider factor DP
+#define RCC_PLLCFGR_PLL_DN_Pos (16)
+#define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider factor DN
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_HSIDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_HSIDLY_HSI_EQU_CNT (0xFFU) ///< HSI delay time
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_HSEDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_HSEDLY_HSI_EQU_CNT (0xFFFFU) ///< HSE delay time
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_PLLDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_PLLDLY_HSI_EQU_CNT (0xFFU) ///< PLL delay time
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
new file mode 100644
index 00000000..7f8acab0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
@@ -0,0 +1,203 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_rtc.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_RTC_H
+#define __REG_RTC_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800) ///< Base Address: 0x40002800
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ union {
+ __IO u32 CR; ///< Control Register, offset: 0x00
+ __IO u32 CRH;
+ };
+ union {
+ __IO u32 CSR; ///< Control & Status Register, offset: 0x04
+ __IO u32 CRL;
+ };
+ __IO u32 PRLH; ///< Prescaler Reload Value High, offset: 0x08
+ __IO u32 PRLL; ///< Prescaler Reload Value Low, offset: 0x0C
+ __IO u32 DIVH; ///< Clock Divider High, offset: 0x10
+ __IO u32 DIVL; ///< Clock Divider Low, offset: 0x14
+ __IO u32 CNTH; ///< Counter High, offset: 0x18
+ __IO u32 CNTL; ///< Counter Low, offset: 0x1C
+ __IO u32 ALRH; ///< Alarm High, offset: 0x20
+ __IO u32 ALRL; ///< Alarm Low, offset: 0x24
+ __IO u32 MSRH; ///< Millisecond alarm high register offset: 0x28
+ __IO u32 MSRL; ///< Millisecond alarm low register offset: 0x2C
+ __IO u32 RESERVED0; ///< Reserved offset: 0x30
+ __IO u32 RESERVED1; ///< Reserved offset: 0x34
+ __IO u32 RESERVED2; ///< Reserved offset: 0x38
+ __IO u32 LSE_CFG; ///< LSE configure register offset: 0x3C
+} RTC_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC ((RTC_TypeDef*)RTC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CR_SECIE_Pos (0)
+#define RTC_CR_SECIE (0x01U << RTC_CR_SECIE_Pos) ///< Second Interrupt Enable
+#define RTC_CR_ALRIE_Pos (1)
+#define RTC_CR_ALRIE (0x01U << RTC_CR_ALRIE_Pos) ///< Alarm Interrupt Enable
+#define RTC_CR_OWIE_Pos (2)
+#define RTC_CR_OWIE (0x01U << RTC_CR_OWIE_Pos) ///< OverfloW Interrupt Enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CSR_SECF_Pos (0)
+#define RTC_CSR_SECF (0x01 << RTC_CSR_SECF_Pos) ///< Second Flag
+#define RTC_CSR_ALRF_Pos (1)
+#define RTC_CSR_ALRF (0x01 << RTC_CSR_ALRF_Pos) ///< Alarm Flag
+#define RTC_CSR_OWF_Pos (2)
+#define RTC_CSR_OWF (0x01 << RTC_CSR_OWF_Pos) ///< OverfloW Flag
+#define RTC_CSR_RSF_Pos (3)
+#define RTC_CSR_RSF (0x01 << RTC_CSR_RSF_Pos) ///< Registers Synchronized Flag
+#define RTC_CSR_CNF_Pos (4)
+#define RTC_CSR_CNF (0x01 << RTC_CSR_CNF_Pos) ///< Configuration Flag
+#define RTC_CSR_RTOFF_Pos (5)
+#define RTC_CSR_RTOFF (0x01 << RTC_CSR_RTOFF_Pos) ///< RTC operation OFF
+#define RTC_CSR_ALPEN_Pos (6)
+#define RTC_CSR_ALPEN (0x01 << RTC_CSR_ALPEN_Pos) ///< RTC Alarm Loop Enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_PRLH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_PRLH_PRL_Pos (0)
+#define RTC_PRLH_PRL (0x0F << RTC_PRLH_PRL_Pos) ///< RTC Prescaler Reload Value High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_PRLL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_PRLL_PRL_Pos (0)
+#define RTC_PRLL_PRL (0xFFFFU << RTC_PRLL_PRL_Pos) ///< RTC Prescaler Reload Value Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_DIVH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_DIVH_DIV_Pos (0)
+#define RTC_DIVH_DIV (0x0F << RTC_DIVH_DIV_Pos) ///< RTC Clock Divider High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_DIVL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_DIVL_DIV_Pos (0)
+#define RTC_DIVL_DIV (0xFFFFU << RTC_DIVL_DIV_Pos) ///< RTC Clock Divider Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CNTH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CNTH_CNT_Pos (0)
+#define RTC_CNTH_CNT (0xFFFFU << RTC_CNTH_CNT_Pos) ///< RTC Counter High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CNTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CNTL_CNT_Pos (0)
+#define RTC_CNTL_CNT (0xFFFFU << RTC_CNTL_CNT_Pos) ///< RTC Counter Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_ALRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_ALRH_ALR_Pos (0)
+#define RTC_ALRH_ALR (0xFFFFU << RTC_ALRH_ALR_Pos) ///< RTC Alarm High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_ALRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_ALRL_ALR_Pos (0)
+#define RTC_ALRL_ALR (0xFFFFU << RTC_ALRL_ALR_Pos) ///< RTC Alarm Low
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_MSRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_MSRH_MSR_Pos (0)
+#define RTC_MSRH_MSR (0xFFFFU << RTC_MSRH_MSR_Pos) ///< RTC MS Alarm Register High
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_MSRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_MSRL_MSR_Pos (0)
+#define RTC_MSRL_MSR (0xFFFFU << RTC_MSRL_MSR_Pos) ///< RTC MS Alarm Register Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_LSE_CFG Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define RTC_LSE_CFG_TEST_Pos (0)
+#define RTC_LSE_CFG_TEST (0x0FU << RTC_LSE_CFG_TEST_Pos) ///< Test control signal
+#define RTC_LSE_CFG_DR_Pos (4)
+#define RTC_LSE_CFG_DR (0x03U << RTC_LSE_CFG_DR_Pos) ///< Drive capability selection
+#define RTC_LSE_CFG_RFB_SEL_Pos (6)
+#define RTC_LSE_CFG_RFB_SEL_3 (0x03U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 3M
+#define RTC_LSE_CFG_RFB_SEL_6 (0x02U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 6M
+#define RTC_LSE_CFG_RFB_SEL_10 (0x01U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 10M
+#define RTC_LSE_CFG_RFB_SEL_12 (0x00U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 12M
+#define RTC_LSE_CFG_IB_Pos (8)
+#define RTC_LSE_CFG_IB (0x01U << RTC_MSRL_MSR_Pos) ///< Bias current regulation
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
new file mode 100644
index 00000000..9c5d0cb6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
@@ -0,0 +1,391 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_sdio.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_SDIO_H
+#define __REG_SDIO_H
+
+// Files includes
+
+#include
+#include
+//#include "types.h"
+#include "mm32_reg.h"
+
+//#if defined ( __CC_ARM )
+//#pragma anon_unions
+//#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_BASE (0x40018000U) ///< Base Address: 0x40018000
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ __IO u32 MMC_CTRL; ///< SDIO transmit data register, offset: 0x00
+ __IO u32 MMC_IO; ///< SDIO receive data register, offset: 0x04
+ __IO u32 MMC_BYTECNTL; ///< SDIO current state register, offset: 0x08
+ __IO u32 MMC_TR_BLOCKCNT; ///< SDIO interruput state register, offset: 0x0C
+ __IO u32 MMC_CRCCTL; ///< SDIO interruput enable register, offset: 0x10
+ __IO u32 CMD_CRC; ///< SDIO interruput control register, offset: 0x14
+ __IO u32 DAT_CRCL; ///< SDIO global control register, offset: 0x18
+ __IO u32 DAT_CRCH; ///< SDIO common control register, offset: 0x1C
+ __IO u32 MMC_PORT; ///< SDIO baud rate control register, offset: 0x20
+ __IO u32 MMC_INT_MASK; ///< SDIO receive data number register, offset: 0x24
+ __IO u32 CLR_MMC_INT; ///< SDIO chip select register, offset: 0x28
+ __IO u32 MMC_CARDSEL; ///< SDIO extand control register, offset: 0x2C
+ __IO u32 MMC_SIG; ///< 0ffset: 0x30
+ __IO u32 MMC_IO_MBCTL; ///< 0ffset: 0x34
+ __IO u32 MMC_BLOCKCNT; ///< 0ffset: 0x38
+ __IO u32 MMC_TIMEOUTCNT; ///< 0ffset: 0x3C
+ __IO u32 CMD_BUF0; ///< 0ffset: 0x40
+ __IO u32 CMD_BUF1; ///< 0ffset: 0x44
+ __IO u32 CMD_BUF2; ///< 0ffset: 0x48
+ __IO u32 CMD_BUF3; ///< 0ffset: 0x4C
+ __IO u32 CMD_BUF4; ///< 0ffset: 0x50
+ __IO u32 CMD_BUF5; ///< 0ffset: 0x54
+ __IO u32 CMD_BUF6; ///< 0ffset: 0x58
+ __IO u32 CMD_BUF7; ///< 0ffset: 0x5C
+ __IO u32 CMD_BUF8; ///< 0ffset: 0x60
+ __IO u32 CMD_BUF9; ///< 0ffset: 0x64
+ __IO u32 CMD_BUF10; ///< 0ffset: 0x68
+ __IO u32 CMD_BUF11; ///< 0ffset: 0x6C
+ __IO u32 CMD_BUF12; ///< 0ffset: 0x70
+ __IO u32 CMD_BUF13; ///< 0ffset: 0x74
+ __IO u32 CMD_BUF14; ///< 0ffset: 0x78
+ __IO u32 CMD_BUF15; ///< 0ffset: 0x7C
+ __IO u32 BUF_CTL; ///< 0ffset: 0x80
+
+ __IO u32 RESERVED[31]; ///< 0ffset: 0x84
+ union {
+ __IO u32 DATA_BUF0; ///< 0ffset: 0x100
+ __IO u32 FIFO;
+ };
+ __IO u32 DATA_BUF1; ///< 0ffset: 0x104
+ __IO u32 DATA_BUF2; ///< 0ffset: 0x108
+ __IO u32 DATA_BUF3; ///< 0ffset: 0x10C
+ __IO u32 DATA_BUF4; ///< 0ffset: 0x110
+} SDIO_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO ((SDIO_TypeDef*) SDIO_BASE)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_CTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_CTRL_OPMSel_Pos (0)
+#define SDIO_MMC_CTRL_OPMSel (0x01U << SDIO_MMC_CTRL_OPMSel_Pos) ///< SD/MMC/SDIO port operation mode select
+#define SDIO_MMC_CTRL_SelSM_Pos (1)
+#define SDIO_MMC_CTRL_SelSM (0x01U << SDIO_MMC_CTRL_SelSM_Pos) ///< Select automatic mode
+#define SDIO_MMC_CTRL_OUTM_Pos (2)
+#define SDIO_MMC_CTRL_OUTM (0x01U << SDIO_MMC_CTRL_OUTM_Pos) ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain
+#define SDIO_MMC_CTRL_CLKSP_Pos (3)
+#define SDIO_MMC_CTRL_CLKSP2 (0x00U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/2 baseclock
+#define SDIO_MMC_CTRL_CLKSP4 (0x01U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/4 baseclock
+#define SDIO_MMC_CTRL_CLKSP6 (0x02U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/6 baseclock
+#define SDIO_MMC_CTRL_CLKSP8 (0x03U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/8 baseclock
+#define SDIO_MMC_CTRL_CLKSP10 (0x04U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock
+#define SDIO_MMC_CTRL_CLKSP12 (0x05U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock
+#define SDIO_MMC_CTRL_CLKSP14 (0x06U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock
+#define SDIO_MMC_CTRL_CLKSP16 (0x07U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock
+#define SDIO_MMC_CTRL_SelPTSM_Pos (6)
+#define SDIO_MMC_CTRL_SelPTSM (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos) ///< SelectSD/MMC/SDIO port transfer high speed mode
+#define SDIO_MMC_CTRL_DATWT_Pos (7)
+#define SDIO_MMC_CTRL_DATWT (0x01U << SDIO_MMC_CTRL_DATWT_Pos) ///< Definethe bus width of SD/MMC/SDIO port DAT line
+#define SDIO_MMC_CTRL_MDEN_Pos (8)
+#define SDIO_MMC_CTRL_MDEN (0x01U << SDIO_MMC_CTRL_MDEN_Pos) ///< SDIO mode enable
+#define SDIO_MMC_CTRL_INTEN_Pos (9)
+#define SDIO_MMC_CTRL_INTEN (0x01U << SDIO_MMC_CTRL_INTEN_Pos) ///< SDIO interrupt enale signal
+#define SDIO_MMC_CTRL_RDWTEN_Pos (10)
+#define SDIO_MMC_CTRL_RDWTEN (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos) ///< SDIO read wait enable signal
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_IO Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_IO_AUTODATTR_Pos (0)
+#define SDIO_MMC_IO_AUTODATTR (0x01U << SDIO_MMC_IO_AUTODATTR_Pos) ///< Set up automatic data transfer
+#define SDIO_MMC_IO_TRANSFDIR_Pos (1)
+#define SDIO_MMC_IO_TRANSFDIR (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos) ///< Set the direction of data transfer
+#define SDIO_MMC_IO_AUTOTR_Pos (2)
+#define SDIO_MMC_IO_AUTOTR (0x01U << SDIO_MMC_IO_AUTOTR_Pos) ///< Set up automatic 8-bit/command/response transmission.
+#define SDIO_MMC_IO_RESPCMDSEL_Pos (3)
+#define SDIO_MMC_IO_RESPCMDSEL (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos) ///< Receive response
+#define SDIO_MMC_IO_CID_CSDRD_Pos (4)
+#define SDIO_MMC_IO_CID_CSDRD (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos) ///< CID and CSD reads
+#define SDIO_MMC_IO_PCLKG_Pos (5)
+#define SDIO_MMC_IO_PCLKG (0x01U << SDIO_MMC_IO_PCLKG_Pos) ///< SD/MMC/SDIO port CLK line 8 empty clock generated
+#define SDIO_MMC_IO_ENRRESP_Pos (6)
+#define SDIO_MMC_IO_ENRRESP (0x01U << SDIO_MMC_IO_ENRRESP_Pos) ///< Enable automatic receiving of responses after a command
+#define SDIO_MMC_IO_AUTOCLKG_Pos (7)
+#define SDIO_MMC_IO_AUTOCLKG (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos) ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data
+#define SDIO_MMC_IO_CMDCH_Pos (8)
+#define SDIO_MMC_IO_CMDCH (0x01U << SDIO_MMC_IO_CMDCH_Pos) ///< SDIO mode enable
+#define SDIO_MMC_IO_CMDAF_Pos (9)
+#define SDIO_MMC_IO_CMDAF (0x01U << SDIO_MMC_IO_CMDAF_Pos) ///< SDIO CMD12 / IO abort flag
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_BYTECNTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_BYTECNTL_CNT (0xFFFFU) ///< Data transfer byte count register
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_TR_BLOCKCNT_CNT (0xFFFFU) ///< The value of the counter that completes the transfer when multiple blocks are transferred.
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_CRCCTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_CRCCTL_DAT_CRCE_Pos (0)
+#define SDIO_MMC_CRCCTL_DAT_CRCE (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos) ///< DAT CRC error
+#define SDIO_MMC_CRCCTL_CMD_CRCE_Pos (1)
+#define SDIO_MMC_CRCCTL_CMD_CRCE (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos) ///< CMD CRC error
+#define SDIO_MMC_CRCCTL_DAT_CRCS_Pos (2)
+#define SDIO_MMC_CRCCTL_DAT_CRCS (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos) ///< DAT CRC selection
+#define SDIO_MMC_CRCCTL_ENRDMB_Pos (4)
+#define SDIO_MMC_CRCCTL_ENRDMB (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos) ///< Enable reading multiple blocks of data before responding
+#define SDIO_MMC_CRCCTL_ENCHK_Pos (5)
+#define SDIO_MMC_CRCCTL_ENCHK (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos) ///< Enable automatic checking
+#define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos (6)
+#define SDIO_MMC_CRCCTL_DAT_CRCEN (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos) ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement
+#define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos (7)
+#define SDIO_MMC_CRCCTL_CMD_CRCEN (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos) ///< SD/MMC/SDIO port CMD line CRC circuit enablement
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_CRC Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_CRC_CMD_CRCV (0x7FU) ///< CMD_CRCV register value
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_DAT_CRCL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_DAT_CRCL_DAT_CRCLV (0xFFU) ///< CMD_CRCV low register value
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_DAT_CRCH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_DAT_CRCL_DAT_CRCHV (0xFFU) ///< CMD_CRCV high register value
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_PORT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_PORT_NTCR_Pos (0)
+#define SDIO_MMC_PORT_NTCR (0x0FU << SDIO_MMC_PORT_NTCR_Pos) ///< Ncr timeout count register
+#define SDIO_MMC_PORT_AUTONTEN_Pos (4)
+#define SDIO_MMC_PORT_AUTONTEN (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos) ///< Automatic Ncr timer output enablement
+#define SDIO_MMC_PORT_PDATS_Pos (5)
+#define SDIO_MMC_PORT_PDATS (0x01U << SDIO_MMC_PORT_PDATS_Pos) ///< SD/MMC/SDIO port DAT line signal
+#define SDIO_MMC_PORT_PCMDS_Pos (6)
+#define SDIO_MMC_PORT_PCMDS (0x01U << SDIO_MMC_PORT_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal
+#define SDIO_MMC_PORT_PCLKS_Pos (7)
+#define SDIO_MMC_PORT_PCLKS (0x01U << SDIO_MMC_PORT_PCLKS_Pos) ///< SD/MMC/SDIO port CLK line signal
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_INT_MASK Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_INT_MASK_CMDDINT_Pos (0)
+#define SDIO_MMC_INT_MASK_CMDDINT (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos) ///© COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_SPI_H
+#define __REG_SPI_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) ///< Base Address: 0x40003800
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) ///< Base Address: 0x400013000
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) ///< Base Address: 0x40003C000
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+#undef USENCOMBINEREGISTER
+#undef USENNEWREGISTER
+#undef USENOLDREGISTER
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+typedef struct {
+ union {
+ __IO u32 TDR; ///< SPI transmit data register, offset: 0x00
+ __IO u32 TXREG;
+ };
+ union {
+ __IO u32 RDR; ///< SPI receive data register, offset: 0x04
+ __IO u32 RXREG;
+ };
+ union {
+ __IO u32 SR; ///< SPI current state register, offset: 0x08
+ __IO u32 CSTAT;
+ };
+ union {
+ __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C
+ __IO u32 INTSTAT;
+ };
+ union {
+ __IO u32 IER; ///< SPI interruput enable register, offset: 0x10
+ __IO u32 INTEN;
+ };
+ union {
+ __IO u32 ICR; ///< SPI interruput control register, offset: 0x14
+ __IO u32 INTCLR;
+ };
+ union {
+ __IO u32 GCR; ///< SPI global control register, offset: 0x18
+ __IO u32 GCTL;
+ };
+ union {
+ __IO u32 CCR; ///< SPI common control register, offset: 0x1C
+ __IO u32 CCTL;
+ };
+ union {
+ __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20
+ __IO u32 SPBRG;
+ };
+ union {
+ __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24
+ __IO u32 RXDNR;
+ };
+ union {
+ __IO u32 NSSR; ///< SPI chip select register, offset: 0x28
+ __IO u32 SCSR;
+ };
+ union {
+ __IO u32 ECR; ///< SPI extand control register, offset: 0x2C
+ __IO u32 EXTCTL;
+ };
+ __IO u32 CFGR; ///< I2S configuration register, offset: 0x30
+} SPI_TypeDef;
+#endif
+#ifdef USENNEWREGISTER
+typedef struct {
+ __IO u32 TDR; ///< SPI transmit data register, offset: 0x00
+ __IO u32 RDR; ///< SPI receive data register, offset: 0x04
+ __IO u32 SR; ///< SPI current state register, offset: 0x08
+ __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C
+ __IO u32 IER; ///< SPI interruput enable register, offset: 0x10
+ __IO u32 ICR; ///< SPI interruput control register, offset: 0x14
+ __IO u32 GCR; ///< SPI global control register, offset: 0x18
+ __IO u32 CCR; ///< SPI common control register, offset: 0x1C
+ __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20
+ __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24
+ __IO u32 NSSR; ///< SPI chip select register, offset: 0x28
+ __IO u32 ECR; ///< SPI extand control register, offset: 0x2C
+} SPI_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+ __IO u32 TXREG; ///< SPI transmit data register, offset: 0x00
+ __IO u32 RXREG; ///< SPI receive data register, offset: 0x04
+ __IO u32 CSTAT; ///< SPI current state register, offset: 0x08
+ __IO u32 INTSTAT; ///< SPI interruput state register, offset: 0x0C
+ __IO u32 INTEN; ///< SPI interruput enable register, offset: 0x10
+ __IO u32 INTCLR; ///< SPI interruput control register, offset: 0x14
+ __IO u32 GCTL; ///< SPI global control register, offset: 0x18
+ __IO u32 CCTL; ///< SPI common control register, offset: 0x1C
+ __IO u32 SPBRG; ///< SPI baud rate control register, offset: 0x20
+ __IO u32 RXDNR; ///< SPI receive data number register, offset: 0x24
+ __IO u32 NSSR; ///< SPI chip select register, offset: 0x28
+ __IO u32 EXTCTL; ///< SPI extand control register, offset: 0x2C
+} SPI_TypeDef;
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI2 ((SPI_TypeDef*) SPI2_BASE)
+#define SPI1 ((SPI_TypeDef*) SPI1_BASE)
+#define SPI3 ((SPI_TypeDef*) SPI3_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_TDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_TDR_TXREG_Pos (0)
+#define SPI_TDR_TXREG (0xFFFFFFFFU << SPI_TDR_TXREG_Pos) ///< Transmit data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_RDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_RDR_RXREG_Pos (0)
+#define SPI_RDR_RXREG (0xFFFFFFFFU << SPI_RDR_RXREG_Pos) ///< Receive data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_SR_TXEPT_Pos (0)
+#define SPI_SR_TXEPT (0x01U << SPI_SR_TXEPT_Pos) ///< Transmitter empty bit
+#define SPI_SR_RXAVL_Pos (1)
+#define SPI_SR_RXAVL (0x01U << SPI_SR_RXAVL_Pos) ///< Receive available byte data message
+#define SPI_SR_TXFULL_Pos (2)
+#define SPI_SR_TXFULL (0x01U << SPI_SR_TXFULL_Pos) ///< Transmitter FIFO full status bit
+#define SPI_SR_RXAVL_4BYTE_Pos (3)
+#define SPI_SR_RXAVL_4BYTE (0x01U << SPI_SR_RXAVL_4BYTE_Pos) ///< Receive available 4 byte data message
+#define SPI_SR_TXFADDR_Pos (4)
+#define SPI_SR_TXFADDR (0x0FU << SPI_SR_TXFADDR_Pos) ///< Transmit FIFO address
+#define SPI_SR_RXFADDR_Pos (8)
+#define SPI_SR_RXFADDR (0x0FU << SPI_SR_RXFADDR_Pos) ///< Receive FIFO address
+#define SPI_SR_BUSY_Pos (12)
+#define SPI_SR_BUSY (0x01U << SPI_SR_BUSY_Pos) ///< Data transfer flag
+#define SPI_SR_CHSIDE_Pos (13)
+#define SPI_SR_CHSIDE (0x01U << SPI_SR_CHSIDE_Pos) ///< transmission channel
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_ISR_TX_INTF_Pos (0)
+#define SPI_ISR_TX_INTF (0x01U << SPI_ISR_TX_INTF_Pos) ///< Transmit FIFO available interrupt flag bit
+#define SPI_ISR_RX_INTF_Pos (1)
+#define SPI_ISR_RX_INTF (0x01U << SPI_ISR_RX_INTF_Pos) ///< Receive data available interrupt flag bit
+#define SPI_ISR_UNDERRUN_INTF_Pos (2)
+#define SPI_ISR_UNDERRUN_INTF (0x01U << SPI_ISR_UNDERRUN_INTF_Pos) ///< SPI underrun interrupt flag bit
+#define SPI_ISR_RXOERR_INTF_Pos (3)
+#define SPI_ISR_RXOERR_INTF (0x01U << SPI_ISR_RXOERR_INTF_Pos) ///< Receive overrun error interrupt flag bit
+#define SPI_ISR_RXMATCH_INTF_Pos (4)
+#define SPI_ISR_RXMATCH_INTF (0x01U << SPI_ISR_RXMATCH_INTF_Pos) ///< Receive data match the RXDNR number, the receive process will be completed and generate the interrupt
+#define SPI_ISR_RXFULL_INTF_Pos (5)
+#define SPI_ISR_RXFULL_INTF (0x01U << SPI_ISR_RXFULL_INTF_Pos) ///< RX FIFO full interrupt flag bit
+#define SPI_ISR_TXEPT_INTF_Pos (6)
+#define SPI_ISR_TXEPT_INTF (0x01U << SPI_ISR_TXEPT_INTF_Pos) ///< Transmitter empty interrupt flag bit
+#define SPI_ISR_FRE_INTF_Pos (7)
+#define SPI_ISR_FRE_INTF (0x01U << SPI_ISR_FRE_INTF_Pos) ///< I2S frame transmission error flag bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_IER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_IER_TX_IEN_Pos (0)
+#define SPI_IER_TX_IEN (0x01U << SPI_IER_TX_IEN_Pos) ///< Transmit FIFO empty interrupt enable bit
+#define SPI_IER_RX_IEN_Pos (1)
+#define SPI_IER_RX_IEN (0x01U << SPI_IER_RX_IEN_Pos) ///< Receive FIFO interrupt enable bit
+#define SPI_IER_UNDERRUN_IEN_Pos (2)
+#define SPI_IER_UNDERRUN_IEN (0x01U << SPI_IER_UNDERRUN_IEN_Pos) ///< Transmitter underrun interrupt enable bit
+#define SPI_IER_RXOERR_IEN_Pos (3)
+#define SPI_IER_RXOERR_IEN (0x01U << SPI_IER_RXOERR_IEN_Pos) ///< Overrun error interrupt enable bit
+#define SPI_IER_RXMATCH_IEN_Pos (4)
+#define SPI_IER_RXMATCH_IEN (0x01U << SPI_IER_RXMATCH_IEN_Pos) ///< Receive data complete interrupt enable bit
+#define SPI_IER_RXFULL_IEN_Pos (5)
+#define SPI_IER_RXFULL_IEN (0x01U << SPI_IER_RXFULL_IEN_Pos) ///< Receive FIFO full interrupt enable bit
+#define SPI_IER_TXEPT_IEN_Pos (6)
+#define SPI_IER_TXEPT_IEN (0x01U << SPI_IER_TXEPT_IEN_Pos) ///< Transmit empty interrupt enable bit
+#define SPI_IER_FRE_IEN_Pos (7)
+#define SPI_IER_FRE_IEN (0x01U << SPI_IER_FRE_IEN_Pos) ///< I2S frame transmission interrupt enable bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_ICR_TX_ICLR_Pos (0)
+#define SPI_ICR_TX_ICLR (0x01U << SPI_ICR_TX_ICLR_Pos) ///< Transmitter FIFO empty interrupt clear bit
+#define SPI_ICR_RX_ICLR_Pos (1)
+#define SPI_ICR_RX_ICLR (0x01U << SPI_ICR_RX_ICLR_Pos) ///< Receive interrupt clear bit
+#define SPI_ICR_UNDERRUN_ICLR_Pos (2)
+#define SPI_ICR_UNDERRUN_ICLR (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos) ///< Transmitter underrun interrupt clear bit
+#define SPI_ICR_RXOERR_ICLR_Pos (3)
+#define SPI_ICR_RXOERR_ICLR (0x01U << SPI_ICR_RXOERR_ICLR_Pos) ///< Overrun error interrupt clear bit
+#define SPI_ICR_RXMATCH_ICLR_Pos (4)
+#define SPI_ICR_RXMATCH_ICLR (0x01U << SPI_ICR_RXMATCH_ICLR_Pos) ///< Receive completed interrupt clear bit
+#define SPI_ICR_RXFULL_ICLR_Pos (5)
+#define SPI_ICR_RXFULL_ICLR (0x01U << SPI_ICR_RXFULL_ICLR_Pos) ///< Receiver buffer full interrupt clear bit
+#define SPI_ICR_TXEPT_ICLR_Pos (6)
+#define SPI_ICR_TXEPT_ICLR (0x01U << SPI_ICR_TXEPT_ICLR_Pos) ///< Transmitter empty interrupt clear bit
+#define SPI_ICR_FRE_ICLR_Pos (7)
+#define SPI_ICR_FRE_ICLR (0x01U << SPI_ICR_FRE_ICLR_Pos) ///< I2S frame transmission interrupt clear bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_GCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_GCR_SPIEN_Pos (0)
+#define SPI_GCR_SPIEN (0x01U << SPI_GCR_SPIEN_Pos) ///< SPI select bit
+#define SPI_GCR_IEN_Pos (1)
+#define SPI_GCR_IEN (0x01U << SPI_GCR_IEN_Pos) ///< SPI interrupt enable bit
+#define SPI_GCR_MODE_Pos (2)
+#define SPI_GCR_MODE (0x01U << SPI_GCR_MODE_Pos) ///< Master mode bit
+#define SPI_GCR_TXEN_Pos (3)
+#define SPI_GCR_TXEN (0x01U << SPI_GCR_TXEN_Pos) ///< Transmit enable bit
+#define SPI_GCR_RXEN_Pos (4)
+#define SPI_GCR_RXEN (0x01U << SPI_GCR_RXEN_Pos) ///< Receive enable bit
+
+#define SPI_GCR_RXTLF_Pos (5)
+#define SPI_GCR_RXTLF (0x03U << SPI_GCR_RXTLF_Pos) ///< RX FIFO trigger level bit
+#define SPI_GCR_RXTLF_One (0x00U << SPI_GCR_RXTLF_Pos) ///<
+#define SPI_GCR_RXTLF_Half (0x01U << SPI_GCR_RXTLF_Pos) ///<
+
+#define SPI_GCR_TXTLF_Pos (7)
+#define SPI_GCR_TXTLF (0x03U << SPI_GCR_TXTLF_Pos) ///< TX FIFO trigger level bit
+#define SPI_GCR_TXTLF_One (0x00U << SPI_GCR_TXTLF_Pos) ///<
+#define SPI_GCR_TXTLF_Half (0x01U << SPI_GCR_TXTLF_Pos) ///<
+#define SPI_GCR_DMAEN_Pos (9)
+#define SPI_GCR_DMAEN (0x01U << SPI_GCR_DMAEN_Pos) ///< DMA access mode enable
+#define SPI_GCR_NSS_Pos (10)
+#define SPI_GCR_NSS (0x01U << SPI_GCR_NSS_Pos) ///< NSS select signal that from software or hardware
+#define SPI_GCR_DWSEL_Pos (11)
+#define SPI_GCR_DWSEL (0x01U << SPI_GCR_DWSEL_Pos) ///< Valid byte or double-word data select signal
+
+#define SPI_GCR_NSSTOG_Pos (12)
+#define SPI_GCR_NSSTOG (0x01U << SPI_GCR_NSSTOG_Pos) ///< Slave select toggle
+#define SPI_GCR_PAD_SEL_Pos (13)
+#define SPI_GCR_PAD_SEL (0x1FU << SPI_GCR_PAD_SEL_Pos) ///< Bus mapping transformation
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_CCR_CPHA_Pos (0)
+#define SPI_CCR_CPHA (0x01U << SPI_CCR_CPHA_Pos) ///< Clock phase select bit
+#define SPI_CCR_CPOL_Pos (1)
+#define SPI_CCR_CPOL (0x01U << SPI_CCR_CPOL_Pos) ///< Clock polarity select bit
+#define SPI_CCR_LSBFE_Pos (2)
+#define SPI_CCR_LSBFE (0x01U << SPI_CCR_LSBFE_Pos) ///< LSI first enable bit
+#define SPI_CCR_SPILEN_Pos (3)
+#define SPI_CCR_SPILEN (0x01U << SPI_CCR_SPILEN_Pos) ///< SPI character length bit
+#define SPI_CCR_RXEDGE_Pos (4)
+#define SPI_CCR_RXEDGE (0x01U << SPI_CCR_RXEDGE_Pos) ///< Receive data edge select
+#define SPI_CCR_TXEDGE_Pos (5)
+#define SPI_CCR_TXEDGE (0x01U << SPI_CCR_TXEDGE_Pos) ///< Transmit data edge select
+
+#define SPI_CCR_CPHASEL_Pos (6)
+#define SPI_CCR_CPHASEL (0x01U << SPI_CCR_CPHASEL) ///< CPHA polarity select
+
+#define SPI_CCR_HISPD_Pos (7)
+#define SPI_CCR_HISPD (0x01U << SPI_CCR_HISPD) ///< High speed slave mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_BRR_DIVF_Pos (0)
+#define SPI_BRR_DIVF (0xFFFFU << SPI_BRR_DIVF_Pos) ///< SPI baud rate control register for baud rate
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_RDNR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_RDNR_RDN_Pos (0)
+#define SPI_RDNR_RDN (0xFFFFU << SPI_RDNR_RDN_Pos) ///< The register is used to hold a count of to be received bytes in next receive process
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_NSSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_NSSR_NSS_Pos (0)
+#define SPI_NSSR_NSS (0xFFU << SPI_NSSR_NSS_Pos) ///< Chip select output signal in Master mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_ECR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_ECR_EXTLEN_Pos (0)
+#define SPI_ECR_EXTLEN (0x1FU << SPI_ECR_EXTLEN_Pos) ///< control SPI data length
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2S_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define I2SCFGR_CLEAR_Mask ((u32)0xFE00F388)
+#define I2S_CFGR_CHLEN_Pos (0)
+#define I2S_CFGR_CHLEN (0x01U << I2S_CFGR_CHLEN_Pos) ///< Vocal tract length
+#define I2S_CFGR_DATLEN_Pos (1)
+#define I2S_CFGR_DATLEN_16 (0x00U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 16
+#define I2S_CFGR_DATLEN_24 (0x01U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 24
+#define I2S_CFGR_DATLEN_32 (0x02U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 32
+
+#define I2S_CFGR_I2SSTD_Pos (4)
+#define I2S_CFGR_I2SSTD_PCM (0x00U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection PCM standard
+#define I2S_CFGR_I2SSTD_MSB_R (0x01U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Right alignment (MSB) standard
+#define I2S_CFGR_I2SSTD_MSB_L (0x02U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Left aligned (MSB) standard
+#define I2S_CFGR_I2SSTD_Philips (0x03U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Philips standard
+
+#define I2S_CFGR_PCMSYNC_Pos (6)
+#define I2S_CFGR_PCMSYNC (0x01U << I2S_CFGR_PCMSYNC_Pos) ///< PCM frame synchronization mode
+#define I2S_CFGR_SPI_I2S_Pos (10)
+#define I2S_CFGR_SPI_I2S (0x01U << I2S_CFGR_SPI_I2S_Pos) ///< SPI/I2S module function selection
+#define I2S_CFGR_MCKOE_Pos (11)
+#define I2S_CFGR_MCKOE (0x01U << I2S_CFGR_MCKOE_Pos) ///< I2S master clock output enable
+#define I2S_CFGR_I2SDIV_Pos (16)
+#define I2S_CFGR_I2SDIV (0x1FFU << I2S_CFGR_I2SDIV_Pos) ///< The frequency division
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
new file mode 100644
index 00000000..677250dc
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
@@ -0,0 +1,299 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_syscfg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_SYSCFG_H
+#define __REG_SYSCFG_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SysTem Configuration Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ union {
+ __IO u32 CFGR; ///< SYSCFG configuration register offset: 0x00
+ __IO u32 CFGR1;
+ };
+ __IO u32 RESERVED0x04; ///< RESERVED register offset: 0x04
+ __IO u32 EXTICR[4]; ///< SYSCFG configuration register offset: 0x08-0x14
+ __IO u32 CFGR2; ///< SYSCFG configuration2 register offset: 0x18
+ __IO u32 PDETCSR; ///< SYSCFG Power Detect configuration stautus reg offset: 0x1C
+ __IO u32 VOSDLY; ///< SYSCFG VOSDLY Counter register offset: 0x20
+} SYSCFG_TypeDef;
+
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+///@brief System Configuration (SYSCFG)
+////////////////////////////////////////////////////////////////////////////////
+
+/// @brief SYSCFG_CFGR Register Bit definition
+#define SYSCFG_CFGR_MEM_MODE_Pos (0)
+#define SYSCFG_CFGR_MEM_MODE ((u32)0x00000003) ///< SYSCFG_Memory Remap Config
+#define SYSCFG_CFGR_MEM_MODE_0 ((u32)0x00000001) ///< SYSCFG_Memory Remap Config Bit 0
+#define SYSCFG_CFGR_MEM_MODE_1 ((u32)0x00000002) ///< SYSCFG_Memory Remap Config Bit 1
+///
+
+#define SYSCFG_CFGR_FSMC_SYNC_EN_Pos (27)
+#define SYSCFG_CFGR_FSMC_SYNC_EN (0x01U << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable
+#define SYSCFG_CFGR_FSMC_AF_ADDR_Pos (28)
+#define SYSCFG_CFGR_FSMC_AF_ADDR (0x01U << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address
+#define SYSCFG_CFGR_FSMC_MODE_Pos (29)
+#define SYSCFG_CFGR_FSMC_MODE ((u32)0x03<© COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_TIM_H
+#define __REG_TIM_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) ///< Base Address: 0x40012C00
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) ///< Base Address: 0x40000000
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) ///< Base Address: 0x40000400
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ///< Base Address: 0x40000800
+
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) ///< Base Address: 0x40000C00
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) ///< Base Address: 0x40001000
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) ///< Base Address: 0x40001400
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) ///< Base Address: 0x40013400
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Timer Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 CR1; ///< TIM control register 1, offset: 0x00
+ __IO u32 CR2; ///< TIM control register 2, offset: 0x04
+ __IO u32 SMCR; ///< TIM slave Mode Control register, offset: 0x08
+ __IO u32 DIER; ///< TIM DMA/interrupt enable register, offset: 0x0C
+ __IO u32 SR; ///< TIM status register, offset: 0x10
+ __IO u32 EGR; ///< TIM event generation register, offset: 0x14
+ __IO u32 CCMR1; ///< TIM capture/compare mode register 1, offset: 0x18
+ __IO u32 CCMR2; ///< TIM capture/compare mode register 2, offset: 0x1C
+ __IO u32 CCER; ///< TIM capture/compare enable register, offset: 0x20
+ __IO u32 CNT; ///< TIM counter register, offset: 0x24
+ __IO u32 PSC; ///< TIM prescaler register, offset: 0x28
+ __IO u32 ARR; ///< TIM auto-reload register, offset: 0x2C
+ __IO u32 RCR; ///< TIM repetition counter register, offset: 0x30
+ __IO u32 CCR1; ///< TIM capture/compare register 1, offset: 0x34
+ __IO u32 CCR2; ///< TIM capture/compare register 2, offset: 0x38
+ __IO u32 CCR3; ///< TIM capture/compare register 3, offset: 0x3C
+ __IO u32 CCR4; ///< TIM capture/compare register 4, offset: 0x40
+ __IO u32 BDTR; ///< TIM break and dead-time register, offset: 0x44
+ __IO u32 DCR; ///< TIM DMA control register, offset: 0x48
+ __IO u32 DMAR; ///< TIM DMA address for full transfer register, offset: 0x4C
+ __IO u32 OR; ///< Option register, offset: 0x50
+ __IO u32 CCMR3; ///< TIM capture/compare mode register 3, offset: 0x54
+ __IO u32 CCR5; ///< TIM capture/compare register 5, offset: 0x58
+ __IO u32 PDER; ///< PWM Shift repeat enable register, offset: 0x5C
+ __IO u32 CCR1FALL; ///< PWM shift count CCR1 register, offset: 0x60
+ __IO u32 CCR2FALL; ///< PWM shift count CCR2 register, offset: 0x64
+ __IO u32 CCR3FALL; ///< PWM shift count CCR3 register, offset: 0x68
+ __IO u32 CCR4FALL; ///< PWM shift count CCR4 register, offset: 0x6c
+ __IO u32 CCR5FALL; ///< PWM shift count CCR5 register, offset: 0x70
+} TIM_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM1 ((TIM_TypeDef*) TIM1_BASE)
+#define TIM2 ((TIM_TypeDef*) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef*) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef*) TIM4_BASE)
+
+#define TIM5 ((TIM_TypeDef*) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef*) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef*) TIM7_BASE)
+
+#define TIM8 ((TIM_TypeDef*) TIM8_BASE)
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CR1_CEN_Pos (0)
+#define TIM_CR1_CEN (0x01U << TIM_CR1_CEN_Pos) ///< Counter enable
+#define TIM_CR1_UDIS_Pos (1)
+#define TIM_CR1_UDIS (0x01U << TIM_CR1_UDIS_Pos) ///< Update disable
+#define TIM_CR1_URS_Pos (2)
+#define TIM_CR1_URS (0x01U << TIM_CR1_URS_Pos) ///< Update request source
+#define TIM_CR1_OPM_Pos (3)
+#define TIM_CR1_OPM (0x01U << TIM_CR1_OPM_Pos) ///< One pulse mode
+#define TIM_CR1_DIR_Pos (4)
+#define TIM_CR1_DIR (0x01U << TIM_CR1_DIR_Pos) ///< Direction
+#define TIM_CR1_CMS_Pos (5)
+#define TIM_CR1_CMS (0x03U << TIM_CR1_CMS_Pos) ///< CMS[1:0] bits (Center-aligned mode selection)
+#define TIM_CR1_CMS_EDGEALIGNED (0x00U << TIM_CR1_CMS_Pos) ///< Edge-aligned mode
+#define TIM_CR1_CMS_CENTERALIGNED1 (0x01U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 1
+#define TIM_CR1_CMS_CENTERALIGNED2 (0x02U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 2
+#define TIM_CR1_CMS_CENTERALIGNED3 (0x03U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 3
+#define TIM_CR1_ARPEN_Pos (7)
+#define TIM_CR1_ARPEN (0x01U << TIM_CR1_ARPEN_Pos) ///< Auto-reload preload enable
+#define TIM_CR1_CKD_Pos (8)
+#define TIM_CR1_CKD (0x03U << TIM_CR1_CKD_Pos) ///< CKD[1:0] bits (clock division)
+#define TIM_CR1_CKD_DIV1 (0x00U << TIM_CR1_CKD_Pos) ///< Divided by 1
+#define TIM_CR1_CKD_DIV2 (0x01U << TIM_CR1_CKD_Pos) ///< Divided by 2
+#define TIM_CR1_CKD_DIV4 (0x02U << TIM_CR1_CKD_Pos) ///< Divided by 4
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CR2_CCPC_Pos (0)
+#define TIM_CR2_CCPC (0x01U << TIM_CR2_CCPC_Pos) ///< Capture/Compare Preloaded Control
+#define TIM_CR2_CCUS_Pos (2)
+#define TIM_CR2_CCUS (0x01U << TIM_CR2_CCUS_Pos) ///< Capture/Compare Control Update Selection
+#define TIM_CR2_CCDS_Pos (3)
+#define TIM_CR2_CCDS (0x01U << TIM_CR2_CCDS_Pos) ///< Capture/Compare DMA Selection
+#define TIM_CR2_MMS_Pos (4)
+#define TIM_CR2_MMS (0x07U << TIM_CR2_MMS_Pos) ///< MMS[2:0] bits (Master Mode Selection)
+#define TIM_CR2_MMS_RESET (0x00U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Reset
+#define TIM_CR2_MMS_ENABLE (0x01U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Enable
+#define TIM_CR2_MMS_UPDATE (0x02U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Update
+#define TIM_CR2_MMS_OC1 (0x03U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1
+#define TIM_CR2_MMS_OC1REF (0x04U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1Ref
+#define TIM_CR2_MMS_OC2REF (0x05U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC2Ref
+#define TIM_CR2_MMS_OC3REF (0x06U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC3Ref
+#define TIM_CR2_MMS_OC4REF (0x07U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC4Ref
+#define TIM_CR2_TI1S_Pos (7)
+#define TIM_CR2_TI1S (0x01U << TIM_CR2_TI1S_Pos) ///< TI1 Selection
+#define TIM_CR2_OIS1_Pos (8)
+#define TIM_CR2_OIS1 (0x01U << TIM_CR2_OIS1_Pos) ///< Output Idle state 1 (OC1 output)
+#define TIM_CR2_OIS1N_Pos (9)
+#define TIM_CR2_OIS1N (0x01U << TIM_CR2_OIS1N_Pos) ///< Output Idle state 1 (OC1N output)
+#define TIM_CR2_OIS2_Pos (10)
+#define TIM_CR2_OIS2 (0x01U << TIM_CR2_OIS2_Pos) ///< Output Idle state 2 (OC2 output)
+#define TIM_CR2_OIS2N_Pos (11)
+#define TIM_CR2_OIS2N (0x01U << TIM_CR2_OIS2N_Pos) ///< Output Idle state 2 (OC2N output)
+#define TIM_CR2_OIS3_Pos (12)
+#define TIM_CR2_OIS3 (0x01U << TIM_CR2_OIS3_Pos) ///< Output Idle state 3 (OC3 output)
+#define TIM_CR2_OIS3N_Pos (13)
+#define TIM_CR2_OIS3N (0x01U << TIM_CR2_OIS3N_Pos) ///< Output Idle state 3 (OC3N output)
+#define TIM_CR2_OIS4_Pos (14)
+#define TIM_CR2_OIS4 (0x01U << TIM_CR2_OIS4_Pos) ///< Output Idle state 4 (OC4 output)
+
+
+#define TIM_CR2_OIS5_Pos (16)
+#define TIM_CR2_OIS5 (0x01U << TIM_CR2_OIS5_Pos) ///< Output Idle state 5 (OC5 output)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_SMCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_SMCR_SMS_Pos (0)
+#define TIM_SMCR_SMS (0x07U << TIM_SMCR_SMS_Pos) ///< SMS[2:0] bits (Slave mode selection)
+#define TIM_SMCR_SMS_OFF (0x00U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: OFF
+#define TIM_SMCR_SMS_ENCODER1 (0x01U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder1
+#define TIM_SMCR_SMS_ENCODER2 (0x02U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder2
+#define TIM_SMCR_SMS_ENCODER3 (0x03U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder3
+#define TIM_SMCR_SMS_RESET (0x04U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Reset
+#define TIM_SMCR_SMS_GATED (0x05U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Gated
+#define TIM_SMCR_SMS_TRIGGER (0x06U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Trigger
+#define TIM_SMCR_SMS_EXTERNAL1 (0x07U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: External1
+
+#define TIM_SMCR_OCCS_Pos (3)
+#define TIM_SMCR_OCCS (0x01U << TIM_SMCR_OCCS_Pos) ///< Output compare clear selection
+
+#define TIM_SMCR_TS_Pos (4)
+#define TIM_SMCR_TS (0x07U << TIM_SMCR_TS_Pos) ///< TS[2:0] bits (Trigger selection)
+#define TIM_SMCR_TS_ITR0 (0x00U << TIM_SMCR_TS_Pos) ///< Internal Trigger 0 (ITR0)
+#define TIM_SMCR_TS_ITR1 (0x01U << TIM_SMCR_TS_Pos) ///< Internal Trigger 1 (ITR1)
+#define TIM_SMCR_TS_ITR2 (0x02U << TIM_SMCR_TS_Pos) ///< Internal Trigger 2 (ITR2)
+#define TIM_SMCR_TS_ITR3 (0x03U << TIM_SMCR_TS_Pos) ///< Internal Trigger 3 (ITR3)
+#define TIM_SMCR_TS_TI1F_ED (0x04U << TIM_SMCR_TS_Pos) ///< TI1 Edge Detector (TI1F_ED)
+#define TIM_SMCR_TS_TI1FP1 (0x05U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 1 (TI1FP1)
+#define TIM_SMCR_TS_TI2FP2 (0x06U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 2 (TI2FP2)
+#define TIM_SMCR_TS_ETRF (0x07U << TIM_SMCR_TS_Pos) ///< External Trigger input (ETRF)
+#define TIM_SMCR_MSM_Pos (7)
+#define TIM_SMCR_MSM (0x01U << TIM_SMCR_MSM_Pos) ///< Master/slave mode
+#define TIM_SMCR_ETF_Pos (8)
+#define TIM_SMCR_ETF (0x0FU << TIM_SMCR_ETF_Pos) ///< ETF[3:0] bits (External trigger filter)
+#define TIM_SMCR_ETF_0 (0x01U << TIM_SMCR_ETF_Pos) ///< Bit 0
+#define TIM_SMCR_ETF_1 (0x02U << TIM_SMCR_ETF_Pos) ///< Bit 1
+#define TIM_SMCR_ETF_2 (0x04U << TIM_SMCR_ETF_Pos) ///< Bit 2
+#define TIM_SMCR_ETF_3 (0x08U << TIM_SMCR_ETF_Pos) ///< Bit 3
+#define TIM_SMCR_ETPS_Pos (12)
+#define TIM_SMCR_ETPS (0x03U << TIM_SMCR_ETPS_Pos) ///< ETPS[1:0] bits (External trigger prescaler)
+#define TIM_SMCR_ETPS_OFF (0x00U << TIM_SMCR_ETPS_Pos) ///< Prescaler OFF
+#define TIM_SMCR_ETPS_DIV2 (0x01U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 2
+#define TIM_SMCR_ETPS_DIV4 (0x02U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 4
+#define TIM_SMCR_ETPS_DIV8 (0x03U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 8
+#define TIM_SMCR_ECEN_Pos (14)
+#define TIM_SMCR_ECEN (0x01U << TIM_SMCR_ECEN_Pos) ///< External clock enable
+#define TIM_SMCR_ETP_Pos (15)
+#define TIM_SMCR_ETP (0x01U << TIM_SMCR_ETP_Pos) ///< External trigger polarity
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DIER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_DIER_UI_Pos (0)
+#define TIM_DIER_UI (0x01U << TIM_DIER_UI_Pos) ///< Update interrupt enable
+#define TIM_DIER_CC1I_Pos (1)
+#define TIM_DIER_CC1I (0x01U << TIM_DIER_CC1I_Pos) ///< Capture/Compare 1 interrupt enable
+#define TIM_DIER_CC2I_Pos (2)
+#define TIM_DIER_CC2I (0x01U << TIM_DIER_CC2I_Pos) ///< Capture/Compare 2 interrupt enable
+#define TIM_DIER_CC3I_Pos (3)
+#define TIM_DIER_CC3I (0x01U << TIM_DIER_CC3I_Pos) ///< Capture/Compare 3 interrupt enable
+#define TIM_DIER_CC4I_Pos (4)
+#define TIM_DIER_CC4I (0x01U << TIM_DIER_CC4I_Pos) ///< Capture/Compare 4 interrupt enable
+#define TIM_DIER_COMI_Pos (5)
+#define TIM_DIER_COMI (0x01U << TIM_DIER_COMI_Pos) ///< COM interrupt enable
+#define TIM_DIER_TI_Pos (6)
+#define TIM_DIER_TI (0x01U << TIM_DIER_TI_Pos) ///< Trigger interrupt enable
+#define TIM_DIER_BI_Pos (7)
+#define TIM_DIER_BI (0x01U << TIM_DIER_BI_Pos) ///< Break interrupt enable
+#define TIM_DIER_UD_Pos (8)
+#define TIM_DIER_UD (0x01U << TIM_DIER_UD_Pos) ///< Update DMA request enable
+#define TIM_DIER_CC1D_Pos (9)
+#define TIM_DIER_CC1D (0x01U << TIM_DIER_CC1D_Pos) ///< Capture/Compare 1 DMA request enable
+#define TIM_DIER_CC2D_Pos (10)
+#define TIM_DIER_CC2D (0x01U << TIM_DIER_CC2D_Pos) ///< Capture/Compare 2 DMA request enable
+#define TIM_DIER_CC3D_Pos (11)
+#define TIM_DIER_CC3D (0x01U << TIM_DIER_CC3D_Pos) ///< Capture/Compare 3 DMA request enable
+#define TIM_DIER_CC4D_Pos (12)
+#define TIM_DIER_CC4D (0x01U << TIM_DIER_CC4D_Pos) ///< Capture/Compare 4 DMA request enable
+#define TIM_DIER_COMD_Pos (13)
+#define TIM_DIER_COMD (0x01U << TIM_DIER_COMD_Pos) ///< COM DMA request enable
+#define TIM_DIER_TD_Pos (14)
+#define TIM_DIER_TD (0x01U << TIM_DIER_TD_Pos) ///< Trigger DMA request enable
+#define TIM_DIER_CC5I_Pos (16)
+#define TIM_DIER_CC5I (0x01U << TIM_DIER_CC5I_Pos) ///< Capture/Compare 5 interrupt enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_SR_UI_Pos (0)
+#define TIM_SR_UI (0x01U << TIM_SR_UI_Pos) ///< Update interrupt Flag
+#define TIM_SR_CC1I_Pos (1)
+#define TIM_SR_CC1I (0x01U << TIM_SR_CC1I_Pos) ///< Capture/Compare 1 interrupt Flag
+#define TIM_SR_CC2I_Pos (2)
+#define TIM_SR_CC2I (0x01U << TIM_SR_CC2I_Pos) ///< Capture/Compare 2 interrupt Flag
+#define TIM_SR_CC3I_Pos (3)
+#define TIM_SR_CC3I (0x01U << TIM_SR_CC3I_Pos) ///< Capture/Compare 3 interrupt Flag
+#define TIM_SR_CC4I_Pos (4)
+#define TIM_SR_CC4I (0x01U << TIM_SR_CC4I_Pos) ///< Capture/Compare 4 interrupt Flag
+#define TIM_SR_COMI_Pos (5)
+#define TIM_SR_COMI (0x01U << TIM_SR_COMI_Pos) ///< COM interrupt Flag
+#define TIM_SR_TI_Pos (6)
+#define TIM_SR_TI (0x01U << TIM_SR_TI_Pos) ///< Trigger interrupt Flag
+#define TIM_SR_BI_Pos (7)
+#define TIM_SR_BI (0x01U << TIM_SR_BI_Pos) ///< Break interrupt Flag
+#define TIM_SR_CC1O_Pos (9)
+#define TIM_SR_CC1O (0x01U << TIM_SR_CC1O_Pos) ///< Capture/Compare 1 Overcapture Flag
+#define TIM_SR_CC2O_Pos (10)
+#define TIM_SR_CC2O (0x01U << TIM_SR_CC2O_Pos) ///< Capture/Compare 2 Overcapture Flag
+#define TIM_SR_CC3O_Pos (11)
+#define TIM_SR_CC3O (0x01U << TIM_SR_CC3O_Pos) ///< Capture/Compare 3 Overcapture Flag
+#define TIM_SR_CC4O_Pos (12)
+#define TIM_SR_CC4O (0x01U << TIM_SR_CC4O_Pos) ///< Capture/Compare 4 Overcapture Flag
+
+#define TIM_SR_CC5I_Pos (16)
+#define TIM_SR_CC5I (0x01U << TIM_SR_CC5I_Pos) ///< Capture/Compare 5 interrupt Flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_EGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_EGR_UG_Pos (0)
+#define TIM_EGR_UG (0x01U << TIM_EGR_UG_Pos) ///< Update Generation
+#define TIM_EGR_CC1G_Pos (1)
+#define TIM_EGR_CC1G (0x01U << TIM_EGR_CC1G_Pos) ///< Capture/Compare 1 Generation
+#define TIM_EGR_CC2G_Pos (2)
+#define TIM_EGR_CC2G (0x01U << TIM_EGR_CC2G_Pos) ///< Capture/Compare 2 Generation
+#define TIM_EGR_CC3G_Pos (3)
+#define TIM_EGR_CC3G (0x01U << TIM_EGR_CC3G_Pos) ///< Capture/Compare 3 Generation
+#define TIM_EGR_CC4G_Pos (4)
+#define TIM_EGR_CC4G (0x01U << TIM_EGR_CC4G_Pos) ///< Capture/Compare 4 Generation
+#define TIM_EGR_COMG_Pos (5)
+#define TIM_EGR_COMG (0x01U << TIM_EGR_COMG_Pos) ///< Capture/Compare Control Update Generation
+#define TIM_EGR_TG_Pos (6)
+#define TIM_EGR_TG (0x01U << TIM_EGR_TG_Pos) ///< Trigger Generation
+#define TIM_EGR_BG_Pos (7)
+#define TIM_EGR_BG (0x01U << TIM_EGR_BG_Pos) ///< Break Generation
+
+#define TIM_EGR_CC5G_Pos (16)
+#define TIM_EGR_CC5G (0x01U << TIM_EGR_CC5G_Pos) ///< Capture/Compare 5 Generation
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCMR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCMR1_CC1S_Pos (0)
+#define TIM_CCMR1_CC1S (0x03U << TIM_CCMR1_CC1S_Pos) ///< CC1S[1:0] bits (Capture/Compare 1 Selection)
+#define TIM_CCMR1_CC1S_OC (0x00U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as output
+#define TIM_CCMR1_CC1S_DIRECTTI (0x01U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI1
+#define TIM_CCMR1_CC1S_INDIRECTTI (0x02U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI2
+#define TIM_CCMR1_CC1S_TRC (0x03U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TRC
+#define TIM_CCMR1_OC1FEN_Pos (2)
+#define TIM_CCMR1_OC1FEN (0x01U << TIM_CCMR1_OC1FEN_Pos) ///< Output Compare 1 Fast enable
+
+#define TIM_CCMR1_OC1PEN_Pos (3)
+#define TIM_CCMR1_OC1PEN (0x01U << TIM_CCMR1_OC1PEN_Pos) ///< Output Compare 1 Preload enable
+#define TIM_CCMR1_OC1M_Pos (4)
+#define TIM_CCMR1_OC1M (0x07U << TIM_CCMR1_OC1M_Pos) ///< OC1M[2:0] bits (Output Compare 1 Mode)
+#define TIM_CCMR1_OC1M_TIMING (0x00U << TIM_CCMR1_OC1M_Pos) ///< Timing
+#define TIM_CCMR1_OC1M_ACTIVE (0x01U << TIM_CCMR1_OC1M_Pos) ///< Active
+#define TIM_CCMR1_OC1M_INACTIVE (0x02U << TIM_CCMR1_OC1M_Pos) ///< Inactive
+#define TIM_CCMR1_OC1M_TOGGLE (0x03U << TIM_CCMR1_OC1M_Pos) ///< Toggle
+#define TIM_CCMR1_OC1M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC1M_Pos) ///< Forceinactive
+#define TIM_CCMR1_OC1M_FORCEACTIVE (0x05U << TIM_CCMR1_OC1M_Pos) ///< Forceactive
+#define TIM_CCMR1_OC1M_PWM1 (0x06U << TIM_CCMR1_OC1M_Pos) ///< PWM1
+#define TIM_CCMR1_OC1M_PWM2 (0x07U << TIM_CCMR1_OC1M_Pos) ///< PWM2
+
+#define TIM_CCMR1_OC1CEN_Pos (7)
+#define TIM_CCMR1_OC1CEN (0x01U << TIM_CCMR1_OC1CEN_Pos) ///< Output Compare 1Clear Enable
+#define TIM_CCMR1_CC2S_Pos (8)
+#define TIM_CCMR1_CC2S (0x03U << TIM_CCMR1_CC2S_Pos) ///< CC2S[1:0] bits (Capture/Compare 2 Selection)
+#define TIM_CCMR1_CC2S_OC (0x00U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as output
+#define TIM_CCMR1_CC2S_DIRECTTI (0x01U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI2
+#define TIM_CCMR1_CC2S_INDIRECTTI (0x02U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI1
+#define TIM_CCMR1_CC2S_TRC (0x03U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TRC
+#define TIM_CCMR1_OC2FEN_Pos (10)
+#define TIM_CCMR1_OC2FEN (0x01U << TIM_CCMR1_OC2FEN_Pos) ///< Output Compare 2 Fast enable
+#define TIM_CCMR1_OC2PEN_Pos (11)
+#define TIM_CCMR1_OC2PEN (0x01U << TIM_CCMR1_OC2PEN_Pos) ///< Output Compare 2 Preload enable
+#define TIM_CCMR1_OC2M_Pos (12)
+#define TIM_CCMR1_OC2M (0x07U << TIM_CCMR1_OC2M_Pos) ///< OC2M[2:0] bits (Output Compare 2 Mode)
+#define TIM_CCMR1_OC2M_TIMING (0x00U << TIM_CCMR1_OC2M_Pos) ///< Timing
+#define TIM_CCMR1_OC2M_ACTIVE (0x01U << TIM_CCMR1_OC2M_Pos) ///< Active
+#define TIM_CCMR1_OC2M_INACTIVE (0x02U << TIM_CCMR1_OC2M_Pos) ///< Inactive
+#define TIM_CCMR1_OC2M_TOGGLE (0x03U << TIM_CCMR1_OC2M_Pos) ///< Toggle
+#define TIM_CCMR1_OC2M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC2M_Pos) ///< Forceinactive
+#define TIM_CCMR1_OC2M_FORCEACTIVE (0x05U << TIM_CCMR1_OC2M_Pos) ///< Forceactive
+#define TIM_CCMR1_OC2M_PWM1 (0x06U << TIM_CCMR1_OC2M_Pos) ///< PWM1
+#define TIM_CCMR1_OC2M_PWM2 (0x07U << TIM_CCMR1_OC2M_Pos) ///< PWM2
+#define TIM_CCMR1_OC2CEN_Pos (15)
+#define TIM_CCMR1_OC2CEN (0x01U << TIM_CCMR1_OC2CEN_Pos) ///< Output Compare 2 Clear Enable
+
+#define TIM_CCMR1_IC1PSC_Pos (2)
+#define TIM_CCMR1_IC1PSC (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler)
+#define TIM_CCMR1_IC1PSC_DIV1 (0x00U << TIM_CCMR1_IC1PSC_Pos) ///< No Prescaler
+#define TIM_CCMR1_IC1PSC_DIV2 (0x01U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 2 events
+#define TIM_CCMR1_IC1PSC_DIV4 (0x02U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 4 events
+#define TIM_CCMR1_IC1PSC_DIV8 (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 8 events
+#define TIM_CCMR1_IC1F_Pos (4)
+#define TIM_CCMR1_IC1F (0x0FU << TIM_CCMR1_IC1F_Pos) ///< IC1F[3:0] bits (Input Capture 1 Filter)
+#define TIM_CCMR1_IC1F_0 (0x01U << TIM_CCMR1_IC1F_Pos) ///< Bit 0
+#define TIM_CCMR1_IC1F_1 (0x02U << TIM_CCMR1_IC1F_Pos) ///< Bit 1
+#define TIM_CCMR1_IC1F_2 (0x04U << TIM_CCMR1_IC1F_Pos) ///< Bit 2
+#define TIM_CCMR1_IC1F_3 (0x08U << TIM_CCMR1_IC1F_Pos) ///< Bit 3
+
+#define TIM_CCMR1_IC2PSC_Pos (10)
+#define TIM_CCMR1_IC2PSC (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler)
+#define TIM_CCMR1_IC2PSC_DIV1 (0x00U << TIM_CCMR1_IC2PSC_Pos) ///< No Prescaler
+#define TIM_CCMR1_IC2PSC_DIV2 (0x01U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 2 events
+#define TIM_CCMR1_IC2PSC_DIV4 (0x02U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 4 events
+#define TIM_CCMR1_IC2PSC_DIV8 (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 8 events
+#define TIM_CCMR1_IC2F_Pos (12)
+#define TIM_CCMR1_IC2F (0x0FU << TIM_CCMR1_IC2F_Pos) ///< IC2F[3:0] bits (Input Capture 2 Filter)
+#define TIM_CCMR1_IC2F_0 (0x01U << TIM_CCMR1_IC2F_Pos) ///< Bit 0
+#define TIM_CCMR1_IC2F_1 (0x02U << TIM_CCMR1_IC2F_Pos) ///< Bit 1
+#define TIM_CCMR1_IC2F_2 (0x04U << TIM_CCMR1_IC2F_Pos) ///< Bit 2
+#define TIM_CCMR1_IC2F_3 (0x08U << TIM_CCMR1_IC2F_Pos) ///< Bit 3
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCMR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCMR2_CC3S_Pos (0)
+#define TIM_CCMR2_CC3S (0x03U << TIM_CCMR2_CC3S_Pos) ///< CC3S[1:0] bits (Capture/Compare 3 Selection)
+#define TIM_CCMR2_CC3S_OC (0x00U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as output
+#define TIM_CCMR2_CC3S_DIRECTTI (0x01U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI3
+#define TIM_CCMR2_CC3S_INDIRECTTI (0x02U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI4
+#define TIM_CCMR2_CC3S_TRC (0x03U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TRC
+#define TIM_CCMR2_OC3FEN_Pos (2)
+#define TIM_CCMR2_OC3FEN (0x01U << TIM_CCMR2_OC3FEN_Pos) ///< Output Compare 3 Fast enable
+#define TIM_CCMR2_IC3PSC_Pos (2)
+#define TIM_CCMR2_IC3PSC (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler)
+#define TIM_CCMR2_IC3PSC_DIV1 (0x00U << TIM_CCMR2_IC3PSC_Pos) ///< No Prescaler
+#define TIM_CCMR2_IC3PSC_DIV2 (0x01U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 2 events
+#define TIM_CCMR2_IC3PSC_DIV4 (0x02U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 4 events
+#define TIM_CCMR2_IC3PSC_DIV8 (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 8 events
+#define TIM_CCMR2_OC3PEN_Pos (3)
+#define TIM_CCMR2_OC3PEN (0x01U << TIM_CCMR2_OC3PEN_Pos) ///< Output Compare 3 Preload enable
+#define TIM_CCMR2_OC3M_Pos (4)
+#define TIM_CCMR2_OC3M (0x07U << TIM_CCMR2_OC3M_Pos) ///< OC3M[2:0] bits (Output Compare 3 Mode)
+#define TIM_CCMR2_OC3M_TIMING (0x00U << TIM_CCMR2_OC3M_Pos) ///< Timing
+#define TIM_CCMR2_OC3M_ACTIVE (0x01U << TIM_CCMR2_OC3M_Pos) ///< Active
+#define TIM_CCMR2_OC3M_INACTIVE (0x02U << TIM_CCMR2_OC3M_Pos) ///< Inactive
+#define TIM_CCMR2_OC3M_TOGGLE (0x03U << TIM_CCMR2_OC3M_Pos) ///< Toggle
+#define TIM_CCMR2_OC3M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC3M_Pos) ///< Forceinactive
+#define TIM_CCMR2_OC3M_FORCEACTIVE (0x05U << TIM_CCMR2_OC3M_Pos) ///< Forceactive
+#define TIM_CCMR2_OC3M_PWM1 (0x06U << TIM_CCMR2_OC3M_Pos) ///< PWM1
+#define TIM_CCMR2_OC3M_PWM2 (0x07U << TIM_CCMR2_OC3M_Pos) ///< PWM2
+#define TIM_CCMR2_IC3F_Pos (4)
+#define TIM_CCMR2_IC3F (0x0FU << TIM_CCMR2_IC3F_Pos) ///< IC3F[3:0] bits (Input Capture 3 Filter)
+#define TIM_CCMR2_IC3F_0 (0x01U << TIM_CCMR2_IC3F_Pos) ///< Bit 0
+#define TIM_CCMR2_IC3F_1 (0x02U << TIM_CCMR2_IC3F_Pos) ///< Bit 1
+#define TIM_CCMR2_IC3F_2 (0x04U << TIM_CCMR2_IC3F_Pos) ///< Bit 2
+#define TIM_CCMR2_IC3F_3 (0x08U << TIM_CCMR2_IC3F_Pos) ///< Bit 3
+#define TIM_CCMR2_OC3CEN_Pos (7)
+#define TIM_CCMR2_OC3CEN (0x01U << TIM_CCMR2_OC3CEN_Pos) ///< Output Compare 3 Clear Enable
+#define TIM_CCMR2_CC4S_Pos (8)
+#define TIM_CCMR2_CC4S (0x03U << TIM_CCMR2_CC4S_Pos) ///< CC4S[1:0] bits (Capture/Compare 4 Selection)
+#define TIM_CCMR2_CC4S_OC (0x00U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as output
+#define TIM_CCMR2_CC4S_DIRECTTI (0x01U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI4
+#define TIM_CCMR2_CC4S_INDIRECTTI (0x02U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI3
+#define TIM_CCMR2_CC4S_TRC (0x03U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TRC
+#define TIM_CCMR2_OC4FEN_Pos (10)
+#define TIM_CCMR2_OC4FEN (0x01U << TIM_CCMR2_OC4FEN_Pos) ///< Output Compare 4 Fast enable
+#define TIM_CCMR2_OC4PEN_Pos (11)
+#define TIM_CCMR2_OC4PEN (0x01U << TIM_CCMR2_OC4PEN_Pos) ///< Output Compare 4 Preload enable
+#define TIM_CCMR2_OC4M_Pos (12)
+#define TIM_CCMR2_OC4M (0x07U << TIM_CCMR2_OC4M_Pos) ///< OC4M[2:0] bits (Output Compare 4 Mode)
+#define TIM_CCMR2_OC4M_TIMING (0x00U << TIM_CCMR2_OC4M_Pos) ///< Timing
+#define TIM_CCMR2_OC4M_ACTIVE (0x01U << TIM_CCMR2_OC4M_Pos) ///< Active
+#define TIM_CCMR2_OC4M_INACTIVE (0x02U << TIM_CCMR2_OC4M_Pos) ///< Inactive
+#define TIM_CCMR2_OC4M_TOGGLE (0x03U << TIM_CCMR2_OC4M_Pos) ///< Toggle
+#define TIM_CCMR2_OC4M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC4M_Pos) ///< Forceinactive
+#define TIM_CCMR2_OC4M_FORCEACTIVE (0x05U << TIM_CCMR2_OC4M_Pos) ///< Forceactive
+#define TIM_CCMR2_OC4M_PWM1 (0x06U << TIM_CCMR2_OC4M_Pos) ///< PWM1
+#define TIM_CCMR2_OC4M_PWM2 (0x07U << TIM_CCMR2_OC4M_Pos) ///< PWM2
+#define TIM_CCMR2_OC4CEN_Pos (15)
+#define TIM_CCMR2_OC4CEN (0x01U << TIM_CCMR2_OC4CEN_Pos) ///< Output Compare 4 Clear Enable
+#define TIM_CCMR2_IC4PSC_Pos (10)
+#define TIM_CCMR2_IC4PSC (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler)
+#define TIM_CCMR2_IC4PSC_DIV1 (0x00U << TIM_CCMR2_IC4PSC_Pos) ///< No Prescaler
+#define TIM_CCMR2_IC4PSC_DIV2 (0x01U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 2 events
+#define TIM_CCMR2_IC4PSC_DIV4 (0x02U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 4 events
+#define TIM_CCMR2_IC4PSC_DIV8 (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 8 events
+#define TIM_CCMR2_IC4F_Pos (12)
+#define TIM_CCMR2_IC4F (0x0FU << TIM_CCMR2_IC4F_Pos) ///< IC4F[3:0] bits (Input Capture 4 Filter)
+#define TIM_CCMR2_IC4F_0 (0x01U << TIM_CCMR2_IC4F_Pos) ///< Bit 0
+#define TIM_CCMR2_IC4F_1 (0x02U << TIM_CCMR2_IC4F_Pos) ///< Bit 1
+#define TIM_CCMR2_IC4F_2 (0x04U << TIM_CCMR2_IC4F_Pos) ///< Bit 2
+#define TIM_CCMR2_IC4F_3 (0x08U << TIM_CCMR2_IC4F_Pos) ///< Bit 3
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCER_CC1EN_Pos (0)
+#define TIM_CCER_CC1EN (0x01U << TIM_CCER_CC1EN_Pos) ///< Capture/Compare 1 output enable
+#define TIM_CCER_CC1P_Pos (1)
+#define TIM_CCER_CC1P (0x01U << TIM_CCER_CC1P_Pos) ///< Capture/Compare 1 output Polarity
+#define TIM_CCER_CC1NEN_Pos (2)
+#define TIM_CCER_CC1NEN (0x01U << TIM_CCER_CC1NEN_Pos) ///< Capture/Compare 1 Complementary output enable
+#define TIM_CCER_CC1NP_Pos (3)
+#define TIM_CCER_CC1NP (0x01U << TIM_CCER_CC1NP_Pos) ///< Capture/Compare 1 Complementary output Polarity
+#define TIM_CCER_CC2EN_Pos (4)
+#define TIM_CCER_CC2EN (0x01U << TIM_CCER_CC2EN_Pos) ///< Capture/Compare 2 output enable
+#define TIM_CCER_CC2P_Pos (5)
+#define TIM_CCER_CC2P (0x01U << TIM_CCER_CC2P_Pos) ///< Capture/Compare 2 output Polarity
+#define TIM_CCER_CC2NEN_Pos (6)
+#define TIM_CCER_CC2NEN (0x01U << TIM_CCER_CC2NEN_Pos) ///< Capture/Compare 2 Complementary output enable
+#define TIM_CCER_CC2NP_Pos (7)
+#define TIM_CCER_CC2NP (0x01U << TIM_CCER_CC2NP_Pos) ///< Capture/Compare 2 Complementary output Polarity
+#define TIM_CCER_CC3EN_Pos (8)
+#define TIM_CCER_CC3EN (0x01U << TIM_CCER_CC3EN_Pos) ///< Capture/Compare 3 output enable
+#define TIM_CCER_CC3P_Pos (9)
+#define TIM_CCER_CC3P (0x01U << TIM_CCER_CC3P_Pos) ///< Capture/Compare 3 output Polarity
+#define TIM_CCER_CC3NEN_Pos (10)
+#define TIM_CCER_CC3NEN (0x01U << TIM_CCER_CC3NEN_Pos) ///< Capture/Compare 3 Complementary output enable
+#define TIM_CCER_CC3NP_Pos (11)
+#define TIM_CCER_CC3NP (0x01U << TIM_CCER_CC3NP_Pos) ///< Capture/Compare 3 Complementary output Polarity
+#define TIM_CCER_CC4EN_Pos (12)
+#define TIM_CCER_CC4EN (0x01U << TIM_CCER_CC4EN_Pos) ///< Capture/Compare 4 output enable
+#define TIM_CCER_CC4P_Pos (13)
+#define TIM_CCER_CC4P (0x01U << TIM_CCER_CC4P_Pos) ///< Capture/Compare 4 output Polarity
+#define TIM_CCER_CC4NP_Pos (15)
+#define TIM_CCER_CC4NP (0x01U << TIM_CCER_CC4NP_Pos) ///< Capture/Compare 4 complementary output polarity
+
+#define TIM_CCER_CC5EN_Pos (16)
+#define TIM_CCER_CC5EN (0x01U << TIM_CCER_CC5EN_Pos) ///< Capture/Compare 5 output enable
+#define TIM_CCER_CC5P_Pos (17)
+#define TIM_CCER_CC5P (0x01U << TIM_CCER_CC5P_Pos) ///< Capture/Compare 5 output Polarity
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CNT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CNT_CNT (0xFFFFU) ///< Counter Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_PSC Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_PSC_PSC (0xFFFFU) ///< Prescaler Value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_ARR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_ARR_ARR (0xFFFFU) ///< actual auto-reload Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_RCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_RCR_REP (0xFFU) ///< Repetition Counter Value
+
+#define TIM_RCR_REP_CNT_Pos (8)
+#define TIM_RCR_REP_CNT (0xFFU << TIM_RCR_REP_CNT_Pos) ///< Repetition counter value of real-time writing
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR1_CCR1 (0xFFFFU) ///< Capture/Compare 1 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR2_CCR2 (0xFFFFU) ///< Capture/Compare 2 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR3_CCR3 (0xFFFFU) ///< Capture/Compare 3 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR4_CCR4 (0xFFFFU) ///< Capture/Compare 4 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_BDTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_BDTR_DTG_Pos (0)
+#define TIM_BDTR_DTG (0xFFU << TIM_BDTR_DTG_Pos) ///< DTG[0:7] bits (Dead-Time Generator set-up)
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) ///< Bit 0
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) ///< Bit 1
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) ///< Bit 2
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) ///< Bit 3
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) ///< Bit 4
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) ///< Bit 5
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) ///< Bit 6
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) ///< Bit 7
+#define TIM_BDTR_LOCK_Pos (8)
+#define TIM_BDTR_LOCK (0x03U << TIM_BDTR_LOCK_Pos) ///< LOCK[1:0] bits (Lock Configuration)
+#define TIM_BDTR_LOCK_OFF (0x00U << TIM_BDTR_LOCK_Pos) ///< Lock Off
+#define TIM_BDTR_LOCK_1 (0x01U << TIM_BDTR_LOCK_Pos) ///< Lock Level 1
+#define TIM_BDTR_LOCK_2 (0x02U << TIM_BDTR_LOCK_Pos) ///< Lock Level 2
+#define TIM_BDTR_LOCK_3 (0x03U << TIM_BDTR_LOCK_Pos) ///< Lock Level 3
+#define TIM_BDTR_OSSI_Pos (10)
+#define TIM_BDTR_OSSI (0x01U << TIM_BDTR_OSSI_Pos) ///< Off-State Selection for Idle mode
+#define TIM_BDTR_OSSR_Pos (11)
+#define TIM_BDTR_OSSR (0x01U << TIM_BDTR_OSSR_Pos) ///< Off-State Selection for Run mode
+#define TIM_BDTR_BKEN_Pos (12)
+#define TIM_BDTR_BKEN (0x01U << TIM_BDTR_BKEN_Pos) ///< Break enable
+#define TIM_BDTR_BKP_Pos (13)
+#define TIM_BDTR_BKP (0x01U << TIM_BDTR_BKP_Pos) ///< Break Polarity
+#define TIM_BDTR_AOEN_Pos (14)
+#define TIM_BDTR_AOEN (0x01U << TIM_BDTR_AOEN_Pos) ///< Automatic Output enable
+#define TIM_BDTR_MOEN_Pos (15)
+#define TIM_BDTR_MOEN (0x01U << TIM_BDTR_MOEN_Pos) ///< Main Output enable
+
+#define TIM_BDTR_DOEN_Pos (16)
+#define TIM_BDTR_DOEN (0x01U << TIM_BDTR_DOEN_Pos) ///< Direct Output enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_DCR_DBA_Pos (0)
+#define TIM_DCR_DBA (0x1FU << TIM_DCR_DBA_Pos) ///< DBA[4:0] bits (DMA Base Address)
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) ///< Bit 0
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) ///< Bit 1
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) ///< Bit 2
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) ///< Bit 3
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) ///< Bit 4
+#define TIM_DCR_DBL_Pos (8)
+#define TIM_DCR_DBL (0x1FU << TIM_DCR_DBL_Pos) ///< DBL[4:0] bits (DMA Burst Length)
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) ///< Bit 0
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) ///< Bit 1
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) ///< Bit 2
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) ///< Bit 3
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) ///< Bit 4
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_DMAR_DMAB (0xFFFFU) ///< DMA register for burst accesses
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCMR3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCMR3_OC5FEN_Pos (2)
+#define TIM_CCMR3_OC5FEN (0x01U << TIM_CCMR3_OC5FEN_Pos) ///< Output Compare 5 Fast enable
+#define TIM_CCMR3_OC5PEN_Pos (3)
+#define TIM_CCMR3_OC5PEN (0x01U << TIM_CCMR3_OC5PEN_Pos) ///< Output Compare 5 Preload enable
+#define TIM_CCMR3_OC5M_Pos (4)
+#define TIM_CCMR3_OC5M (0x07U << TIM_CCMR3_OC5M_Pos) ///< OC5M[2:0] bits (Output Compare 5 Mode)
+
+#define TIM_CCMR3_OC5CEN_Pos (7)
+#define TIM_CCMR3_OC5CEN (0x01U << TIM_CCMR3_OC5CEN_Pos) ///< Output Compare 5 Clear Enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR5 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR5_CCR5 (0xFFFF) ///< Capture/Compare 5 Value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_PDER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_PDER_CCDREPE_Pos (0)
+#define TIM_PDER_CCDREPE (0x01U << TIM_PDER_CCDREPE_Pos) ///< DMA request flow enable
+#define TIM_PDER_CCR1SHIFTEN_Pos (1)
+#define TIM_PDER_CCR1SHIFTEN (0x01U << TIM_PDER_CCR1SHIFTEN_Pos) ///< CCR1 pwm shift enable
+#define TIM_PDER_CCR2SHIFTEN_Pos (2)
+#define TIM_PDER_CCR2SHIFTEN (0x01U << TIM_PDER_CCR2SHIFTEN_Pos) ///< CCR2 pwm shift enable
+#define TIM_PDER_CCR3SHIFTEN_Pos (3)
+#define TIM_PDER_CCR3SHIFTEN (0x01U << TIM_PDER_CCR3SHIFTEN_Pos) ///< CCR3 pwm shift enable
+#define TIM_PDER_CCR4SHIFTEN_Pos (4)
+#define TIM_PDER_CCR4SHIFTEN (0x01U << TIM_PDER_CCR4SHIFTEN_Pos) ///< CCR4 pwm shift enable
+#define TIM_PDER_CCR5SHIFTEN_Pos (5)
+#define TIM_PDER_CCR5SHIFTEN (0x01U << TIM_PDER_CCR5SHIFTEN_Pos) ///< CCR5 pwm shift enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR1FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR1FALL_CCR1FALL (0xFFFFU) ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR2FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR2FALL_CCR2FALL (0xFFFFU) ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR3FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR3FALL_CCR3FALL (0xFFFFU) ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR4FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR4FALL_CCR4FALL (0xFFFFU) ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR5FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR5FALL_CCR5FALL (0xFFFFU) ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
new file mode 100644
index 00000000..069ff2cf
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
@@ -0,0 +1,362 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_uart.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_UART_H
+#define __REG_UART_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART1_BASE (APB2PERIPH_BASE + 0x3800) ///< Base Address: 0x40013800
+#define UART2_BASE (APB1PERIPH_BASE + 0x4400) ///< Base Address: 0x40004400
+#define UART3_BASE (APB1PERIPH_BASE + 0x4800) ///< Base Address: 0x40004800
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) ///< Base Address: 0x40004C00
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000) ///< Base Address: 0x40005000
+#define UART6_BASE (APB2PERIPH_BASE + 0x3C00) ///< Base Address: 0x40013C00
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800) ///< Base Address: 0x40007800
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) ///< Base Address: 0x40007C00
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+ __IO u32 TDR; ///< Transmit Data Register, offset: 0x00
+ __IO u32 RDR; ///< Receive Data Register, offset: 0x04
+ __IO u32 CSR; ///< Current Status Register, offset: 0x08
+ __IO u32 ISR; ///< Interrupt Status Register, offset: 0x0C
+ __IO u32 IER; ///< Interrupt Enable Register, offset: 0x10
+ __IO u32 ICR; ///< Interrupt Clear Register, offset: 0x14
+ __IO u32 GCR; ///< Global Control Register, offset: 0x18
+ __IO u32 CCR; ///< Config Control Register, offset: 0x1C
+ __IO u32 BRR; ///< Baud Rate Register, offset: 0x20
+ __IO u32 FRA; ///< Fraction Register, offset: 0x24
+
+ __IO u32 RXAR; ///< Receive Address Register, offset: 0x28
+ __IO u32 RXMR; ///< Receive Address Mask Register, offset: 0x2C
+ __IO u32 SCR; ///< Smart Card Register, offset: 0x30
+
+ __IO u32 IDLR; ///< Data length register offset: 0x34
+ __IO u32 ABRCR; ///< automatic Baud rate control delivery offset: 0x38
+ __IO u32 IRDA; ///< Infrared function control register, offset: 0x3C
+} UART_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART1 ((UART_TypeDef*) UART1_BASE)
+#define UART2 ((UART_TypeDef*) UART2_BASE)
+
+#define UART3 ((UART_TypeDef*) UART3_BASE)
+#define UART4 ((UART_TypeDef*) UART4_BASE)
+#define UART5 ((UART_TypeDef*) UART5_BASE)
+#define UART6 ((UART_TypeDef*) UART6_BASE)
+#define UART7 ((UART_TypeDef*) UART7_BASE)
+#define UART8 ((UART_TypeDef*) UART8_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_TDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_TDR_DATA_Pos (0)
+#define UART_TDR_DATA (0xFFU << UART_TDR_DATA_Pos) ///< Transmit data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_RDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_RDR_DATA_Pos (0)
+#define UART_RDR_DATA (0xFFU << UART_RDR_DATA_Pos) ///< Receive data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_CSR_TXC_Pos (0)
+#define UART_CSR_TXC (0x01U << UART_CSR_TXC_Pos) ///< Transmit complete flag bit
+#define UART_CSR_RXAVL_Pos (1)
+#define UART_CSR_RXAVL (0x01U << UART_CSR_RXAVL_Pos) ///< Receive valid data flag bit
+#define UART_CSR_TXFULL_Pos (2)
+#define UART_CSR_TXFULL (0x01U << UART_CSR_TXFULL_Pos) ///< Transmit buffer full flag bit
+#define UART_CSR_TXEPT_Pos (3)
+#define UART_CSR_TXEPT (0x01U << UART_CSR_TXEPT_Pos) ///< Transmit buffer empty flag bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_ISR_TX_Pos (0)
+#define UART_ISR_TX (0x01U << UART_ISR_TX_Pos) ///< Transmit buffer empty interrupt flag bit
+#define UART_ISR_RX_Pos (1)
+#define UART_ISR_RX (0x01U << UART_ISR_RX_Pos) ///< Receive valid data interrupt flag bit
+
+#define UART_ISR_TXC_Pos (2)
+#define UART_ISR_TXC (0x01U << UART_ISR_TXC_Pos) ///< Transmit complete interrupt flag bit
+
+#define UART_ISR_RXOERR_Pos (3)
+#define UART_ISR_RXOERR (0x01U << UART_ISR_RXOERR_Pos) ///< Receive overflow error interrupt flag bit
+#define UART_ISR_RXPERR_Pos (4)
+#define UART_ISR_RXPERR (0x01U << UART_ISR_RXPERR_Pos) ///< Parity error interrupt flag bit
+#define UART_ISR_RXFERR_Pos (5)
+#define UART_ISR_RXFERR (0x01U << UART_ISR_RXFERR_Pos) ///< Frame error interrupt flag bit
+#define UART_ISR_RXBRK_Pos (6)
+#define UART_ISR_RXBRK (0x01U << UART_ISR_RXBRK_Pos) ///< Receive frame break interrupt flag bit
+
+#define UART_ISR_TXBRK_Pos (7)
+#define UART_ISR_TXBRK (0x01U << UART_ISR_TXBRK_Pos) ///< Transmit Break Frame Interrupt Flag Bit
+#define UART_ISR_RXB8_Pos (8)
+#define UART_ISR_RXB8 (0x01U << UART_ISR_RXB8_Pos) ///< Receive Bit 8 Interrupt Flag Bit
+
+#define UART_ISR_RXIDLE_Pos (9)
+#define UART_ISR_RXIDLE (0x01U << UART_ISR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit
+#define UART_ISR_ABREND_INTF_Pos (10)
+#define UART_ISR_ABREND_INTF (0x01U << UART_ISR_ABREND_INTF_Pos) ///< Auto baud rate end interrupt flag bit
+#define UART_ISR_ABRERR_INTF_Pos (11)
+#define UART_ISR_ABRERR_INTF (0x01U << UART_ISR_ABRERR_INTF_Pos) ///< Auto baud rate error interrupt flag bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_IER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_IER_TX_Pos (0)
+#define UART_IER_TX (0x01U << UART_IER_TX_Pos) ///< Transmit buffer empty interrupt enable bit
+#define UART_IER_RX_Pos (1)
+#define UART_IER_RX (0x01U << UART_IER_RX_Pos) ///< Receive buffer interrupt enable bit
+
+#define UART_IER_TXC_Pos (2)
+#define UART_IER_TXC (0x01U << UART_IER_TXC_Pos) ///< Transmit complete interrupt enable bit
+
+#define UART_IER_RXOERR_Pos (3)
+#define UART_IER_RXOERR (0x01U << UART_IER_RXOERR_Pos) ///< Receive overflow error interrupt enable bit
+#define UART_IER_RXPERR_Pos (4)
+#define UART_IER_RXPERR (0x01U << UART_IER_RXPERR_Pos) ///< Parity error interrupt enable bit
+#define UART_IER_RXFERR_Pos (5)
+#define UART_IER_RXFERR (0x01U << UART_IER_RXFERR_Pos) ///< Frame error interrupt enable bit
+#define UART_IER_RXBRK_Pos (6)
+#define UART_IER_RXBRK (0x01U << UART_IER_RXBRK_Pos) ///< Receive frame break interrupt enable bit
+
+#define UART_IER_TXBRK_Pos (7)
+#define UART_IER_TXBRK (0x01U << UART_IER_TXBRK_Pos) ///< Transmit Break Frame Interrupt Enable Bit
+#define UART_IER_RXB8_Pos (8)
+#define UART_IER_RXB8 (0x01U << UART_IER_RXB8_Pos) ///< Receive Bit 8 Interrupt Enable Bit
+
+#define UART_IER_RXIDLE_Pos (9)
+#define UART_IER_RXIDLE (0x01U << UART_IER_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit
+#define UART_IER_ABREND_IEN_Pos (10)
+#define UART_IER_ABREND_IEN (0x01U << UART_IER_ABREND_IEN_Pos) ///< Auto baud rate end enable bit
+#define UART_IER_ABRERR_IEN_Pos (11)
+#define UART_IER_ABRERR_IEN (0x01U << UART_IER_ABRERR_IEN_Pos) ///< Auto baud rate error enable bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define UART_ICR_TX_Pos (0)
+#define UART_ICR_TX (0x01U << UART_ICR_TX_Pos) ///< Transmit buffer empty interrupt clear bit
+#define UART_ICR_RX_Pos (1)
+#define UART_ICR_RX (0x01U << UART_ICR_RX_Pos) ///< Receive interrupt clear bit
+
+#define UART_ICR_TXC_Pos (2)
+#define UART_ICR_TXC (0x01U << UART_ICR_TXC_Pos) ///< Transmit complete interrupt clear bit
+
+#define UART_ICR_RXOERR_Pos (3)
+#define UART_ICR_RXOERR (0x01U << UART_ICR_RXOERR_Pos) ///< Receive overflow error interrupt clear bit
+#define UART_ICR_RXPERR_Pos (4)
+#define UART_ICR_RXPERR (0x01U << UART_ICR_RXPERR_Pos) ///< Parity error interrupt clear bit
+
+#define UART_ICR_RXFERR_Pos (5)
+#define UART_ICR_RXFERR (0x01U << UART_ICR_RXFERR_Pos) ///< Frame error interrupt clear bit
+#define UART_ICR_RXBRK_Pos (6)
+#define UART_ICR_RXBRK (0x01U << UART_ICR_RXBRK_Pos) ///< Receive frame break interrupt clear bit
+
+#define UART_ICR_TXBRK_Pos (7)
+#define UART_ICR_TXBRK (0x01U << UART_ICR_TXBRK_Pos) ///< Transmit Break Frame Interrupt clear Bit
+#define UART_ICR_RXB8_Pos (8)
+#define UART_ICR_RXB8 (0x01U << UART_ICR_RXB8_Pos) ///< Receive Bit 8 Interrupt clear Bit
+
+#define UART_ICR_RXIDLE_Pos (9)
+#define UART_ICR_RXIDLE (0x01U << UART_ICR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit
+#define UART_ICR_ABRENDCLR_Pos (10)
+#define UART_ICR_ABRENDCLR (0x01U << UART_ICR_ABRENDCLR_Pos) ///< Auto baud rate end clear bit
+#define UART_ICR_ABRERRCLR_Pos (11)
+#define UART_ICR_ABRERRCLR (0x01U << UART_ICR_ABRERRCLR_Pos) ///< Auto baud rate error clear bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_GCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_GCR_UART_Pos (0)
+#define UART_GCR_UART (0x01U << UART_GCR_UART_Pos) ///< UART mode selection bit
+#define UART_GCR_DMA_Pos (1)
+#define UART_GCR_DMA (0x01U << UART_GCR_DMA_Pos) ///< DMA mode selection bit
+#define UART_GCR_AUTOFLOW_Pos (2)
+#define UART_GCR_AUTOFLOW (0x01U << UART_GCR_AUTOFLOW_Pos) ///< Automatic flow control enable bit
+#define UART_GCR_RX_Pos (3)
+#define UART_GCR_RX (0x01U << UART_GCR_RX_Pos) ///< Enable receive
+#define UART_GCR_TX_Pos (4)
+#define UART_GCR_TX (0x01U << UART_GCR_TX_Pos) ///< Enable transmit
+
+#define UART_GCR_SELB8_Pos (7)
+#define UART_GCR_SELB8 (0x01U << UART_GCR_SELB8_Pos) ///< UART mode selection bit
+#define UART_GCR_SWAP_Pos (8)
+#define UART_GCR_SWAP (0x01U << UART_GCR_SWAP_Pos) ///< DMA mode selection bit
+#define UART_GCR_RXTOG_Pos (9)
+#define UART_GCR_RXTOG (0x01U << UART_GCR_RXTOG_Pos) ///< Automatic flow control enable bit
+#define UART_GCR_TXTOG_Pos (10)
+#define UART_GCR_TXTOG (0x01U << UART_GCR_TXTOG_Pos) ///< Enable receive
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_CCR_PEN_Pos (0)
+#define UART_CCR_PEN (0x01U << UART_CCR_PEN_Pos) ///< Parity enable bit
+#define UART_CCR_PSEL_Pos (1)
+#define UART_CCR_PSEL (0x01U << UART_CCR_PSEL_Pos) ///< Parity selection bit
+
+#define UART_CCR_SPB_Pos (2)
+#define UART_CCR_SPB (0x01U << UART_CCR_SPB_Pos) ///< Stop bit selection
+
+
+
+#define UART_CCR_SPB0_Pos UART_CCR_SPB_Pos
+#define UART_CCR_SPB0 UART_CCR_SPB ///< Stop bit 0 selection
+
+#define UART_CCR_BRK_Pos (3)
+#define UART_CCR_BRK (0x01U << UART_CCR_BRK_Pos) ///< UART transmit frame break
+#define UART_CCR_CHAR_Pos (4)
+#define UART_CCR_CHAR (0x03U << UART_CCR_CHAR_Pos) ///< UART width bit
+#define UART_CCR_CHAR_5b (0x00U << UART_CCR_CHAR_Pos) ///< UART Word Length 5b
+#define UART_CCR_CHAR_6b (0x01U << UART_CCR_CHAR_Pos) ///< UART Word Length 6b
+#define UART_CCR_CHAR_7b (0x02U << UART_CCR_CHAR_Pos) ///< UART Word Length 7b
+#define UART_CCR_CHAR_8b (0x03U << UART_CCR_CHAR_Pos) ///< UART Word Length 8b
+
+#define UART_CCR_SPB1_Pos (6)
+#define UART_CCR_SPB1 (0x01U << UART_CCR_SPB1_Pos) ///< Stop bit 1 selection
+#define UART_CCR_B8RXD_Pos (7)
+#define UART_CCR_B8RXD (0x01U << UART_CCR_B8RXD_Pos) ///< Synchronous frame receive
+#define UART_CCR_B8TXD_Pos (8)
+#define UART_CCR_B8TXD (0x01U << UART_CCR_B8TXD_Pos) ///< Synchronous frame transmit
+#define UART_CCR_B8POL_Pos (9)
+#define UART_CCR_B8POL (0x01U << UART_CCR_B8POL_Pos) ///< Synchronous frame polarity control bit
+#define UART_CCR_B8TOG_Pos (10)
+#define UART_CCR_B8TOG (0x01U << UART_CCR_B8TOG_Pos) ///< Synchronous frame auto toggle bit
+#define UART_CCR_B8EN_Pos (11)
+#define UART_CCR_B8EN (0x01U << UART_CCR_B8EN_Pos) ///< Synchronous frame enable bit
+#define UART_CCR_RWU_Pos (12)
+#define UART_CCR_RWU (0x01U << UART_CCR_RWU_Pos) ///< Receive wake up method
+#define UART_CCR_WAKE_Pos (13)
+#define UART_CCR_WAKE (0x01U << UART_CCR_WAKE_Pos) ///< Wake up method
+
+#define UART_CCR_LIN_Pos (14)
+#define UART_CCR_LIN (0x01U << UART_CCR_LIN_Pos) ///< Wake up method
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_BRR_MANTISSA_Pos (0)
+#define UART_BRR_MANTISSA (0xFFFFU << UART_BRR_MANTISSA_Pos) ///< UART DIV MANTISSA
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_FRA Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_BRR_FRACTION_Pos (0)
+#define UART_BRR_FRACTION (0x0FU << UART_BRR_FRACTION_Pos) ///< UART DIV FRACTION
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_RXAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_RXAR_ADDR_Pos (0)
+#define UART_RXAR_ADDR (0xFFU << UART_RXAR_ADDR_Pos) ///< Synchronous frame match address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_RXMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_RXMR_MASK_Pos (0)
+#define UART_RXMR_MASK (0xFFU << UART_RXMR_MASK_Pos) ///< Synchronous frame match address mask
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_SCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_SCR_SCEN_Pos (0)
+#define UART_SCR_SCEN (0x01U << UART_SCR_SCEN_Pos) ///< ISO7816 enable bit
+#define UART_SCR_SCARB_Pos (1)
+#define UART_SCR_SCARB (0x01U << UART_SCR_SCARB_Pos) ///< ISO7816 check auto answer bit
+#define UART_SCR_NACK_Pos (2)
+#define UART_SCR_NACK (0x01U << UART_SCR_NACK_Pos) ///< Master receive frame answer bit
+#define UART_SCR_SCFCNT_Pos (4)
+#define UART_SCR_SCFCNT (0xFFU << UART_SCR_SCFCNT_Pos) ///< ISO7816 protection counter bit
+#define UART_SCR_HDSEL_Pos (12)
+#define UART_SCR_HDSEL (0x01U << UART_SCR_HDSEL_Pos) ///< Single-line half-duplex mode selection bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_ABRCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_ABRCR_ABREN_Pos (0)
+#define UART_ABRCR_ABREN (0x01U<© COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_USB_OTG_FS_H
+#define __REG_USB_OTG_FS_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USB Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define USB_OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000) ///< Base Address: 0x50000000
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USB Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+ __IO u32 PER_ID; ///< Peripheral ID register offset: 0x00
+ __IO u32 ID_COMP; ///< Peripheral ID complement register offset: 0x04
+ __IO u32 REV; ///< Peripheral revision register offset: 0x08
+ __IO u32 ADD_INFO; ///< Peripheral additional info register offset: 0x0C
+ __IO u32 OTG_ISTAT; ///< OTG Interrupt Status Register offset: 0x10
+ __IO u32 OTG_ICTRL; ///< OTG Interrupt Control Register offset: 0x14
+ __IO u32 OTG_STAT; ///< OTG Status Register offset: 0x18
+ __IO u32 OTG_CTRL; ///< OTG Control register offset: 0x1C
+ __IO u32 RESERVED0[24]; ///< Reserved offset: 0x20
+ __IO u32 INT_STAT; ///< Interrupt status register offset: 0x80
+ __IO u32 INT_ENB; ///< Interrupt enable register offset: 0x84
+ __IO u32 ERR_STAT; ///< Error interrupt status register offset: 0x88
+ __IO u32 ERR_ENB; ///< Error interrupt enable register offset: 0x8C
+ __IO u32 STAT; ///< Status register offset: 0x90
+ __IO u32 CTL; ///< Control register offset: 0x94
+ __IO u32 ADDR; ///< Address register offset: 0x98
+ __IO u32 BDT_PAGE_01; ///< BDT page register 1 offset: 0x9C
+ __IO u32 FRM_NUML; ///< Frame number register offset: 0xA0
+ __IO u32 FRM_NUMH; ///< Frame number register offset: 0xA4
+ __IO u32 TOKEN; ///< Token register offset: 0xA8
+ __IO u32 SOF_THLD; ///< SOF threshold register offset: 0xAC
+ __IO u32 BDT_PAGE_02; ///< BDT page register 2 offset: 0xB0
+ __IO u32 BDT_PAGE_03; ///< BDT page register 3 offset: 0xB4
+ __IO u32 RESERVED1; ///< Reserved offset: 0xB8
+ __IO u32 RESERVED2; ///< Reserved offset: 0xBC
+ __IO u32 EP_CTL[16]; ///< Endpoint control register offset: 0xC0
+} USB_OTG_FS_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USBD type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define USB_OTG_FS ((USB_OTG_FS_TypeDef*) USB_OTG_FS_BASE )
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_PER_ID Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_PER_ID_ID_Pos (0)
+#define OTG_FS_PER_ID_ID (0x3FU << OTG_FS_PER_ID_ID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ID_COMP Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ID_COMP_NID_Pos (0)
+#define OTG_FS_ID_COMP_NID (0x3FU << OTG_FS_ID_COMP_NID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_REV Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_REV_REV_Pos (0)
+#define OTG_FS_REV_REV (0xFFU << OTG_FS_REV_REV_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ADD_INFO Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ADD_INFO_HOST_Pos (0)
+#define OTG_FS_ADD_INFO_HOST (0x01U << OTG_FS_ADD_INFO_HOST_Pos)
+#define OTG_FS_ADD_INFO_IRQ_NUM_Pos (3)
+#define OTG_FS_ADD_INFO_IRQ_NUM (0x1FU << OTG_FS_ADD_INFO_IRQ_NUM_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_ISTAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos (0)
+#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos (2)
+#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG (0x01U << OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos (3)
+#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos (5)
+#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG (0x01U << OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_1_MSEC_Pos (6)
+#define OTG_FS_OTG_ISTAT_1_MSEC (0x01U << OTG_FS_OTG_ISTAT_1_MSEC_Pos)
+#define OTG_FS_OTG_ISTAT_ID_CHG_Pos (7)
+#define OTG_FS_OTG_ISTAT_ID_CHG (0x01U << OTG_FS_OTG_ISTAT_ID_CHG_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_ICTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos (0)
+#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos)
+#define OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos (2)
+#define OTG_FS_OTG_ICTRL_B_SESS_END_EN (0x01U << OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos)
+#define OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos (3)
+#define OTG_FS_OTG_ICTRL_SESS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos)
+#define OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos (5)
+#define OTG_FS_OTG_ICTRL_LINE_STATE_EN (0x01U << OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos)
+#define OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos (6)
+#define OTG_FS_OTG_ICTRL_1_MSEC_EN (0x01U << OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos)
+#define OTG_FS_OTG_ICTRL_ID_EN_Pos (7)
+#define OTG_FS_OTG_ICTRL_ID_EN (0x01U << OTG_FS_OTG_ICTRL_ID_EN_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_STAT_A_VBUS_VLD_Pos (0)
+#define OTG_FS_OTG_STAT_A_VBUS_VLD (0x01U << OTG_FS_OTG_STAT_A_VBUS_VLD_Pos)
+#define OTG_FS_OTG_STAT_B_SESS_END_Pos (2)
+#define OTG_FS_OTG_STAT_B_SESS_END (0x01U << OTG_FS_OTG_STAT_B_SESS_END_Pos)
+#define OTG_FS_OTG_STAT_SESS_VLD_Pos (3)
+#define OTG_FS_OTG_STAT_SESS_VLD (0x01U << OTG_FS_OTG_STAT_SESS_VLD_Pos)
+#define OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos (5)
+#define OTG_FS_OTG_STAT_LINE_STATE_STABLE (0x01U << OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos)
+#define OTG_FS_OTG_STAT_1_MSEC_Pos (6)
+#define OTG_FS_OTG_STAT_1_MSEC (0x01U << OTG_FS_OTG_STAT_1_MSEC_Pos)
+#define OTG_FS_OTG_STAT_ID_Pos (7)
+#define OTG_FS_OTG_STAT_ID (0x01U << OTG_FS_OTG_STAT_ID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_CTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos (0)
+#define OTG_FS_OTG_CTRL_VBUS_DSCHG (0x01U << OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos)
+#define OTG_FS_OTG_CTRL_VBUS_CHG_Pos (1)
+#define OTG_FS_OTG_CTRL_VBUS_CHG (0x01U << OTG_FS_OTG_CTRL_VBUS_CHG_Pos)
+#define OTG_FS_OTG_CTRL_OTG_EN_Pos (2)
+#define OTG_FS_OTG_CTRL_OTG_EN (0x01U << OTG_FS_OTG_CTRL_OTG_EN_Pos)
+#define OTG_FS_OTG_CTRL_VBUS_ON_Pos (3)
+#define OTG_FS_OTG_CTRL_VBUS_ON (0x01U << OTG_FS_OTG_CTRL_VBUS_ON_Pos)
+#define OTG_FS_OTG_CTRL_DM_LOW_Pos (4)
+#define OTG_FS_OTG_CTRL_DM_LOW (0x01U << OTG_FS_OTG_CTRL_DM_LOW_Pos)
+#define OTG_FS_OTG_CTRL_DP_LOW_Pos (5)
+#define OTG_FS_OTG_CTRL_DP_LOW (0x01U << OTG_FS_OTG_CTRL_DP_LOW_Pos)
+#define OTG_FS_OTG_CTRL_DM_HIGH_Pos (6)
+#define OTG_FS_OTG_CTRL_DM_HIGH (0x01U << OTG_FS_OTG_CTRL_DM_HIGH_Pos)
+#define OTG_FS_OTG_CTRL_DP_HIGH_Pos (7)
+#define OTG_FS_OTG_CTRL_DP_HIGH (0x01U << OTG_FS_OTG_CTRL_DP_HIGH_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_INT_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_INT_STAT_USB_RST_Pos (0)
+#define OTG_FS_INT_STAT_USB_RST (0x01U << OTG_FS_INT_STAT_USB_RST_Pos)
+#define OTG_FS_INT_STAT_ERROR_Pos (1)
+#define OTG_FS_INT_STAT_ERROR (0x01U << OTG_FS_INT_STAT_ERROR_Pos)
+#define OTG_FS_INT_STAT_SOF_TOK_Pos (2)
+#define OTG_FS_INT_STAT_SOF_TOK (0x01U << OTG_FS_INT_STAT_SOF_TOK_Pos)
+#define OTG_FS_INT_STAT_TOK_DNE_Pos (3)
+#define OTG_FS_INT_STAT_TOK_DNE (0x01U << OTG_FS_INT_STAT_TOK_DNE_Pos)
+#define OTG_FS_INT_STAT_SLEEP_Pos (4)
+#define OTG_FS_INT_STAT_SLEEP (0x01U << OTG_FS_INT_STAT_SLEEP_Pos)
+#define OTG_FS_INT_STAT_RESUME_Pos (5)
+#define OTG_FS_INT_STAT_RESUME (0x01U << OTG_FS_INT_STAT_RESUME_Pos)
+#define OTG_FS_INT_STAT_ATTACH_Pos (6)
+#define OTG_FS_INT_STAT_ATTACH (0x01U << OTG_FS_INT_STAT_ATTACH_Pos)
+#define OTG_FS_INT_STAT_STALL_Pos (7)
+#define OTG_FS_INT_STAT_STALL (0x01U << OTG_FS_INT_STAT_STALL_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_INT_ENB Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_INT_ENB_USB_RST_EN_Pos (0)
+#define OTG_FS_INT_ENB_USB_RST_EN (0x01U << OTG_FS_INT_ENB_USB_RST_EN_Pos)
+#define OTG_FS_INT_ENB_ERROR_EN_Pos (1)
+#define OTG_FS_INT_ENB_ERROR_EN (0x01U << OTG_FS_INT_ENB_ERROR_EN_Pos)
+#define OTG_FS_INT_ENB_SOF_TOK_EN_Pos (2)
+#define OTG_FS_INT_ENB_SOF_TOK_EN (0x01U << OTG_FS_INT_ENB_SOF_TOK_EN_Pos)
+#define OTG_FS_INT_ENB_TOK_DNE_EN_Pos (3)
+#define OTG_FS_INT_ENB_TOK_DNE_EN (0x01U << OTG_FS_INT_ENB_TOK_DNE_EN_Pos)
+#define OTG_FS_INT_ENB_SLEEP_EN_Pos (4)
+#define OTG_FS_INT_ENB_SLEEP_EN (0x01U << OTG_FS_INT_ENB_SLEEP_EN_Pos)
+#define OTG_FS_INT_ENB_RESUME_EN_Pos (5)
+#define OTG_FS_INT_ENB_RESUME_EN (0x01U << OTG_FS_INT_ENB_RESUME_EN_Pos)
+#define OTG_FS_INT_ENB_ATTACH_EN_Pos (6)
+#define OTG_FS_INT_ENB_ATTACH_EN (0x01U << OTG_FS_INT_ENB_ATTACH_EN_Pos)
+#define OTG_FS_INT_ENB_STALL_EN_Pos (7)
+#define OTG_FS_INT_ENB_STALL_EN (0x01U << OTG_FS_INT_ENB_STALL_EN_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ERR_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ERR_STAT_PID_ERR_Pos (0)
+#define OTG_FS_ERR_STAT_PID_ERR (0x01U << OTG_FS_ERR_STAT_PID_ERR_Pos)
+#define OTG_FS_ERR_STAT_CRC5_EOF_Pos (1)
+#define OTG_FS_ERR_STAT_CRC5_EOF (0x01U << OTG_FS_ERR_STAT_CRC5_EOF_Pos)
+#define OTG_FS_ERR_STAT_CRC16_Pos (2)
+#define OTG_FS_ERR_STAT_CRC16 (0x01U << OTG_FS_ERR_STAT_CRC16_Pos)
+#define OTG_FS_ERR_STAT_DFN8_Pos (3)
+#define OTG_FS_ERR_STAT_DFN8 (0x01U << OTG_FS_ERR_STAT_DFN8_Pos)
+#define OTG_FS_ERR_STAT_BTO_ERR_Pos (4)
+#define OTG_FS_ERR_STAT_BTO_ERR (0x01U << OTG_FS_ERR_STAT_BTO_ERR_Pos)
+#define OTG_FS_ERR_STAT_DMA_ERR_Pos (5)
+#define OTG_FS_ERR_STAT_DMA_ERR (0x01U << OTG_FS_ERR_STAT_DMA_ERR_Pos)
+#define OTG_FS_ERR_STAT_BTS_ERR_Pos (7)
+#define OTG_FS_ERR_STAT_BTS_ERR (0x01U << OTG_FS_ERR_STAT_BTS_ERR_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ERR_ENB Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ERR_ENB_PID_ERR_EN_Pos (0)
+#define OTG_FS_ERR_ENB_PID_ERR_EN (0x01U << OTG_FS_ERR_ENB_PID_ERR_EN_Pos)
+#define OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos (1)
+#define OTG_FS_ERR_ENB_CRC5_EOF_EN (0x01U << OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos)
+#define OTG_FS_ERR_ENB_CRC16_EN_Pos (2)
+#define OTG_FS_ERR_ENB_CRC16_EN (0x01U << OTG_FS_ERR_ENB_CRC16_EN_Pos)
+#define OTG_FS_ERR_ENB_DFN8_EN_Pos (3)
+#define OTG_FS_ERR_ENB_DFN8_EN (0x01U << OTG_FS_ERR_ENB_DFN8_EN_Pos)
+#define OTG_FS_ERR_ENB_BTO_ERR_EN_Pos (4)
+#define OTG_FS_ERR_ENB_BTO_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTO_ERR_EN_Pos)
+#define OTG_FS_ERR_ENB_DMA_ERR_EN_Pos (5)
+#define OTG_FS_ERR_ENB_DMA_ERR_EN (0x01U << OTG_FS_ERR_ENB_DMA_ERR_EN_Pos)
+#define OTG_FS_ERR_ENB_BTS_ERR_EN_Pos (7)
+#define OTG_FS_ERR_ENB_BTS_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTS_ERR_EN_Pos)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_STAT_ODD_Pos (2)
+#define OTG_FS_STAT_ODD (0x01U << OTG_FS_STAT_ODD_Pos)
+#define OTG_FS_STAT_TX_Pos (3)
+#define OTG_FS_STAT_TX (0x01U << OTG_FS_STAT_TX_Pos)
+#define OTG_FS_STAT_ENDP_Pos (4)
+#define OTG_FS_STAT_ENDP (0x0FU << OTG_FS_STAT_ENDP_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_CTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_CTL_USB_EN_SOF_EN_Pos (0)
+#define OTG_FS_CTL_USB_EN_SOF_EN (0x01U << OTG_FS_CTL_USB_EN_SOF_EN_Pos)
+#define OTG_FS_CTL_ODD_RST_Pos (1)
+#define OTG_FS_CTL_ODD_RST (0x01U << OTG_FS_CTL_ODD_RST_Pos)
+#define OTG_FS_CTL_RESUME_Pos (2)
+#define OTG_FS_CTL_RESUME (0x01U << OTG_FS_CTL_RESUME_Pos)
+#define OTG_FS_CTL_HOST_MODE_EN_Pos (3)
+#define OTG_FS_CTL_HOST_MODE_EN (0x01U << OTG_FS_CTL_HOST_MODE_EN_Pos)
+#define OTG_FS_CTL_RESET_Pos (4)
+#define OTG_FS_CTL_RESET (0x01U << OTG_FS_CTL_RESET_Pos)
+#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos (5)
+#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY (0x01U << OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos)
+#define OTG_FS_CTL_SE0_Pos (6)
+#define OTG_FS_CTL_SE0 (0x01U << OTG_FS_CTL_SE0_Pos)
+#define OTG_FS_CTL_JSTATE_Pos (7)
+#define OTG_FS_CTL_JSTATE (0x01U << OTG_FS_CTL_JSTATE_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ADDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ADDR_ADDR_Pos (0)
+#define OTG_FS_ADDR_ADDR (0x7FU << OTG_FS_ADDR_ADDR_Pos)
+#define OTG_FS_ADDR_LS_EN_Pos (7)
+#define OTG_FS_ADDR_LS_EN (0x01U << OTG_FS_ADDR_LS_EN_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_BDT_PAGE_01 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos (1)
+#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9 (0x7FU << OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_FRM_NUML Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_FRM_NUML_FRM_Pos (0)
+#define OTG_FS_FRM_NUML_FRM (0xFFU << OTG_FS_FRM_NUML_FRM_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_FRM_NUMH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_FRM_NUMH_FRM_Pos (0)
+#define OTG_FS_FRM_NUMH_FRM (0x07U << OTG_FS_FRM_NUMH_FRM_Pos)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_TOKEN Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_TOKEN_TOKEN_ENDPT_Pos (0)
+#define OTG_FS_TOKEN_TOKEN_ENDPT (0x0FU << OTG_FS_TOKEN_TOKEN_ENDPT_Pos)
+#define OTG_FS_TOKEN_TOKEN_PID_Pos (4)
+#define OTG_FS_TOKEN_TOKEN_PID (0x0FU << OTG_FS_TOKEN_TOKEN_PID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_SOF_THLD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_SOF_THLD_CNT_Pos (0)
+#define OTG_FS_SOF_THLD_CNT (0xFFU << OTG_FS_SOF_THLD_CNT_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_BDT_PAGE_02 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos (0)
+#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16 (0xFFU << OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_BDT_PAGE_03 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos (0)
+#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24 (0xFFU << OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_EP_CTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_EP_CTL_EP_HSHK_Pos (0)
+#define OTG_FS_EP_CTL_EP_HSHK (0x01U << OTG_FS_EP_CTL_EP_HSHK_Pos)
+#define OTG_FS_EP_CTL_EP_STALL_Pos (1)
+#define OTG_FS_EP_CTL_EP_STALL (0x01U << OTG_FS_EP_CTL_EP_STALL_Pos)
+#define OTG_FS_EP_CTL_EP_TX_EN_Pos (2)
+#define OTG_FS_EP_CTL_EP_TX_EN (0x01U << OTG_FS_EP_CTL_EP_TX_EN_Pos)
+#define OTG_FS_EP_CTL_EP_RX_EN_Pos (3)
+#define OTG_FS_EP_CTL_EP_RX_EN (0x01U << OTG_FS_EP_CTL_EP_RX_EN_Pos)
+#define OTG_FS_EP_CTL_EP_CTL_DIS_Pos (4)
+#define OTG_FS_EP_CTL_EP_CTL_DIS (0x01U << OTG_FS_EP_CTL_EP_CTL_DIS_Pos)
+#define OTG_FS_EP_CTL_RETRY_DIS_Pos (6)
+#define OTG_FS_EP_CTL_RETRY_DIS (0x01U << OTG_FS_EP_CTL_RETRY_DIS_Pos)
+#define OTG_FS_EP_CTL_HOST_WO_HUB_Pos (7)
+#define OTG_FS_EP_CTL_HOST_WO_HUB (0x01U << OTG_FS_EP_CTL_HOST_WO_HUB_Pos)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS Buffer Descriptor Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define OTG_FS_BD_TOK_PID_Pos (2)
+#define OTG_FS_BD_TOK_PID (0x0FU << OTG_FS_BD_TOK_PID_Pos)
+#define OTG_FS_BD_DATA01_Pos (6)
+#define OTG_FS_BD_DATA01 (0x01U << OTG_FS_BD_DATA01_Pos)
+#define OTG_FS_BD_OWN_Pos (7)
+#define OTG_FS_BD_OWN (0x01U << OTG_FS_BD_OWN_Pos)
+#define OTG_FS_BD_BC_Pos (16)
+#define OTG_FS_BD_BC (0x3FFU << OTG_FS_BD_BC_Pos)
+#define OTG_FS_BD_ADDRESS_Pos (0)
+#define OTG_FS_BD_ADDRESS (0xFFFFFFFFU << OTG_FS_BD_ADDRESS_Pos)
+
+
+
+/**
+* @}
+*/
+//#define OTG_FS_INT_STAT_RST ((uint32_t)0x01)
+//#define OTG_FS_INT_STAT_ERROR ((uint32_t)0x02)
+//#define OTG_FS_INT_STAT_SOF ((uint32_t)0x04)
+//#define OTG_FS_INT_STAT_DNE ((uint32_t)0x08)
+//#define OTG_FS_INT_STAT_SLEEP ((uint32_t)0x10)
+//#define OTG_FS_INT_STAT_RESUME ((uint32_t)0x20)
+//#define OTG_FS_INT_STAT_ATTACH ((uint32_t)0x40)
+//#define OTG_FS_INT_STAT_STALL ((uint32_t)0x80)
+
+//TEMP
+#define USB_INT_STAT_RST 0x01
+#define USB_INT_STAT_ERROR 0x02
+#define USB_INT_STAT_SOF_TOK 0x04
+#define USB_INT_STAT_TOK_DNE 0x08
+#define USB_INT_STAT_SLEEP 0x10
+#define USB_INT_STAT_RESUME 0x20
+#define USB_INT_STAT_ATTACH 0x40
+#define USB_INT_STAT_STALL 0x80
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_OWNERR_MASK (0x40U)
+#define USB_ERRSTAT_OWNERR_SHIFT (6U)
+#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_OWNERREN_MASK (0x40U)
+#define USB_ERREN_OWNERREN_SHIFT (6U)
+#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_UARTSEL_MASK (0x10U)
+#define USB_USBCTRL_UARTSEL_SHIFT (4U)
+#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
+#define USB_USBCTRL_UARTCHLS_MASK (0x20U)
+#define USB_USBCTRL_UARTCHLS_SHIFT (5U)
+#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_VREDG_DET_MASK (0x8U)
+#define USB_USBTRC0_VREDG_DET_SHIFT (3U)
+#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
+#define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
+#define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
+#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+/*! @name MISCCTRL - Miscellaneous Control register */
+#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U)
+#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U)
+#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
+#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U)
+#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U)
+#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
+#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
+#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
+#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
+#define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
+#define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
+#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
+#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
+#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
+#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
+#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U)
+#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U)
+#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
+
+/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
+#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
+
+/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
+#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
+
+/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
+#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
+
+/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
+#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+#define USB0_BASE ((0x50000000))
+
+#define USB_BASE_ADDRS { USB0_BASE }
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__REG_USB_OTG_FS_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
new file mode 100644
index 00000000..a802bbab
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
@@ -0,0 +1,133 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file reg_wwdg.h
+/// @author AE TEAM
+/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+/// MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_WWDG_H
+#define __REG_WWDG_H
+
+// Files includes
+
+#include
+#include
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) ///< Base Address: 0x40002C00
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+#undef USENCOMBINEREGISTER
+#undef USENNEWREGISTER
+#undef USENOLDREGISTER
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+typedef struct {
+ __IO u32 CR; ///< Control register offset: 0x00
+ union {
+ __IO u32 CFGR; ///< Configuration register offset: 0x04
+ __IO u32 CFR;
+ };
+ __IO u32 SR; ///< Status register offset: 0x08
+} WWDG_TypeDef;
+#endif
+#ifdef USENNEWREGISTER
+typedef struct {
+ __IO u32 CR; ///< Control register offset: 0x00
+ __IO u32 CFGR; ///< Configuration register offset: 0x04
+ __IO u32 SR; ///< Status register offset: 0x08
+} WWDG_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+ __IO u32 CR;
+ __IO u32 CFR;
+ __IO u32 SR;
+} WWDG_TypeDef;
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG ((WWDG_TypeDef*) WWDG_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_CR_CNT_Pos (0)
+#define WWDG_CR_CNT (0x7FU << WWDG_CR_CNT_Pos) ///< T[6:0] bits (7-Bit counter (MSB to LSB))
+#define WWDG_CR_WDGA_Pos (7)
+#define WWDG_CR_WDGA (0x01U << WWDG_CR_WDGA_Pos) ///< Activation bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_CFR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_CFGR_WINDOW_Pos (0)
+#define WWDG_CFGR_WINDOW (0x7FU << WWDG_CFGR_WINDOW_Pos) ///< W[6:0] bits (7-bit window value)
+#define WWDG_CFGR_WDGTB_Pos (7)
+#define WWDG_CFGR_WDGTB (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base)
+#define WWDG_CFGR_WDGTB_1 (0x00U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /1)
+#define WWDG_CFGR_WDGTB_2 (0x01U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /2)
+#define WWDG_CFGR_WDGTB_4 (0x02U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /4)
+#define WWDG_CFGR_WDGTB_8 (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /8)
+#define WWDG_CFGR_EWI_Pos (9)
+#define WWDG_CFGR_EWI (0x01U << WWDG_CFGR_EWI_Pos) ///< Early Wakeup Interrupt
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_SR_EWIF_Pos (0)
+#define WWDG_SR_EWIF (0x01U << WWDG_SR_EWIF_Pos) ///< Early Wakeup Interrupt Flag
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
new file mode 100644
index 00000000..baceddd0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
@@ -0,0 +1,105 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file types.h
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE TYPE FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __TYPES_H
+#define __TYPES_H
+
+// Files includes
+#include
+#include
+
+
+
+#ifdef __cplusplus
+#define __I volatile ///< Defines 'read only' permissions
+#else
+#define __I volatile const ///< Defines 'read only' permissions
+#endif
+#define __O volatile ///< Defines 'write only' permissions
+#define __IO volatile ///< Defines 'read / write' permissions
+
+typedef long long s64; ///< used for signed 64bit
+
+typedef signed int s32;
+typedef signed short s16;
+typedef signed char s8;
+
+typedef signed int const sc32; ///< Read Only
+typedef signed short const sc16; ///< Read Only
+typedef signed char const sc8; ///< Read Only
+
+typedef volatile signed int vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char vs8;
+
+typedef volatile signed int const vsc32; ///< Read Only
+typedef volatile signed short const vsc16; ///< Read Only
+typedef volatile signed char const vsc8; ///< Read Only
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+typedef unsigned int const uc32; ///< Read Only
+typedef unsigned short const uc16; ///< Read Only
+typedef unsigned char const uc8; ///< Read Only
+
+typedef volatile unsigned int vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char vu8;
+
+typedef volatile unsigned int const vuc32; ///< Read Only
+typedef volatile unsigned short const vuc16; ///< Read Only
+typedef volatile unsigned char const vuc8; ///< Read Only
+typedef bool BOOL;
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define U8_MAX ((u8)255)
+#define S8_MAX ((s8)127)
+#define S8_MIN ((s8)-128)
+#define U16_MAX ((u16)65535u)
+#define S16_MAX ((s16)32767)
+#define S16_MIN ((s16)-32768)
+#define U32_MAX ((u32)4294967295uL)
+#define S32_MAX ((s32)2147483647)
+#define S32_MIN ((s32)-2147483648uL)
+
+#define MAX(a,b)((a)>(b)?(a):(b))
+#define MIN(a,b)((a)<(b)?(a):(b))
+
+#define SET_BIT(reg, bit) ((reg) |= (bit))
+#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
+#define READ_BIT(reg, bit) ((reg) & (bit))
+#define CLEAR_REG(reg) ((reg) = (0x0))
+#define WRITE_REG(reg, value) ((reg) = (value))
+#define READ_REG(reg) ((reg))
+#define MODIFY_REG(reg, CLEARMASK, SETMASK) WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) | (SETMASK)))
+#define POSITION_VAL(value) (__CLZ(__RBIT(value)))
+
+#define LEFT_SHIFT_BIT(x) (1 << x)
+
+
+#endif
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
new file mode 100644
index 00000000..920aefcb
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
@@ -0,0 +1,440 @@
+/**
+ ******************************************************************************
+ * @file startup_mm32m3ux_u_gcc.s
+ * @author AE Team
+ * @brief MM32 devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+ .global g_pfnVectors
+ .global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+ .word _sidata
+/* start address for the .data section. defined in linker script */
+ .word _sdata
+/* end address for the .data section. defined in linker script */
+ .word _edata
+/* start address for the .bss section. defined in linker script */
+ .word _sbss
+/* end address for the .bss section. defined in linker script */
+ .word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack /* Top of Stack */
+ .word Reset_Handler /* Reset Handler */
+ .word NMI_Handler /*-14 NMI Handler */
+ .word HardFault_Handler /*-13 Hard Fault Handler */
+ .word MemManage_Handler /*-12 MPU Fault Handler */
+ .word BusFault_Handler /*-11 Bus Fault Handler */
+ .word UsageFault_Handler /*-10 Usage Fault Handler */
+ .word 0 /*-9 Reserved */
+ .word 0 /*-8 Reserved */
+ .word 0 /*-7 Reserved */
+ .word 0 /*-6 Reserved */
+ .word SVC_Handler /*-5 SVCall Handler */
+ .word DebugMon_Handler /*-4 Debug Monitor Handler */
+ .word 0 /*-3 Reserved */
+ .word PendSV_Handler /*-2 PendSV Handler */
+ .word SysTick_Handler /*-1 SysTick Handler */
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /*0 Window Watchdog */
+ .word PVD_IRQHandler /*1 PVD through EXTI Line detect */
+ .word TAMPER_IRQHandler /*2 Tamper */
+ .word RTC_IRQHandler /*3 RTC */
+ .word FLASH_IRQHandler /*4 Flash */
+ .word RCC_CRS_IRQHandler /*5 RCC */
+ .word EXTI0_IRQHandler /*6 EXTI Line 0 */
+ .word EXTI1_IRQHandler /*7 EXTI Line 1 */
+ .word EXTI2_IRQHandler /*8 EXTI Line 2 */
+ .word EXTI3_IRQHandler /*9 EXTI Line 3 */
+ .word EXTI4_IRQHandler /*10 EXTI Line 4 */
+ .word DMA1_Channel1_IRQHandler /*11 DMA1 Channel 1 */
+ .word DMA1_Channel2_IRQHandler /*12 DMA1 Channel 2 */
+ .word DMA1_Channel3_IRQHandler /*13 DMA1 Channel 3 */
+ .word DMA1_Channel4_IRQHandler /*14 DMA1 Channel 4 */
+ .word DMA1_Channel5_IRQHandler /*15 DMA1 Channel 5 */
+ .word DMA1_Channel6_IRQHandler /*16 DMA1 Channel 6 */
+ .word DMA1_Channel7_IRQHandler /*17 DMA1 Channel 7 */
+ .word ADC1_2_IRQHandler /*18 ADC1 and ADC2 */
+ .word FlashCache_IRQHandler /*19 FlashCache outage */
+ .word 0 /*20 Reserved */
+ .word CAN1_RX_IRQHandler /*21 CAN1_RX */
+ .word 0 /*22 Reserved */
+ .word EXTI9_5_IRQHandler /*23 EXTI Line 9..5 */
+ .word TIM1_BRK_IRQHandler /*24 TIM1 Break */
+ .word TIM1_UP_IRQHandler /*25 TIM1 Update */
+ .word TIM1_TRG_COM_IRQHandler /*26 TIM1 Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /*27 TIM1 Capture Compare */
+ .word TIM2_IRQHandler /*28 TIM2 */
+ .word TIM3_IRQHandler /*29 TIM3 */
+ .word TIM4_IRQHandler /*30 TIM4 */
+ .word I2C1_IRQHandler /*31 I2C1 Event */
+ .word 0 /*32 Reserved */
+ .word I2C2_IRQHandler /*33 I2C2 Event */
+ .word 0 /*34 Reserved */
+ .word SPI1_IRQHandler /*35 SPI1 */
+ .word SPI2_IRQHandler /*36 SPI2 */
+ .word UART1_IRQHandler /*37 UART1 */
+ .word UART2_IRQHandler /*38 UART2 */
+ .word UART3_IRQHandler /*39 UART3 */
+ .word EXTI15_10_IRQHandler /*40 EXTI Line 15..10 */
+ .word RTCAlarm_IRQHandler /*41 RTC Alarm through EXTI Line 17 */
+ .word OTG_FS_WKUP_IRQHandler /*42 USB OTG FS Wakeup through EXTI line */
+ .word TIM8_BRK_IRQHandler /*43 TIM8 Break */
+ .word TIM8_UP_IRQHandler /*44 TIM8 Update */
+ .word TIM8_TRG_COM_IRQHandler /*45 TIM8 Trigger and Commutation */
+ .word TIM8_CC_IRQHandler /*46 TIM8 Capture Compare */
+ .word ADC3_IRQHandler /*47 ADC3 */
+ .word 0 /*48 Reserved */
+ .word SDIO_IRQHandler /*49 SDIO */
+ .word TIM5_IRQHandler /*50 TIM5 */
+ .word SPI3_IRQHandler /*51 SPI3 */
+ .word UART4_IRQHandler /*52 UART4 */
+ .word UART5_IRQHandler /*53 UART5 */
+ .word TIM6_IRQHandler /*54 TIM6 */
+ .word TIM7_IRQHandler /*55 TIM7 */
+ .word DMA2_Channel1_IRQHandler /*56 DMA2 Channel 1 */
+ .word DMA2_Channel2_IRQHandler /*57 DMA2 Channel 2 */
+ .word DMA2_Channel3_IRQHandler /*58 DMA2 Channel 3 */
+ .word DMA2_Channel4_IRQHandler /*59 DMA2 Channel 4 */
+ .word DMA2_Channel5_IRQHandler /*60 DMA2 Channel 5 */
+ .word ETH_IRQHandler /*61 Ethernet */
+ .word 0 /*62 Reserved */
+ .word 0 /*63 Reserved */
+ .word COMP1_2_IRQHandler /*64 COMP1,COMP2 */
+ .word 0 /*65 Reserved */
+ .word 0 /*66 Reserved */
+ .word OTG_FS_IRQHandler /*67 USB OTG_FullSpeed */
+ .word 0 /*68 Reserved */
+ .word 0 /*69 Reserved */
+ .word 0 /*70 Reserved */
+ .word UART6_IRQHandler /*71 UART6 */
+ .word 0 /*72 Reserved */
+ .word 0 /*73 Reserved */
+ .word 0 /*74 Reserved */
+ .word 0 /*75 Reserved */
+ .word 0 /*76 Reserved */
+ .word 0 /*77 Reserved */
+ .word 0 /*78 Reserved */
+ .word 0 /*79 Reserved */
+ .word 0 /*80 Reserved */
+ .word 0 /*81 Reserved */
+ .word UART7_IRQHandler /*82 UART7 */
+ .word UART8_IRQHandler /*83 UART8 */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler ,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler ,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler ,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler ,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler ,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler ,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler ,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler ,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler ,Default_Handler
+
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler ,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler ,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler ,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler ,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler ,Default_Handler
+
+ .weak RCC_CRS_IRQHandler
+ .thumb_set RCC_CRS_IRQHandler ,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler ,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler ,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler ,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler ,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler ,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler ,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler ,Default_Handler
+
+ .weak FlashCache_IRQHandler
+ .thumb_set FlashCache_IRQHandler ,Default_Handler
+
+ .weak CAN1_RX_IRQHandler
+ .thumb_set CAN1_RX_IRQHandler ,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler ,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler ,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler ,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler ,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler ,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler ,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler ,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler ,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler ,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler ,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler ,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler ,Default_Handler
+
+ .weak UART1_IRQHandler
+ .thumb_set UART1_IRQHandler ,Default_Handler
+
+ .weak UART2_IRQHandler
+ .thumb_set UART2_IRQHandler ,Default_Handler
+
+ .weak UART3_IRQHandler
+ .thumb_set UART3_IRQHandler ,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler ,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler ,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler ,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler ,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler ,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler ,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler ,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler ,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler ,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler ,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler ,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler ,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler ,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler ,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler ,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler ,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler ,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler ,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler ,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler ,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler ,Default_Handler
+
+ .weak COMP1_2_IRQHandler
+ .thumb_set COMP1_2_IRQHandler ,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler ,Default_Handler
+
+ .weak UART6_IRQHandler
+ .thumb_set UART6_IRQHandler ,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler ,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler ,Default_Handler
+
+
+
+
+/****END OF FILE****/
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
new file mode 100644
index 00000000..cdfa8e80
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
@@ -0,0 +1,866 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file SYSTEM_MM32.C
+/// @author AE TEAM
+/// @brief THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _SYSTEM_MM32_C_
+
+// Files includes
+
+/// @addtogroup CMSIS
+/// @{
+
+#include "mm32_device.h"
+
+
+/// @}
+
+
+
+/// @}
+
+
+/// Uncomment the line corresponding to the desired System clock (SYSCLK)
+/// frequency (after reset the HSI is used as SYSCLK source)
+///
+/// IMPORTANT NOTE:
+/// ==============
+/// 1. After each device reset the HSI is used as System clock source.
+///
+/// 2. Please make sure that the selected System clock doesn't exceed your device's
+/// maximum frequency.
+///
+/// 3. If none of the define below is enabled, the HSI is used as System clock
+/// source.
+///
+/// 4. The System clock configuration functions provided within this file assume that:
+/// - For Low, Medium and High density Value line devices an external 8MHz
+/// crystal is used to drive the System clock.
+/// - For Low, Medium and High density devices an external 8MHz crystal is
+/// used to drive the System clock.
+/// - For Connectivity line devices an external 25MHz crystal is used to drive
+/// the System clock.
+/// If you are using different crystal you have to adapt those functions accordingly.
+
+//#define SYSCLK_FREQ_HSE HSE_VALUE //HSE_VALUE is define in reg_common.h
+//#define SYSCLK_FREQ_24MHz (HSE_VALUE*3) //24000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_36MHz (HSE_VALUE*9/2) //36000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_48MHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*9) //72000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //96000000 based HSE_VALUE = 8000000
+#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //120000000 based HSE_VALUE = 8000000
+
+#if defined(SYSCLK_FREQ_HSE) || defined(SYSCLK_FREQ_24MHz) || defined(SYSCLK_FREQ_36MHz) || defined(SYSCLK_FREQ_48MHz) || defined(SYSCLK_FREQ_XXMHz)
+
+#if defined(HSE_VALUE) && (!(HSE_VALUE == 8000000))
+#warning redefine HSE_VALUE in reg_common.h Line 48 and ignore this warning
+#endif
+
+#endif
+
+
+//#define SYSCLK_HSI_24MHz 24000000
+//#define SYSCLK_HSI_36MHz 36000000
+//#define SYSCLK_HSI_48MHz 48000000
+//#define SYSCLK_HSI_XXMHz 48000000
+//#define SYSCLK_HSI_XXMHz 72000000
+//#define SYSCLK_HSI_XXMHz 96000000
+#define SYSCLK_HSI_XXMHz 120000000
+/// Uncomment the following line if you need to relocate your vector Table in
+/// Internal SRAM.
+///#define VECT_TAB_SRAM
+#define VECT_TAB_OFFSET 0x0
+/// Vector Table base offset field.
+/// This value must be a multiple of 0x200.
+
+
+/// @}
+
+
+
+
+///////////////////////////////////////////////////////////////
+///Clock Definitions
+///////////////////////////////////////////////////////////////
+#if defined SYSCLK_FREQ_HSE
+u32 SystemCoreClock = SYSCLK_FREQ_HSE;
+#elif defined SYSCLK_FREQ_24MHz
+u32 SystemCoreClock = SYSCLK_FREQ_24MHz;
+#elif defined SYSCLK_FREQ_36MHz
+u32 SystemCoreClock = SYSCLK_FREQ_36MHz;
+#elif defined SYSCLK_FREQ_48MHz
+u32 SystemCoreClock = SYSCLK_FREQ_48MHz;
+#elif defined SYSCLK_FREQ_XXMHz
+u32 SystemCoreClock = SYSCLK_FREQ_XXMHz;
+
+
+#elif defined SYSCLK_HSI_24MHz
+u32 SystemCoreClock = SYSCLK_HSI_24MHz;
+#elif defined SYSCLK_HSI_36MHz
+u32 SystemCoreClock = SYSCLK_HSI_36MHz;
+#elif defined SYSCLK_HSI_48MHz
+u32 SystemCoreClock = SYSCLK_HSI_48MHz;
+#elif defined SYSCLK_HSI_XXMHz
+u32 SystemCoreClock = SYSCLK_HSI_XXMHz;
+#else //HSI Selected as System Clock source
+u32 SystemCoreClock = HSI_VALUE;
+#endif
+
+__I u8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/// @}
+
+
+static void SetSysClock(void);
+
+#if defined SYSCLK_FREQ_HSE
+static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_XXMHz
+static void SetSysClockToXX(void);
+
+#elif defined SYSCLK_HSI_24MHz
+static void SetSysClockTo24_HSI(void);
+#elif defined SYSCLK_HSI_36MHz
+static void SetSysClockTo36_HSI(void);
+#elif defined SYSCLK_HSI_48MHz
+static void SetSysClockTo48_HSI(void);
+#elif defined SYSCLK_HSI_XXMHz
+static void SetSysClockToXX_HSI(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif //DATA_IN_ExtSRAM
+
+
+/// @}
+
+
+
+/// @brief Setup the microcontroller system
+/// Initialize the Embedded Flash Interface, the PLL and update the
+/// SystemCoreClock variable.
+/// @note This function should be used only after reset.
+/// @param None
+/// @retval None
+
+void SystemInit (void)
+{
+ //Reset the RCC clock configuration to the default reset state(for debug purpose)
+ //Set HSION bit
+ RCC->CR |= (u32)0x00000001;
+
+ //Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits
+ RCC->CFGR &= (u32)0xF8FFC00C;
+
+ //Reset HSEON, CSSON and PLLON bits
+ RCC->CR &= (u32)0xFEF6FFFF;
+
+ //Reset HSEBYP bit
+ RCC->CR &= (u32)0xFFFBFFFF;
+
+ //Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits
+ RCC->CFGR &= (u32)0xFF3CFFFF;
+ RCC->CR &= (u32)0x008FFFFF;
+
+ //Disable all interrupts and clear pending bits
+ RCC->CIR = 0x009F0000;
+ //Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
+ //Configure the Flash Latency cycles and enable prefetch buffer
+ SetSysClock();
+}
+
+
+/// @brief use to return the pllm&plln.
+/// @param pllclkSourceFrq : PLL source clock frquency;
+/// pllclkFrq : Target PLL clock frquency;
+/// plln : PLL factor PLLN
+/// pllm : PLL factor PLLM
+/// @retval amount of error
+u32 AutoCalPllFactor(u32 pllclkSourceFrq, u32 pllclkFrq, u8* plln, u8* pllm)
+{
+ u32 n, m;
+ u32 tempFrq;
+ u32 minDiff = pllclkFrq;
+ u8 flag = 0;
+ for(m = 0; m < 4 ; m++) {
+ for(n = 0; n < 64 ; n++) {
+ tempFrq = pllclkSourceFrq * (n + 1) / (m + 1);
+ tempFrq = (tempFrq > pllclkFrq) ? (tempFrq - pllclkFrq) : (pllclkFrq - tempFrq) ;
+
+ if(minDiff > tempFrq) {
+ minDiff = tempFrq;
+ *plln = n;
+ *pllm = m;
+ }
+ if(minDiff == 0) {
+ flag = 1;
+ break;
+ }
+ }
+ if(flag != 0) {
+ break;
+ }
+ }
+ return minDiff;
+}
+static void DELAY_xUs(u32 count)
+{
+ u32 temp;
+ SysTick->CTRL = 0x0; //disable systick function
+ SysTick->LOAD = count * 8; //time count for 1us with HSI as SYSCLK
+ SysTick->VAL = 0x00; //clear counter
+ SysTick->CTRL = 0x5; //start discrease with Polling
+ do {
+ temp = SysTick->CTRL;
+ } while((temp & 0x01) && !(temp & (1 << 16))); //wait time count done
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; //Close Counter
+ SysTick->VAL = 0X00; //clear counter
+}
+/// @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+/// @param None
+/// @retval None
+
+static void SetSysClock(void)
+{
+ CACHE->CCR &= ~(0x3 << 3);
+ CACHE->CCR |= 1;
+ while((CACHE->SR & 0x3) != 2);
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_XXMHz
+ SetSysClockToXX();
+
+#elif defined SYSCLK_HSI_24MHz
+ SetSysClockTo24_HSI();
+#elif defined SYSCLK_HSI_36MHz
+ SetSysClockTo36_HSI();
+#elif defined SYSCLK_HSI_48MHz
+ SetSysClockTo48_HSI();
+#elif defined SYSCLK_HSI_XXMHz
+ SetSysClockToXX_HSI();
+#endif
+
+ //If none of the define above is enabled, the HSI is used as System clock
+ //source (default after reset)
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/// @brief Selects HSE as System clock source and configure HCLK, PCLK2
+/// and PCLK1 prescalers.
+/// @note This function should be used only after reset.
+/// @param None
+/// @retval None
+
+static void SetSysClockToHSE(void)
+{
+ __IO u32 StartUpCounter = 0, HSEStatus = 0;
+ s32 i;
+
+ //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+ //Enable HSE
+ RCC->CR |= ((u32)RCC_CR_HSEON);
+
+ //Wait till HSE is ready and if Time out is reached exit
+ do {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+ HSEStatus = (u32)0x01;
+ i = 2000;
+ while(i--);
+ }
+ else {
+ HSEStatus = (u32)0x00;
+ }
+
+ if (HSEStatus == (u32)0x01) {
+ //Enable Prefetch Buffer
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ //Flash 0 wait state ,bit0~2
+ FLASH->ACR &= ~0x07;
+ //HCLK = SYSCLK
+ RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+ //PCLK2 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+ //PCLK1 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
+
+ //Select HSE as system clock source
+ RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+ RCC->CFGR |= (u32)RCC_CFGR_SW_HSE;
+
+ //Wait till HSE is used as system clock source
+ while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) {
+ }
+ }
+ else {
+ //If HSE fails to start-up, the application will have wrong clock
+ //configuration. User can add here some code to deal with this error
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+
+/// @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+/// and PCLK1 prescalers.
+/// @note This function should be used only after reset.
+/// @param None
+/// @retval None
+
+static void SetSysClockTo24(void)
+{
+ __IO u32 StartUpCounter = 0, HSEStatus = 0;
+ s32 i;
+
+ //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+ //Enable HSE
+ RCC->CR |= ((u32)RCC_CR_HSEON);
+
+ //Wait till HSE is ready and if Time out is reached exit
+ do {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+ HSEStatus = (u32)0x01;
+ i = 2000;
+ while(i--);
+ }
+ else {
+ HSEStatus = (u32)0x00;
+ }
+
+ if (HSEStatus == (u32)0x01) {
+ //Enable Prefetch Buffer
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ //Flash 0 wait state ,bit0~2
+ FLASH->ACR &= ~0x07;
+ FLASH->ACR |= 0x01;
+ //HCLK = SYSCLK
+ RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+ //PCLK2 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+ //PCLK1 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
+
+ // PLL configuration: = (HSE ) * (2+1) = 24 MHz
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
+ //Enable PLL
+ RCC->CR |= RCC_CR_PLLON;
+
+ //Wait till PLL is ready
+ while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+ }
+
+ //Select PLL as system clock source
+ RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+ RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+ //Wait till PLL is used as system clock source
+ while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
+ }
+ }
+ else {
+ //If HSE fails to start-up, the application will have wrong clock
+ //configuration. User can add here some code to deal with this error
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+
+/// @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+/// and PCLK1 prescalers.
+/// @note This function should be used only after reset.
+/// @param None
+/// @retval None
+
+static void SetSysClockTo36(void)
+{
+ s32 i;
+ __IO u32 StartUpCounter = 0, HSEStatus = 0;
+
+ //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+ //Enable HSE
+ RCC->CR |= ((u32)RCC_CR_HSEON);
+
+ //Wait till HSE is ready and if Time out is reached exit
+ do {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+ HSEStatus = (u32)0x01;
+ i = 2000;
+ while(i--);
+ }
+ else {
+ HSEStatus = (u32)0x00;
+ }
+
+ if (HSEStatus == (u32)0x01) {
+ //Enable Prefetch Buffer
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ //Flash 0 wait state ,bit0~2
+ FLASH->ACR &= ~0x07;
+ FLASH->ACR |= 0x01;
+ //HCLK = SYSCLK
+ RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+ //PCLK2 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+ //PCLK1 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
+ //Enable PLL
+ RCC->CR |= RCC_CR_PLLON;
+
+ //Wait till PLL is ready
+ while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+ }
+
+ //Select PLL as system clock source
+ RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+ RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+ //Wait till PLL is used as system clock source
+ while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
+ }
+ }
+ else {
+ //If HSE fails to start-up, the application will have wrong clock
+ //configuration. User can add here some code to deal with this error
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+
+/// @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+/// and PCLK1 prescalers.
+/// @note This function should be used only after reset.
+/// @param None
+/// @retval None
+
+static void SetSysClockTo48(void)
+{
+ __IO u32 StartUpCounter = 0, HSEStatus = 0;
+ s32 i;
+ //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+ //Enable HSE
+ RCC->CR |= ((u32)RCC_CR_HSEON);
+
+ //Wait till HSE is ready and if Time out is reached exit
+ do {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+ HSEStatus = (u32)0x01;
+ i = 2000;
+ while(i--);
+ }
+ else {
+ HSEStatus = (u32)0x00;
+ }
+
+ if (HSEStatus == (u32)0x01) {
+ //Enable Prefetch Buffer
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ //Flash 0 wait state ,bit0~2
+ FLASH->ACR &= ~0x07;
+ FLASH->ACR |= 0x02;
+ //HCLK = SYSCLK
+ RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+ //PCLK2 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+ //PCLK1 = HCLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
+
+ // PLL configuration: = (HSE ) * (5+1) = 48MHz
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
+ //Enable PLL
+ RCC->CR |= RCC_CR_PLLON;
+
+ //Wait till PLL is ready
+ while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+ }
+
+ //Select PLL as system clock source
+ RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+ RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+ //Wait till PLL is used as system clock source
+ while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
+ }
+ }
+ else {
+ //If HSE fails to start-up, the application will have wrong clock
+ //configuration. User can add here some code to deal with this error
+ }
+}
+#elif defined SYSCLK_FREQ_XXMHz
+
+/// @brief Sets System clock frequency to XXMHz and configure HCLK, PCLK2
+/// and PCLK1 prescalers.
+/// @note This function should be used only after reset.
+/// @param None
+/// @retval None
+
+static void SetSysClockToXX(void)
+{
+ __IO u32 temp, tn, tm;//j,
+ __IO u32 StartUpCounter = 0, HSEStatus = 0;
+
+ u8 plln, pllm;
+
+ RCC->CR |= RCC_CR_HSION;
+ while(!(RCC->CR & RCC_CR_HSIRDY));
+ //PLL SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+ //Enable HSE
+ RCC->CR |= ((u32)RCC_CR_HSEON);
+
+ DELAY_xUs(5);
+
+ if(SystemCoreClock > 96000000) {
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ PWR->CR &= ~(3 << 14);
+ PWR->CR |= 3 << 14;
+ }
+ //Wait till HSE is ready and if Time out is reached exit
+ while(1) {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ if(HSEStatus != 0)
+ break;
+ StartUpCounter++;
+ if(StartUpCounter >= (10 * HSE_STARTUP_TIMEOUT))
+ return;
+ }
+
+ if ((RCC->CR & RCC_CR_HSERDY) == RESET) {
+ //If HSE fails to start-up, the application will have wrong clock
+ //configuration. User can add here some code to deal with this error
+ HSEStatus = (u32)0x00;
+ return;
+ }
+
+ HSEStatus = (u32)0x01;
+ DELAY_xUs(5);
+
+ SystemCoreClock = SYSCLK_FREQ_XXMHz;
+ //Enable Prefetch Buffer
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ //Flash 0 wait state ,bit0~2
+ FLASH->ACR &= ~FLASH_ACR_LATENCY;
+ temp = (SystemCoreClock - 1) / 24000000;
+ FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
+ RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
+
+ //HCLK = AHB = FCLK = SYSCLK divided by 4
+ RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
+
+ //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+ if(SystemCoreClock > 72000000) {
+ //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
+ }
+ else if(SystemCoreClock > 36000000) {
+ //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
+ }
+
+ AutoCalPllFactor(HSE_VALUE, SystemCoreClock, &plln, &pllm);
+
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ tm = (((u32)pllm) & 0x07);
+ tn = (((u32)plln) & 0x7F);
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
+ //Enable PLL
+ RCC->CR |= RCC_CR_PLLON;
+ //Wait till PLL is ready
+ while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+ __ASM ("nop") ;//__NOP();
+ }
+ //Select PLL as system clock source
+ RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+ RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+ //Wait till PLL is used as system clock source
+ while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
+ __ASM ("nop") ;//__NOP();
+ }
+
+ DELAY_xUs(1);
+ // set HCLK = AHB = FCLK = SYSCLK divided by 2
+ RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
+ DELAY_xUs(1);
+
+ // set HCLK = AHB = FCLK = SYSCLK divided by 1
+ RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
+
+ DELAY_xUs(1);
+
+}
+#elif defined SYSCLK_HSI_24MHz
+void SetSysClockTo24_HSI(void)
+{
+ u8 temp = 0;
+
+ RCC->CR |= RCC_CR_HSION;
+
+ while(!(RCC->CR & RCC_CR_HSIRDY));
+ FLASH->ACR = FLASH_ACR_PRFTBE;
+
+ RCC->CFGR = RCC_CFGR_PPRE1_2;
+ // PLL configuration: = (HSI = 8M ) * (2+1)/(0+1) = 24 MHz
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
+
+
+ RCC->CR |= RCC_CR_PLLON;
+
+ while(!(RCC->CR & RCC_CR_PLLRDY));
+
+ RCC->CFGR &= ~RCC_CFGR_SW;
+
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+ while(temp != 0x02) {
+ temp = RCC->CFGR >> 2;
+ temp &= 0x03;
+ }
+}
+
+#elif defined SYSCLK_HSI_36MHz
+void SetSysClockTo36_HSI(void)
+{
+ u8 temp = 0;
+
+ RCC->CR |= RCC_CR_HSION;
+
+ while(!(RCC->CR & RCC_CR_HSIRDY));
+ FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
+ RCC->CFGR = RCC_CFGR_PPRE1_2;
+ // PLL configuration: = (HSI = 8M ) * (8+1)/(1+1) = 36 MHz
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
+
+ RCC->CR |= RCC_CR_PLLON;
+
+ while(!(RCC->CR & RCC_CR_PLLRDY));
+
+ RCC->CFGR &= ~ RCC_CFGR_SW;
+
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+ while(temp != 0x02) {
+ temp = RCC->CFGR >> 2;
+ temp &= 0x03;
+ }
+}
+
+#elif defined SYSCLK_HSI_48MHz
+void SetSysClockTo48_HSI(void)
+{
+ u8 temp = 0;
+
+ RCC->CR |= RCC_CR_HSION;
+
+ while(!(RCC->CR & RCC_CR_HSIRDY));
+ FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
+ RCC->CFGR = RCC_CFGR_PPRE1_2;
+
+
+
+
+
+ // PLL configuration: = (HSI = 8M ) * (5+1)/(0+1) = 36 MHz
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
+
+ RCC->CR |= RCC_CR_PLLON;
+
+ while(!(RCC->CR & RCC_CR_PLLRDY));
+
+ RCC->CFGR &= ~RCC_CFGR_SW;
+
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+ while(temp != 0x02) {
+ temp = RCC->CFGR >> 2;
+ temp &= 0x03;
+ }
+}
+#elif defined SYSCLK_HSI_XXMHz
+
+
+static void SetSysClockToXX_HSI(void)
+{
+ __IO u32 temp, tn, tm;
+ u8 plln, pllm;
+
+ RCC->CR |= RCC_CR_HSION;
+ while(!(RCC->CR & RCC_CR_HSIRDY));
+
+ if(SystemCoreClock > 96000000) {
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ PWR->CR &= ~(3 << 14);
+ PWR->CR |= 3 << 14;
+ }
+
+
+
+ SystemCoreClock = SYSCLK_HSI_XXMHz;
+ //Enable Prefetch Buffer
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ //Flash 0 wait state ,bit0~2
+ FLASH->ACR &= ~FLASH_ACR_LATENCY;
+
+ temp = (SystemCoreClock - 1) / 24000000;
+
+ FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
+
+
+ RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
+ //HCLK = AHB = FCLK = SYSCLK divided by 4
+ RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
+
+ //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+ if(SystemCoreClock > 72000000) {
+ //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
+ }
+ else if(SystemCoreClock > 36000000) {
+ //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
+ RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
+ }
+
+
+
+ AutoCalPllFactor(HSI_VALUE_PLL_ON, SystemCoreClock, &plln, &pllm);
+
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+ RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC);
+
+ tm = (((u32)pllm) & 0x07);
+ tn = (((u32)plln) & 0x7F);
+
+ RCC->APB1ENR |= RCC_APB1ENR_PWR;
+ RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+ RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
+ //Enable PLL
+ RCC->CR |= RCC_CR_PLLON;
+ //Wait till PLL is ready
+ while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+ __ASM ("nop") ;//__NOP();
+ }
+ //Select PLL as system clock source
+ RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+ RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+ //Wait till PLL is used as system clock source
+ while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
+ __ASM ("nop") ;//__NOP();
+ }
+
+ DELAY_xUs(1);
+ // set HCLK = AHB = FCLK = SYSCLK divided by 2
+ RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
+ DELAY_xUs(1);
+
+ // set HCLK = AHB = FCLK = SYSCLK divided by 1
+ RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
+
+ DELAY_xUs(1);
+
+}
+
+#endif
+
+
+
+/// @}
+
+
+
+/// @}
+
+
+
+/// @}
+
+
+
diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c
new file mode 100644
index 00000000..914bbb38
--- /dev/null
+++ b/src/portable/mm32/dcd_mm32f327x_otg.c
@@ -0,0 +1,462 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file dcd_mm32f327x_otg.c
+/// @author SE TEAM
+/// @brief tinyusb driver.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// © COPYRIGHT MINDMOTION
+////////////////////////////////////////////////////////////////////////////////
+
+#include "tusb_option.h"
+#include "reg_usb_otg_fs.h"
+#include "mm32_device.h"
+#include "hal_conf.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+ TOK_PID_OUT = 0x1u,
+ TOK_PID_IN = 0x9u,
+ TOK_PID_SETUP = 0xDu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+ union {
+ uint32_t head;
+ struct {
+ union {
+ struct {
+ uint16_t : 2;
+ uint16_t tok_pid : 4;
+ uint16_t data : 1;
+ uint16_t own : 1;
+ uint16_t : 8;
+ };
+ struct {
+ uint16_t : 2;
+ uint16_t bdt_stall: 1;
+ uint16_t dts : 1;
+ uint16_t ninc : 1;
+ uint16_t keep : 1;
+ uint16_t : 10;
+ };
+ };
+ uint16_t bc : 10;
+ uint16_t : 6;
+ };
+ };
+ uint8_t *addr;
+}buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+ union {
+ uint32_t state;
+ struct {
+ uint32_t max_packet_size :11;
+ uint32_t : 5;
+ uint32_t odd : 1;
+ uint32_t :15;
+ };
+ };
+ uint16_t length;
+ uint16_t remaining;
+}endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct
+{
+ union {
+ /* [#EP][OUT,IN][EVEN,ODD] */
+ buffer_descriptor_t bdt[16][2][2];
+ uint16_t bda[512];
+ };
+ TU_ATTR_ALIGNED(4) union {
+ endpoint_state_t endpoint[16][2];
+ endpoint_state_t endpoint_unified[16 * 2];
+ };
+ uint8_t setup_packet[8];
+ uint8_t addr;
+}dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+
+static void prepare_next_setup_packet(uint8_t rhport)
+{
+ const unsigned out_odd = _dcd.endpoint[0][0].odd;
+ const unsigned in_odd = _dcd.endpoint[0][1].odd;
+ if (_dcd.bdt[0][0][out_odd].own) {
+ TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
+ return;
+ }
+ _dcd.bdt[0][0][out_odd].data = 0;
+ _dcd.bdt[0][0][out_odd ^ 1].data = 1;
+ _dcd.bdt[0][1][in_odd].data = 1;
+ _dcd.bdt[0][1][in_odd ^ 1].data = 0;
+ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+ _dcd.setup_packet, sizeof(_dcd.setup_packet));
+}
+
+static void process_stall(uint8_t rhport)
+{
+ if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) {
+ /* clear stall condition of the control pipe */
+ prepare_next_setup_packet(rhport);
+ USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK;
+ }
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+ const unsigned s = USB_OTG_FS->STAT;
+ USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+ buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
+ endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3];
+ unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
+
+ /* fetch pid before discarded by the next steps */
+ const unsigned pid = bd->tok_pid;
+ /* reset values for a next transfer */
+ bd->bdt_stall = 0;
+ bd->dts = 1;
+ bd->ninc = 0;
+ bd->keep = 0;
+ /* update the odd variable to prepare for the next transfer */
+ ep->odd = odd ^ 1;
+ if (pid == TOK_PID_SETUP) {
+ dcd_event_setup_received(rhport, bd->addr, true);
+ USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+ return;
+ }
+ if (s >> 4) {
+ TU_LOG1("TKDNE %x\r\n", s);
+ }
+
+ const unsigned bc = bd->bc;
+ const unsigned remaining = ep->remaining - bc;
+ if (remaining && bc == ep->max_packet_size) {
+ /* continue the transferring consecutive data */
+ ep->remaining = remaining;
+ const int next_remaining = remaining - ep->max_packet_size;
+ if (next_remaining > 0) {
+ /* prepare to the after next transfer */
+ bd->addr += ep->max_packet_size * 2;
+ bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+ __DSB();
+ bd->own = 1; /* the own bit must set after addr */
+ }
+ return;
+ }
+ const unsigned length = ep->length;
+ dcd_event_xfer_complete(rhport,
+ ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
+ length - remaining, XFER_RESULT_SUCCESS, true);
+ if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
+ /* After completion a ZLP of control transfer,
+ * it prepares for the next steup transfer. */
+ if (_dcd.addr) {
+ /* When the transfer was the SetAddress,
+ * the device address should be updated here. */
+ USB_OTG_FS->ADDR = _dcd.addr;
+ _dcd.addr = 0;
+ }
+ prepare_next_setup_packet(rhport);
+ }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+ USB_OTG_FS->CTL |= USB_CTL_ODDRST_MASK;
+ USB_OTG_FS->ADDR = 0;
+ USB_OTG_FS->INT_ENB = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+
+ USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+ for (unsigned i = 1; i < 16; ++i) {
+ USB_OTG_FS->EP_CTL[i] = 0;
+ }
+ buffer_descriptor_t *bd = _dcd.bdt[0][0];
+ for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+ bd->head = 0;
+ }
+ const endpoint_state_t ep0 = {
+ .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+ .odd = 0,
+ .length = 0,
+ .remaining = 0,
+ };
+ _dcd.endpoint[0][0] = ep0;
+ _dcd.endpoint[0][1] = ep0;
+ tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
+ _dcd.addr = 0;
+ prepare_next_setup_packet(rhport);
+ USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK;
+ dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+static void process_bus_inactive(uint8_t rhport)
+{
+ (void) rhport;
+ const unsigned inten = USB_OTG_FS->INT_ENB;
+ USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
+ dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+}
+
+static void process_bus_active(uint8_t rhport)
+{
+ (void) rhport;
+ const unsigned inten = USB_OTG_FS->INT_ENB;
+ USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+ dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+ (void) rhport;
+
+ tu_memclr(&_dcd, sizeof(_dcd));
+ USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
+ USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
+ USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
+
+ dcd_connect(rhport);
+ NVIC_ClearPendingIRQ(USB_FS_IRQn);
+}
+#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
+void dcd_int_enable(uint8_t rhport)
+{
+ uint8_t irqNumber;
+ irqNumber = USB_FS_IRQn;
+ (void) rhport;
+ USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
+ USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+ NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
+ NVIC_EnableIRQ(USB_FS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+ (void) rhport;
+ NVIC_DisableIRQ(USB_FS_IRQn);
+ USB_OTG_FS->INT_ENB = 0;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+ (void) rhport;
+ _dcd.addr = dev_addr & 0x7F;
+ /* Response with status first before changing device address */
+ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+extern u32 SystemCoreClock ;
+void dcd_remote_wakeup(uint8_t rhport)
+{
+ (void) rhport;
+ unsigned cnt = SystemCoreClock / 100;
+ USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK;
+ while (cnt--) __NOP();
+ USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+ (void) rhport;
+ USB_OTG_FS->CTL |= USB_CTL_USBENSOFEN_MASK;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+ (void) rhport;
+ USB_OTG_FS->CTL = 0;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+ (void) rhport;
+
+ const unsigned ep_addr = ep_desc->bEndpointAddress;
+ const unsigned epn = ep_addr & 0xFu;
+ const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+ const unsigned xfer = ep_desc->bmAttributes.xfer;
+ endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
+ const unsigned odd = ep->odd;
+ buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+
+ /* No support for control transfer */
+ TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
+
+ ep->max_packet_size = ep_desc->wMaxPacketSize.size;
+ unsigned val = USB_ENDPT_EPCTLDIS_MASK;
+ val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
+ val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+ USB_OTG_FS->EP_CTL[epn] |= val;
+
+ if (xfer != TUSB_XFER_ISOCHRONOUS) {
+ bd[odd].dts = 1;
+ bd[odd].data = 0;
+ bd[odd ^ 1].dts = 1;
+ bd[odd ^ 1].data = 1;
+ }
+
+ return true;
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ const unsigned epn = ep_addr & 0xFu;
+ const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+ endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
+ buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+ const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+ USB_OTG_FS->EP_CTL[epn] &= ~msk;
+ ep->max_packet_size = 0;
+ ep->length = 0;
+ ep->remaining = 0;
+ bd->head = 0;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+ (void) rhport;
+ NVIC_DisableIRQ(USB_FS_IRQn);
+ const unsigned epn = ep_addr & 0xFu;
+ const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+ endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
+ buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+
+ if (bd->own) {
+ TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
+ return false; /* The last transfer has not completed */
+ }
+ ep->length = total_bytes;
+ ep->remaining = total_bytes;
+
+ const unsigned mps = ep->max_packet_size;
+ if (total_bytes > mps) {
+ buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+ /* When total_bytes is greater than the max packet size,
+ * it prepares to the next transfer to avoid NAK in advance. */
+ next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+ next->addr = buffer + mps;
+ next->own = 1;
+ }
+ bd->bc = total_bytes >= mps ? mps: total_bytes;
+ bd->addr = buffer;
+ __DSB();
+ bd->own = 1; /* the own bit must set after addr */
+ NVIC_EnableIRQ(USB_FS_IRQn);
+ return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+ const unsigned epn = ep_addr & 0xFu;
+ if (0 == epn) {
+ USB_OTG_FS->EP_CTL[epn] |= USB_ENDPT_EPSTALL_MASK;
+ } else {
+ const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+ buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+ bd[0].bdt_stall = 1;
+ bd[1].bdt_stall = 1;
+ }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+ const unsigned epn = ep_addr & 0xFu;
+ const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+ const unsigned odd = _dcd.endpoint[epn][dir].odd;
+ buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+
+ bd[odd ^ 1].own = 0;
+ bd[odd ^ 1].data = 1;
+ bd[odd ^ 1].bdt_stall = 0;
+ bd[odd].own = 0;
+ bd[odd].data = 0;
+ bd[odd].bdt_stall = 0;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+ (void) rhport;
+
+ uint32_t is = USB_OTG_FS->INT_STAT;
+ uint32_t msk = USB_OTG_FS->INT_ENB;
+ USB_OTG_FS->INT_STAT = is & ~msk;
+ is &= msk;
+ if (is & USB_ISTAT_ERROR_MASK) {
+ /* TODO: */
+ uint32_t es = USB_OTG_FS->ERR_STAT;
+ USB_OTG_FS->ERR_STAT = es;
+ USB_OTG_FS->INT_STAT = is; /* discard any pending events */
+ return;
+ }
+
+ if (is & USB_ISTAT_USBRST_MASK) {
+ USB_OTG_FS->INT_STAT = is; /* discard any pending events */
+ process_bus_reset(rhport);
+ return;
+ }
+ if (is & USB_ISTAT_SLEEP_MASK) {
+ USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK;
+ process_bus_inactive(rhport);
+ return;
+ }
+ if (is & USB_ISTAT_RESUME_MASK) {
+ USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK;
+ process_bus_active(rhport);
+ return;
+ }
+ if (is & USB_ISTAT_SOFTOK_MASK) {
+ USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK;
+ dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+ return;
+ }
+ if (is & USB_ISTAT_STALL_MASK) {
+ USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK;
+ process_stall(rhport);
+ return;
+ }
+ if (is & USB_ISTAT_TOKDNE_MASK) {
+ process_tokdne(rhport);
+ return;
+ }
+}
+
+#endif
From 373b977cc3b0bbb0144429d52d4ad6132b8319e2 Mon Sep 17 00:00:00 2001
From: zhangslice <1304224508@qq.com>
Date: Wed, 2 Jun 2021 09:54:21 +0800
Subject: [PATCH 02/14] add keil projrct Signed-off-by: zhangslice
<1304224508@qq.com>
---
tinyusb_keil.zip | Bin 0 -> 1001190 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
create mode 100644 tinyusb_keil.zip
diff --git a/tinyusb_keil.zip b/tinyusb_keil.zip
new file mode 100644
index 0000000000000000000000000000000000000000..6b178fcfc3c8d45f0b6515d2311d571bce2ccb69
GIT binary patch
literal 1001190
zcmb5Tb8s&(^FCVJc6(~uHa@j&yFImS+qP}nwr!iIz3=y@JC}2BX0qAr>?VIao6R$c
zf;1=?8qj|=3I745|EBy80so)T+0xF##mPwD+SJm9LE(S6LIJS@M3r3Lk|%6{fq?YD
zfPg6ft1THm1&|(qd9FIOhvS#2Kb2Op9ENriv#uv|MpReV^A=szInH2|U&=)U6M{;%Nv7v%p3a79gBEsah8
z7smhB2%P_i2oYIjDdqo{IFkR@xc_8_zKH$b|9xX9pt^8PB`at%aA|NLAUG@_Aol-n
z3mE>j)i<`cwY9g?cQ!QouVk~R(a?2T6h!lJ8~t^V@UgHiAPq))jsR(~D1a$f9W`t<
z1icC-wM$+6@w(e-ZbpZ~rInw#?a=qS<=Z$t2ZEV<^!fln*l&vVb&~G^{b%j`dBe~8
zm3N?{BSmh{W=5pakDTz6o*mO|!5%f3V5AN#AE_K;^*EeFtVRrjyw$0w6Uun1*H2m`
zc25Fb@uxV{q*Qi~HNz9ifDrS51ojMz;5yMITiEkki*%FYrx(4(sKkN}A1*!HL2SgG
zSBm%p0VhG_yL5gaTuH(+S2-xCD2*Z3Spg1t55SZ`y>5N2Tv`HB0{fx|8D~$9MhKcp
zs{%6pCPq|0UJUg@1jIaKIvqV_%}-Acd*NrNhcO#6HWZAxX-q(U02}+VYZ?b!lk+%eO7=l-`iM&G&)JCtZBUB$9y4YP
zPE0y#B*XX2NgJFwNWvgy`%U5kwvb{JZf=2ml=O=QEkn1YM~fj=`a~=K_b*y;`0;u7
zj)lut4F#Dme1q(H_Rn<4FrdyZV1y}C;a9L9!@1vvnCrG8d{I}jK$Md!nDlWaP^$J{
zv{+$rduG+wl4oMJWG)afEpf0Xp#z%SB_~qYeGeaJ*E{!oZ||B{kEh$b-OE8CWK5J@
z6Q6~?^TP$&6{-vXoYK+hV=e}O=2d($^iy(A`IzqT-}8mc}#3{a{3Dp@?qOU=j(#RDyck5q(~IP2i*waB?YRD
zIr?|Mz`qUDRE=RTqd4y)m2f+3iu
zWULRUnv9WJ&mhpF@{ng(yE|Ka{?L6Tu1_ee>KZE5s4{vYX@swMR{j26vsCyaM+gOWdL2cT=jcFDr*R
zdd2YFwlNM=HgEKP$wt_Z0ME9&>*z<9fRnN8<;P&T0&(`%=w(Yl`yQkE<(FPy{m>Xe
zyXtWrgOJ5mvA~@ZgWsT`{&Xmt{`P;>_y1m=acQq0WI%y{0%8AumS;OBXMHEJWZD9^+eBMA{SUtj{
z-&{NX-QD`#xmn_g{8L{2A;25zk@+#mXCTtg;b}V)Uh4_d=1-KNf5eKrf}%3&NRR$U
zgbersOwrCyW}YhQsstQYoJQoY$3_?k4^cxsCtEHOI}EUyBmYJjL!m-v2ty}3ga#Ht
z%}+Mj)>%gmsbiEOuL_be3HO6VBavsD^rM;PnlQmAQx<5o+pxg35ax1*Ng$aKGuE7J
zJi+L9$<*m`ond^N5R=U9v)(+Jjw6}toP=8NX|=92UcZ46tcco@W92JFbQ3Kp9a;a2
zy_Qr#d*)IHAB*|dBd(VWD2AP&P=*i7Az89)vfB)Ky^p=6J{{QqlEGvnkZ?`
z#}YF#f6C+(WFNTmLBI8Wb@@(#qQPACFv%u_;Z4Z%m=2&_#jbeA>4qvM$V4kR`+?cnmP;$SIFS%G0{m}
zS^&|=Obm`Gp9r6s@!t?7&bb(F=1B`~PRC*u;iDLT;x(4Leo`#mD{Wc9Q`ZJ&Wgzan
z0qN-@wDk;ObHDW92!dpods!wx*z&1!I~g>9$`R_@dh!h7zo{+Q@e9@O@oj?`uL$&@
zsvw2rf;5Y*>Vm*@YyyA!eCz=*<>MlbXQi9i2+vVx6rh1!wpcd|3hHA`l#jbK6kJ66De~Z22ahUUm*@}WE#YLN;EDlTYaAT
z&5KClMDAthC_3MUdQerqi~lWL^#hjU8A|%VukNcX*!V(*`MUnAei6~s^nC4XUUB2S
zrFqrt>bBMB)@IF-vjfjFv$TVs$KIExtCoLsGQ69d<)g|CC|13oOi(K+64lCxMX@#I
z1~jK!P%fyI6^ZKP#G*Weo!4t;{cWm~kx=}PLt!&BzL=#8cjV@!Gg`~a1*MgMpoHQ#
zFn8o39XEnPv`2g28{+?DdjI`=(q(hw7TN#-kuQJ((fxm?Pqv267W5X^x?ajh>`1?T
zEdLNLjkN~J{*Z%h{_SB0qqGbtB7OF-9hJg!xEijw5j;QYa&sfo^c{6YfpO!T+dddy
zv}*ZUvT8}Zu8~#KoO-$Cu}RY9e6=6#|B7B%;l66-xvqB_kelf(;(1Fhv-V5{=6WyT
zIoj2Dv#aEIzMpr1jOBWf@dDALH}jdotH%`~#6iH#NF5MwO_E8A^m8xwihO<5OYy0Z
zH;WIlU2EpcJy~pL(=9|?b5pI^EVtqhsJ+#}C1^D^Xs^BT9@T0+!hV{>#$As+5H5Xz
zing`u`I^O0g;ABc!+-i5HO8$$`Kwh$)K%@_0YQhCmCIx@Z?oi-!4E=}J}=oenVC9L
zk3|Y<9_nNbSLG|hjTt7OA~zGjFIS9roLuv_f3Ua~dHpLo(Y2^P1_3czJ0mUHZ+a_IQ
z_}bQ6f2}%@&y%vVWj9p1>$MR*v*F(reIu|MI(ifVaf*=}S_h8^As-EN0GnH65o5o<&HPAwxPv;2L
z0bdhcj^;zIb>{*VP~ELj1~1q!=bsji*Rw06?QNKfyDzRan8OWN2nw?emg%#o|Eu8&
z?miuE3J967+2+7I7E(0@(%Jw*51>5Ah_pHm|Syz4ufw*gL>G`x%&Gpm!v2Z2SNSiJ6Da6H(#O}=Qxn^
z0-=?)jk+((EracjH@8uHCsRzwLCoUO&U@Xwh{r!O;_4#R)S=+=K1qnru)#+voO`WaaF~SD${%7UoqwC`Z#^q0$b}o=
zOxq~n6G?JE0AijvCWOVVhfN$<8GZ&ts6H!KaWdAe3GU%^d}Pi8TTQ7h5O!q93VI(`
zf*_?Y#^cpU9x$YIh>f^bD++hylyCoyvMkG!jC-e)o1PrdhQXC0V<}OTudL548}t;Y
zFfj{hDTcAOiTZe(dtBDLIwMLNg=tT0%ge^khR{5)=WU_k+G}|mTSYq
zUS0+uAh~gz?nCINRFoi^C}#BVVQVxMB=Dv?&tC*TM4l=B@L`Ks{JRsC%nRIObusWg
zbfUYA-(`Q4H~k!Cn}s&GM;$Wn&QP`bS0U-z@dgAc0Ihh>7Bh#G=k#M-Bk@MWoOOhX
zOq0((ki8dGSzQztL*zqgtl7`s87)%Cl?XVN8-z=4cl35t1#ueyMj>#+viQpbk}XOW
zLgL%M$7|h6uYb5)=eByC`>bW|wf_X^cej6MAdHXV4nMH0RjhGy_*@BEo*_Kc?j;)S
z?mbv_8FwY!=m#ec{iNh6Vj~an>+pn+Ly(7?;_iA`6ji$INZmv5T(CQGqIh=RJvEIS
z<;-q{sXV&X6^ar`-^oY;=fR1r^PzvYM<}8
z>eK!LxqpGMb|r9SGa00?tgVO&l)%4A!e?Qm1rv(aU#@HDB-u2rUWer0zh0$|?{x|n
ztzMTegW#8ymAgUr$b5!v6r*qr_Y4h){`&XND|=WbSVbw~bB6U_Ych89aXebCb|k%?
zc#UG(i_{jH`BF_WL3Ga+=+2+wPew!d3wR!DG6g|G&ep7wHj?x&z{tn+-gz5iaz;@C
zaFZ;f$e&K*LK>^r5^tAXURysGU+48J9bKL7?(0{Ct(?<=i-dHZuxPrn1ijMfO>fte
zOoLmSbE(z?BP?kxbaqf+p?jcX#!xwg>MKwahUsKxTgaO_PYI+6%iOZ2q-0$GNktrX
zoK{q<=wNa~1KxHC*-MtGBux*)OwcG`IxWf&;WI)II)8A4EWkVR55n%Ct
z-go>8F8z8}{DgS>DUbTYjf>DslV9$P^SfPShB%}2{o48~1P811{H8vsVe9&6tUJFy
z^uNxx%NRgx(_Zt}?Z>v*8JLc9w$ynoT{+aLT_v2gLTYKAZx>RW3`4;@W_)hrDc=bmbf8^fuRo`aTEE3%8*MhYE?>1y2si)zW@Z3#*cO^5#C
zspiyc>O?e~9MzdBeo{IXm@Csd0dZxw%nzbgCq=wKA4lkD>^MGqHLq_Mf<*NzZVpbg
zX%$WP)>tnWpASOHyf_yokv(HLw{cBs(Tkj5c3UJ$_kuIXyfkVvZ&l(aQ-e`BMYb}N
z!ev;#!oU}>;X}?NT8L=w3d)L_4KX=aO$*l458`&$sa28bDQBtAcU#bqcPOb~^`Eqc
zQo}Y4^5ELnnTJJ9WDDzmy(gzBEot1%;yKg_rid5~SL=jNE{1Ac8GkdBv-sU1PX&I<
zw`=6iE}d1Ssbta!5l-MsRutd#gb;*3~Z
z)8zk!ObmfXidIpEYPO+?=yf&UeLtO{^p+w9T7ls1Gl)`?*hnTp%BB?%{tV21#
z+)>H?w;wYPw+{Mx@#U-=1(T=iAdxgjB+v7Oi)p+t2_W{&P}Q5@vxSx&e|SQkF#5kp
z?Iu909CKdfC3>1%A$^^A*UhiIthnLtD{YV-|{IzJu=y
zS_}d00%%;(NI=uO7jL2x`9jVQlpvz^bI;!^r+lY-r*1#m%|mgkE6cV&hwbq5s#(B0
zk`vE=iT^VEoYpaR`!PP#+%k8F2Z}9G7q8q*&VwP&o=h2;#mCzintMT$*9}H
z%m*fy=OecFTAHTp#-_|Jw-df4auoJMo~%Tl19OO0
zEA{1-$qZaKK?B+X8{!&(|BeZ_3qv$r`ty3CgpY)&D|JstIr;vYgOA|r!~uv~n$RjdQ7X9O
zwN%PeRmw3c^iOW_Ip#LY1V$;v*Q!t|Yf)
z-%CWS8OdH3BoatpxvHm<0TYqQ;bgfwpue058c}Z}iJAQVm;W?a26bs)9@uh-u%-s|
zc?$Gj-T_9OWQIL6@=8X~Z*|xk`C|X3(vL6n0E>*j{;7%Ks>I@%#mf!C)sFs1gMN3t
z#?y|Tle_jpv3+QMf2uaazzdQ07V~GL!Zm*Shi9M-5)SqZ$ZuYQbB2%tmq^ClJy(%K
z)i3Vv&zrZd4`i15*sYvu)M!Q?E#Oni*zL>D959a0A>$p+vihHJbYF~3PZ&0Rk=xA=
zst~;Vnn%mFx?((!lH}j`@uiTD(FDtUd__Agdxo`LVE*8dx*3CT+PQY(;p=WY3+XW%
z!`t%wft{>aqCng@21$YORM47?5
zq8h0E*~Uk)1MpYt9DfzJ7Qchku27y5G1b8QK}g?DCGzBfgh8_qqA>BQ>eWu_pvIYf
z&$VoLqKFT}9GCz;eqf{o4J!%e=n_%^h>8ncA6C-fVhL^x*xeYYOIwq&-2m(o6MD7R
zKP313imb}ucqW^vvS0y8wc=Engr9A<5uoZlyQ857#>QnT)KXdx#L2LalHXH(+bE{Y
zF|tw8N8vUNuzGhgau?_M*l#7t*s$_`$@&yW(-6~YRGoNvKt}!`)Aq+8{JBBUMyyys
z4U!9|C+h0vjLpxn^bGoXAR&=z2|(rimUQWddHvLIcXIsyz#o4C?Uc9FFDxTsoZ%{HPj!izEE*`<%*Ww@NI0pT3
zAM^s$vzS1fp>Ic6n2?p?vHbf3vgjKU8rG_tOklK5Dqrd1Nzc%@Oyu3joyqTFJM!sHj7}$|-
zKT2R7kh(p5UDy3~dJ+cy-0wrDR&7wiI>jlQg(9|K#7gpvE-XSn(T#kC*=z?*sg3Mc4>X(#6A+8d4L-
zEWP^$S)qvi`nGo|C9F|+yfy#!Z8M-CL^ULAY%kR|Q>lo#myPEf@Tk7eGWfgoEKuJD
z{J4$ePPy=e;`Nh#3cD`zi=0Axs*=EFhKaW~Uk|`S;keizzW=9+_B^B5{icIZ;wU
zSW{zqkh!K#zjW(AB)HW#WA$;|*|5FN^nj|*-tB4~ng|T7Aq-ifbjj9ri|!$74sjib
z@_9V3&C&_R9)zr(OJ$DYnV25vTA51W0B=SV|M+|Nj5>uv7%$yNXhfyT`l-j*w?V&1
z#r2A;ecgPTq6v|ub9&V(M!04LCt+21a;P;`EAnMj8%J&xr(}e#)_VD{M;LxL=?2`j
zqQ|SSdGbS?sU$FVyI<
zFg16e7YJ29;20!%9g(qOBtCo}cFEy9FpvItDB|6z?-?^betipAj=hf-e$|vGu6A@3m5{vdcaaxJ`NKkx2X2r~uA2VegT%2*s_(I5*}N
zu2qlB46wAtD9bbZ(Wt%(AsAzb8Q?1;b1r}1TH6$_e?bKCsPQWS(s<_|{-R@mKmBxn
z)AmmPFr=2$L17%FF*L@H!?F0~H%f5cfaku=o;i?eV66
zA1Wcfp&fn24X;u6&m23kB-wlYvwB39%-AhNg#8!K-cW}b4AFbyY7_xN5s@)zW%&~W
z;72mGffMZt)E~&4j&BueXqERFjNIk|3x+uOs3pj99`sQaMVI|wC##XCGv5@!B?=6!
z;bsXPPDxR_H@NCcA$2fEz#=b=g8H@ypHcNzoXG(PAvgwOkPOlpTGJTEHj}Jc03c)$
zxaLY^1nZvK`9u?RBOE`-Zo}{FYsN%>&v4&dF8BkH
zAx2_w<315+FLEPkXxqQy#L1$p1^`%lphxFnAj~Q9BT7--VZb5>ndYoyO*0|wOq4kO
zIxUQ&jZwF{-N^HWJ%TP#Yz6R$6mAHt?rV7e2BgCv-&x3YT-{K;<`d5xOTEuvcg}s6$Y^jDmn*G0?S9IZxHnHE(QJm_G1?$;Z~|!2v~u4#p#}Cm(SuGT40}
zeLgpIHtbMPuqpeK%T4{9soUm#&63VAr>W#c2D8uGfkX-O7bzJ8t^Yx(TK)~WT0h}Q
zUB7e<5P)3uzf^-%9bnxF^!b#!KnHzA68vp|)Gxff(3x<7SK5>OTWon{@}803RtL8R
zAws~qU-;0Z$Wi^{JZCj8D*{a&Ji0({V_yf*)gH8O9#yt
z(`@JU!Z_P`GDA=Ey|JTB+{>Teu^<0uCcfYyeh0=|J}dlW+m?K$0)&2ZIr^W81#nKd
z1NqF7VSy6n@4R;R)D_5cKy5&6He0dC_(?WBY|89}R>L9}6&!|XtMI0locuF~w&GMp
z_z!br42vkc8Nm|2iQmv*%
z67jj|Yk59{t(KS1PI$7mWXG!ANlYPnB9`Xa^USnVKw8v@@MQe6utcPF6VUQp
z{=ai}MJ&r}s+v9cLvT@@+W@68ia>vvBuv$Ew~n4C16*H&%xj^g#o5jIM@+`an-Z
zg!%}0(FZ!P%88vvK+9ozSz$lwIABh6mXxGrR
zK-??BBa5@`vLD-Jq!$?VFQbp!O0yBoD-7>85;qxxk6Ebu`OCo*wkx^
z=sUKitlF$mLuWF-qpx9IkN#0vU5UvaBSUdd{?zj?FmnN?s>%#~$09~TF?Q7*?#3df
z@Up@>t}3_lmGVCdVg*5JAz^uIzV9Hzl9rtHfap&mcmcyc^8qD>`1SQchv>eYY5g?v29xVV5-|CPe
zQl!K%>xkjL2YO9g2d8o3@L|$Nwqf0^GCuJ+m5kHg)`@cDx^L6p51G``BEa4y4b&Ky
zjV)bpTOyleM2Sk%ts4K68o&ges%RnRl3vT(P73w#+AXLqLqzr^CX*p`oCp=(J8gfo
zqtUI#QgBR6G|pgse%UlP%7~2AezqzxLd-jSqscV@PCb^>P^h7~KG!np$<1B%WajEv
z(@-C03{j%;{>Q5WpxK&LRzCYXYbfeB&?a#|(fey{?y}Q6poVAqk?uLmex_w?`^wwK
zoz`}BKZu>C*8;2mkcotFP}E}3SxBV#-5d;o3-8{DBKeUGAxk3D+
zFz0=$;%JYfYe^R>V*&C>f(2GI}1!2ux49oQ_ZbZzR;DHFv6kB
zP28)zd?Z5UfsG(_UG1&?l$x;4`Wfhde_LcNV?Um;=h^^$rdaaKm^fbGggDU`SHMGDv7bn
zX@4*@gzxhZ{<#Q=x;u7X`v5KwoGxyKwZ&G_pWkY>cYQzR&n@DlJ)H_x%#$`C`DyeQSq|f8NZ8ky`~Wrmg1W&g
z5+Q-wPn;@u0waa)0cOa>!G!5-!7Q=uzQI2;=jkcYLZ2X%JvL*3zM%icu=dw(%BD2(
zAz@O`g|D)Vau~y3(PUHx6_RfX>FcgKUj>%g-aWWhz73d`$f^Z(zvOHBe^Ib4z;i)(
z8}U;*Uy)(~e@gmXR9275ms?~cN@`CWR30JDoVcmMg`Yg)HTqwJD=-C*ag9SSw?1g+
zm!gi&0)&~0nptu5Hn2iodu;H{mu5
zF-goK`eQCO<$|0S_YpQh-}KKz5FDfXZt-s3OGV4th{1#}t&7($9?p@^
z1bTI(g+@n{R>mXRJ7~+Yf3|YQ2+Zfub}z~6>>|?#Te8~j>)%~fzV9SP%C3_!MJ8|z
z8WFOO!6Ws%v{qS1^zuW>L)f??s7^eguttvh#>?n97>$Z;nbL7Ml#!yX
z0bdsHUy0;;mJ1LiZTUVTg0MJ#G4a}KksI?X3+)h$r^AQV(0RhQY6!>G#;4Gf9*keF
z7z&7Rl=JgTqNO=U=8n2+PdgU?
zMLZ#}iv1*LcufR#EXhqf3TxIo1iytV^{lNFYab$~n!oB^
z)t`c1&SnHN?LB5i0B#i{10KpZ(AKG=nl^c(+&S&dr-h&kv&L9FR~Qyj-=x=!_y>jS
z0dET+kXWD-X-4-cOoj8fpP%gkYrNQk;NUNFKl5f^djC*sFY|3beoqPJlS^|mB~ifL
z{BM5F_WdKkup`tylv0_TBp&j;9Eb$H6<+2WK3iqQEgi(=9@SM~&2Ixy@n}M4C}0hG
zg~T2ZR7!p?O!4w-dS~Ue)f#ZGe=z1E-Lw#y20Xw|yTOfS(Ks^$0XKv+o|+BgU?Z=z
zdAt`_EUAnlbw#O^cvMcfD2fudyfbtb%fS6OPo~oVL3M(n%hh`6l$SXvdisXo^myBy
z{QYc_C0a{(*Dr)(0Gzl=NwtMVT4rP_HVQ^+ENo(-MdWA*3#XM0JcNPWOe7Kt&uZ}p
z0-nOAy_6kvNHiWZ2+-u%ET~9o=wHmOqC$o0j|Pm<(hU}kuM-Refz8t&UI@qPFdl9M
z$BvLs#jo`8sOgT)e+mWqF2;$xilkcXh;e2E{=P%qO@UJ&@FeS~>+9wdN%_5s%Uln$
z_NJ1zoed`aVxGe2UjcvzT{mTeh$pGgI+7XKjOITPsgr^TUjh6rwsNtT!9{dGY25$|
zmk8`e#iJob;AZU}XUdK(+I)b!U`
z<@<8PrI&QFCd`YP+9XBud#YPmnOiwhi8g$4=rv0H!1bZuq~iOIyf}{K>#Lb>)%NF<
zhnb*6-Ym6hop+<70PgrXlr?;vK(X)dg|`j$z>NiP54Z`dxNj1>
z0=;hMSv%RTZFAr*%-?xY-z2sFX2Pneg@}Pzz!jZ!9-mjh5$o~3ptvy#y6f?LyM5iN
zdOI$&_3zO+B|Kz%ak(T4k=Kj-gP%}KFp+=+>>TbD
z5h&pM24QP4f6pb?)b5PmN7XAwMngW0JWivtFd@@oSK`Dk&lNsMg9{
zdhirk9ZKY+lZfh;T~R(Id=HX|JKUa!ONg4{Btx91ql81l{!Bd1vyirshzwvDr+bg(
zQz4XB*Q@Z6o>W?Puoa4TO$$|gWL*g9JwHo7JwSNkthB9Fl&(@{t#sg0ExHM$`1EyY
zM0~Y>mNiXQwHNcT$F5HylNV50Vp2w}UW;vBCZWsWT3Foh)#B!X(&DaKLa9$N)oRQx
z%U0~Lr*K|oN?bxZMl-Pf+X?=%laTF6S|(-sxssYq-c>R;noiX(lCTu4h7g@$CE?dh
zR+f;ghd?#(c`XUxOI*YbPIfkg^1;IjP511i1JAvotY_lC3I{1DR?*$K@z3LBTz0@)
zA(5Vt5}i<);XT3P{V=ZtJ+9PSuQU>F)*O2>-z8a2t@pt}1AX5*%owGNo|f5Cnit)v
zx4_ti1_y5U5T*$eGweKy+Y~nI`esp95OTqLs*siO)jm2}Fo=N>aX$18^V(X(7t`dWhGiwfjb(X;iEwlWCWPD`Nyqo@ogeX(`G&iH6s&
zF5O%i>$c~Uf=Mfv(U41KkddJyR&FX+NzwM{rN(*S@xhSsDbe8t#epFb6|K2p7~^BR
zQI-73{&*A>192!MLb<$zcomV#4(G5-Y^MZk+fr5FC=x>PqzFGxolSr@B8?+6GwWeS
zbAVkvB!Gl}Y&H4a+D+^FD9N|0eCh!%CjW=X3L3<6jhFqEb$IV-+jwv1~tax7SY6^G{L)Z5JW
zddma?-Zy$aX22UA!<%8?z3on?8!}70VbrDRjq5}^gqz53W68G|Zvs%>B2YN9t5Ywv
zu8XOqdp1o*xG@Z%9scB|fV`ocx~}%`H?JjMY^`!MJHRXu*TGn4kc@(ge4rB+A}MroYSB+21}^ooRCy@
zLW`_tiZub7(bt|)p*5@xWxMVieEs5P3RCZzFUwy>g&)g3*IfMWIla3Gy-d`o_R&91
zZ(cJ=v@4DzE>w%Mz*oDGtG4fX`|Z{1Mqgdc$nx(tueDHZDcVw~27
zMI1s{jAXH^cj(!gMAfZ>c=N{Q$}m&P?d~pc*rnN>oOh^P90wS4z)Hwho{uk}PW<5U
zA+Ihjpw@rh--^Oz^ApkMKrMehwA$(TQZCTiJMXZq`5Y}7PkG4G#m*39?Sy*TJX+w!
z$wqQ{T7$6W(Pu`2I#&cej$cl*cP+dtg4tGfpAMlOT_AfH@xB~HJT$|~N0;Sz8S&ms
zq8?R9{AXgz$CT^&FzkN0@gKt;G8-}{LJ{IHW|S?mCux=sQy2W}i2LRw=21lz!>Dpy
zFP6N1?thdV2D|Ab!7S=JA)f|*3Jol=iK;mW@nl97=6Zoy327BNCc)lu#g~vvNB|mF
zWuLB`Wk<%UP}Af2tkavD=OSPN
zthF%^qO;ka$D3E<{|4JI#&cKd4XIcL_3Y2Ov0
z3nnXgJg#PCq6e(8@)q$%yNVhh!je{~1K?iirj^yXtn6HK+=Y|(86^ScaRlT1Rq-g(
zA!rWqA4lZ}8t)Ir*!eOIz8}WTV>eNen>7>_ZOXZ)(0-feu@4JOOU$Vh@D;2^L`_@}
zc?oGr>2(Iy^q2=91KVhzxY790dVN<1W{6M8qRZ$DGQAN*rj;c#&5R`|#nu?i=dG1;
z_Rad&=@8L>?x%@RtO(|E$e$6C(}}zv(?fxW;-P9xJF#emF5ZNdZcE2M%Dz_ku+70C
z9?wIW#!yQqL=skmT%LQzn!Nb3S9{H-2;ewvKK0#WoxlV&S9_hNN)TFYJ`Qodk%e#}
zBjUvlvj2_~@y&agXhGbw-p|k*){M>%)rY73(C`Pl{T9gI?{oTs^AvkFIH#?9&4O5E
zR-4MU%}?HNf#mgDz%x(HB1gT_nfB~MfcmUxSZ6-aV%`|DV(iMFqEiI(MFg0l%{1c;
z8dk4#bNDlS6wqB8R16lg?1c%`9NUvT?2~T2m(J@uVYxHFCDgNQ4og!}H2
zRjG18ohoBZY?>9%PD<)J{^70HO~g4Y_iI`3ba5WWIkQCE;eTP0^9-P-Swgi><>AAA
zS>`*@IEf^l;UNr~dinB|xo#p9
zDpJHCuMLpc%?O5NIs^Yf<9>DfC_AI0UIFhD62A|b!Jpl8_)iGgUSG-8Odk7%VVwgo
zr2@HXg7qw0+gcPTn@3WlWmQ7rI!W|P2Kn#7J?L+_c{k8r-0Lsn@m;}X5RCIG)AWUQ
zftm3e4%&@D^cjJN=T~k6OXy*Ja}s}7pvR$17=>^u&*JQY`NMEbiQ#smQFJx}2dCuS
zRFEqu9Xo%Cv@H^2HSrvUdN3@QR3Pm{Q-8js6DTwR!GcmOC_3@_Z1wWN8SPFkX$k#{
zbLy_gK!Lc`0FjEkp3^TEG=Yd6s}VB2aQUw%(J;%|
z*{{kzaBcGUo^ox;1R6-;M4RpG6MeF^!}3&br_m&vQE23Z%fGhF8^jc(@<)K<_`O9|
zz2mC0Q17f}cR)(Ug3`tjZ8xt+X%&@|f>?;#UE?Tp--NwwQP+Hn>6zcZb9{xrj{2dVP2rki&7d`ZU+re_lK~
z%DA8T7?d@P8SuR>44)T$*VaaBVdw;0RT*?$;0_TJ9rRpC5p@vpBhJWB=a^hJc2}Xa
zpH;$oIYJ?g8TbnIHt+uWzUj6!KXSSD9bNmTE_CemK-mVmZ0$gejWYS%mDCqtrlsR+
zE-X;d9ZXA(XC%e*(EM@J6Rw>O=5<7UoRB*&anW5~_dskpYUO!--}%ChJQRCGI?ZbS
z=r_*1y!jONGh;{-ksXtlQHo9TgX+Ysxi4qi4wWk{PKHq6_kutwNcB`C{u3chIC
z5PNzU;7J(HwS4!Ew3{$}r3o1`oA9cz*rlqFu>Hv8xXE8DNC&5_#FwIs^_m-CdKUEdi+DIQ!|;Re${G7
zUXd4W!%o15-7&Q+wjy$nlMf_7%0!$d2gakm78yEh2KQ&W#EPzb51oQFdp^Ka*Y(xM}LRb;+-n{OEg@q&GqyO
zclxXDspkrpgj7o?@bZnwVd2~?B7^r+jix9LVFkik;z9ws5f`7@V|24X&0P6-Bo@!o
z-!OK0*)15&eXrnpzdz-bwPPuc&0)rurC-4pjxogFYg7WW==F&0M##ZNkEMSmc^?*$
z?%UMg=TjQjDeh+x!gTC{!IlSdSzqn6EVY``y
z*RFK?;d~xM1QxFDg0poI2aiWXj*!vY&DE5uk&Y)7kHYfqFQ{9MZB6k`o^O}d1has;
zQ>y4G^bTyw@^Vt=lO{sMY4Yv$tTC(KowoEu#Al*|
zZpF&9C#D|)8Oct|JKHVaE%ySoxYp<*W^=F3v9Dz^wDp+IY*}mTvyzm$g5&dmKP~ke
z7vSds`Q-Wbz6CXKKlKh&=ry#1<^qB3F1b$noEabD00;)ZhaMVhhMhR>^3DX>9TqlN
zJ^+W#2(3Phs5*(eY!YV@PnH>;r=SH+D5Y6!s9YiN?<`gu`V`ahm8u}fFjarg_)Apk
zA%H+!)Dywj#mT1|GaLmQ&YCHV2b)LBg{0~8P?-*m=_s-9Ut}K`?r;o`BOm)`2*ZVv
z$n|BfY{QEzZg)E7n!1eRo}*RORH^p!##eQDYVlQ1NEnInj}yE4oc~MjL>ERl5uW1%
z)`N9@nLI3ZTpo{so;deT7@pB)_2~>o(&N%p?4D8{lV-k1(Rm0*kbG4T7bn<)wP+;~W}8EVh62r+JlHCtkA0j1>(x{+1ww7r<=jN-4T&
z^K%0ZTz4?uJOCKXt8fAiE>lx3b`3Io)vFC8912b@R(+PxHBhJwft7x4sIQG3N>!|~
zI36atuyj6-xmqu-C)hpeX_R}6^mf4q3
z|G8?cYH508Uwfgq3$~uRpkvN0=A3h8+|0*zYd_)VwK^{oSG6hc?rmmoTs`C`%YCEG
zTP2q6>Nl~itv15yEptMfMN^Gx=@jj%%_GqzM|}vpQ(9nfpy?WQ!5z9{o0PWaiF^7L
z#6A51OV|J=W8=hU-##{NAXIl<)?;O8v8SisWP$roYiy)veAO9S;HrQ7k3Ff|XS_@9
zD&8G8iEytIv1KZreP|dC=AhYX
z(DG}1(`Hwau&Ni-Uo%^95xp_;Wlwv#PtC-Y%ViKo$5({sY>w{mf*u*EHH7D&RS2)@
zBO&l%&FZW3BVpsRfCNxz8mxO~xKw4Sr@F$|0(;GAzuMMJ?L8z=O_JV$e(n}#!H%U1
znXRV7dGC(emi5~LY08yIG~S#8OOFp(sN8roWNQimGqcVA>bBi3N2iUiRNG(^VW#H7
zX2L0ja>^`LJ772*@_XjtE*j?H53N3nnaQN>rp6;9V{N%J={^C>Q^efxA~(a1nWhag
zY>T6dHr9Y4pVNF<%2^HiCGnIhqW5?9g-JeNM@LVST<$%5!Rwt!E0^wqoLA{7wDA;{
ztIB?S;L@s+V9E1?lrePy^ACkV<-k-TRx?wi`c@_J1LnM=dxAW(5tRw6vqas^vQr|s
zZJC?9t@|0?rLo&ZDv+6?xp9KmkNxf(@99v#_~P-9MK-C~{0ypeEs^}t>#P{kLaA%A
zrAYTArM3
zY`@WUCdRw#k;=?J3NW+HdJ}ke?p3+ERweY&rN@KY^l-6)N9dAcdU$}~QX;;v+AIx{
zwxx_JFoll;YPg%l$cneY)caV4qD(*tW`AMWhN?a-4HoE=?(AW(<-|s<)6juLMtD3t
z;EHsX8SIv>omtc#H2}xk%fUQ{5)d}E)*+^xdMCKUl$(p~PD0mwDR$X)^;Santb{{p
zt$~DSZ3A%unviI%f|%$ElyW}5Q;C#l?LtmuL}3QXbdfHiG%r0lX{y@h)vQ^)2`uO&H})v-!UPgSynQPw_>
zk5c00mU5_w=WfUZZU`C-5LJF9#sB+Xnk|(+7jx%jJR;qXX$b1O*TV|gqC1`sEFKPP
zjrqmP1s^A0jtpI?9EmX;!YbbQJ(kXx@+rY)zs4-UR#Q`T!8oMiWS)Q7fQQV
zf7cF9dp-b9p|>0CrcGqrJ2D4Jw}f8;APmAx!HGsCNj(m~#wdcqf2k+$2ttn8t68$m
z^aOzuI;{NY*3>%^@WBv>g+9{UPCR{LwXM>-#EQtAiMJ
z9BuZ(r!lnobM$}9GK#j(9_@d}RU>G#<$vpgn3|(#v*YnwGZQnG;i2?EpT3dpJPN`z2>UGl@kJp6g{G$&Eh^}~R
zC+Fggmt7|hA6}?GfetQz%WFx#(p-60a=KZ{yOMvpwBC!R8!84Q9hZT^dQXRgF*aES
z9zwu$?Pm}d<7JRZC;%Q>zQQ6d+T`VbVfw2bZvG%0XiFVPxhe8i_>TBq$WVf;CcZm42wGy=D?T$4?UR36Ulamb}
zsJNiu(7mewZ(QaagWPi~{5I5W~pbq6G~?|+wP`hcA&qTVBxrLWp7t+HEUh#4)#X9rN$M4g)DJLxSh4oc5oNtZhr%J
z|04dD-xF-kqpHWwG26x8l!rE8$28||rWgLI*g<1C;^=L}o^jw;D6$y3u}J+|Se~Bd
z@Lxzz;g6H{CC1E|OIg-B^)mpY07%^e?(%m=BiY)3d|u{R}*LGd8eyw`GaaZ+>6h23!`F
z8+)3yOOa`u83&yk&kn3mYlUJ@
zI{~|YHE}$~v5WXIP3+ihUjM~4ju!F5@+zSI=s|htpuXrKX7Sw;J6RqzafQm`h%I8N
zhS7stj}~$prJnoO&+^+g*fXZ*g{G^sRq&QfUrou`5QbZ4-N?YgOZ4kt7jpoehd?_VD%$_C5DF-HutAI}UB%dN8Ae+RYm*Af`V~pH!ux~vE+kbwF=oYX+>M0-
zv1|)1lNjba8Ej5GxY4HxiMmU)1ZV}dgvWJ3z!CNN12T3-{GI*R+3(6!ZG*l*?$TV+
zD&Zw)%ZpPJ_s=bn0A_@+F(*-a-fQ{kE(F1L41?#{BiQ#)qgfv?zNlj!OTmH{ZqE;w
z2xX?p9k#P-C70O?ycxU+?x~|W^c5@Yak&fBoD-hH(0{Hc84T?cg{kwBwM1_@&58AC
z)e3{lo49l1O`#6=nw!=>1ZG$F=2aSP-NE1=OU4|;-`EOCv_Rt~XHkL4P
zAEp8p3~z>_w-gg3(uru93jeba!mL3a!u$o~3}(F60snz)Q_FMFMg&877_y^liDpPE
z8ujrOepw9jQA;Fg%Wu{&lR~WmDO}o54_|N~jG22uO#L89#S!J~HcQ@P#bO>Avj7#w
z{0c`^Jc8Y_E=u(azX(I*HU?N0Rjl;quNcw1@j-vxiAV@7r(0OR*opee_
zs_SDz``Q}$ACmmKTE3t7zb+Rp-DT@t0M;ThAq5O*NeUf{-sBww*EDXLO)Z!4$_Sms
zJBHJ7O_!`7wC9FBt`738G_qP(rAs
z9ma7cHltX*F;91#qUDA-vQN+86dm(d-XlB)@|?qfYdAI%iJT^6BIq_nTnO?pWd+$x
z7hxUJ>AEL*LdDEHLxV-jglbpS2#w58SD|pM?=y=h
zP%ND9WjO>syGFjm3-9Y#W|ZYMRBVuIcBZNvHFxmL_o9wMf-TWJ`P3mk`?8HeSt#%D
z#(dHX@RTD9Kw^MntzgI{R;$w@D|(Od;m)v=CeEH`yWmAFJ~pWZxSxIt89U=KhJ(>s
z>|>+YyEFPNKtCsY@FH@N%ekQw+Li=wtpx``WRl}d;hPUmbci-dK)rkU^N4oHD`1A4
zOvb59vN~pk_GvOuegQFcp=F2BjPgJrA;2z^R*baCx{;m@+nl4n2h-!4tU@k91ygB^
zmcKXq4jFC52-7CC+Vs#=*4rNun1XFnK?R|#SUsIoOgROVs`x*Sh}eQIPh2lJOc5(`
z*3#6^)Y;GW^s@cGKs!1*I{CWz{AvBvmG$^`(nCWf8@m@<_0cvV3+DP#s@Bo?md4p#
z-J^#8ZL`EKGMsjD`HVn^y`wR2C-}eP(t-V+82_}z{RW6XUJV_(itD8H!T+t(w?2vU
zL@GRnR_mgM@u5_`7d!nCcjJ$)ObNH^sQ!boOZqkt$_v(ArMSBlEa>+9(>y>oLnq6(
z-KlSN>^>#@eqTWiNtCdY5ZsgGODukWD8rA{w;U*66w*llw;(W2a%U)}40A3Q3qNM4
zM!dZXz-7@98PS^&)`q9p@EC#59!Tk>FTz=)tOt6#_wskPy}zt1J8oxKh>u{AXS0+ID^adki_l_V9Y%LfI5Hvy{|>*I;iUlb0HFI;
z8h#PuVFm(C=QVzLU2@4b3FyW|kO
z(g&9DGKgidCaGB2QW1&E6F`X!%vJOU$5xQwy-(^&hyTk2p4#UnvVFFDeBvFYS(tjN
z4o&j)G=$m_Aigf3Z7_Y8H*vlXVxou4{}yG*Q*l4UL=x7ISZpNrKugC;8X(j;|UH&f(X3u__rHb*hxHYY*s4HjE(>wFgz_5An8p>bUN
zI_Jm1)7jJQ=Vd0V>hA4hX}$7kiXDMj|L^e!9Y5YXc9m!-dy0@CE~BDYDZhx#F4UQJ
z)$8MEBddqEL!^EVcP5}5dR}x#IUVH66Mfvg(z>qi>-EwL(K%RSXTdO-ZkDc+)+v&f
zNQw9GaDq_>gp%Uk7mLxV8ngmz_re$X&1?RUShs9q%L<;2LwPrX1A<&jIQhytzT|tU
zEDy6!INkFWjHp452bh$}n19pCLlzH7JBh@81^`ed^`*Sux((
zG@ZJwL~c7;6j-25frKnE-)YII-`7eUx;ejupLiwO+l;x5>pWF1bMA~hCGRoocnK4kTKHTKASb@_QO=js1gA7wRYWDgDjCz~Iu9Y8
zWK-8Mn);=Qc=wnBWZXU_A?j89+89ex+LPWl%zP#Fa06$!fqNK_qtz=m3kDh(ft==iuT{&Qh&qS14Q{qVZN0GZs>ygp
zb1@3d7>uGYmij-eFjx90rF@kR3{ch;C*eP91#MlYNkE0Z%Vrzv(o%Fk*YEtET^>X$`&m3tqVLnc(9)%ySoMB
zH%7n-wf^dS|z=D#7*
z6Cl%0_-BS>py6S&5t{6KpzKsk(-so3_nW@312q?K#t0i)WWn)5KqyN>qZ6XQV38mIrjx_t{eQG_wTD#4VueV
zYXSi&hLu3AH(uvA;f0@tBlI{tes}zf9c1$sI7J#s*>ErzWL@ZBg5T%okEc{RRBI%?
zis(vCdR=gH-~oYK_0u$C$%SbmmFY+I18(+e)lf9()!X9my^Ks(dW;$S#IZK!qU&y)
z^*-17%f^IzobPjJRuTUUGUVt2F4S81m6}5b#HP9^Y`%UDnDQ<QAu=m#hLF;>ummpOOyx@sPxQv+F;dIr0$6JS
zo}(hWzlU@!R4{##E!UuWuEARt
zf*ZM}!&?^WyDk73`2NHX1Q6@y9E|9dFtqRs$JBTZ+Q&uVhBqoWYYBSIFhPXym)A=X
zqnc)Eo28(CI;Vbn)cA3_v<@4me7OwexCC93z$)nc7M`jlz(G)|=Uqq|;)A%Uh|$pv)jg<=J1
z`3Pj^)Q`P&h1e**enU<$)9?sPH}uljas`Czgq@c(p4f6NYwV^LBo{=C2>FK)c?20I
z7gqTF+_7*VFnKut?q@<)wH`Qy&&Pj2cd`3b#K7C1sW?InD$F-f6(vVJ=ey?b%
zIhcYbSTG`%l3f0?8upp3mms*{Ag_kfKhBCM-VZdXnf^`}(j{^6wsz#VDg?)VDUvZg
z`gw%arsAw7#-}8-fu{oF)%q&*7-I*gkfW-|Jbi^FsI3ZYUj<8uY#mzsPt{Mws3KV&
zr=+=>S=t2px5>Jif{$O3AO*K!ts6}(ibO#fQ;g@cG-O@lYs51uw^-(|vQDqD`@&oR
zu;7uG2-ZmdYIt*rUc;o1zV8r&2^mBcz@Ty))(}rSiG@-|AAbT%LVN3VX~*NZw`SQT
z9gMMBkno@LRzyBoRSxXK6MSt7TZEfmF-i>gM25xAi~0_(Z9!KhW^{H?O@gE(wq2sA
zqN>*m2~_ixp#m^C&O8>$XNgNd80w*+Y^<5dFGQE9r6#57B
zj3b-9>aIP1jB6YUceQDAtQzjynn|<55=-ioQm}Ycvzk%f22>K%M2$keHt`tgX#J#<
zDz_|C(#0mnTxf-uiJaeBAl|k@f@p6QM-8a_^hQ0rRT>~tw@;j4%FPCwB#bhgaoV7V
z03}T3)JrQZf#s@=)_n>pP;Q?o<@`gp~?IU(u$DE!O7jIbs8MVN4jr)JH0jw5hEWa0@usu79G)G?^jv&YzU+f^
z-h?rYxg+JdW9MD)Bt!Q>>L
z4R3IS5yX`}_cL1=08(E@Av*Fv9(>V8)#Baz!c-Pu|AM0ld@XkOLsJ>C$537}C0bkqYFgWsYzbt*P>0RxJB~}=}D}s))h-Ub5pwL4T$JSyyS%ZLM>r_TF)ZLTY$pX8lPggGQ$~D
zl300{04G=`wvQpSgG_RAq~!tuYS(Fb2|Fw-u~{c6bt>6in%KtJZwOz`jOl9Owb%xA
z|DI2U?o6ajEjrWlSGkZy4lybZd*y*-k=iCogb(M=1EzJaB{2ru;)
z$u)t2J!?VRI`X}U^$$IxaDKWb2B#LsO)O?AlAMw7I8O2pvc3h6P~`(LbY4Aua#|q;
zYJL8Q01NABvGoYvyM(99oebAvI=bAeljF6{Ge8=(+nzO{2CnzPjVWw>ECMcpcB_M-
z2*J14r85k0QY3?(R0HRsfSpJ58-q3U8W`1&Bq#4b{rpP*fuuS#4pW=7V*hau~PE
zycrEsw)YI-;gZO(kBB7GCy%uVSBQw7=d$$QIc;d%syz-fk(&XR++{$*k-5CV>H^Ok
zNjnI={knLs&l{x(i)42WC^H8X2RUDKi_&3{R-QF^N@H^qn532gvbHrjtF_7rNMC3}
z!Q`KC7G$v>?@4mv815c-k@+R48DfhDl}4c~7ji{%G}up_(rmS5e-W#3s)(|A5ZUaI
zCvRWU$;r!)Xq%=_16@pK@GP8GMOWCEqWEUP%8JcN=%%wm*zOQ9cr;g9100|dmw{-A;^HRC=8DgRm-D*{IRW4Wdauq%7Fj6x37P4XOo
z3Drb8|G}7$zC`0(O7%t0BCt`k2&d6JmXR}QUSW8
z11q}#Z>KXf3Ts}oQx`VD4{sv((;#Z8GZ3{POhythfkG0PE+ndLf<(2+ZQ`kvPD&lX
zBmtG8tyH#Cipp0w*IFp$T8XwQQHU9Q>0+*yvz@X+w~0)nb=|7eBhlV#<-4>u(cU@A
zvF(xFq6&K*&{C&SJJ%bDw=)yEo7U<48Txe$>{*^EHX@deF`lx(&9TzBHeYZ+)Dt`-
zULoil8v#qWW6>x*?5QxsVKGDp=Wg<#HfvZWftyBitlyl}-NUoPu!g&yIk?#v@0?A7AV-cz83#R0Fm8qf`ii8TxI3XqC(T&OA7
zfJxmHZ1tM$jTB}@nMYx&MglHhP;CngW+hYDBP^*doruWADq=DNL
zNjj$rpeJq+R&J;$eK{500Ww>)z0Yoa*Mh`7Ue9%Xzxu+-z;4$gKH3F<(H<
z#~$B$UxH#(5oo!T%;V`Q!je8ifoxt=^pGjFWj)9HF#QnSN=}gm@DqVZ*y?Qb~x85A;>6@
z0nNEK%dx9v3h0I`@*He&27fGtIM(_Q#Mvztjv7^IXsJZaANG`BwNJf!kC%gSHUl-e
zJH9QA1or0>s`$qexp3&n@lmaQE;E!3F*2cTe=3;x9Y~w8OveHu4?J*vgz_O%J*OnS
z?JH^%P3B*2BLKPf_E{fYx3yc;=W9k1%GQD?Dz4Zb{yDmapHIW@-!9scHR0#^dOh;d
zflP%U0CS8T$zJuwXJq&Me4VA=>;3REhfY5`>&Fq?is=YNj;WXlV$Ty+aNYjN{jX@+
zElg)+m`Y@3M>0#<4>TDJ{
zp8TH`-$9iWV43+GT>z6p)6DD%UeFlrI#2~;e`=e3m@#vIY6wIq0F1!z=i&AD3H)Bv
z;J5Jblj2(FmPn_qaoLck2V|o87U$c~%v&E%SGxs5Y5x3_`J93q9S$cJ4)`}x5ki@f
z8COU_uK(KSxq7xic-c?xlVjUc!&kyn=+i>dhB$4YJhuM;yg(2=>xzPz$j79@&d=Oj
zNFqQ|Kv8=3`8-r91TbqKOn7Q_t6%?2nUjBEGv7zWH}^T;z7&e_H5LDP*nQAmc#R2+
zm&nt-LioJ=B0i`bJ{Ni0xa`CPF1jn7)h(^_0i)x!M>a^4&Q1Zqy%W==
zN$uS+U!q4bTR*vuwtrQqEhV{-;(tIK6^1({n`HL9!V4tO9Czx-Z<0Ew?iaI*I1#ID
z-gwUuR4|$laB^JpT-I+pc`vmA78oBXU_`or(_Dh&*v&RY7F2r+A_+VjH*6~YlCbo>
zJ{X6uLv@DVZ@XEDN8dLw|zP{xsFG%a^6)2ogOwoaP~wOoJ-0
zK#&ioi)m1XLe%rJz57Hh^2DTsQ@+{t?djv&^woLNs9Y3Sr+yREXXxG(Ji*=g>L
z$YgcHx`mZ?+T@>{UznLK_R@foE5Su9l=wtZ_#^})K}2LN&1d8cht+P8C2s#^)!!hl
zA;~C^fvO?rQIhRzWSx%$%nrHLAS^|eztpO(jEOD>=B3nA2eV
z?V{pmxnG>z@@0`ojZZED0Bt8{HkGSp|hliqOmV_F$ZEX7x{YZo4zMUhKiPob0ZN9QfVNN7-d}(D$=BAbwV3U7oA%yW|0C
zO=FD}Q(5MR%VHZTZp#X<5N(urFBLu1apP#zjdG_iJ-nCIzKxg{nY@s9a^>YW4Gks5
z)w=|&w)9^
z@Ds|;yB%Y$6fSo*BueF_5!I|iw=I++Mmu4o->C4~SA1SD1^7r
zXOrH{kmk<(8semUB)F6UwxlN@DN*!U^I2no?h(cF*vfknN6wNurR*=#F5$n3xnW|d
z<;3M3?E!+Ra+iry6c|N7Ku0P+_vKm)OBWMh%Pw*J0#<19{yvK^tUng6l*tLX@-ZNY
z>R=W_^H~12HrXIW7Kg%DWaAO`1n7(?8)8`OaL0gbCIm)`1p0|kKH%satPq6vfdu<+
z4u>Ps)C^qGfs5!8mdyHjZq4HQ=+0_6$~<#E}8v^JEbWO;K(FYtDbnploxBrFZyu1Sd>aAndC+71}
zneRNmAx5a>dQhZd(=zb4m=-Y#QRUo};kQu}6ticX}nG?1n%+C!#9jP&!p_!7sE(;7YwR5ypaK(>YR=tDE)zX^JE2K(Q)ojb2h793MEtQARCe8IgP
z4){4zW|eU02?87LD^x1xa+_ynkl!^=6XBjX7!z?uio6*h=
zIOgX3L2SYs(CHg?WY38iqjyg1zcF2?c0QBvSops$DR-EkPRxhumaVz{(PX5}4sF{^
z(B{PBL7^8HU`IBnPRc(RwmERXBIs<8h`WOl=tutR