From 154daf584c01fd2131d92233535c83ee15c246a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 8 Sep 2018 16:39:42 +0700
Subject: [PATCH] better qspi

---
 examples/device/nrf52840/src/msc_flash_qspi.c | 46 ++++++++++++++-
 hw/bsp/pca10056/board_pca10056.c              | 58 +++++++++++--------
 2 files changed, 78 insertions(+), 26 deletions(-)

diff --git a/examples/device/nrf52840/src/msc_flash_qspi.c b/examples/device/nrf52840/src/msc_flash_qspi.c
index 3496d06b..c2cca9b2 100644
--- a/examples/device/nrf52840/src/msc_flash_qspi.c
+++ b/examples/device/nrf52840/src/msc_flash_qspi.c
@@ -47,6 +47,19 @@ void flash_flush (void);
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
+enum
+{
+  FLASH_STATE_IDLE,
+  FLASH_STATE_BUSY,
+  FLASH_STATE_COMPLETE
+};
+
+volatile uint8_t _fl_state = FLASH_STATE_IDLE;
+
+void qspi_flash_complete (void)
+{
+  _fl_state = FLASH_STATE_COMPLETE;
+}
 
 //------------- IMPLEMENTATION -------------//
 // Callback invoked when received READ10 command.
@@ -55,8 +68,27 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
 {
   uint32_t addr = lba * CFG_TUD_MSC_BLOCK_SZ + offset;
 
-  flash_read(buffer, addr, bufsize);
 
+//  switch ( _fl_state )
+//  {
+//    case FLASH_STATE_IDLE:
+//      _fl_state = FLASH_STATE_BUSY;
+//      flash_read(buffer, addr, bufsize);
+//      return 0;  // data not ready
+//
+//    case FLASH_STATE_BUSY:
+//      return 0;  // data not ready
+//
+//    case FLASH_STATE_COMPLETE:
+//      _fl_state = FLASH_STATE_IDLE;
+//      return bufsize;
+//
+//    default:
+//      _fl_state = FLASH_STATE_IDLE;
+//      return -1;
+//  }
+
+  flash_read(buffer, addr, bufsize);
   return bufsize;
 }
 
@@ -96,7 +128,16 @@ void flash_flush (void)
   if ( _fl_addr == NO_CACHE ) return;
 
   TU_ASSERT(NRFX_SUCCESS == nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, _fl_addr),);
+//  while ( _fl_state != FLASH_STATE_COMPLETE )
+//  {
+//  }
+//  _fl_state = FLASH_STATE_IDLE;
+
   TU_ASSERT(NRFX_SUCCESS == nrfx_qspi_write(_fl_buf, FLASH_PAGE_SIZE, _fl_addr),);
+//  while ( _fl_state != FLASH_STATE_COMPLETE )
+//  {
+//  }
+//  _fl_state = FLASH_STATE_IDLE;
 
   _fl_addr = NO_CACHE;
 }
@@ -109,7 +150,8 @@ void flash_write (uint32_t dst, const void *src, int len)
   {
     flash_flush();
     _fl_addr = newAddr;
-    memset(_fl_buf, 0xff, FLASH_PAGE_SIZE);
+
+    flash_read(_fl_buf, newAddr, FLASH_PAGE_SIZE);
   }
   memcpy(_fl_buf + (dst & (FLASH_PAGE_SIZE - 1)), src, len);
 }
diff --git a/hw/bsp/pca10056/board_pca10056.c b/hw/bsp/pca10056/board_pca10056.c
index cfa40ff3..45078a98 100644
--- a/hw/bsp/pca10056/board_pca10056.c
+++ b/hw/bsp/pca10056/board_pca10056.c
@@ -80,6 +80,17 @@ uint32_t tusb_hal_millis(void)
 #define QSPI_STD_CMD_RST    0x99
 #define QSPI_STD_CMD_WRSR   0x01
 
+extern void qspi_flash_complete (void);
+
+void qflash_hdl (nrfx_qspi_evt_t event, void * p_context)
+{
+  (void) p_context;
+  (void) event;
+
+  qspi_flash_complete();
+}
+
+
 /* tinyusb function that handles power event (detected, ready, removed)
  * We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
  */
@@ -104,42 +115,41 @@ void board_init(void)
 
 // 64 Mbit qspi flash
 #ifdef BOARD_MSC_FLASH_QSPI
-  nrfx_qspi_config_t qspi_cfg =
-  {
-    .xip_offset  = 0,
+  nrfx_qspi_config_t qspi_cfg = {
+    .xip_offset = 0,
     .pins = {
-       .sck_pin     = 19,
-       .csn_pin     = 17,
-       .io0_pin     = 20,
-       .io1_pin     = 21,
-       .io2_pin     = 22,
-       .io3_pin     = 23,
+       .sck_pin = 19,
+       .csn_pin = 17,
+       .io0_pin = 20,
+       .io1_pin = 21,
+       .io2_pin = 22,
+       .io3_pin = 23,
     },
     .prot_if = {
-        .readoc     = NRF_QSPI_READOC_FASTREAD,
-        .writeoc    = NRF_QSPI_WRITEOC_PP,
-        .addrmode   = NRF_QSPI_ADDRMODE_24BIT,
-        .dpmconfig  = false, // deep power down
+      .readoc    = NRF_QSPI_READOC_READ4IO,
+      .writeoc   = NRF_QSPI_WRITEOC_PP,
+      .addrmode  = NRF_QSPI_ADDRMODE_24BIT,
+      .dpmconfig = false,  // deep power down
     },
     .phy_if = {
-        .sck_freq   = NRF_QSPI_FREQ_32MDIV16,
-        .sck_delay  = 1,
-        .spi_mode   = NRF_QSPI_MODE_0,
-        .dpmen      = false
+      .sck_freq  = NRF_QSPI_FREQ_32MDIV4,
+      .sck_delay = 1,
+      .spi_mode  = NRF_QSPI_MODE_0,
+      .dpmen     = false
     },
     .irq_priority   = 7,
   };
 
-  // callback = NULL --> blocking
   nrfx_qspi_init(&qspi_cfg, NULL, NULL);
+//  nrfx_qspi_init(&qspi_cfg, qflash_hdl, NULL);
 
   nrf_qspi_cinstr_conf_t cinstr_cfg = {
-      .opcode = 0,
-      .length = 0,
-      .io2_level = true,
-      .io3_level = true,
-      .wipwait   = true,
-      .wren      = true
+    .opcode    = 0,
+    .length    = 0,
+    .io2_level = true,
+    .io3_level = true,
+    .wipwait   = true,
+    .wren      = true
   };
 
   // Send reset enable