From 0afbf1a9bbffef250528d4be762b9af7078a4e71 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 26 Aug 2019 16:48:24 -0400
Subject: [PATCH] board_stm32h743nucleo: Route USB clock and pins.

---
 hw/bsp/stm32h743nucleo/board.mk               |  1 +
 .../stm32h743nucleo/board_stm32h743nucleo.c   | 37 ++++++++++++++++++-
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/stm32h743nucleo/board.mk b/hw/bsp/stm32h743nucleo/board.mk
index d1ad97bb..fb3a48dd 100644
--- a/hw/bsp/stm32h743nucleo/board.mk
+++ b/hw/bsp/stm32h743nucleo/board.mk
@@ -20,6 +20,7 @@ SRC_C += \
 	hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
 	hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
 	hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
+	hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
 	hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
 
 SRC_S += \
diff --git a/hw/bsp/stm32h743nucleo/board_stm32h743nucleo.c b/hw/bsp/stm32h743nucleo/board_stm32h743nucleo.c
index d7b86d3a..de09703a 100644
--- a/hw/bsp/stm32h743nucleo/board_stm32h743nucleo.c
+++ b/hw/bsp/stm32h743nucleo/board_stm32h743nucleo.c
@@ -53,7 +53,8 @@
   *            PLL1_M                         = 8
   *            PLL1_N                         = 336
   *            PLL1_P                         = 2
-  *            PLL1_Q                         = Unused (TODO: figure out how
+  *            PLL1_Q                         = 7
+  *            PLL1_R                         = Unused (TODO: figure out how
   *                                             to gate from HAL?)
   *            VDD(V)                         = 3.3
   *            Main regulator output voltage  = Scale3 mode
@@ -81,6 +82,7 @@ static void SystemClock_Config(void)
   RCC_OscInitStruct.PLL.PLLM = 8;
   RCC_OscInitStruct.PLL.PLLN = 336;
   RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
   RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
   RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
   RCC_OscInitStruct.PLL.PLLFRACN = 0;
@@ -107,7 +109,12 @@ static void SystemClock_Config(void)
   /* Like on F4, on H7, USB's actual peripheral clock and bus clock are
      separate. However, the main system PLL (PLL1) doesn't have a direct
      connection to the USB peripheral clock to generate 48 MHz, so we do this
-     dance. */
+     dance. This will connect PLL1's Q output to the USB peripheral clock. */
+  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
+
+  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
 }
 
 void board_init(void)
@@ -123,6 +130,32 @@ void board_init(void)
 
   GPIO_InitTypeDef  GPIO_InitStruct;
 
+  // USB Pin Init
+  // PA9- VUSB, PA10- ID, PA11- DM, PA12- DP
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+  /* Configure DM DP Pins */
+  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Configure VBUS Pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* This for ID line debug */
+  GPIO_InitStruct.Pin = GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
   __HAL_RCC_GPIOB_CLK_ENABLE();
 
   GPIO_InitStruct.Pin = LED_PIN;