ehci.h

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/**************************************************************************/
/**************************************************************************/

#ifndef _TUSB_EHCI_H_
#define _TUSB_EHCI_H_

#include "common/common.h"

/* Abbreviation
 * HC: Host Controller
 * HCD: Host Controller Driver
 * QHD: Queue Head for non-ISO transfer
 * QTD: Queue Transfer Descriptor for non-ISO transfer
 * ITD: Iso Transfer Descriptor for highspeed
 * SITD: Split ISO Transfer Descriptor for full-speed
 * SMASK: Start Split mask for Slipt Transaction
 * CMASK: Complete Split mask for Slipt Transaction
 * RO: Read Only
 * R/WC: Read, Write to Clear
*/

#ifdef __cplusplus
 extern "C" {
#endif

//--------------------------------------------------------------------+
// EHCI CONFIGURATION & CONSTANTS
//--------------------------------------------------------------------+
#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed
#define EHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)

// TODO merge OHCI with EHCI
#define EHCI_MAX_QHD  8
#define EHCI_MAX_QTD  20
#define EHCI_MAX_ITD  4
#define EHCI_MAX_SITD 16

#define EHCI_CFG_FRAMELIST_SIZE_BITS            7           
#define EHCI_FRAMELIST_SIZE  (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS)

//------------- Validation -------------//
#if EHCI_CFG_FRAMELIST_SIZE_BITS > 7
 #error EHCI_CFG_FRAMELIST_SIZE_BITS must be from 0-7
#endif

//--------------------------------------------------------------------+
// EHCI Data Structure
//--------------------------------------------------------------------+
enum ehci_queue_element_type_{
  EHCI_QUEUE_ELEMENT_ITD = 0 , 
  EHCI_QUEUE_ELEMENT_QHD     , 
  EHCI_QUEUE_ELEMENT_SITD    , 
  EHCI_QUEUE_ELEMENT_FSTN      
};

enum tusb_pid_{
  EHCI_PID_OUT = 0 ,
  EHCI_PID_IN      ,
  EHCI_PID_SETUP
};

typedef union {
    uint32_t address;
    struct  {
        uint32_t terminate : 1;
        uint32_t type      : 2;
    };
}ehci_link_t;

typedef struct {

    ehci_link_t next;

    union{
      ehci_link_t alternate;
      struct {
        uint32_t                : 5;
        uint32_t used           : 1;
        uint32_t                : 10;
        uint32_t expected_bytes : 16;
      };
    };

    volatile uint32_t pingstate_err               : 1  ; 
    volatile uint32_t non_hs_split_state          : 1  ; 
    volatile uint32_t non_hs_period_missed_uframe : 1  ; 
    volatile uint32_t xact_err                    : 1  ; 
    volatile uint32_t babble_err                  : 1  ; 
    volatile uint32_t buffer_err                  : 1  ; 
    volatile uint32_t halted                      : 1  ; 
    volatile uint32_t active                      : 1  ; 

    uint32_t pid                                  : 2  ; 
    volatile uint32_t cerr                        : 2  ; 
    volatile uint32_t current_page                : 3  ; 
    uint32_t int_on_complete                      : 1  ; 

    volatile uint32_t total_bytes                 : 15 ; 
    volatile uint32_t data_toggle                 : 1  ; 
    uint32_t                                      : 0  ; // padding to the end of current storage unit
    // End of Word 2

    uint32_t buffer[5];
} ehci_qtd_t; // XXX qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with ATTR_ALIGNED(32)

STATIC_ASSERT( sizeof(ehci_qtd_t) == 32, "size is not correct" );

typedef struct {
    ehci_link_t next;

    uint32_t device_address                   : 7  ; 
    uint32_t non_hs_period_inactive_next_xact : 1  ; 
    uint32_t endpoint_number                  : 4  ; 
    uint32_t endpoint_speed                   : 2  ; 
    uint32_t data_toggle_control              : 1  ; 
    uint32_t head_list_flag                   : 1  ; 
    uint32_t max_package_size                 : 11 ; 
    uint32_t non_hs_control_endpoint          : 1  ; 
    uint32_t nak_count_reload                 : 4  ; 
    uint32_t                                  : 0  ; // padding to the end of current storage unit
    // End of Word 1

    uint32_t interrupt_smask                  : 8  ; 
    uint32_t non_hs_interrupt_cmask           : 8  ; 
    uint32_t hub_address                      : 7  ; 
    uint32_t hub_port                         : 7  ; 
    uint32_t mult                             : 2  ; 
    uint32_t                                  : 0  ; // padding to the end of current storage unit
    // End of Word 2

    volatile uint32_t qtd_addr;

    volatile ehci_qtd_t qtd_overlay;

    //--------------------------------------------------------------------+
  //--------------------------------------------------------------------+
    uint8_t used;
    uint8_t is_removing;
    uint8_t pid_non_control;
    uint8_t class_code;

    uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
    uint8_t interval_ms; // polling interval in frames (or milisecond)
    uint8_t reserved;

    ehci_qtd_t * volatile p_qtd_list_head;  // head of the scheduled TD list
    ehci_qtd_t * volatile p_qtd_list_tail;  // tail of the scheduled TD list
} ehci_qhd_t;

STATIC_ASSERT( sizeof(ehci_qhd_t) == 64, "size is not correct" );

typedef struct ATTR_ALIGNED(32) {
    ehci_link_t next;

    struct  {
      // iTD Control
        volatile uint32_t offset          : 12 ; 
        volatile uint32_t page_select     : 3  ; 
             uint32_t int_on_complete : 1  ; 
        volatile uint32_t length          : 12 ; 
        // iTD Status
        volatile uint32_t error           : 1  ; 
        volatile uint32_t babble_err      : 1  ; 
        volatile uint32_t buffer_err      : 1  ; 
        volatile uint32_t active          : 1  ; 
    } xact[8];

    uint32_t BufferPointer[7];

//  // FIXME: Store meta data into buffer pointer reserved for saving memory
//  /*---------- HCD Area ----------*/
//  uint32_t used;
//  uint32_t IhdIdx;
//  uint32_t reserved[6];
} ehci_itd_t;

STATIC_ASSERT( sizeof(ehci_itd_t) == 64, "size is not correct" );

typedef struct ATTR_ALIGNED(32) {
    ehci_link_t next;

    uint32_t device_address  : 7; 
    uint32_t                 : 1; 
    uint32_t endpoint_number : 4; 
    uint32_t                 : 4; 
    uint32_t hub_address     : 7; 
    uint32_t                 : 1; 
    uint32_t port_number     : 7; 
    uint32_t direction       : 1; 
    uint32_t                 : 0; // padding to the end of current storage unit
    // End of Word 1

    uint8_t interrupt_smask            ; 
    uint8_t non_hs_interrupt_cmask     ; 
    uint16_t reserved ; 
    // End of Word 2

    // Status [7:0] TODO indentical to qTD Token'status --> refractor later
    volatile uint32_t                 : 1  ; // reserved
    volatile uint32_t split_state     : 1  ;
    volatile uint32_t missed_uframe   : 1  ;
    volatile uint32_t xact_err        : 1  ;
    volatile uint32_t babble_err      : 1  ;
    volatile uint32_t buffer_err      : 1  ;
    volatile uint32_t error           : 1  ;
    volatile uint32_t active          : 1  ;
    // Micro-frame Schedule Control
    volatile uint32_t cmask_progress  : 8  ; 
    volatile uint32_t total_bytes     : 10 ; 
    volatile uint32_t                 : 4  ; 
    volatile uint32_t page_select     : 1  ; 
                     uint32_t int_on_complete : 1  ; 
                     uint32_t                 : 0  ; // padding to the end of current storage unit
    // End of Word 3

    uint32_t buffer[2];     // buffer[1] TP: Transaction Position - T-Count: Transaction Count

//  union{
//      uint32_t BufferPointer1;
//      struct  {
//          volatile uint32_t TCount : 3;
//          volatile uint32_t TPosition : 2;
//      };
//  };

    /*---------- Word 6 ----------*/
    ehci_link_t back;

    uint8_t used;
    uint8_t ihd_idx;
    uint8_t reserved2[2];
} ehci_sitd_t;

STATIC_ASSERT( sizeof(ehci_sitd_t) == 32, "size is not correct" );

//--------------------------------------------------------------------+
// EHCI Operational Register
//--------------------------------------------------------------------+
enum ehci_interrupt_mask_{
  EHCI_INT_MASK_USB                   = BIT_(0),
  EHCI_INT_MASK_ERROR                 = BIT_(1),
  EHCI_INT_MASK_PORT_CHANGE           = BIT_(2),

  EHCI_INT_MASK_FRAMELIST_ROLLOVER    = BIT_(3),
  EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = BIT_(4),
  EHCI_INT_MASK_ASYNC_ADVANCE         = BIT_(5),
  EHCI_INT_MASK_NXP_SOF               = BIT_(7),

  EHCI_INT_MASK_NXP_ASYNC             = BIT_(18),
  EHCI_INT_MASK_NXP_PERIODIC          = BIT_(19),

  EHCI_INT_MASK_ALL                   =
      EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
      EHCI_INT_MASK_FRAMELIST_ROLLOVER | EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR |
      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF |
      EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
};

enum ehci_usbcmd_pos_ {
  EHCI_USBCMD_POS_RUN_STOP               = 0,
  EHCI_USBCMD_POS_FRAMELIST_SZIE         = 2,
  EHCI_USBCMD_POS_PERIOD_ENABLE          = 4,
  EHCI_USBCMD_POS_ASYNC_ENABLE           = 5,
  EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15,
  EHCI_USBCMD_POS_INTERRUPT_THRESHOLD    = 16
};

enum ehci_portsc_change_mask_{
  EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = BIT_(1),
  EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = BIT_(3),
  EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = BIT_(5),

  EHCI_PORTSC_MASK_ALL =
      EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
      EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE |
      EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
};

typedef volatile struct {
  union {
    uint32_t usb_cmd                  ; 
    struct {
      uint32_t run_stop               : 1 ; 
      uint32_t reset                  : 1 ; 
      uint32_t framelist_size         : 2 ; 
      uint32_t periodic_enable        : 1 ; 
      uint32_t async_enable           : 1 ; 
      uint32_t advacne_async          : 1 ; 
      uint32_t light_reset            : 1 ; 
      uint32_t async_park             : 2 ; 
      uint32_t                        : 1 ; 
      uint32_t async_park_enable      : 1 ; 
      uint32_t                        : 3 ; 
      uint32_t nxp_framelist_size_msb : 1 ; 
      uint32_t int_threshold          : 8 ; 
      uint32_t                        : 0 ; // padding to the boundary of storage unit
    }usb_cmd_bit;
  };

  union {
    uint32_t usb_sts            ; 
    struct {
      uint32_t usb                    : 1  ; 
      uint32_t usb_error              : 1  ; 
      uint32_t port_change_detect     : 1  ; 
      uint32_t framelist_rollover     : 1  ; 
      uint32_t pci_host_system_error  : 1  ; 
      uint32_t async_advance          : 1  ; 
      uint32_t                        : 1  ; 
      uint32_t nxp_int_sof            : 1  ; 
      uint32_t                        : 4  ; 
      uint32_t hc_halted              : 1  ; 
      uint32_t reclamation            : 1  ; 
      uint32_t period_schedule_status : 1  ; 
      uint32_t async_schedule_status  : 1  ; 
      uint32_t                        : 2  ; 
      uint32_t nxp_int_async          : 1  ; 
      uint32_t nxp_int_period         : 1  ; 
      uint32_t                        : 12 ; 
      uint32_t                        : 0  ; // padding to the boundary of storage unit
    }usb_sts_bit;
  };

  union{
    uint32_t usb_int_enable     ; 
    struct {
      uint32_t usb                   : 1  ; 
      uint32_t usb_error             : 1  ; 
      uint32_t port_change_detect    : 1  ; 
      uint32_t framelist_rollover    : 1  ; 
      uint32_t pci_host_system_error : 1  ; 
      uint32_t async_advance         : 1  ; 
      uint32_t                       : 1  ; 
      uint32_t nxp_int_sof           : 1  ; 
      uint32_t                       : 10 ; 
      uint32_t nxp_int_async         : 1  ; 
      uint32_t nxp_int_period        : 1  ; 
      uint32_t                       : 12 ; 
      uint32_t                       : 0  ; // padding to the boundary of storage unit
    }usb_int_enable_bit;
  };

  uint32_t frame_index        ; 
  uint32_t ctrl_ds_seg        ; 
  uint32_t periodic_list_base ; 
  uint32_t async_list_base    ; 
  uint32_t tt_control         ; 
  uint32_t reserved[8]        ; 
  uint32_t config_flag        ; 

  union {
    uint32_t portsc             ; 
    struct {
      uint32_t current_connect_status      : 1; 
      uint32_t connect_status_change       : 1; 
      uint32_t port_enable                 : 1; 
      uint32_t port_enable_change          : 1; 
      uint32_t over_current_active         : 1; 
      uint32_t over_current_change         : 1; 
      uint32_t force_port_resume           : 1; 
      uint32_t suspend                     : 1; 
      uint32_t port_reset                  : 1; 
      uint32_t nxp_highspeed_status        : 1; 
      uint32_t line_status                 : 2; 
      uint32_t port_power                  : 1; 
      uint32_t port_owner                  : 1; 
      uint32_t port_indicator_control      : 2; 
      uint32_t port_test_control           : 4; 
      uint32_t wake_on_connect_enable      : 1; 
      uint32_t wake_on_disconnect_enable   : 1; 
      uint32_t wake_on_over_current_enable : 1; 
      uint32_t nxp_phy_clock_disable       : 1; 
      uint32_t nxp_port_force_fullspeed    : 1; 
      uint32_t                             : 1;
      uint32_t nxp_port_speed              : 2; 
      uint32_t                             : 0; // padding to the boundary of storage unit
    }portsc_bit;
  };
}ehci_registers_t;

//--------------------------------------------------------------------+
// EHCI Data Organization
//--------------------------------------------------------------------+
typedef struct {
  //------------- Static Async/Period List Head, Each for one controller -------------//
  ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; 

#if EHCI_PERIODIC_LIST
  // for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
  // [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
  ehci_qhd_t period_head_arr[CONTROLLER_HOST_NUMBER][4];
#endif

  //------------- Data for Address 0 (use async head as its queue head) -------------//
  ehci_qtd_t addr0_qtd[3];

  struct {
    struct {
      ehci_qhd_t qhd;
      ehci_qtd_t qtd[3];
    }control;

    ehci_qhd_t  qhd[EHCI_MAX_QHD]                  ; 
    ehci_qtd_t  qtd[EHCI_MAX_QTD] ATTR_ALIGNED(32) ; 
//  ehci_itd_t  itd[EHCI_MAX_ITD]                  ; ///< Iso Transfer Pool
//  ehci_sitd_t sitd[EHCI_MAX_SITD]                ; ///< Split (FS) Isochronous Transfer Pool
  }device[TUSB_CFG_HOST_DEVICE_MAX];
}ehci_data_t;

#ifdef __cplusplus
 }
#endif

#endif /* _TUSB_EHCI_H_ */