diff --git a/demos/bsp/boards/embedded_artists/oem_base_board/pca9532.h b/demos/bsp/boards/embedded_artists/oem_base_board/pca9532.h
index 6a55804c8..885075326 100644
--- a/demos/bsp/boards/embedded_artists/oem_base_board/pca9532.h
+++ b/demos/bsp/boards/embedded_artists/oem_base_board/pca9532.h
@@ -48,7 +48,7 @@
#define KEY_MASK 0x000F
/*
- * MMC Card Detect and MMC Write Protect are mapped to LED4
+ * MMC Card Detect and MMC Write Protect are mapped to LED4
* and LED5 on the PCA9532. Please note that WP is active low.
*/
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/LPC17xx.h b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/LPC17xx.h
index 377fdf240..7df6d5ffb 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/LPC17xx.h
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/LPC17xx.h
@@ -1,6 +1,6 @@
/**************************************************************************//**
* @file LPC17xx.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* NXP LPC17xx Device Series
* @version: V1.09
* @date: 17. March 2010
@@ -10,9 +10,9 @@
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cm3.h b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cm3.h
index a2b29eeaf..4847a18d2 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cm3.h
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cm3.h
@@ -8,9 +8,9 @@
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,37 +20,37 @@
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
-#if defined ( __ICCARM__ )
+#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
-#endif
+#endif
#ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC
/** \mainpage CMSIS Cortex-M3
-
+
This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
It consists of:
-
+
- Cortex-M Core Register Definitions
- Cortex-M functions
- Cortex-M instructions
-
- The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
access to the Cortex-M Core
- */
+ */
/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
List of Lint messages which will be suppressed and not shown:
- not yet checked
.
Note: To re-enable a Message, insert a space before 'lint' *
-
+
*/
@@ -60,7 +60,7 @@
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- - Cortex-M core
+ - Cortex-M core
- Cortex-M core Revision Number
@{
*/
@@ -129,7 +129,7 @@
- Core MPU Register
*/
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE CMSIS Core
Type definitions for the Cortex-M Core Registers
@{
@@ -154,7 +154,7 @@ typedef union
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
+ uint32_t w; /*!< Type used for word access */
} APSR_Type;
@@ -214,7 +214,7 @@ typedef union
/*@} end of group CMSIS_CORE */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC CMSIS NVIC
Type definitions for the Cortex-M NVIC Registers
@{
@@ -225,24 +225,24 @@ typedef union
typedef struct
{
__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
+ uint32_t RESERVED0[24];
__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
+ uint32_t RSERVED1[24];
__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
+ uint32_t RESERVED2[24];
__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
+ uint32_t RESERVED3[24];
__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
+ uint32_t RESERVED4[56];
__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
+ uint32_t RESERVED5[644];
__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
+} NVIC_Type;
/*@} end of group CMSIS_NVIC */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
@@ -271,7 +271,7 @@ typedef struct
__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
-} SCB_Type;
+} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
@@ -408,7 +408,7 @@ typedef struct
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
+
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
@@ -457,7 +457,7 @@ typedef struct
/*@} end of group CMSIS_SCB */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick CMSIS SysTick
Type definitions for the Cortex-M System Timer Registers
@{
@@ -507,7 +507,7 @@ typedef struct
/*@} end of group CMSIS_SysTick */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_ITM CMSIS ITM
Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
@{
@@ -517,26 +517,26 @@ typedef struct
*/
typedef struct
{
- __O union
+ __O union
{
__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
+ uint32_t RESERVED0[864];
__IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
+ uint32_t RESERVED1[15];
__IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
+ uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
+ uint32_t RESERVED3[29];
__IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */
__IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
+ uint32_t RESERVED4[43];
__IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */
__IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */
- uint32_t RESERVED5[6];
+ uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */
@@ -549,7 +549,7 @@ typedef struct
__I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */
__I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */
__I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
+} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
@@ -605,7 +605,7 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_InterruptType CMSIS Interrupt Type
Type definitions for the Cortex-M Interrupt Type Register
@{
@@ -642,7 +642,7 @@ typedef struct
#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU CMSIS MPU
Type definitions for the Cortex-M Memory Protection Unit (MPU)
@{
@@ -663,7 +663,7 @@ typedef struct
__IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
+} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
@@ -731,7 +731,7 @@ typedef struct
#endif
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug CMSIS Core Debug
Type definitions for the Cortex-M Core Debug Registers
@{
@@ -834,10 +834,10 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
@{
*/
-
+
/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
@@ -876,7 +876,7 @@ typedef struct
/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
+/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
@{
*/
@@ -895,11 +895,11 @@ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
+
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -921,7 +921,7 @@ static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
/** \brief Enable External Interrupt
This function enables a device specific interupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to enable
*/
@@ -934,7 +934,7 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
/** \brief Disable External Interrupt
This function disables a device specific interupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to disable
*/
@@ -947,7 +947,7 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
/** \brief Get Pending Interrupt
This function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
+ for the specified interrupt.
\param [in] IRQn Number of the interrupt for get pending
\return 0 Interrupt status is not pending
@@ -961,7 +961,7 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
/** \brief Set Pending Interrupt
- This function sets the pending bit for the specified interrupt.
+ This function sets the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for set pending
@@ -974,7 +974,7 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
/** \brief Clear Pending Interrupt
- This function clears the pending bit for the specified interrupt.
+ This function clears the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for clear pending
@@ -987,7 +987,7 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
/** \brief Get Active Interrupt
- This function reads the active register in NVIC and returns the active bit.
+ This function reads the active register in NVIC and returns the active bit.
\param [in] IRQn Number of the interrupt for get active
\return 0 Interrupt status is not active
\return 1 Interrupt status is active
@@ -1000,8 +1000,8 @@ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
/** \brief Set Interrupt Priority
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
+ This function sets the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
Note: The priority cannot be set for every core interrupt.
@@ -1020,8 +1020,8 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
/** \brief Get Interrupt Priority
- This function reads the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
+ This function reads the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
The returned priority value is automatically aligned to the implemented
@@ -1046,7 +1046,7 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
preemptive priority value and sub priority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
+
The returned priority value can be used for NVIC_SetPriority(...) function
\param [in] PriorityGroup Used priority group
@@ -1062,7 +1062,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
@@ -1072,13 +1072,13 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
/** \brief Decode Priority
- This function decodes an interrupt priority value with the given priority group to
+ This function decodes an interrupt priority value with the given priority group to
preemptive priority value and sub priority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
+
The priority value can be retrieved with NVIC_GetPriority(...) function
-
+
\param [in] Priority Priority value
\param [in] PriorityGroup Used priority group
\param [out] pPreemptPriority Preemptive priority value (starting from 0)
@@ -1092,7 +1092,7 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
@@ -1105,11 +1105,11 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
static __INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
+ __DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
@@ -1118,7 +1118,7 @@ static __INLINE void NVIC_SystemReset(void)
/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
+/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
@{
*/
@@ -1135,14 +1135,14 @@ static __INLINE void NVIC_SystemReset(void)
\return 1 Function failed
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
+{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
+
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
@@ -1154,7 +1154,7 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks)
/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
+/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
@{
*/
@@ -1165,9 +1165,9 @@ extern volatile int32_t ITM_RxBuffer; /*!< external variable
/** \brief ITM Send Character
- This function transmits a character via the ITM channel 0.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ This function transmits a character via the ITM channel 0.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
\param [in] ch Character to transmit
\return Character to transmit
@@ -1180,16 +1180,16 @@ static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
- }
+ }
return (ch);
}
/** \brief ITM Receive Character
- This function inputs a character via external variable ITM_RxBuffer.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ This function inputs a character via external variable ITM_RxBuffer.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
\return Received character
\return -1 No character received
@@ -1201,15 +1201,15 @@ static __INLINE int32_t ITM_ReceiveChar (void) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
-
- return (ch);
+
+ return (ch);
}
/** \brief ITM Check Character
- This function checks external variable ITM_RxBuffer whether a character is available or not.
- It returns '1' if a character is available and '0' if no character is available.
+ This function checks external variable ITM_RxBuffer whether a character is available or not.
+ It returns '1' if a character is available and '0' if no character is available.
\return 0 No character available
\return 1 Character available
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmFunc.h b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
index e1ed2666b..33baa1923 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
@@ -8,9 +8,9 @@
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -25,7 +25,7 @@
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
+/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
@@ -50,7 +50,7 @@ static __INLINE uint32_t __get_CONTROL(void)
register uint32_t __regControl __ASM("control");
return(__regControl);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
@@ -67,7 +67,7 @@ static __INLINE void __set_CONTROL(uint32_t control)
register uint32_t __regControl __ASM("control");
__regControl = control;
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
@@ -84,7 +84,7 @@ static __INLINE uint32_t __get_IPSR(void)
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
@@ -101,7 +101,7 @@ static __INLINE uint32_t __get_APSR(void)
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
@@ -118,7 +118,7 @@ static __INLINE uint32_t __get_xPSR(void)
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
@@ -135,7 +135,7 @@ static __INLINE uint32_t __get_PSP(void)
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
@@ -152,7 +152,7 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack)
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
@@ -169,7 +169,7 @@ static __INLINE uint32_t __get_MSP(void)
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
@@ -186,7 +186,7 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack)
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
@@ -203,7 +203,7 @@ static __INLINE uint32_t __get_PRIMASK(void)
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
@@ -220,8 +220,8 @@ static __INLINE void __set_PRIMASK(uint32_t priMask)
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
-#endif /* __ARMCC_VERSION */
-
+#endif /* __ARMCC_VERSION */
+
#if (__CORTEX_M >= 0x03)
@@ -255,7 +255,7 @@ static __INLINE uint32_t __get_BASEPRI(void)
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
@@ -272,8 +272,8 @@ static __INLINE void __set_BASEPRI(uint32_t basePri)
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
-#endif /* __ARMCC_VERSION */
-
+#endif /* __ARMCC_VERSION */
+
/** \brief Get Fault Mask
@@ -289,7 +289,7 @@ static __INLINE uint32_t __get_FAULTMASK(void)
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Fault Mask
@@ -306,7 +306,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask)
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
@@ -469,7 +469,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
-
+
/** \brief Set Process Stack Pointer
@@ -496,7 +496,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
-
+
/** \brief Set Main Stack Pointer
@@ -535,7 +535,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
-
+
#if (__CORTEX_M >= 0x03)
@@ -570,7 +570,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
-
+
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
@@ -597,7 +597,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
-
+
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmInstr.h b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
index 8cfafe418..7e5463335 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
@@ -8,9 +8,9 @@
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -66,8 +66,8 @@
/** \brief Instruction Synchronization Barrier
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
@@ -75,7 +75,7 @@
/** \brief Data Synchronization Barrier
- This function acts as a special kind of Data Memory Barrier.
+ This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
@@ -83,7 +83,7 @@
/** \brief Data Memory Barrier
- This function ensures the apparent order of the explicit memory operations before
+ This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
@@ -114,7 +114,7 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value)
rev16 r0, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
@@ -132,7 +132,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
revsh r0, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
@@ -222,7 +222,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Signed Saturate
@@ -254,7 +254,7 @@ extern void __CLREX(void);
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
-#define __CLZ __clz
+#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
@@ -319,8 +319,8 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
/** \brief Instruction Synchronization Barrier
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
@@ -331,7 +331,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
/** \brief Data Synchronization Barrier
- This function acts as a special kind of Data Memory Barrier.
+ This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
@@ -342,7 +342,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
/** \brief Data Memory Barrier
- This function ensures the apparent order of the explicit memory operations before
+ This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
@@ -361,7 +361,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
-
+
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -377,7 +377,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
-
+
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -393,7 +393,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
-
+
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -411,7 +411,7 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
-
+
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -427,7 +427,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
-
+
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
@@ -443,7 +443,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
-
+
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
@@ -459,7 +459,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
-
+
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
@@ -477,7 +477,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
-
+
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
@@ -495,7 +495,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
-
+
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
@@ -513,7 +513,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
-
+
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
@@ -572,7 +572,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
-
+
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
index d72cb509e..4399e0480 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
@@ -9,9 +9,9 @@
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -52,7 +52,7 @@ extern void SystemInit (void);
* @param none
* @return none
*
- * @brief Updates the SystemCoreClock with current core Clock
+ * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/core_cm3.c b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/core_cm3.c
index 6e13f4c66..eb472aca3 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/core_cm3.c
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/core_cm3.c
@@ -8,9 +8,9 @@
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -60,7 +60,7 @@ __ASM uint32_t __REV16(uint32_t value)
rev16 r0, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
@@ -76,7 +76,7 @@ __ASM int32_t __REVSH(int32_t value)
revsh r0, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Remove the exclusive lock
@@ -89,7 +89,7 @@ __ASM void __CLREX(void)
{
clrex
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
@@ -117,7 +117,7 @@ __ASM uint32_t __get_CONTROL(void)
mrs r0, control
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
@@ -132,7 +132,7 @@ __ASM void __set_CONTROL(uint32_t control)
msr control, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
@@ -147,7 +147,7 @@ __ASM uint32_t __get_IPSR(void)
mrs r0, ipsr
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
@@ -162,7 +162,7 @@ __ASM uint32_t __get_APSR(void)
mrs r0, apsr
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
@@ -177,7 +177,7 @@ __ASM uint32_t __get_xPSR(void)
mrs r0, xpsr
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
@@ -192,7 +192,7 @@ __ASM uint32_t __get_PSP(void)
mrs r0, psp
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
@@ -207,7 +207,7 @@ __ASM void __set_PSP(uint32_t topOfProcStack)
msr psp, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
@@ -222,7 +222,7 @@ __ASM uint32_t __get_MSP(void)
mrs r0, msp
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
@@ -237,7 +237,7 @@ __ASM void __set_MSP(uint32_t mainStackPointer)
msr msp, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Get Base Priority
@@ -252,7 +252,7 @@ __ASM uint32_t __get_BASEPRI(void)
mrs r0, basepri
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
@@ -267,8 +267,8 @@ __ASM void __set_BASEPRI(uint32_t basePri)
msr basepri, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
-
+#endif /* __ARMCC_VERSION */
+
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
@@ -281,7 +281,7 @@ __ASM uint32_t __get_PRIMASK(void)
mrs r0, primask
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
@@ -296,8 +296,8 @@ __ASM void __set_PRIMASK(uint32_t priMask)
msr primask, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
-
+#endif /* __ARMCC_VERSION */
+
/** \brief Get Fault Mask
@@ -311,7 +311,7 @@ __ASM uint32_t __get_FAULTMASK(void)
mrs r0, faultmask
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
/** \brief Set the Fault Mask
@@ -326,7 +326,7 @@ __ASM void __set_FAULTMASK(uint32_t faultMask)
msr faultmask, r0
bx lr
}
-#endif /* __ARMCC_VERSION */
+#endif /* __ARMCC_VERSION */
diff --git a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/system_LPC17xx.c b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
index b5359089c..d1e9bc40e 100644
--- a/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
+++ b/demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
@@ -9,9 +9,9 @@
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -376,7 +376,7 @@
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
-
+
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
@@ -389,7 +389,7 @@
/* F_cco0 = (2 * M * F_in) / N */
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
-#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
+#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
/* Determine core clock frequency according to settings */
@@ -398,7 +398,7 @@
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
#elif ((CLKSRCSEL_Val & 0x03) == 2)
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
- #else
+ #else
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
#endif
#else
@@ -428,19 +428,19 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
switch (LPC_SC->CLKSRCSEL & 0x03) {
case 0: /* Int. RC oscillator => PLL0 */
case 3: /* Reserved, default to Int. RC */
- SystemCoreClock = (IRC_OSC *
+ SystemCoreClock = (IRC_OSC *
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 1: /* Main oscillator => PLL0 */
- SystemCoreClock = (OSC_CLK *
+ SystemCoreClock = (OSC_CLK *
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 2: /* RTC oscillator => PLL0 */
- SystemCoreClock = (RTC_CLK *
+ SystemCoreClock = (RTC_CLK *
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
diff --git a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h
index 21204cc53..c2eff87ed 100644
--- a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h
+++ b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h
@@ -1,28 +1,28 @@
-/***********************************************************************
- * $Id: fpu_enable.h
- *
- * Project: LPC43xx
- *
+/***********************************************************************
+ * $Id: fpu_enable.h
+ *
+ * Project: LPC43xx
+ *
* Description: fpu initialization routine header
- *
+ *
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
- *
+ *
***********************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
**********************************************************************/
-#ifndef __FPU_ENABLE_H
-#define __FPU_ENABLE_H
+#ifndef __FPU_ENABLE_H
+#define __FPU_ENABLE_H
#if defined(__ARMCC_VERSION)
void fpuEnable(void) __attribute__ ((section("BOOTSTRAP_CODE")));
diff --git a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c
index b091668c8..1de4c4d5d 100644
--- a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c
+++ b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c
@@ -696,11 +696,11 @@ uint32_t CGU_SetPLL0audio(void){
LPC_CGU->PLL0AUDIO_MDIV = (0 << 28) /* SELR */
| (40 << 22) /* SELI */
| (31 << 17) /* SELP */
- | 11372; /* MDEC */
+ | 11372; /* MDEC */
/* set ndec, pdec register */
LPC_CGU->PLL0AUDIO_NP_DIV = (22 << 12) /* ndec */
- | (10); /* pdec */
-
+ | (10); /* pdec */
+
/* set fraction divider register. [21:15] = m, [14:0] = fractional value */
LPC_CGU->PLL0AUDIO_FRAC = (86 << 15) | 0x1B7;
LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
@@ -708,8 +708,8 @@ uint32_t CGU_SetPLL0audio(void){
| _BIT(4); /* CLKEN */
#endif
/* wait for lock */
- while (!(LPC_CGU->PLL0AUDIO_STAT & 1));
-
+ while (!(LPC_CGU->PLL0AUDIO_STAT & 1));
+
return CGU_ERROR_SUCCESS;
}
diff --git a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c
index 418d9a3df..996307919 100644
--- a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c
+++ b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c
@@ -552,7 +552,7 @@ end_stage:
I2C_IntCmd(I2Cx, FALSE);
// Send stop
I2C_Stop(I2Cx);
-
+
I2C_MasterComplete[tmp] = TRUE;
}
break;
diff --git a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c
index fa5afd9ef..53c6bd93c 100644
--- a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c
+++ b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c
@@ -40,7 +40,7 @@
#include "lpc43xx_scu.h"
/* Pin modes
-* =========
+* =========
* The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip
* pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the
* selection of the repeater mode.
@@ -53,16 +53,16 @@
* typically be used to prevent a pin from floating (and potentially using significant power if it
* floats to an indeterminate state) if it is temporarily not driven.
* Repeater mode is enabled when both pull-up and pull-down are enabled.
-*
+*
* To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
* the pin configuration registers. By default, the input buffer is disabled.
* For pads that support both a digital and an analog function, the input buffer must be
* disabled before enabling the analog function.
-*
+*
* All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
* off. By default, the glitch filter is on. The glitch filter should be disabled for
* clocking signals with frequencies higher than 30 MHz.
-*
+*
* Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
* between lower noise and low speed or higher noise and high speed . The typical
* frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for
diff --git a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c
index 7e132ef03..c5fe8d961 100644
--- a/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c
+++ b/demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c
@@ -69,7 +69,7 @@ void SystemInit (void)
fpuEnable();
#endif
#endif
-
+
#if !defined(CORE_M0)
// Set up Cortex_M3 or M4 VTOR register to point to vector table
// This code uses a toolchain defined symbol to locate the vector table
diff --git a/demos/device/device_os_none/device_os_none.ewp b/demos/device/device_os_none/device_os_none.ewp
index 4d237ce72..f8a554612 100644
--- a/demos/device/device_os_none/device_os_none.ewp
+++ b/demos/device/device_os_none/device_os_none.ewp
@@ -219,7 +219,7 @@