From 6a736db159b60a843b96b1b4b1ca1db7a5269253 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 10 Mar 2014 15:31:12 +0700 Subject: [PATCH] try to port lpc11uxx device demo with IAR --- demos/device/device_os_none/.cproject | 127 +-- .../device/device_os_none/device_os_none.ewp | 945 ++++++++++++++++++ .../device_os_none/device_os_none.uvopt | 84 +- .../device_os_none/device_os_none.uvproj | 80 +- demos/device/src/tusb_config.h | 6 +- tinyusb/device/dcd_lpc_11uxx_13uxx.c | 6 +- 6 files changed, 1102 insertions(+), 146 deletions(-) diff --git a/demos/device/device_os_none/.cproject b/demos/device/device_os_none/.cproject index 72f3110e3..6ae2d644e 100644 --- a/demos/device/device_os_none/.cproject +++ b/demos/device/device_os_none/.cproject @@ -473,73 +473,86 @@ <?xml version="1.0" encoding="UTF-8"?> <TargetConfig> -<Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/> -<infoList vendor="NXP"><info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"><chip><name>LPC1769</name> -<family>LPC17xx</family> +<Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="1"/> +<infoList vendor="NXP"><info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC4357</name> +<family>LPC43xx</family> <vendor>NXP (formerly Philips)</vendor> <reset board="None" core="Real" sys="Real"/> <clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/> <memory can_program="true" id="Flash" is_ro="true" type="Flash"/> <memory id="RAM" type="RAM"/> <memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/> +<memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/> +<memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/> <memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/> -<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/> -<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/> -<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/> -<peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/> -<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/> -<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/> -<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/> -<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&amp;0x1" id="TIMER3" location="0x40094000"/> -<peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&amp;0x1" id="RIT" location="0x400B0000"/> -<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO0" location="0x2009C000"/> -<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/> -<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/> -<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/> -<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/> -<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/> -<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/> -<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/> -<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/> -<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/> -<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/> -<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/> -<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/> -<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/> -<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/> -<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/> -<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/> -<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/> -<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/> -<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/> -<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/> -<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/> -<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/> -<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/> -<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/> -<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/> -<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/> -<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/> -<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/> -<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/> -<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/> -<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/> -<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/> -<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/> -<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/> -<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/> -<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/> -<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/> -<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/> -<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/> -<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&amp;0x1" id="MCPWM" location="0x400B8000"/> -<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/> +<memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/> +<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/> +<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/> +<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/> +<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/> +<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/> +<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/> +<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/> +<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/> +<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/> +<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/> +<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/> +<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/> +<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/> +<peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/> +<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/> +<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/> +<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/> +<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/> +<peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/> +<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/> +<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/> +<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/> +<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/> +<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/> +<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/> +<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/> +<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/> +<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/> +<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/> +<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/> +<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/> +<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/> +<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/> +<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/> +<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/> +<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/> +<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/> +<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/> +<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/> +<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/> +<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/> +<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/> +<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/> +<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/> +<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/> +<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/> +<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/> +<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/> +<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/> +<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/> +<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/> +<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/> +<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/> +<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/> +<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/> +<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/> +<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/> +<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/> +<peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/> +<peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/> </chip> -<processor><name gcc_name="cortex-m3">Cortex-M3</name> +<processor><name gcc_name="cortex-m4">Cortex-M4</name> <family>Cortex-M</family> </processor> -<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/> +<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/> </info> </infoList> </TargetConfig> diff --git a/demos/device/device_os_none/device_os_none.ewp b/demos/device/device_os_none/device_os_none.ewp index 90a02772d..57be60bff 100644 --- a/demos/device/device_os_none/device_os_none.ewp +++ b/demos/device/device_os_none/device_os_none.ewp @@ -2768,6 +2768,928 @@ + + Board rf1ghznode + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + app @@ -2821,6 +3743,28 @@ $PROJ_DIR$\..\..\bsp\boards\printf_retarget.c + + lpc11uxx + + Board LPCXpresso1769 + Board rf1ghznode + + + $PROJ_DIR$\..\..\bsp\lpc11uxx\CMSISv2p00_LPC11Uxx\src\core_cm0.c + + + $PROJ_DIR$\..\..\bsp\lpc11uxx\LPC11Uxx_DriverLib\lpc11uxx_gpio.c + + + $PROJ_DIR$\..\..\bsp\lpc11uxx\LPC11Uxx_DriverLib\lpc11uxx_uart.c + + + $PROJ_DIR$\..\..\bsp\lpc11uxx\startup_iar\startup_lpc11xx.s + + + $PROJ_DIR$\..\..\bsp\lpc11uxx\CMSISv2p00_LPC11Uxx\src\system_LPC11Uxx.c + + lpc175x_6x @@ -2853,6 +3797,7 @@ lpc43xx Board LPCXpresso1769 + Board rf1ghznode $PROJ_DIR$\..\..\bsp\lpc43xx\CMSIS_LPC43xx_DriverLib\src\lpc43xx_cgu.c diff --git a/demos/device/device_os_none/device_os_none.uvopt b/demos/device/device_os_none/device_os_none.uvopt index 9f71a431f..731a9f659 100644 --- a/demos/device/device_os_none/device_os_none.uvopt +++ b/demos/device/device_os_none/device_os_none.uvopt @@ -295,7 +295,7 @@ 12000000 - 0 + 1 1 1 0 @@ -387,6 +387,13 @@ Segger\JL2CM3.dll + + + 0 + JL2CM3 + -U268003250 -O78 -S8 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000 + + 0 @@ -475,7 +482,7 @@ 1 0 - 1 + 0 8 @@ -564,7 +571,7 @@ - Board LPCXpresso11u14 + Board rf1ghznode 0x4 ARM-ADS @@ -616,18 +623,40 @@ 1 0 - 0 + 1 8 + + + 0 + Data Sheet + DATASHTS\NXP\LPC11Uxx\LPC11U3x_DS.pdf + + + 1 + User Manual + DATASHTS\NXP\LPC11Uxx\LPC11U3x_UM.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m0\r0p0\DUI0497A_CORTEX_M0_R0P0_GENERIC_UG.PDF + + SARMCM3.DLL - DARMP1.DLL - -pLPC11U14 + DARMCM1.DLL + -pCM0 SARMCM3.DLL - TARMP1.DLL - -pLPC11U14 + TARMCM1.DLL + -pCM0 0 @@ -649,7 +678,7 @@ 1 0 0 - 1 + 7 @@ -660,8 +689,15 @@ - BIN\UL2CM3.DLL + Segger\JL2CM3.dll + + + 0 + JL2CM3 + -U268003250 -O78 -S8 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000 + + 0 @@ -699,7 +735,7 @@ app - 1 + 0 0 0 0 @@ -773,10 +809,10 @@ 1 0 0 - 22 + 0 0 - 78 - 84 + 1 + 1 0 ..\src\mscd_app.c mscd_app.c @@ -835,7 +871,7 @@ tinyusb - 1 + 0 0 0 0 @@ -1117,10 +1153,10 @@ 1 0 0 - 0 + 49 0 - 0 - 0 + 402 + 420 0 ..\..\..\tinyusb\device\dcd_lpc_11uxx_13uxx.c dcd_lpc_11uxx_13uxx.c @@ -1285,10 +1321,10 @@ 1 0 0 - 6 + 25 0 - 184 - 202 + 190 + 208 0 ..\..\bsp\boards\embedded_artists\oem_base_board\pca9532.c pca9532.c @@ -1299,7 +1335,7 @@ 3 37 1 - 1 + 0 0 0 0 @@ -1439,7 +1475,7 @@ 0 19 0 - 17 + 18 23 0 ..\..\bsp\lpc11uxx\LPC11Uxx_DriverLib\lpc11uxx_gpio.c @@ -1455,7 +1491,7 @@ 0 19 0 - 8 + 9 14 0 ..\..\bsp\lpc11uxx\LPC11Uxx_DriverLib\lpc11uxx_uart.c diff --git a/demos/device/device_os_none/device_os_none.uvproj b/demos/device/device_os_none/device_os_none.uvproj index d62debcfd..a27ec6db4 100644 --- a/demos/device/device_os_none/device_os_none.uvproj +++ b/demos/device/device_os_none/device_os_none.uvproj @@ -2037,9 +2037,9 @@ 0 1 1 - 4096 + 4099 - BIN\UL2CM3.DLL + Segger\JL2CM3.dll "" () @@ -3371,46 +3371,6 @@ pca9532.c 1 ..\..\bsp\boards\embedded_artists\oem_base_board\pca9532.c - - - 2 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 11 - - - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - - - - - - - - - board_ngx4330.c @@ -3755,18 +3715,18 @@ - Board LPCXpresso11u14 + Board rf1ghznode 0x4 ARM-ADS - LPC11U14/201 + LPC11U37/401 NXP (founded by Philips) - IRAM(0x10000000-0x10000FFF) IROM(0-0x7FFF) CLOCK(12000000) CPUTYPE("Cortex-M0") + IRAM(0x10000000-0x10001FFF) IRAM2(0x20004000-0x200047FF) IROM(0-0x1FFFF) CLOCK(12000000) CPUTYPE("Cortex-M0") "STARTUP\NXP\LPC11Uxx\startup_LPC11Uxx.s" ("NXP LPC11Uxx Startup Code") - UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000) - 5738 + UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_128 -FS00 -FL020000) + 6508 LPC11Uxx.h @@ -3849,12 +3809,12 @@ SARMCM3.DLL - DARMP1.DLL - -pLPC11U14 + DARMCM1.DLL + -pCM0 SARMCM3.DLL - TARMP1.DLL - -pLPC11U14 + TARMCM1.DLL + -pCM0 @@ -3887,7 +3847,7 @@ 1 0 - 1 + 7 @@ -3901,7 +3861,7 @@ - BIN\UL2CM3.DLL + Segger\JL2CM3.dll @@ -3911,9 +3871,9 @@ 0 1 1 - 4096 + 4099 - BIN\UL2CM3.DLL + Segger\JL2CM3.dll "" () @@ -3956,7 +3916,7 @@ 0 0 0 - 0 + 1 0 8 1 @@ -4015,12 +3975,12 @@ 0 0x10000000 - 0x1000 + 0x2000 1 0x0 - 0x8000 + 0x20000 0 @@ -4045,7 +4005,7 @@ 1 0x0 - 0x8000 + 0x20000 1 @@ -4070,7 +4030,7 @@ 0 0x10000000 - 0x1000 + 0x2000 0 diff --git a/demos/device/src/tusb_config.h b/demos/device/src/tusb_config.h index 25b37da72..35f414d5a 100644 --- a/demos/device/src/tusb_config.h +++ b/demos/device/src/tusb_config.h @@ -85,7 +85,7 @@ #define TUSB_CFG_DEVICE_HID_KEYBOARD 1 #define TUSB_CFG_DEVICE_HID_MOUSE 1 #define TUSB_CFG_DEVICE_HID_GENERIC 0 -#define TUSB_CFG_DEVICE_MSC 1 +#define TUSB_CFG_DEVICE_MSC 0 #define TUSB_CFG_DEVICE_CDC 1 //--------------------------------------------------------------------+ @@ -114,7 +114,7 @@ #elif defined __CC_ARM // Compiled with Keil armcc, USBRAM_SECTION is defined in scatter files #if (TUSB_CFG_MCU == MCU_LPC11UXX) || (TUSB_CFG_MCU == MCU_LPC13UXX) - #define TUSB_CFG_ATTR_USBRAM __attribute__ ((section("USBRAM_SECTION"))) + #define TUSB_CFG_ATTR_USBRAM __attribute__ ((section("USBRAM_SECTION"))) // TODO Keil linker file #elif (TUSB_CFG_MCU == MCU_LPC43XX) #define TUSB_CFG_ATTR_USBRAM // Use keil tool configure to have AHB SRAM as default memory #elif (TUSB_CFG_MCU == MCU_LPC175X_6X) @@ -129,6 +129,8 @@ #define TUSB_CFG_ATTR_USBRAM _Pragma("location=\".ahb_sram1\"") #elif (TUSB_CFG_MCU == MCU_LPC175X_6X) #define TUSB_CFG_ATTR_USBRAM + #elif (TUSB_CFG_MCU == MCU_LPC11UXX) + #define TUSB_CFG_ATTR_USBRAM _Pragma("location=\"USB_PACKET_MEMORY\"") #endif #else diff --git a/tinyusb/device/dcd_lpc_11uxx_13uxx.c b/tinyusb/device/dcd_lpc_11uxx_13uxx.c index 0b2e539fb..d87c80ad2 100644 --- a/tinyusb/device/dcd_lpc_11uxx_13uxx.c +++ b/tinyusb/device/dcd_lpc_11uxx_13uxx.c @@ -362,7 +362,7 @@ void dcd_pipe_control_stall(uint8_t coreid) dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1; } -tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length, bool int_on_complete) +tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete) { (void) coreid; @@ -518,7 +518,7 @@ static void queue_xfer_in_next_td(uint8_t ep_id) dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available } -tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes) +tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes) { ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring @@ -529,7 +529,7 @@ tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint return TUSB_ERROR_NONE; } -tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void* buffer, uint16_t total_bytes, bool int_on_complete) +tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete) { if( dcd_pipe_is_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) ) { // save this transfer data to next td if pipe is busy or already been stalled