diff --git a/hw/bsp/mcb1800/board.mk b/hw/bsp/mcb1800/board.mk new file mode 100644 index 000000000..7fdcc077a --- /dev/null +++ b/hw/bsp/mcb1800/board.mk @@ -0,0 +1,39 @@ +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m3 \ + -nostdlib \ + -DCORE_M3 \ + -DCFG_TUSB_MCU=OPT_MCU_LPC18XX \ + -D__USE_LPCOPEN + +# All source paths should be relative to the top level. +LD_FILE = hw/bsp/mcb1800/lpc1857.ld + +# TODO remove later +SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c + +SRC_C += \ + hw/mcu/nxp/lpcopen/lpc_chip_18xx/src/chip_18xx_43xx.c \ + hw/mcu/nxp/lpcopen/lpc_chip_18xx/src/clock_18xx_43xx.c \ + hw/mcu/nxp/lpcopen/lpc_chip_18xx/src/gpio_18xx_43xx.c \ + hw/mcu/nxp/lpcopen/lpc_chip_18xx/src/sysinit_18xx_43xx.c \ + hw/mcu/nxp/lpcopen/lpc_chip_18xx/src/uart_18xx_43xx.c + +INC += \ + $(TOP)/hw/mcu/nxp/lpcopen/lpc_chip_18xx/inc \ + $(TOP)/hw/mcu/nxp/lpcopen/lpc_chip_18xx/inc/config_18xx + +# For TinyUSB port source +VENDOR = nxp +CHIP_FAMILY = lpc18_43 + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM3 + +# For flash-jlink target +JLINK_DEVICE = LPC1857 +JLINK_IF = swd + +# flash using jlink +flash: flash-jlink diff --git a/hw/bsp/mcb1800/board_mcb1800.c b/hw/bsp/mcb1800/board_mcb1800.c index 85fcc2bfb..db3b84d9b 100644 --- a/hw/bsp/mcb1800/board_mcb1800.c +++ b/hw/bsp/mcb1800/board_mcb1800.c @@ -30,24 +30,28 @@ #define LED_PORT 6 #define LED_PIN 24 +#define BUTTON_PORT 4 +#define BUTTON_PIN 0 + + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ /* System configuration variables used by chip driver */ -const uint32_t ExtRateIn = 0; const uint32_t OscRateIn = 12000000; +const uint32_t ExtRateIn = 0; static const PINMUX_GRP_T pinmuxing[] = { /* Board LEDs */ {0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, - {0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, - {0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, - {0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, - {0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, - {0x9, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, - {0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, - {0x9, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN)}, + {0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN)}, + {0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN)}, + {0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN)}, + {0x9, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN)}, + {0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN)}, + {0x9, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN)}, /* I2S */ {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)}, @@ -67,10 +71,6 @@ static const PINMUX_GRP_T pinclockmuxing[] = {0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, }; - -/*------------------------------------------------------------------*/ -/* BOARD API - *------------------------------------------------------------------*/ // Invoked by startup code void SystemInit(void) { @@ -97,25 +97,13 @@ void board_init(void) Chip_GPIO_Init(LPC_GPIO_PORT); - //------------- LED -------------// - /* Port and bit mapping for LEDs on GPIOs */ - const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4}; - const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14}; + // LED + Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN); - for (uint32_t i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) - { - Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, ledports[i], ledbits[i]); - Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, false); - } + // Button + Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN); #if 0 - //------------- BUTTON -------------// - for(uint8_t i=0; iRESET_CTRL0 @ 0x40053100 + // LPC_RGU->RESET_CTRL1 @ 0x40053104 + // Note that we do not use the CMSIS register access mechanism, + // as there is no guarantee that the project has been configured + // to use CMSIS. + + // Write to LPC_RGU->RESET_CTRL0 + *(RESET_CONTROL+0) = 0x10DF0000; + // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST| + // USB1_RST|USB0_RST|LCD_RST + + // Write to LPC_RGU->RESET_CTRL1 + *(RESET_CONTROL+1) = 0x00DFF7FF; + // CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST| + // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST| + // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST| + // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST + + // Clear all pending interrupts in the NVIC + volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280; + unsigned int irqpendloop; + for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) { + *(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF; + } + + // Reenable interrupts + __asm volatile ("cpsie i"); + // equivalent to CMSIS '__enable_irq()' function + +#endif // ifndef DONT_RESET_ON_RESTART +// ************************************************************* + + +#if defined (__USE_LPCOPEN) + SystemInit(); +#endif + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + // ****************************** + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + + // Note that we do not use the CMSIS register access mechanism, + // as there is no guarantee that the project has been configured + // to use CMSIS. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + // CMSIS : SCB->VTOR =
+ *pSCB_VTOR = (unsigned int)g_pfnVectors; + } + +#if defined (__USE_CMSIS) + SystemInit(); +#endif + +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main() ; +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void NMI_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void HardFault_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void MemManage_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void BusFault_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void UsageFault_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void SVC_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void DebugMon_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void PendSV_Handler(void) { + while (1) { + } +} +__attribute__ ((section(".after_vectors"))) +void SysTick_Handler(void) { + while (1) { + } +} + +//***************************************************************************** +// +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +// +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void IntDefaultHandler(void) { + while (1) { + } +} + + + + + + diff --git a/hw/bsp/mcb1800/lpc1857.ld b/hw/bsp/mcb1800/lpc1857.ld new file mode 100644 index 000000000..983b41eb0 --- /dev/null +++ b/hw/bsp/mcb1800/lpc1857.ld @@ -0,0 +1,323 @@ +/* + * GENERATED FILE - DO NOT EDIT + * (c) Code Red Technologies Ltd, 2008-2013 + * (c) NXP Semiconductors 2013-2019 + * Generated linker script file for LPC1857 + * Created from linkscript.ldt by FMCreateLinkLibraries + * Using Freemarker v2.3.23 + * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 1:01:52 PM + */ + +MEMORY +{ + /* Define each memory region */ + MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ + RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ + RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ + RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ +} + + /* Define a symbol for the top of each memory region */ + __base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ + __base_Flash = 0x1a000000 ; /* Flash */ + __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ + __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ + __base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ + __base_Flash2 = 0x1b000000 ; /* Flash2 */ + __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ + __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ + __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ + __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ + __base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ + __base_RAM2 = 0x10080000 ; /* RAM2 */ + __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ + __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ + __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ + __base_RAM3 = 0x20000000 ; /* RAM3 */ + __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ + __base_RAM4 = 0x20008000 ; /* RAM4 */ + __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ + __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ + __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ + __base_RAM5 = 0x2000c000 ; /* RAM5 */ + __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ + __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ + +ENTRY(ResetISR) + +SECTIONS +{ + .text_Flash2 : ALIGN(4) + { + FILL(0xff) + *(.text_Flash2*) /* for compatibility with previous releases */ + *(.text_MFlashB512*) /* for compatibility with previous releases */ + *(.text.$Flash2*) + *(.text.$MFlashB512*) + *(.rodata.$Flash2*) + *(.rodata.$MFlashB512*) + } > MFlashB512 + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + __vectors_start__ = ABSOLUTE(.) ; + KEEP(*(.isr_vector)) + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)); + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)); + LONG( SIZEOF(.data_RAM2)); + LONG(LOADADDR(.data_RAM3)); + LONG( ADDR(.data_RAM3)); + LONG( SIZEOF(.data_RAM3)); + LONG(LOADADDR(.data_RAM4)); + LONG( ADDR(.data_RAM4)); + LONG( SIZEOF(.data_RAM4)); + LONG(LOADADDR(.data_RAM5)); + LONG( ADDR(.data_RAM5)); + LONG( SIZEOF(.data_RAM5)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + LONG( ADDR(.bss_RAM3)); + LONG( SIZEOF(.bss_RAM3)); + LONG( ADDR(.bss_RAM4)); + LONG( SIZEOF(.bss_RAM4)); + LONG( ADDR(.bss_RAM5)); + LONG( SIZEOF(.bss_RAM5)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + *(.after_vectors*) + + } > MFlashA512 + + .text : ALIGN(4) + { + *(.text*) + *(.rodata .rodata.* .constdata .constdata.*) + . = ALIGN(4); + } > MFlashA512 + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > MFlashA512 + + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > MFlashA512 + __exidx_end = .; + + _etext = .; + + /* DATA section for RamLoc40 */ + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM2 = .) ; + *(.ramfunc.$RAM2) + *(.ramfunc.$RamLoc40) + *(.data.$RAM2*) + *(.data.$RamLoc40*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM2 = .) ; + } > RamLoc40 AT>MFlashA512 + /* DATA section for RamAHB32 */ + + .data_RAM3 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM3 = .) ; + *(.ramfunc.$RAM3) + *(.ramfunc.$RamAHB32) + *(.data.$RAM3*) + *(.data.$RamAHB32*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM3 = .) ; + } > RamAHB32 AT>MFlashA512 + /* DATA section for RamAHB16 */ + + .data_RAM4 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM4 = .) ; + *(.ramfunc.$RAM4) + *(.ramfunc.$RamAHB16) + *(.data.$RAM4*) + *(.data.$RamAHB16*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM4 = .) ; + } > RamAHB16 AT>MFlashA512 + /* DATA section for RamAHB_ETB16 */ + + .data_RAM5 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM5 = .) ; + *(.ramfunc.$RAM5) + *(.ramfunc.$RamAHB_ETB16) + *(.data.$RAM5*) + *(.data.$RamAHB_ETB16*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM5 = .) ; + } > RamAHB_ETB16 AT>MFlashA512 + /* MAIN DATA SECTION */ + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4) ; + _end_uninit_RESERVED = .; + } > RamLoc32 + + /* Main DATA section (RamLoc32) */ + .data : ALIGN(4) + { + FILL(0xff) + _data = . ; + *(vtable) + *(.ramfunc*) + *(.data*) + . = ALIGN(4) ; + _edata = . ; + } > RamLoc32 AT>MFlashA512 + + /* BSS section for RamLoc40 */ + .bss_RAM2 : ALIGN(4) + { + PROVIDE(__start_bss_RAM2 = .) ; + *(.bss.$RAM2*) + *(.bss.$RamLoc40*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM2 = .) ; + } > RamLoc40 + + /* BSS section for RamAHB32 */ + .bss_RAM3 : ALIGN(4) + { + PROVIDE(__start_bss_RAM3 = .) ; + *(.bss.$RAM3*) + *(.bss.$RamAHB32*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM3 = .) ; + } > RamAHB32 + + /* BSS section for RamAHB16 */ + .bss_RAM4 : ALIGN(4) + { + PROVIDE(__start_bss_RAM4 = .) ; + *(.bss.$RAM4*) + *(.bss.$RamAHB16*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM4 = .) ; + } > RamAHB16 + + /* BSS section for RamAHB_ETB16 */ + .bss_RAM5 : ALIGN(4) + { + PROVIDE(__start_bss_RAM5 = .) ; + *(.bss.$RAM5*) + *(.bss.$RamAHB_ETB16*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM5 = .) ; + } > RamAHB_ETB16 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + } > RamLoc32 + + /* NOINIT section for RamLoc40 */ + .noinit_RAM2 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM2*) + *(.noinit.$RamLoc40*) + . = ALIGN(4) ; + } > RamLoc40 + + /* NOINIT section for RamAHB32 */ + .noinit_RAM3 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM3*) + *(.noinit.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 + + /* NOINIT section for RamAHB16 */ + .noinit_RAM4 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM4*) + *(.noinit.$RamAHB16*) + . = ALIGN(4) ; + } > RamAHB16 + + /* NOINIT section for RamAHB_ETB16 */ + .noinit_RAM5 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM5*) + *(.noinit.$RamAHB_ETB16*) + . = ALIGN(4) ; + } > RamAHB_ETB16 + + /* DEFAULT NOINIT SECTION */ + .noinit (NOLOAD): ALIGN(4) + { + _noinit = .; + *(.noinit*) + . = ALIGN(4) ; + _end_noinit = .; + } > RamLoc32 + PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); + PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); + + /* ## Create checksum value (used in startup) ## */ + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ + ) ); + + /* Provide basic symbols giving location and size of main text + * block, including initial values of RW data sections. Note that + * these will need extending to give a complete picture with + * complex images (e.g multiple Flash banks). + */ + _image_start = LOADADDR(.text); + _image_end = LOADADDR(.data) + SIZEOF(.data); + _image_size = _image_end - _image_start; +} \ No newline at end of file