From a3e50242b9239e1fc0c10d15651222fb3ae3f6d1 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 17:07:28 +0700 Subject: [PATCH 01/61] add dcd_esp32s2 skip esp32s2_saola for make build since idf use cmake --- examples/device/cdc_msc_freertos/src/main.c | 17 +- examples/rules.mk | 4 +- src/portable/espressif/esp32s2/dcd_esp32s2.c | 749 +++++++++++++++++++ tools/build_all.py | 3 +- 4 files changed, 768 insertions(+), 5 deletions(-) create mode 100644 src/portable/espressif/esp32s2/dcd_esp32s2.c diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 704d0803b..514ffa724 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -56,12 +56,12 @@ StaticTimer_t static_blink; TimerHandle_t blink_tm; // static task for usbd -#define USBD_STACK_SIZE 150 +#define USBD_STACK_SIZE (3*(configMINIMAL_STACK_SIZE/2)) StackType_t stack_usbd[USBD_STACK_SIZE]; StaticTask_t static_task_usbd; // static task for cdc -#define CDC_STACK_SZIE 128 +#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE StackType_t stack_cdc[CDC_STACK_SZIE]; StaticTask_t static_task_cdc; @@ -71,6 +71,11 @@ void usb_device_task(void* param); void cdc_task(void* params); /*------------- MAIN -------------*/ +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 +// ESP32S2 entry function is app_main() +#define main app_main +#endif + int main(void) { board_init(); @@ -89,8 +94,16 @@ int main(void) (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, stack_cdc, &static_task_cdc); #endif +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 + // skip starting scheduler for ESP32 S2 (already started) + while(1) + { + vTaskSuspend(NULL); + } +#else vTaskStartScheduler(); NVIC_SystemReset(); +#endif return 0; } diff --git a/examples/rules.mk b/examples/rules.mk index 0343391cb..55c70af4b 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -15,14 +15,14 @@ SRC_C += \ src/common/tusb_fifo.c \ src/device/usbd.c \ src/device/usbd_control.c \ - src/class/msc/msc_device.c \ src/class/cdc/cdc_device.c \ src/class/dfu/dfu_rt_device.c \ src/class/hid/hid_device.c \ src/class/midi/midi_device.c \ + src/class/msc/msc_device.c \ + src/class/net/net_device.c \ src/class/usbtmc/usbtmc_device.c \ src/class/vendor/vendor_device.c \ - src/class/net/net_device.c \ src/portable/$(VENDOR)/$(CHIP_FAMILY)/dcd_$(CHIP_FAMILY).c # TinyUSB stack include diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c new file mode 100644 index 000000000..e4e8e30fe --- /dev/null +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -0,0 +1,749 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Additions Copyright (c) 2020, Espressif Systems (Shanghai) Co. Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +// Espressif +#include "driver/periph_ctrl.h" +#include "freertos/xtensa_api.h" +#include "esp_intr_alloc.h" +#include "esp_log.h" +#include "esp32s2/rom/gpio.h" +#include "soc/dport_reg.h" +#include "soc/gpio_sig_map.h" +#include "soc/usb_periph.h" +#include "tusb_config.h" +// TinyUSB +#include "tusb_option.h" +//#include "descriptors_control.h" +#include "device/dcd.h" + + +#define USB_EP_DIRECTIONS 2 +#define USB_MAX_EP_NUM 16 + +typedef struct { + uint8_t *buffer; + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; +} xfer_ctl_t; + +static const char *TAG = "TUSB:DCD"; +static intr_handle_t usb_ih; +static volatile TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6]; +static uint8_t s_setup_phase = 0; /* 00 - got setup, + 01 - got done setup, + 02 - setup cmd sent*/ + +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +static xfer_ctl_t xfer_status[USB_MAX_EP_NUM][USB_EP_DIRECTIONS]; + +static inline void readyfor1setup_pkg(int ep_num) +{ + USB0.out_ep_reg[ep_num].doeptsiz |= (1 << USB_SUPCNT0_S); // doeptsiz 29:30 will decremented on every setup received +} + +// Setup the control endpoint 0. +static void bus_reset(void) +{ + + for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) { + USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK + } + + USB0.dcfg &= ~USB_DEVADDR_M; // reset address + + // Peripheral FIFO architecture + // + // --------------- 320 ( 1280 bytes ) + // | IN FIFO 3 | + // --------------- y + x + 16 + GRXFSIZ + // | IN FIFO 2 | + // --------------- x + 16 + GRXFSIZ + // | IN FIFO 1 | + // --------------- 16 + GRXFSIZ + // | IN FIFO 0 | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // FIFO sizes are set up by the following rules (each word 32-bits): + // All EP OUT shared a unique OUT FIFO which uses (based on page 1354 of Rev 17 of reference manual): + // * 10 locations in hardware for setup packets + setup control words + // (up to 3 setup packets). + // * 2 locations for OUT endpoint control words. + // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) + // * 1 location for global NAK (not required/used here). + // + // It is recommended to allocate 2 times the largest packet size, therefore + // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50 + USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10, + USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo + USB0.grxfsiz = 50; + + USB0.gintmsk = USB_MODEMISMSK_M | + USB_SOFMSK_M | + USB_RXFLVIMSK_M | + USB_ERLYSUSPMSK_M | + USB_USBSUSPMSK_M | + USB_USBRSTMSK_M | + USB_ENUMDONEMSK_M | + USB_IEPINTMSK_M | + USB_OEPINTMSK_M | + USB_RESETDETMSK_M | + USB_DISCONNINTMSK_M; + + USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; + USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; + USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M; + + USB0.gnptxfsiz = 16 << USB_NPTXFDEP_S; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + + readyfor1setup_pkg(0); +} + +static void enum_done_processing(void) +{ + + ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + // On current silicon on the Full Speed core, speed is fixed to Full Speed. + // However, keep for debugging and in case Low Speed is ever supported. + uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); + + // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL + if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz) + USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V; // 64 bytes + USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + } else { + USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V; // 8 bytes + USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall + xfer_status[0][TUSB_DIR_OUT].max_size = 8; + xfer_status[0][TUSB_DIR_IN].max_size = 8; + } + + USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask +} + + + + +/*------------------------------------------------------------------*/ +/* Controller API + *------------------------------------------------------------------*/ +void dcd_init(uint8_t rhport) +{ + ESP_LOGV(TAG, "DCD init - Start"); + + // A. Disconnect + ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up"); + USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect + + // B. Programming DCFG + /* If USB host misbehaves during status portion of control xfer + (non zero-length packet), send STALL back and discard. Full speed. */ + USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL + (3 << 0); // dev speed: fullspeed 1.1 on 48 mhz // TODO no value in usb_reg.h (IDF-1476) + + USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON + USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode + + USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA // needed for beta chip only + //C. chip 7.2.2 hack + ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack"); + USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value + ets_delay_us(20); + USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable + ets_delay_us(20); +#endif + + // C. Setting SNAKs, then connect + for (int n = 0; n < USB_OUT_EP_NUM; n++) { + USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK + } + ESP_LOGV(TAG, "DCD init - Soft CONNECT"); + USB0.dctl &= ~USB_SFTDISCON_M; // Connect + + // D. Interruption masking + USB0.gintmsk = 0; //mask all + USB0.gotgint = ~0U; //clear OTG ints + USB0.gintsts = ~0U; //clear pending ints + USB0.gintmsk = USB_MODEMISMSK_M | + USB_SOFMSK_M | + USB_RXFLVIMSK_M | + USB_ERLYSUSPMSK_M | + USB_USBSUSPMSK_M | + USB_USBRSTMSK_M | + USB_ENUMDONEMSK_M | + USB_RESETDETMSK_M | + USB_DISCONNINTMSK_M; + ets_delay_us(100); +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr); + USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S); + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); +} + +void dcd_set_config(uint8_t rhport, uint8_t config_num) +{ + (void)rhport; + (void)config_num; + // Nothing to do +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; +} + +/*------------------------------------------------------------------*/ +/* DCD Endpoint port + *------------------------------------------------------------------*/ + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) +{ + + ESP_LOGV(TAG, "DCD endpoint opened"); + (void)rhport; + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + // Unsupported endpoint numbers/size. + if ((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 3)) { + return false; + } + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = desc_edpt->wMaxPacketSize.size; + + if (dir == TUSB_DIR_OUT) { + out_ep[epnum].doepctl |= USB_USBACTEP0_M | + desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S | + desc_edpt->wMaxPacketSize.size << USB_MPS0_S; + USB0.daintmsk |= (1 << (16 + epnum)); + } else { + // Peripheral FIFO architecture (Rev18 RM 29.11) + // + // --------------- 320 ( 1280 bytes ) + // | IN FIFO 3 | + // --------------- y + x + 16 + GRXFSIZ + // | IN FIFO 2 | + // --------------- x + 16 + GRXFSIZ + // | IN FIFO 1 | + // --------------- 16 + GRXFSIZ + // | IN FIFO 0 | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (312-50-16) / 3 = 82 ~ 80 + in_ep[epnum].diepctl |= USB_D_USBACTEP1_M | + (epnum - 1) << USB_D_TXFNUM1_S | + desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | + desc_edpt->wMaxPacketSize.size << 0; + USB0.daintmsk |= (1 << (0 + epnum)); + + // Both TXFD and TXSA are in unit of 32-bit words + uint16_t const fifo_size = 80; + uint32_t const fifo_offset = (USB0.grxfsiz & USB_NPTXFDEP_V) + 16 + fifo_size * (epnum - 1); + USB0.dieptxf[epnum - 1] = (80 << USB_NPTXFDEP_S) | fifo_offset; + } + return true; +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint8_t short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if (short_packet_size > 0 || (total_bytes == 0)) { + num_packets++; + } + + ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i", + epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"), + num_packets, total_bytes); + + // IN and OUT endpoint xfers are interrupt-driven, we just schedule them + // here. + if (dir == TUSB_DIR_IN) { + // A full IN transfer (multiple packets, possibly) triggers XFRC. + int bytes2fifo_left = total_bytes; + uint32_t val; // 32 bit val from 4 buff addresses + + USB0.in_ep_reg[epnum].diepint = ~0U; // clear all ints + USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; + USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK + while (bytes2fifo_left > 0) { // TODO move it to ep_in_handle (IDF-1475) + /* ATTENTION! In cases when CFG_TUD_ENDOINT0_SIZE, CFG_TUD_CDC_EPSIZE, CFG_TUD_MIDI_EPSIZE or + CFG_TUD_MSC_BUFSIZE < 4 next line can be a cause of an error.*/ + val = (*(buffer + 3) << 24) | + (*(buffer + 2) << 16) | + (*(buffer + 1) << 8) | + (*(buffer + 0) << 0); + ESP_LOGV(TAG, "Transfer 0x%08x -> FIFO%d", val, epnum); + USB0.fifo[epnum][0] = val; //copy and next buffer address + buffer += 4; + bytes2fifo_left -= 4; + } + // USB0.dtknqr4_fifoemptymsk |= (1 << epnum); + } else { + // Each complete packet for OUT xfers triggers XFRC. + USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M | + ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; + } + return true; +} + +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) { + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M); + } else { + // Stop transmitting packets and NAK IN xfers. + in_ep[epnum].diepctl |= USB_DI_SNAK1_M; + while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) + ; + + // Disable the endpoint. Note that both SNAK and STALL are set here. + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | + USB_D_EPDIS1_M); + while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) + ; + in_ep[epnum].diepint = USB_D_EPDISBLD0_M; + } + + // Flush the FIFO, and wait until we have confirmed it cleared. + USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S); + USB0.grstctl |= USB_TXFFLSH_M; + while ((USB0.grstctl & USB_TXFFLSH_M) != 0) + ; + } else { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) { + out_ep[epnum].doepctl |= USB_STALL0_M; + } else { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + USB0.dctl |= USB_SGOUTNAK_M; + while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) + ; + + // Ditto here- disable the endpoint. Note that only STALL and not SNAK + // is set here. + out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M); + while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) + ; + out_ep[epnum].doepint = USB_EPDISBLD0_M; + + // Allow other OUT endpoints to keep receiving. + USB0.dctl |= USB_CGOUTNAK_M; + } + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) { + in_ep[epnum].diepctl &= ~USB_D_STALL1_M; + + uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S; + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + if (eptype == 2 || eptype == 3) { + in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M; + } + } else { + out_ep[epnum].doepctl &= ~USB_STALL1_M; + + uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S; + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + if (eptype == 2 || eptype == 3) { + out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M; + } + } +} + +/*------------------------------------------------------------------*/ + +static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size) +{ + ESP_EARLY_LOGV(TAG, "USB - receive_packet"); + uint32_t *rx_fifo = USB0.fifo[0]; + + // See above TODO + // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos; + // xfer->queued_len = xfer->total_len - remaining; + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if (remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + uint8_t to_recv_rem = to_recv_size % 4; + uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem; + + // Do not assume xfer buffer is aligned. + uint8_t *base = (xfer->buffer + xfer->queued_len); + + // This for loop always runs at least once- skip if less than 4 bytes + // to collect. + if (to_recv_size >= 4) { + for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) { + uint32_t tmp = (*rx_fifo); + base[i] = tmp & 0x000000FF; + base[i + 1] = (tmp & 0x0000FF00) >> 8; + base[i + 2] = (tmp & 0x00FF0000) >> 16; + base[i + 3] = (tmp & 0xFF000000) >> 24; + } + } + + // Do not read invalid bytes from RX FIFO. + if (to_recv_rem != 0) { + uint32_t tmp = (*rx_fifo); + uint8_t *last_32b_bound = base + to_recv_size_aligned; + + last_32b_bound[0] = tmp & 0x000000FF; + if (to_recv_rem > 1) { + last_32b_bound[1] = (tmp & 0x0000FF00) >> 8; + } + if (to_recv_rem > 2) { + last_32b_bound[2] = (tmp & 0x00FF0000) >> 16; + } + } + + xfer->queued_len += xfer_size; + + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); +} + +static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num) +{ + + ESP_EARLY_LOGV(TAG, "USB - transmit_packet"); + uint32_t *tx_fifo = USB0.fifo[0]; + + uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S; + xfer->queued_len = xfer->total_len - remaining; + + uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining; + uint8_t to_xfer_rem = to_xfer_size % 4; + uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem; + + // Buffer might not be aligned to 32b, so we need to force alignment + // by copying to a temp var. + uint8_t *base = (xfer->buffer + xfer->queued_len); + + // This for loop always runs at least once- skip if less than 4 bytes + // to send off. + if (to_xfer_size >= 4) { + for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) { + uint32_t tmp = base[i] | (base[i + 1] << 8) | + (base[i + 2] << 16) | (base[i + 3] << 24); + (*tx_fifo) = tmp; + } + } + + // Do not read beyond end of buffer if not divisible by 4. + if (to_xfer_rem != 0) { + uint32_t tmp = 0; + uint8_t *last_32b_bound = base + to_xfer_size_aligned; + + tmp |= last_32b_bound[0]; + if (to_xfer_rem > 1) { + tmp |= (last_32b_bound[1] << 8); + } + if (to_xfer_rem > 2) { + tmp |= (last_32b_bound[2] << 16); + } + + (*tx_fifo) = tmp; + } +} + +static void read_rx_fifo(void) +{ + // Pop control word off FIFO (completed xfers will have 2 control words, + // we only pop one ctl word each interrupt). + volatile uint32_t ctl_word = USB0.grxstsp; + uint8_t pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; + uint8_t epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S; + uint16_t bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S; + switch (pktsts) { + case 0x01: // Global OUT NAK (Interrupt) + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); + break; + case 0x02: { // Out packet recvd + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet"); + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + receive_packet(xfer, bcnt); + } + break; + case 0x03: // Out packet done (Interrupt) + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done"); + break; + case 0x04: // Setup packet done (Interrupt) + if (s_setup_phase == 0) { // only if setup is started + s_setup_phase = 1; + ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); + } + + break; + case 0x06: { // Setup packet recvd + s_setup_phase = 0; + ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 0"); // new setup process + // For some reason, it's possible to get a mismatch between + // how many setup packets were received versus the location + // of the Setup packet done word. This leads to situations + // where stale setup packets are in the RX FIFO that were received + // after the core loaded the Setup packet done word. Workaround by + // only accepting one setup packet at a time for now. + _setup_packet[0] = (USB0.grxstsp); + _setup_packet[1] = (USB0.grxstsp); + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", + _setup_packet[0], _setup_packet[1]); + } + break; + default: // Invalid, do something here, like breakpoint? + break; + } +} + +static void handle_epout_ints(void) +{ + // GINTSTS will be cleared with DAINT == 0 + // DAINT for a given EP clears when DOEPINTx is cleared. + // DOEPINT will be cleared when DAINT's out bits are cleared. + for (int n = 0; n < USB_OUT_EP_NUM; n++) { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + if (USB0.daint & (1 << (16 + n))) { + // SETUP packet Setup Phase done. + if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) { + USB0.out_ep_reg[n].doepint |= USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear + if (s_setup_phase == 1) { // only if setup is done, but not handled + s_setup_phase = 2; + ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 2"); // sending to a handling queue + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - Setup Phase done (irq-s 0x%08x)", USB0.out_ep_reg[n].doepint); + dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); + } + readyfor1setup_pkg(0); + } + + // OUT XFER complete (single packet).q + if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) { + + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)"); + USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M; + + // Transfer complete if short packet or total len is transferred + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } else { + // Schedule another packet to be received. + USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M | + ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M; + } + } + } + } +} + +static void handle_epin_ints(void) +{ + + // GINTSTS will be cleared with DAINT == 0 + // DAINT for a given EP clears when DIEPINTx is cleared. + // IEPINT will be cleared when DAINT's out bits are cleared. + for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) { + xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN]; + + if (USB0.daint & (1 << (0 + n))) { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n); + // IN XFER complete (entire xfer). + if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!"); + USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M; + // USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive. + dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + + // XFER FIFO empty + if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!"); + USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M; + transmit_packet(xfer, &USB0.in_ep_reg[n], n); + } + } + } +} + + +static void dcd_int_handler(void) +{ + uint32_t int_status = USB0.gintsts; + uint32_t int_msk = USB0.gintmsk; + + if (int_status & USB_DISCONNINT_M) { + ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); + USB0.gintsts = USB_DISCONNINT_M; + } + + if (int_status & USB_USBRST_M) { + + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); + USB0.gintsts = USB_USBRST_M; + bus_reset(); + } + + if (int_status & USB_RESETDET_M) { + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); + USB0.gintsts = USB_RESETDET_M; + bus_reset(); + } + + if (int_status & USB_ENUMDONE_M) { + // ENUMDNE detects speed of the link. For full-speed, we + // always expect the same value. This interrupt is considered + // the end of reset. + USB0.gintsts = USB_ENUMDONE_M; + enum_done_processing(); + dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); + } + + if (int_status & USB_SOF_M) { + USB0.gintsts = USB_SOF_M; + dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually + } + + if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) { + ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); + read_rx_fifo(); + } + + // OUT endpoint interrupt handling. + if (int_status & USB_OEPINT_M) { + ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); + handle_epout_ints(); + } + + // IN endpoint interrupt handling. + if (int_status & USB_IEPINT_M) { + ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); + handle_epin_ints(); + } + + // Without handling + USB0.gintsts |= USB_CURMOD_INT_M | + USB_MODEMIS_M | + USB_OTGINT_M | + USB_NPTXFEMP_M | + USB_GINNAKEFF_M | + USB_GOUTNAKEFF | + USB_ERLYSUSP_M | + USB_USBSUSP_M | + USB_ISOOUTDROP_M | + USB_EOPF_M | + USB_EPMIS_M | + USB_INCOMPISOIN_M | + USB_INCOMPIP_M | + USB_FETSUSP_M | + USB_PTXFEMP_M; +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; + esp_intr_free(usb_ih); +} diff --git a/tools/build_all.py b/tools/build_all.py index 0437bcaac..65f41422f 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -27,7 +27,8 @@ if len(sys.argv) > 2: all_boards.append(sys.argv[2]) else: for entry in os.scandir("hw/bsp"): - if entry.is_dir(): + # Skip board without board.mk e.g esp32s2 + if entry.is_dir() and os.path.exists(entry.path + "/board.mk"): all_boards.append(entry.name) all_boards.sort() From 19f977a27489fb54c3bf1e392826fa76bec49d5f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 20:24:46 +0700 Subject: [PATCH 02/61] add esp32s2 saola bsp update cdc_msc_freertos main.c to work with esp32s2 add CMake file --- .../device/cdc_msc_freertos/CMakeLists.txt | 10 + examples/device/cdc_msc_freertos/sdkconfig | 1060 +++++++++++++++++ .../cdc_msc_freertos/src/CMakeLists.txt | 36 + examples/device/cdc_msc_freertos/src/main.c | 27 +- hw/bsp/esp32s2_saola/esp32s2_saola.c | 77 ++ 5 files changed, 1194 insertions(+), 16 deletions(-) create mode 100644 examples/device/cdc_msc_freertos/CMakeLists.txt create mode 100644 examples/device/cdc_msc_freertos/sdkconfig create mode 100644 examples/device/cdc_msc_freertos/src/CMakeLists.txt create mode 100644 hw/bsp/esp32s2_saola/esp32s2_saola.c diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt new file mode 100644 index 000000000..6afab304f --- /dev/null +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -0,0 +1,10 @@ +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +# example src directory +set(EXTRA_COMPONENT_DIRS "src") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(blink) diff --git a/examples/device/cdc_msc_freertos/sdkconfig b/examples/device/cdc_msc_freertos/sdkconfig new file mode 100644 index 000000000..feb6d6454 --- /dev/null +++ b/examples/device/cdc_msc_freertos/sdkconfig @@ -0,0 +1,1060 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET="esp32s2" +CONFIG_IDF_TARGET_ESP32S2=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0002 + +# +# SDK tool configuration +# +CONFIG_SDK_TOOLPREFIX="xtensa-esp32s2-elf-" +# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set +# end of SDK tool configuration + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# end of Build type + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +# +# Bootloader config +# +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 +# CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +# end of Security features + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y +# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_TRAX is not set +CONFIG_APPTRACE_DEST_NONE=y +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 +CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 +CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 +CONFIG_BT_RESERVE_DRAM=0 + +# +# CoAP Configuration +# +CONFIG_COAP_MBEDTLS_PSK=y +# CONFIG_COAP_MBEDTLS_PKI is not set +# CONFIG_COAP_MBEDTLS_DEBUG is not set +CONFIG_COAP_LOG_DEFAULT_LEVEL=0 +# end of CoAP Configuration + +# +# Driver configurations +# + +# +# ADC configuration +# +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC_DISABLE_DAC=y +# end of ADC configuration + +# +# SPI configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI configuration + +# +# UART configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART configuration +# end of Driver configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# end of ESP-TLS + +# +# ESP32S2-specific +# +# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set +# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y +# CONFIG_ESP32S2_DATA_CACHE_0KB is not set +CONFIG_ESP32S2_DATA_CACHE_8KB=y +# CONFIG_ESP32S2_DATA_CACHE_16KB is not set +# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set +# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set +# end of Cache config + +# CONFIG_ESP32S2_SPIRAM_SUPPORT is not set +# CONFIG_ESP32S2_TRAX is not set +CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2 +# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set +CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32S2_DEBUG_OCDAWARE=y +# CONFIG_ESP32S2_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S2_BROWNOUT_DET=y +CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP32S2_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 +# CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE is not set +# CONFIG_ESP32S2_NO_BLOBS is not set +# end of ESP32S2-specific + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# end of Power Management + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_TX_GPIO=43 +CONFIG_ESP_CONSOLE_UART_RX_GPIO=44 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_TASK_WDT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_USE_OPENETH is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y +# end of ESP NETIF Adapter + +# +# ESP System Settings +# +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +# end of ESP System Settings + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE is not set +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +# CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE is not set +# end of Wi-Fi + +# +# PHY +# +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# end of PHY + +# +# Core dump +# +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# end of FAT Filesystem support + +# +# Modbus configuration +# +CONFIG_FMB_COMM_MODE_RTU_EN=y +CONFIG_FMB_COMM_MODE_ASCII_EN=y +CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_FMB_QUEUE_LENGTH=20 +CONFIG_FMB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_FMB_SERIAL_BUF_SIZE=256 +CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 +CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 +CONFIG_FMB_SERIAL_TASK_PRIO=10 +# CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT is not set +CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 +CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_FMB_TIMER_PORT_ENABLED=y +CONFIG_FMB_TIMER_GROUP=0 +CONFIG_FMB_TIMER_INDEX=0 +# CONFIG_FMB_TIMER_ISR_IN_IRAM is not set +# end of Modbus configuration + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE=y +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# end of Heap memory debugging + +# +# jsmn +# +# CONFIG_JSMN_PARENT_LINKS is not set +# CONFIG_JSMN_STRICT is not set +# end of jsmn + +# +# libsodium +# +# end of libsodium + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP_FRAG=y +# CONFIG_LWIP_IP_REASSEMBLY is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=6 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set + +# +# ICMP +# +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_ESP_LWIP_ASSERT=y +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DEBUG is not set + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_GCM=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES=y +CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS=y +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MDNS_TASK_PRIORITY=1 +# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_MDNS_TASK_AFFINITY_CPU0=y +CONFIG_MDNS_TASK_AFFINITY=0x0 +CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 +CONFIG_MDNS_TIMER_PERIOD_MS=100 +# end of mDNS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +# end of Newlib + +# +# NVS +# +# end of NVS + +# +# OpenSSL +# +# CONFIG_OPENSSL_DEBUG is not set +# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set +CONFIG_OPENSSL_ASSERT_EXIT=y +# end of OpenSSL + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +# end of Auto-detect flash chips +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TinyUSB +# +# CONFIG_USB_ENABLED is not set + +# +# Descriptor configuration +# +CONFIG_USB_DESC_CUSTOM_VID=0x1234 +CONFIG_USB_DESC_CUSTOM_PID=0x5678 +# end of Descriptor configuration +# end of TinyUSB + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +CONFIG_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +# CONFIG_WPA_DEBUG_PRINT is not set +# end of Supplicant +# end of Component config + +# +# Compatibility options +# +# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set +# end of Compatibility options + +# Deprecated options for backward compatibility +CONFIG_TOOLPREFIX="xtensa-esp32s2-elf-" +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +# CONFIG_MONITOR_BAUD_9600B is not set +# CONFIG_MONITOR_BAUD_57600B is not set +CONFIG_MONITOR_BAUD_115200B=y +# CONFIG_MONITOR_BAUD_230400B is not set +# CONFIG_MONITOR_BAUD_921600B is not set +# CONFIG_MONITOR_BAUD_2MB is not set +# CONFIG_MONITOR_BAUD_OTHER is not set +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 +CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_DISABLE_GCC8_WARNINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_ADC2_DISABLE_DAC=y +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_TX_GPIO=43 +CONFIG_CONSOLE_UART_RX_GPIO=44 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set +CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y +# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP32S2_PANIC_GDBSTUB is not set +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +# CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_L2_TO_L3_COPY is not set +# CONFIG_USE_ONLY_LWIP_SELECT is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +# End of deprecated options diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt new file mode 100644 index 000000000..3d2010ed2 --- /dev/null +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -0,0 +1,36 @@ +# TOP is absolute path to root directory of TinyUSB git repo +set(TOP "../../../..") +get_filename_component(TOP "${TOP}" REALPATH) + +idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c" + INCLUDE_DIRS "." + REQUIRES freertos soc) + +target_compile_options(${COMPONENT_TARGET} PUBLIC + "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" +) + +idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) +target_include_directories(${COMPONENT_TARGET} PUBLIC + "${FREERTOS_ORIG_INCLUDE_PATH}" + "${TOP}/hw" + "${TOP}/src" +) + +target_sources(${COMPONENT_TARGET} PUBLIC + "${TOP}/hw/bsp/esp32s2_saola/esp32s2_saola.c" + "${TOP}/src/tusb.c" + "${TOP}/src/common/tusb_fifo.c" + "${TOP}/src/device/usbd.c" + "${TOP}/src/device/usbd_control.c" + "${TOP}/src/class/cdc/cdc_device.c" + "${TOP}/src/class/dfu/dfu_rt_device.c" + "${TOP}/src/class/hid/hid_device.c" + "${TOP}/src/class/midi/midi_device.c" + "${TOP}/src/class/msc/msc_device.c" + "${TOP}/src/class/net/net_device.c" + "${TOP}/src/class/usbtmc/usbtmc_device.c" + "${TOP}/src/class/vendor/vendor_device.c" + "${TOP}/src/portable/espressif/esp32s2/dcd_esp32s2.c" +) + diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 514ffa724..eb439a90d 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -56,12 +56,12 @@ StaticTimer_t static_blink; TimerHandle_t blink_tm; // static task for usbd -#define USBD_STACK_SIZE (3*(configMINIMAL_STACK_SIZE/2)) +#define USBD_STACK_SIZE (2*configMINIMAL_STACK_SIZE) StackType_t stack_usbd[USBD_STACK_SIZE]; StaticTask_t static_task_usbd; // static task for cdc -#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE +#define CDC_STACK_SZIE (2*configMINIMAL_STACK_SIZE) StackType_t stack_cdc[CDC_STACK_SZIE]; StaticTask_t static_task_cdc; @@ -72,11 +72,10 @@ void cdc_task(void* params); /*------------- MAIN -------------*/ #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 -// ESP32S2 entry function is app_main() -#define main app_main -#endif - +void app_main(void) +#else int main(void) +#endif { board_init(); @@ -91,21 +90,16 @@ int main(void) // Create task #if CFG_TUD_CDC - (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, stack_cdc, &static_task_cdc); + (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-1, stack_cdc, &static_task_cdc); #endif -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 - // skip starting scheduler for ESP32 S2 (already started) - while(1) - { - vTaskSuspend(NULL); - } -#else + // skip starting scheduler (and return) for ESP32-S2 +#if CFG_TUSB_MCU != OPT_MCU_ESP32S2 vTaskStartScheduler(); NVIC_SystemReset(); + return 0; #endif - return 0; } // USB Device Driver task @@ -186,7 +180,8 @@ void cdc_task(void* params) } } - taskYIELD(); + // For ESP32-S2 this delay is essential to allow idle how to run and reset wdt + vTaskDelay(pdMS_TO_TICKS(10)); } } diff --git a/hw/bsp/esp32s2_saola/esp32s2_saola.c b/hw/bsp/esp32s2_saola/esp32s2_saola.c new file mode 100644 index 000000000..06590c684 --- /dev/null +++ b/hw/bsp/esp32s2_saola/esp32s2_saola.c @@ -0,0 +1,77 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "driver/gpio.h" +#include "hal/usb_hal.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +#define LED_PIN 21 + +// Initialize on-board peripherals : led, button, uart and USB +void board_init(void) +{ + // LED + gpio_pad_select_gpio(LED_PIN); + gpio_set_direction(LED_PIN, GPIO_MODE_OUTPUT); + + // USB Controller Hal init + usb_hal_context_t hal = { + .use_external_phy = false // use built-in PHY + }; + usb_hal_init(&hal); +} + +// Turn LED on or off +void board_led_write(bool state) +{ + gpio_set_level(LED_PIN, state); +} + +// Get the current state of button +// a '1' means active (pressed), a '0' means inactive. +uint32_t board_button_read(void) +{ + return 0; +} + +// Get characters from UART +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +// Send characters to UART +int board_uart_write(void const * buf, int len) +{ + (void) buf; (void) len; + return 0; +} + From ff9ceb65d2c5033e80aaa795b508cdff6356b14b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 20:56:46 +0700 Subject: [PATCH 03/61] doc update --- docs/getting_started.md | 6 +++--- docs/porting.md | 4 ++-- examples/readme.md | 16 ++++++++++------ tools/build_all.py | 5 +---- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/docs/getting_started.md b/docs/getting_started.md index 123a9d2ab..588c879f1 100644 --- a/docs/getting_started.md +++ b/docs/getting_started.md @@ -17,11 +17,11 @@ It is relatively simple to incorporate tinyusb to your (existing) project 1. Copy or `git submodule` this repo into your project in a subfolder. Let's say it is *your_project/tinyusb* 2. Add all the .c in the src folder to your project settings (uvproj, ewp, makefile) 3. Add *your_project/tinysb* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h. Or you could simply put the tusb_config.h into the tinyusb folder as well. -4. Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all demo projects). -5. If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to fill out required pointers in tusbd_descriptor_pointers for that stack to work. +4. Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards). +5. If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud_descriptor_** callbacks for that stack to work. 6. Add tusb_init() call to your reset initialization code. 7. Implement all enabled classes's callbacks. -8. If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. Most of the callbacks and functionality are handled and invoke within the call of that task runner. +8. If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoke within the call of that task runner. ~~~{.c} int main(void) diff --git a/docs/porting.md b/docs/porting.md index deb1b9efb..ccafa7999 100644 --- a/docs/porting.md +++ b/docs/porting.md @@ -6,7 +6,7 @@ data transactions on different endpoints. Porting is the process of adding low-l the rest of the common stack. Once the low-level is implemented, it is very easy to add USB support for the microcontroller to other projects, especially those already using TinyUSB such as CircuitPython. -Below are instructions on how to get the cdc_msc_hid device example running on a new microcontroller. Doing so includes adding the common code necessary for other uses while minimizing other extra code. Whenever you see a phrase or word in <> it should be replaced. +Below are instructions on how to get the cdc_msc device example running on a new microcontroller. Doing so includes adding the common code necessary for other uses while minimizing other extra code. Whenever you see a phrase or word in <> it should be replaced. ## Register defs @@ -19,7 +19,7 @@ Once this is done, create a directory in `hw/bsp/` for the spec ## Build Now that those directories are in place, we can start our iteration process to get the example building successfully. To build, run from the root of TinyUSB: -`make -C examples/device/cdc_msc_hid BOARD=` +`make -C examples/device/cdc_msc BOARD=` Unless, you've read ahead, this will fail miserably. Now, lets get it to fail less by updating the files in the board directory. The code in the board's directory is responsible for setting up the microcontroller's clocks and pins so that USB works. TinyUSB itself only operates on the USB peripheral. The board directory also includes information what files are needed to build the example. diff --git a/examples/readme.md b/examples/readme.md index 897931b0e..b661d169f 100644 --- a/examples/readme.md +++ b/examples/readme.md @@ -15,22 +15,26 @@ TinyUSB examples includes external repos aka submodules to provide low-level MCU $ git submodule update --init --recursive ``` -It will takes a bit of time due to the number of supported MCUs, luckily we only need to do this once. +It will takes a bit of time due to the number of supported MCUs, luckily we only need to do this once. Or if you only want to test with a specific mcu, you could only update its driver submodule ## Build -[Here is the list of supported Boards](docs/boards.md) that should work out of the box with provided examples. - -To build example, go to its folder project then type `make BOARD=[our_board] all` e.g +[Here is the list of supported Boards](docs/boards.md) that should work out of the box with provided examples (hopefully). +To build example, first change directory to example folder. + +``` +$ cd examples/device/cdc_msc +``` + +Then compile with `make BOARD=[your_board] all`, for example ``` -$ cd examples/device/cdc_msc_hid $ make BOARD=feather_nrf52840_express all ``` ## Flash -`flash` target will use the on-board debugger (jlink/cmsisdap/stlink/dfu) to flash the binary. We should install those debugger/programmer software in advance. Futhermore, since external jlink can be used with most of the board, there is also `flash-jlink` target for out convenience. +`flash` target will use the on-board debugger (jlink/cmsisdap/stlink/dfu) to flash the binary. We should install those debugger/programmer software in advance. Furthermore, since external jlink can be used with most of the board, there is also `flash-jlink` target for your convenience. ``` $ make BOARD=feather_nrf52840_express flash diff --git a/tools/build_all.py b/tools/build_all.py index 65f41422f..c95f88b79 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -94,10 +94,7 @@ for example in all_examples: if build_result.returncode != 0: print(build_result.stdout.decode("utf-8")) -# FreeRTOS example -# example = 'cdc_msc_hid_freertos' -# board = 'pca10056' -# build_example(example, board) + total_time = time.monotonic() - total_time print(build_separator) From 1c0d7a3577d6555aafbbc00fd83b858f839a5426 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 21:43:23 +0700 Subject: [PATCH 04/61] reduce freertos task stack size to fit small mcu --- examples/device/cdc_msc_freertos/src/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index eb439a90d..f673a7932 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -56,12 +56,12 @@ StaticTimer_t static_blink; TimerHandle_t blink_tm; // static task for usbd -#define USBD_STACK_SIZE (2*configMINIMAL_STACK_SIZE) +#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) StackType_t stack_usbd[USBD_STACK_SIZE]; StaticTask_t static_task_usbd; // static task for cdc -#define CDC_STACK_SZIE (2*configMINIMAL_STACK_SIZE) +#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE StackType_t stack_cdc[CDC_STACK_SZIE]; StaticTask_t static_task_cdc; @@ -90,7 +90,7 @@ int main(void) // Create task #if CFG_TUD_CDC - (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-1, stack_cdc, &static_task_cdc); + (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, stack_cdc, &static_task_cdc); #endif // skip starting scheduler (and return) for ESP32-S2 From f8422b5a48fc812edf41413827d31ebcc956fb53 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 22:55:26 +0700 Subject: [PATCH 05/61] rename project to cdc_msc_freertos --- examples/device/cdc_msc_freertos/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 6afab304f..f2e711944 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -7,4 +7,4 @@ set(EXTRA_COMPONENT_DIRS "src") include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(blink) +project(cdc_msc_freertos) From ec578fa8cb9d3053abc274829616cb30521b1695 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 22:55:44 +0700 Subject: [PATCH 06/61] try adding esp32 to ci --- .github/workflows/esp32s2.yml | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 .github/workflows/esp32s2.yml diff --git a/.github/workflows/esp32s2.yml b/.github/workflows/esp32s2.yml new file mode 100644 index 000000000..0b70c44b6 --- /dev/null +++ b/.github/workflows/esp32s2.yml @@ -0,0 +1,34 @@ +name: Build + +on: [pull_request, push, repository_dispatch] + +jobs: + build: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + example: ['cdc_msc_freertos'] + + steps: + - name: Setup Python + uses: actions/setup-python@v1 + + - name: Install Toolchains + run: | + git clone https://github.com/espressif/esp-idf.git $HOME/esp-idf + cd $HOME/esp-idf + ./install.sh + #echo "::add-path::`echo $HOME/msp430-gcc-*_linux64/bin`" + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + + - name: Checkout Submodules + run: | + git submodule sync --recursive + git submodule update --init --recursive + +# - name: Build +# run: python3 tools/build_all.py ${{ matrix.example }} + From 2824e5c97aedfe46a621d786fb6577f632a0097c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Apr 2020 23:03:57 +0700 Subject: [PATCH 07/61] more ci test --- .github/workflows/esp32s2.yml | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/.github/workflows/esp32s2.yml b/.github/workflows/esp32s2.yml index 0b70c44b6..a3f30c8f8 100644 --- a/.github/workflows/esp32s2.yml +++ b/.github/workflows/esp32s2.yml @@ -1,4 +1,4 @@ -name: Build +name: Build ESP32-S2 on: [pull_request, push, repository_dispatch] @@ -14,7 +14,7 @@ jobs: - name: Setup Python uses: actions/setup-python@v1 - - name: Install Toolchains + - name: Install ESP-IDF run: | git clone https://github.com/espressif/esp-idf.git $HOME/esp-idf cd $HOME/esp-idf @@ -24,11 +24,15 @@ jobs: - name: Checkout TinyUSB uses: actions/checkout@v2 - - name: Checkout Submodules - run: | - git submodule sync --recursive - git submodule update --init --recursive +# - name: Checkout Submodules +# run: | +# git submodule sync --recursive +# git submodule update --init --recursive -# - name: Build -# run: python3 tools/build_all.py ${{ matrix.example }} + - name: Build + run: | + . $HOME/esp-idf/export.sh + cd examples/device/cdc_msc_freertos + idf.py build + #python3 tools/build_all.py ${{ matrix.example }} From 7c33a7127f009c54fa43b94243def846284865af Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 3 Apr 2020 12:08:06 +0700 Subject: [PATCH 08/61] make as wrapper to idf.py for consistency update ci build script to only build esp32-s2 target with freertos examples --- .github/workflows/build.yml | 18 +++++++++++++---- .github/workflows/esp32s2.yml | 38 ----------------------------------- examples/rules.mk | 30 +++++++++++++++++++++++---- tools/build_all.py | 22 +++++++++++++------- 4 files changed, 55 insertions(+), 53 deletions(-) delete mode 100644 .github/workflows/esp32s2.yml diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 551c7cb92..7edb1fcba 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -36,15 +36,23 @@ jobs: - name: Install Toolchains run: | + # ARM & RISC-V GCC from xpack npm install --global xpm xpm install --global @xpack-dev-tools/arm-none-eabi-gcc@latest xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 - tar -C $HOME -xaf /tmp/msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" + + # TI MSP430 GCC + wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 + tar -C $HOME -xaf /tmp/msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/msp430-gcc-*_linux64/bin`" - + + # ESP IDF + git clone https://github.com/espressif/esp-idf.git $HOME/esp-idf + cd $HOME/esp-idf + ./install.sh + - name: Checkout TinyUSB uses: actions/checkout@v2 @@ -54,5 +62,7 @@ jobs: git submodule update --init --recursive - name: Build - run: python3 tools/build_all.py ${{ matrix.example }} + run: | + . $HOME/esp-idf/export.sh + python3 tools/build_all.py ${{ matrix.example }} diff --git a/.github/workflows/esp32s2.yml b/.github/workflows/esp32s2.yml deleted file mode 100644 index a3f30c8f8..000000000 --- a/.github/workflows/esp32s2.yml +++ /dev/null @@ -1,38 +0,0 @@ -name: Build ESP32-S2 - -on: [pull_request, push, repository_dispatch] - -jobs: - build: - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - example: ['cdc_msc_freertos'] - - steps: - - name: Setup Python - uses: actions/setup-python@v1 - - - name: Install ESP-IDF - run: | - git clone https://github.com/espressif/esp-idf.git $HOME/esp-idf - cd $HOME/esp-idf - ./install.sh - #echo "::add-path::`echo $HOME/msp430-gcc-*_linux64/bin`" - - - name: Checkout TinyUSB - uses: actions/checkout@v2 - -# - name: Checkout Submodules -# run: | -# git submodule sync --recursive -# git submodule update --init --recursive - - - name: Build - run: | - . $HOME/esp-idf/export.sh - cd examples/device/cdc_msc_freertos - idf.py build - #python3 tools/build_all.py ${{ matrix.example }} - diff --git a/examples/rules.mk b/examples/rules.mk index 55c70af4b..92204cf72 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -1,6 +1,25 @@ -# -# Common make definition for all examples -# +# --------------------------------------- +# Common make rules for all examples +# --------------------------------------- + +ifeq ($(CROSS_COMPILE),xtensa-esp32-elf-) +# Espressif IDF use CMake build system, this add wrapper target to call idf.py + +.PHONY: all clean flash +.DEFAULT_GOAL := all + +all: + idf.py -B$(BUILD) -DBOARD=$(BOARD) build + +clean: + idf.py clean + +flash: + @:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyUSB0) + idf.py -p $(SERIAL) flash + +else +# GNU Make build system # libc LIBS += -lgcc -lm -lnosys @@ -28,8 +47,9 @@ SRC_C += \ # TinyUSB stack include INC += $(TOP)/src -# CFLAGS += $(addprefix -I,$(INC)) + +# TODO Skip nanolib for MSP430 ifeq ($(BOARD), msp_exp430f5529lp) LDFLAGS += $(CFLAGS) -fshort-enums -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections else @@ -135,3 +155,5 @@ flash-jlink: $(BUILD)/$(BOARD)-firmware.hex # flash STM32 MCU using stlink with STM32 Cube Programmer CLI flash-stlink: $(BUILD)/$(BOARD)-firmware.elf STM32_Programmer_CLI --connect port=swd --write $< --go + +endif # Make target diff --git a/tools/build_all.py b/tools/build_all.py index c95f88b79..a5e29a4ae 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -27,8 +27,7 @@ if len(sys.argv) > 2: all_boards.append(sys.argv[2]) else: for entry in os.scandir("hw/bsp"): - # Skip board without board.mk e.g esp32s2 - if entry.is_dir() and os.path.exists(entry.path + "/board.mk"): + if entry.is_dir(): all_boards.append(entry.name) all_boards.sort() @@ -40,7 +39,8 @@ def build_example(example, board): stdout=subprocess.PIPE, stderr=subprocess.STDOUT) def build_size(example, board): - elf_file = 'examples/device/{}/_build/build-{}/{}-firmware.elf'.format(example, board, board) + #elf_file = 'examples/device/{}/_build/build-{}/{}-firmware.elf'.format(example, board, board) + elf_file = 'examples/device/{}/_build/build-{}/*.elf'.format(example, board) size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8") size_list = size_output.split('\n')[1].split('\t') flash_size = int(size_list[0]) @@ -50,10 +50,18 @@ def build_size(example, board): def skip_example(example, board): ex_dir = 'examples/device/' + example board_mk = 'hw/bsp/{}/board.mk'.format(board) - for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'): - mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2] - with open(board_mk) as mk: - if mcu_cflag in mk.read(): + + with open(board_mk) as mk: + mk_contents = mk.read() + + # Skip ESP32-S2 board if example is not FreeRTOS one + if 'freertos' not in example and 'CROSS_COMPILE = xtensa-esp32-elf-' in mk_contents: + return 1 + + # Skip if CFG_TUSB_MCU in board.mk to match skip file + for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'): + mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2] + if mcu_cflag in mk_contents: return 1 return 0 From 748cc88769ffd2039fcb0f4db9bb2cb4bc84965f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 3 Apr 2020 12:20:06 +0700 Subject: [PATCH 09/61] add saola board.mk --- hw/bsp/esp32s2_saola/board.mk | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 hw/bsp/esp32s2_saola/board.mk diff --git a/hw/bsp/esp32s2_saola/board.mk b/hw/bsp/esp32s2_saola/board.mk new file mode 100644 index 000000000..92ca884c4 --- /dev/null +++ b/hw/bsp/esp32s2_saola/board.mk @@ -0,0 +1,2 @@ +# Cross Compiler for ESP32 +CROSS_COMPILE = xtensa-esp32-elf- From 0814bd99487c67494fe2c8321dba53e3e8529ff2 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 3 Apr 2020 12:39:57 +0700 Subject: [PATCH 10/61] minor clean up --- tools/build_all.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/build_all.py b/tools/build_all.py index a5e29a4ae..325e671fd 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -11,6 +11,9 @@ exit_status = 0 total_time = time.monotonic() +build_format = '| {:20} | {:30} | {:9} | {:7} | {:6} | {:6} |' +build_separator = '-' * 97 + # 1st Argument is Example, build all examples if not existed all_examples = [] if len(sys.argv) > 1: @@ -66,8 +69,6 @@ def skip_example(example, board): return 0 -build_format = '| {:20} | {:30} | {:9} | {:5} | {:6} | {:6} |' -build_separator = '-' * 95 print(build_separator) print(build_format.format('Example', 'Board', 'Result', 'Time', 'Flash', 'SRAM')) From 1e7c3cf95eb4c1e078a9083277b2abbbda5e19bf Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 3 Apr 2020 17:09:38 +0700 Subject: [PATCH 11/61] update dcd esp32s2 fifo allocation to match current dcd synopsys --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 116 +++++++++++-------- 1 file changed, 69 insertions(+), 47 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index e4e8e30fe..b2593383c 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -26,6 +26,10 @@ * This file is part of the TinyUSB stack. */ +#include "tusb_option.h" + +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 && TUSB_OPT_DEVICE_ENABLED + // Espressif #include "driver/periph_ctrl.h" #include "freertos/xtensa_api.h" @@ -35,15 +39,12 @@ #include "soc/dport_reg.h" #include "soc/gpio_sig_map.h" #include "soc/usb_periph.h" -#include "tusb_config.h" -// TinyUSB -#include "tusb_option.h" -//#include "descriptors_control.h" + #include "device/dcd.h" - -#define USB_EP_DIRECTIONS 2 -#define USB_MAX_EP_NUM 16 +// FIFO size in bytes TODO need confirmation from Espressif +#define EP_MAX USB_OUT_EP_NUM +#define EP_FIFO_SIZE 1280 typedef struct { uint8_t *buffer; @@ -61,7 +62,7 @@ static uint8_t s_setup_phase = 0; /* 00 - got setup, 02 - setup cmd sent*/ #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] -static xfer_ctl_t xfer_status[USB_MAX_EP_NUM][USB_EP_DIRECTIONS]; +static xfer_ctl_t xfer_status[EP_MAX][2]; static inline void readyfor1setup_pkg(int ep_num) { @@ -78,34 +79,37 @@ static void bus_reset(void) USB0.dcfg &= ~USB_DEVADDR_M; // reset address + // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture // - // --------------- 320 ( 1280 bytes ) - // | IN FIFO 3 | + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO MAX | + // --------------- + // | ... | // --------------- y + x + 16 + GRXFSIZ - // | IN FIFO 2 | + // | IN FIFO 2 | // --------------- x + 16 + GRXFSIZ - // | IN FIFO 1 | + // | IN FIFO 1 | // --------------- 16 + GRXFSIZ - // | IN FIFO 0 | + // | IN FIFO 0 | // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | + // | OUT FIFO | + // | ( Shared ) | // --------------- 0 // - // FIFO sizes are set up by the following rules (each word 32-bits): - // All EP OUT shared a unique OUT FIFO which uses (based on page 1354 of Rev 17 of reference manual): - // * 10 locations in hardware for setup packets + setup control words - // (up to 3 setup packets). - // * 2 locations for OUT endpoint control words. - // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) - // * 1 location for global NAK (not required/used here). + // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN // - // It is recommended to allocate 2 times the largest packet size, therefore - // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50 + // - All EP OUT shared a unique OUT FIFO which uses + // * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets). + // * 2 locations for OUT endpoint control words. + // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) + // * 1 location for global NAK (not required/used here). + // * It is recommended to allocate 2 times the largest packet size, therefore + // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52 USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10, USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo - USB0.grxfsiz = 50; + USB0.grxfsiz = 52; USB0.gintmsk = USB_MODEMISMSK_M | USB_SOFMSK_M | @@ -123,7 +127,8 @@ static void bus_reset(void) USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M; - USB0.gnptxfsiz = 16 << USB_NPTXFDEP_S; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); readyfor1setup_pkg(0); } @@ -245,10 +250,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - // Unsupported endpoint numbers/size. - if ((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 3)) { - return false; - } + TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64); + TU_ASSERT(epnum < EP_MAX); xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); xfer->max_size = desc_edpt->wMaxPacketSize.size; @@ -259,33 +262,44 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) desc_edpt->wMaxPacketSize.size << USB_MPS0_S; USB0.daintmsk |= (1 << (16 + epnum)); } else { - // Peripheral FIFO architecture (Rev18 RM 29.11) + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture // - // --------------- 320 ( 1280 bytes ) - // | IN FIFO 3 | + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO MAX | + // --------------- + // | ... | // --------------- y + x + 16 + GRXFSIZ - // | IN FIFO 2 | + // | IN FIFO 2 | // --------------- x + 16 + GRXFSIZ - // | IN FIFO 1 | + // | IN FIFO 1 | // --------------- 16 + GRXFSIZ - // | IN FIFO 0 | + // | IN FIFO 0 | // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | + // | OUT FIFO | + // | ( Shared ) | // --------------- 0 // - // Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (312-50-16) / 3 = 82 ~ 80 + // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints + // - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1) + // - Offset: GRXFSIZ + 16 + Size*(epnum-1) + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + in_ep[epnum].diepctl |= USB_D_USBACTEP1_M | - (epnum - 1) << USB_D_TXFNUM1_S | + epnum << USB_D_TXFNUM1_S | desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | desc_edpt->wMaxPacketSize.size << 0; USB0.daintmsk |= (1 << (0 + epnum)); - // Both TXFD and TXSA are in unit of 32-bit words - uint16_t const fifo_size = 80; - uint32_t const fifo_offset = (USB0.grxfsiz & USB_NPTXFDEP_V) + 16 + fifo_size * (epnum - 1); - USB0.dieptxf[epnum - 1] = (80 << USB_NPTXFDEP_S) | fifo_offset; + // Both TXFD and TXSA are in unit of 32-bit words. + // IN FIFO 0 was configured during enumeration, hence the "+ 16". + uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16; + uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1); + uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1); + + // DIEPTXF starts at FIFO #1. + USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset; } return true; } @@ -320,12 +334,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // here. if (dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - int bytes2fifo_left = total_bytes; - uint32_t val; // 32 bit val from 4 buff addresses - USB0.in_ep_reg[epnum].diepint = ~0U; // clear all ints USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK + +#if 1 + //int bytes2fifo_left = tu_min16(total_bytes, xfer->max_size); + int bytes2fifo_left = total_bytes; + uint32_t val; // 32 bit val from 4 buff addresses while (bytes2fifo_left > 0) { // TODO move it to ep_in_handle (IDF-1475) /* ATTENTION! In cases when CFG_TUD_ENDOINT0_SIZE, CFG_TUD_CDC_EPSIZE, CFG_TUD_MIDI_EPSIZE or CFG_TUD_MSC_BUFSIZE < 4 next line can be a cause of an error.*/ @@ -338,7 +354,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to buffer += 4; bytes2fifo_left -= 4; } +#else +// transmit_packet(xfer, &USB0.in_ep_reg[epnum], epnum); // USB0.dtknqr4_fifoemptymsk |= (1 << epnum); +#endif } else { // Each complete packet for OUT xfers triggers XFRC. USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M | @@ -747,3 +766,6 @@ void dcd_int_disable(uint8_t rhport) (void)rhport; esp_intr_free(usb_ih); } + +#endif // OPT_MCU_ESP32S2 + From 5963ace5ab2ea208c89335636ecef77d83491b1a Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 14:33:36 +0700 Subject: [PATCH 12/61] add -B for clean and flash --- examples/rules.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/rules.mk b/examples/rules.mk index 92204cf72..9e5226aca 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -12,11 +12,11 @@ all: idf.py -B$(BUILD) -DBOARD=$(BOARD) build clean: - idf.py clean + idf.py -B$(BUILD) clean flash: @:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyUSB0) - idf.py -p $(SERIAL) flash + idf.py -B$(BUILD) -p $(SERIAL) flash else # GNU Make build system From 050de0ec33752d0a24b53c9e18d82161185d0176 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 16:32:55 +0700 Subject: [PATCH 13/61] fix issue and typo with In token when Fifo empty fix transmit packet endpoint's fifo --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 45 ++++++-------------- 1 file changed, 12 insertions(+), 33 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index b2593383c..3361bde36 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -57,9 +57,9 @@ typedef struct { static const char *TAG = "TUSB:DCD"; static intr_handle_t usb_ih; static volatile TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6]; -static uint8_t s_setup_phase = 0; /* 00 - got setup, - 01 - got done setup, - 02 - setup cmd sent*/ +static volatile uint8_t s_setup_phase = 0; /* 00 - got setup, + 01 - got done setup, + 02 - setup cmd sent*/ #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] static xfer_ctl_t xfer_status[EP_MAX][2]; @@ -125,7 +125,7 @@ static void bus_reset(void) USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; - USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M; + USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); @@ -334,30 +334,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // here. if (dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB0.in_ep_reg[epnum].diepint = ~0U; // clear all ints USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK - -#if 1 - //int bytes2fifo_left = tu_min16(total_bytes, xfer->max_size); - int bytes2fifo_left = total_bytes; - uint32_t val; // 32 bit val from 4 buff addresses - while (bytes2fifo_left > 0) { // TODO move it to ep_in_handle (IDF-1475) - /* ATTENTION! In cases when CFG_TUD_ENDOINT0_SIZE, CFG_TUD_CDC_EPSIZE, CFG_TUD_MIDI_EPSIZE or - CFG_TUD_MSC_BUFSIZE < 4 next line can be a cause of an error.*/ - val = (*(buffer + 3) << 24) | - (*(buffer + 2) << 16) | - (*(buffer + 1) << 8) | - (*(buffer + 0) << 0); - ESP_LOGV(TAG, "Transfer 0x%08x -> FIFO%d", val, epnum); - USB0.fifo[epnum][0] = val; //copy and next buffer address - buffer += 4; - bytes2fifo_left -= 4; - } -#else -// transmit_packet(xfer, &USB0.in_ep_reg[epnum], epnum); - // USB0.dtknqr4_fifoemptymsk |= (1 << epnum); -#endif + USB0.dtknqr4_fifoemptymsk |= (1 << epnum); } else { // Each complete packet for OUT xfers triggers XFRC. USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M | @@ -521,9 +500,8 @@ static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num) { - ESP_EARLY_LOGV(TAG, "USB - transmit_packet"); - uint32_t *tx_fifo = USB0.fifo[0]; + volatile uint32_t *tx_fifo = USB0.fifo[fifo_num]; uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S; xfer->queued_len = xfer->total_len - remaining; @@ -567,10 +545,11 @@ static void read_rx_fifo(void) { // Pop control word off FIFO (completed xfers will have 2 control words, // we only pop one ctl word each interrupt). - volatile uint32_t ctl_word = USB0.grxstsp; + uint32_t ctl_word = USB0.grxstsp; uint8_t pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; uint8_t epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S; uint16_t bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S; + switch (pktsts) { case 0x01: // Global OUT NAK (Interrupt) ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); @@ -668,12 +647,12 @@ static void handle_epin_ints(void) if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) { ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!"); USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M; - // USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive. + USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive. dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } // XFER FIFO empty - if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) { + if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) { ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!"); USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M; transmit_packet(xfer, &USB0.in_ep_reg[n], n); @@ -685,8 +664,8 @@ static void handle_epin_ints(void) static void dcd_int_handler(void) { - uint32_t int_status = USB0.gintsts; - uint32_t int_msk = USB0.gintmsk; + const uint32_t int_status = USB0.gintsts; + const uint32_t int_msk = USB0.gintmsk; if (int_status & USB_DISCONNINT_M) { ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); From c026236824e95d9409136cd48481b69e2cea56dc Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 16:33:04 +0700 Subject: [PATCH 14/61] house keeping --- src/device/usbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index ddd99d7f1..125aa351c 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -421,7 +421,7 @@ void tud_task (void) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - TU_LOG2(" Endpoint: 0x%02X, Bytes: %ld\r\n", ep_addr, event.xfer_complete.len); + TU_LOG2(" Endpoint: 0x%02X, Bytes: %lu\r\n", ep_addr, event.xfer_complete.len); _usbd_dev.ep_status[epnum][ep_dir].busy = false; From cfb2ef1cffff98a1ad33d52a391cfa52b086d612 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 19:43:47 +0700 Subject: [PATCH 15/61] move setup nodes before cache msp430 --- .github/workflows/build.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 55bde832c..1f4ae5ae1 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -30,7 +30,10 @@ jobs: steps: - name: Setup Python uses: actions/setup-python@v1 - + + - name: Setup Node.js + uses: actions/setup-node@v1.1.0 + - name: Cache MSP430 Toolchain id: cache-msp430 uses: actions/cache@v1 @@ -38,10 +41,7 @@ jobs: path: /tmp/dl/ # Increment serial number at end when updating downloads key: msp430-${{ runner.os }}-0 - - - name: Setup Node.js - uses: actions/setup-node@v1.1.0 - + - name: Install Toolchains run: | # ARM & RISC-V GCC from xpack From 22a9b05834504471a4446f45e5f8153a8f99d9fa Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 19:49:25 +0700 Subject: [PATCH 16/61] rename dcd_int_handler to dcd_irq_handler for consistency with other port --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 3361bde36..df4cbf445 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -136,7 +136,7 @@ static void bus_reset(void) static void enum_done_processing(void) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); // On current silicon on the Full Speed core, speed is fixed to Full Speed. // However, keep for debugging and in case Low Speed is ever supported. uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); @@ -662,25 +662,25 @@ static void handle_epin_ints(void) } -static void dcd_int_handler(void) +void dcd_irq_handler(void) { const uint32_t int_status = USB0.gintsts; const uint32_t int_msk = USB0.gintmsk; if (int_status & USB_DISCONNINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected"); USB0.gintsts = USB_DISCONNINT_M; } if (int_status & USB_USBRST_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset"); USB0.gintsts = USB_USBRST_M; bus_reset(); } if (int_status & USB_RESETDET_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend"); USB0.gintsts = USB_RESETDET_M; bus_reset(); } @@ -700,19 +700,19 @@ static void dcd_int_handler(void) } if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); read_rx_fifo(); } // OUT endpoint interrupt handling. if (int_status & USB_OEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!"); handle_epout_ints(); } // IN endpoint interrupt handling. if (int_status & USB_IEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!"); handle_epin_ints(); } @@ -737,7 +737,7 @@ static void dcd_int_handler(void) void dcd_int_enable(uint8_t rhport) { (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih); + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih); } void dcd_int_disable(uint8_t rhport) From 9d26666c9177653be431b02f5262405ee39f3f59 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 20:35:52 +0700 Subject: [PATCH 17/61] update ci setup-node / setup-ruby --- .github/workflows/build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 1f4ae5ae1..8840d369b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -7,7 +7,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Setup Ruby - uses: actions/setup-ruby@v1.0.0 + uses: actions/setup-ruby@v1 - name: Checkout TinyUSB uses: actions/checkout@v2 @@ -32,7 +32,7 @@ jobs: uses: actions/setup-python@v1 - name: Setup Node.js - uses: actions/setup-node@v1.1.0 + uses: actions/setup-node@v1 - name: Cache MSP430 Toolchain id: cache-msp430 From a344427e3f27b04744778241f235262b42a8d003 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 20:39:20 +0700 Subject: [PATCH 18/61] fix CROSS_COMPILE for esp32s2 --- hw/bsp/esp32s2_saola/board.mk | 2 +- tools/build_all.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/bsp/esp32s2_saola/board.mk b/hw/bsp/esp32s2_saola/board.mk index 92ca884c4..167ef6226 100644 --- a/hw/bsp/esp32s2_saola/board.mk +++ b/hw/bsp/esp32s2_saola/board.mk @@ -1,2 +1,2 @@ # Cross Compiler for ESP32 -CROSS_COMPILE = xtensa-esp32-elf- +CROSS_COMPILE = xtensa-esp32s2-elf- diff --git a/tools/build_all.py b/tools/build_all.py index 325e671fd..ba918425a 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -58,7 +58,7 @@ def skip_example(example, board): mk_contents = mk.read() # Skip ESP32-S2 board if example is not FreeRTOS one - if 'freertos' not in example and 'CROSS_COMPILE = xtensa-esp32-elf-' in mk_contents: + if 'freertos' not in example and 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk_contents: return 1 # Skip if CFG_TUSB_MCU in board.mk to match skip file From 06e87b47a29a0d8c304a08cd1f8bb1ad2168880f Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 21:28:02 +0700 Subject: [PATCH 19/61] revert name to dcd_init_handler() since the function signature is different --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index df4cbf445..3361bde36 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -136,7 +136,7 @@ static void bus_reset(void) static void enum_done_processing(void) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); // On current silicon on the Full Speed core, speed is fixed to Full Speed. // However, keep for debugging and in case Low Speed is ever supported. uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); @@ -662,25 +662,25 @@ static void handle_epin_ints(void) } -void dcd_irq_handler(void) +static void dcd_int_handler(void) { const uint32_t int_status = USB0.gintsts; const uint32_t int_msk = USB0.gintmsk; if (int_status & USB_DISCONNINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); USB0.gintsts = USB_DISCONNINT_M; } if (int_status & USB_USBRST_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); USB0.gintsts = USB_USBRST_M; bus_reset(); } if (int_status & USB_RESETDET_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); USB0.gintsts = USB_RESETDET_M; bus_reset(); } @@ -700,19 +700,19 @@ void dcd_irq_handler(void) } if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); read_rx_fifo(); } // OUT endpoint interrupt handling. if (int_status & USB_OEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); handle_epout_ints(); } // IN endpoint interrupt handling. if (int_status & USB_IEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); handle_epin_ints(); } @@ -737,7 +737,7 @@ void dcd_irq_handler(void) void dcd_int_enable(uint8_t rhport) { (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih); + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih); } void dcd_int_disable(uint8_t rhport) From ef7992ce65f243d838bf79197f5c55e792e4ce87 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 21:36:53 +0700 Subject: [PATCH 20/61] fix CI --- examples/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/rules.mk b/examples/rules.mk index 9e5226aca..2f4c8b860 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -2,7 +2,7 @@ # Common make rules for all examples # --------------------------------------- -ifeq ($(CROSS_COMPILE),xtensa-esp32-elf-) +ifeq ($(CROSS_COMPILE),xtensa-esp32s2-elf-) # Espressif IDF use CMake build system, this add wrapper target to call idf.py .PHONY: all clean flash From c64db32b82715f7bd1e8a42e5658822741dab99b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 22:23:24 +0700 Subject: [PATCH 21/61] ci test --- .github/workflows/build_esp32s.yml | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 .github/workflows/build_esp32s.yml diff --git a/.github/workflows/build_esp32s.yml b/.github/workflows/build_esp32s.yml new file mode 100644 index 000000000..102e22c60 --- /dev/null +++ b/.github/workflows/build_esp32s.yml @@ -0,0 +1,34 @@ +name: Build ESP32S + +on: [pull_request, push, repository_dispatch] + +jobs: + build: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + example: ['cdc_msc_freertos'] + + steps: + - name: Setup Python + uses: actions/setup-python@v1 + + - name: Install Toolchains + run: | + # ESP IDF + git clone --depth 1 https://github.com/espressif/esp-idf.git $HOME/esp-idf + cd $HOME/esp-idf + ./install.sh + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + with: + # Cannot do submodule checkout here since LWIP's git server cannot checkout unadventised commits (it must use tags) + submodules: 'false' + + - name: Build + run: | + . $HOME/esp-idf/export.sh + python3 tools/build_all.py ${{ matrix.example }} + From 19f767317f9f19490e032cbc22de30f16f645e99 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Apr 2020 23:33:09 +0700 Subject: [PATCH 22/61] more ci --- .github/workflows/build_esp32s.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build_esp32s.yml b/.github/workflows/build_esp32s.yml index 102e22c60..71155073f 100644 --- a/.github/workflows/build_esp32s.yml +++ b/.github/workflows/build_esp32s.yml @@ -30,5 +30,5 @@ jobs: - name: Build run: | . $HOME/esp-idf/export.sh - python3 tools/build_all.py ${{ matrix.example }} + python3 tools/build_all.py ${{ matrix.example }} esp32s2_saola From f073a5ecd37a705fae89400a50ff24fa985c895a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 11:15:59 +0700 Subject: [PATCH 23/61] CI: seperate esp32s2 into different job skip esp32s in build_all.py script --- .github/workflows/build.yml | 30 +++++++++++++++++++++----- .github/workflows/build_esp32s.yml | 34 ------------------------------ tools/build_all.py | 4 ++-- 3 files changed, 27 insertions(+), 41 deletions(-) delete mode 100644 .github/workflows/build_esp32s.yml diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8840d369b..c96664488 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -3,6 +3,7 @@ name: Build on: [pull_request, push, repository_dispatch] jobs: + # Unit testing with Ceedling unit-test: runs-on: ubuntu-latest steps: @@ -19,6 +20,7 @@ jobs: cd test ceedling test:all + # Build most of the ports build: runs-on: ubuntu-latest strategy: @@ -57,11 +59,6 @@ jobs: tar -C $HOME -xaf /tmp/dl/msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/msp430-gcc-*_linux64/bin`" - # ESP IDF - git clone --depth 1 https://github.com/espressif/esp-idf.git $HOME/esp-idf - cd $HOME/esp-idf - ./install.sh - - name: Checkout TinyUSB uses: actions/checkout@v2 with: @@ -80,3 +77,26 @@ jobs: . $HOME/esp-idf/export.sh python3 tools/build_all.py ${{ matrix.example }} + # Build ESP32S + build-esp32s: + runs-on: ubuntu-latest + steps: + - name: Setup Python + uses: actions/setup-python@v1 + + - name: Install Toolchains + run: | + git clone --depth 1 https://github.com/espressif/esp-idf.git $HOME/esp-idf + cd $HOME/esp-idf + ./install.sh + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + with: + submodules: 'false' + + - name: Build + run: | + . $HOME/esp-idf/export.sh + cd examples/device/cdc_msc_freertos + idf.py build diff --git a/.github/workflows/build_esp32s.yml b/.github/workflows/build_esp32s.yml deleted file mode 100644 index 71155073f..000000000 --- a/.github/workflows/build_esp32s.yml +++ /dev/null @@ -1,34 +0,0 @@ -name: Build ESP32S - -on: [pull_request, push, repository_dispatch] - -jobs: - build: - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - example: ['cdc_msc_freertos'] - - steps: - - name: Setup Python - uses: actions/setup-python@v1 - - - name: Install Toolchains - run: | - # ESP IDF - git clone --depth 1 https://github.com/espressif/esp-idf.git $HOME/esp-idf - cd $HOME/esp-idf - ./install.sh - - - name: Checkout TinyUSB - uses: actions/checkout@v2 - with: - # Cannot do submodule checkout here since LWIP's git server cannot checkout unadventised commits (it must use tags) - submodules: 'false' - - - name: Build - run: | - . $HOME/esp-idf/export.sh - python3 tools/build_all.py ${{ matrix.example }} esp32s2_saola - diff --git a/tools/build_all.py b/tools/build_all.py index ba918425a..c78192d63 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -57,8 +57,8 @@ def skip_example(example, board): with open(board_mk) as mk: mk_contents = mk.read() - # Skip ESP32-S2 board if example is not FreeRTOS one - if 'freertos' not in example and 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk_contents: + # Skip all ESP32-S2 board for CI + if 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk_contents: return 1 # Skip if CFG_TUSB_MCU in board.mk to match skip file From f44440df5d27f8a8f64e53b3c8892f73585c2323 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 11:21:34 +0700 Subject: [PATCH 24/61] ci again --- .github/workflows/build.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c96664488..584ee1d70 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -74,7 +74,6 @@ jobs: - name: Build run: | - . $HOME/esp-idf/export.sh python3 tools/build_all.py ${{ matrix.example }} # Build ESP32S From 51944f0dc9921660129283effc794b9800d04fbb Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 12:19:12 +0700 Subject: [PATCH 25/61] only check in sdkconfig.defaults --- examples/device/cdc_msc_freertos/sdkconfig | 1060 ----------------- .../cdc_msc_freertos/sdkconfig.defaults | 4 + 2 files changed, 4 insertions(+), 1060 deletions(-) delete mode 100644 examples/device/cdc_msc_freertos/sdkconfig create mode 100644 examples/device/cdc_msc_freertos/sdkconfig.defaults diff --git a/examples/device/cdc_msc_freertos/sdkconfig b/examples/device/cdc_msc_freertos/sdkconfig deleted file mode 100644 index feb6d6454..000000000 --- a/examples/device/cdc_msc_freertos/sdkconfig +++ /dev/null @@ -1,1060 +0,0 @@ -# -# Automatically generated file. DO NOT EDIT. -# Espressif IoT Development Framework (ESP-IDF) Project Configuration -# -CONFIG_IDF_CMAKE=y -CONFIG_IDF_TARGET="esp32s2" -CONFIG_IDF_TARGET_ESP32S2=y -CONFIG_IDF_FIRMWARE_CHIP_ID=0x0002 - -# -# SDK tool configuration -# -CONFIG_SDK_TOOLPREFIX="xtensa-esp32s2-elf-" -# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set -# end of SDK tool configuration - -# -# Build type -# -CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y -# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set -CONFIG_APP_BUILD_GENERATE_BINARIES=y -CONFIG_APP_BUILD_BOOTLOADER=y -CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y -# end of Build type - -# -# Application manager -# -CONFIG_APP_COMPILE_TIME_DATE=y -# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set -# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set -# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set -CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 -# end of Application manager - -# -# Bootloader config -# -CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y -# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set -# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set -# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set -# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set -# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set -# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set -CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y -# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set -# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set -CONFIG_BOOTLOADER_LOG_LEVEL=3 -# CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set -CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y -# CONFIG_BOOTLOADER_FACTORY_RESET is not set -# CONFIG_BOOTLOADER_APP_TEST is not set -CONFIG_BOOTLOADER_WDT_ENABLE=y -# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set -CONFIG_BOOTLOADER_WDT_TIME_MS=9000 -# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set -# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set -CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 -# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set -# end of Bootloader config - -# -# Security features -# -# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set -# CONFIG_SECURE_BOOT is not set -# CONFIG_SECURE_FLASH_ENC_ENABLED is not set -# end of Security features - -# -# Serial flasher config -# -CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 -# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set -# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set -CONFIG_ESPTOOLPY_FLASHMODE_DIO=y -# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set -CONFIG_ESPTOOLPY_FLASHMODE="dio" -# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set -CONFIG_ESPTOOLPY_FLASHFREQ_40M=y -# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set -# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set -CONFIG_ESPTOOLPY_FLASHFREQ="40m" -# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set -CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y -# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set -# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set -# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set -CONFIG_ESPTOOLPY_FLASHSIZE="2MB" -CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y -CONFIG_ESPTOOLPY_BEFORE_RESET=y -# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set -CONFIG_ESPTOOLPY_BEFORE="default_reset" -CONFIG_ESPTOOLPY_AFTER_RESET=y -# CONFIG_ESPTOOLPY_AFTER_NORESET is not set -CONFIG_ESPTOOLPY_AFTER="hard_reset" -# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set -# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set -CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y -# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set -# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set -# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set -# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set -CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 -CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 -# end of Serial flasher config - -# -# Partition Table -# -CONFIG_PARTITION_TABLE_SINGLE_APP=y -# CONFIG_PARTITION_TABLE_TWO_OTA is not set -# CONFIG_PARTITION_TABLE_CUSTOM is not set -CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" -CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" -CONFIG_PARTITION_TABLE_OFFSET=0x8000 -CONFIG_PARTITION_TABLE_MD5=y -# end of Partition Table - -# -# Compiler options -# -CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y -# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set -# CONFIG_COMPILER_OPTIMIZATION_PERF is not set -# CONFIG_COMPILER_OPTIMIZATION_NONE is not set -CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y -# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set -# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set -# CONFIG_COMPILER_CXX_EXCEPTIONS is not set -# CONFIG_COMPILER_CXX_RTTI is not set -CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y -# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set -# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set -# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set -# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set -# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set -# end of Compiler options - -# -# Component config -# - -# -# Application Level Tracing -# -# CONFIG_APPTRACE_DEST_TRAX is not set -CONFIG_APPTRACE_DEST_NONE=y -CONFIG_APPTRACE_LOCK_ENABLE=y -# end of Application Level Tracing - -CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 -CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 -CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 -CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 -CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 -CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 -CONFIG_BT_RESERVE_DRAM=0 - -# -# CoAP Configuration -# -CONFIG_COAP_MBEDTLS_PSK=y -# CONFIG_COAP_MBEDTLS_PKI is not set -# CONFIG_COAP_MBEDTLS_DEBUG is not set -CONFIG_COAP_LOG_DEFAULT_LEVEL=0 -# end of CoAP Configuration - -# -# Driver configurations -# - -# -# ADC configuration -# -# CONFIG_ADC_FORCE_XPD_FSM is not set -CONFIG_ADC_DISABLE_DAC=y -# end of ADC configuration - -# -# SPI configuration -# -# CONFIG_SPI_MASTER_IN_IRAM is not set -CONFIG_SPI_MASTER_ISR_IN_IRAM=y -# CONFIG_SPI_SLAVE_IN_IRAM is not set -CONFIG_SPI_SLAVE_ISR_IN_IRAM=y -# end of SPI configuration - -# -# UART configuration -# -# CONFIG_UART_ISR_IN_IRAM is not set -# end of UART configuration -# end of Driver configurations - -# -# eFuse Bit Manager -# -# CONFIG_EFUSE_CUSTOM_TABLE is not set -# CONFIG_EFUSE_VIRTUAL is not set -CONFIG_EFUSE_MAX_BLK_LEN=256 -# end of eFuse Bit Manager - -# -# ESP-TLS -# -CONFIG_ESP_TLS_USING_MBEDTLS=y -# CONFIG_ESP_TLS_SERVER is not set -# CONFIG_ESP_TLS_PSK_VERIFICATION is not set -# end of ESP-TLS - -# -# ESP32S2-specific -# -# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 is not set -CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160=y -# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 is not set -CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=160 - -# -# Cache config -# -CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y -# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set -# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set -CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y -# CONFIG_ESP32S2_DATA_CACHE_0KB is not set -CONFIG_ESP32S2_DATA_CACHE_8KB=y -# CONFIG_ESP32S2_DATA_CACHE_16KB is not set -# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set -CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y -# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set -# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set -# end of Cache config - -# CONFIG_ESP32S2_SPIRAM_SUPPORT is not set -# CONFIG_ESP32S2_TRAX is not set -CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0 -# CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set -CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y -CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2 -# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set -CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=0 -CONFIG_ESP32S2_DEBUG_OCDAWARE=y -# CONFIG_ESP32S2_DEBUG_STUBS_ENABLE is not set -CONFIG_ESP32S2_BROWNOUT_DET=y -CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y -# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set -# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set -# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set -# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set -# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set -# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set -CONFIG_ESP32S2_BROWNOUT_DET_LVL=7 -CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y -# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set -# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set -# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set -CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y -# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set -# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set -# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set -CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 -# CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE is not set -# CONFIG_ESP32S2_NO_BLOBS is not set -# end of ESP32S2-specific - -# -# Power Management -# -# CONFIG_PM_ENABLE is not set -# end of Power Management - -# -# Common ESP-related -# -CONFIG_ESP_ERR_TO_NAME_LOOKUP=y -CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 -CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 -CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 -CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 -CONFIG_ESP_CONSOLE_UART_DEFAULT=y -# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set -# CONFIG_ESP_CONSOLE_UART_NONE is not set -CONFIG_ESP_CONSOLE_UART_NUM=0 -CONFIG_ESP_CONSOLE_UART_TX_GPIO=43 -CONFIG_ESP_CONSOLE_UART_RX_GPIO=44 -CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 -CONFIG_ESP_INT_WDT=y -CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 -CONFIG_ESP_TASK_WDT=y -# CONFIG_ESP_TASK_WDT_PANIC is not set -CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 -CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y -CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y -CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y -# end of Common ESP-related - -# -# Ethernet -# -CONFIG_ETH_ENABLED=y -CONFIG_ETH_USE_SPI_ETHERNET=y -# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set -# CONFIG_ETH_USE_OPENETH is not set -# end of Ethernet - -# -# Event Loop Library -# -# CONFIG_ESP_EVENT_LOOP_PROFILING is not set -CONFIG_ESP_EVENT_POST_FROM_ISR=y -CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y -# end of Event Loop Library - -# -# GDB Stub -# -# end of GDB Stub - -# -# ESP HTTP client -# -CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y -# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set -# end of ESP HTTP client - -# -# HTTP Server -# -CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 -CONFIG_HTTPD_MAX_URI_LEN=512 -CONFIG_HTTPD_ERR_RESP_NO_DELAY=y -CONFIG_HTTPD_PURGE_BUF_LEN=32 -# CONFIG_HTTPD_LOG_PURGE_DATA is not set -# CONFIG_HTTPD_WS_SUPPORT is not set -# end of HTTP Server - -# -# ESP HTTPS OTA -# -# CONFIG_OTA_ALLOW_HTTP is not set -# end of ESP HTTPS OTA - -# -# ESP HTTPS server -# -# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set -# end of ESP HTTPS server - -# -# ESP NETIF Adapter -# -CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 -CONFIG_ESP_NETIF_TCPIP_LWIP=y -# CONFIG_ESP_NETIF_LOOPBACK is not set -CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y -# end of ESP NETIF Adapter - -# -# ESP System Settings -# -# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set -CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y -# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set -# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set -# end of ESP System Settings - -# -# High resolution timer (esp_timer) -# -# CONFIG_ESP_TIMER_PROFILING is not set -CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 -CONFIG_ESP_TIMER_IMPL_SYSTIMER=y -# end of High resolution timer (esp_timer) - -# -# Wi-Fi -# -CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 -CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 -# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set -CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y -CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 -CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 -# CONFIG_ESP32_WIFI_CSI_ENABLED is not set -CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y -CONFIG_ESP32_WIFI_TX_BA_WIN=6 -CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y -CONFIG_ESP32_WIFI_RX_BA_WIN=6 -CONFIG_ESP32_WIFI_NVS_ENABLED=y -CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 -CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 -# CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE is not set -CONFIG_ESP32_WIFI_IRAM_OPT=y -CONFIG_ESP32_WIFI_RX_IRAM_OPT=y -# CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE is not set -# end of Wi-Fi - -# -# PHY -# -# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set -CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 -CONFIG_ESP32_PHY_MAX_TX_POWER=20 -# end of PHY - -# -# Core dump -# -# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set -# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set -CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y -# end of Core dump - -# -# FAT Filesystem support -# -# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set -CONFIG_FATFS_CODEPAGE_437=y -# CONFIG_FATFS_CODEPAGE_720 is not set -# CONFIG_FATFS_CODEPAGE_737 is not set -# CONFIG_FATFS_CODEPAGE_771 is not set -# CONFIG_FATFS_CODEPAGE_775 is not set -# CONFIG_FATFS_CODEPAGE_850 is not set -# CONFIG_FATFS_CODEPAGE_852 is not set -# CONFIG_FATFS_CODEPAGE_855 is not set -# CONFIG_FATFS_CODEPAGE_857 is not set -# CONFIG_FATFS_CODEPAGE_860 is not set -# CONFIG_FATFS_CODEPAGE_861 is not set -# CONFIG_FATFS_CODEPAGE_862 is not set -# CONFIG_FATFS_CODEPAGE_863 is not set -# CONFIG_FATFS_CODEPAGE_864 is not set -# CONFIG_FATFS_CODEPAGE_865 is not set -# CONFIG_FATFS_CODEPAGE_866 is not set -# CONFIG_FATFS_CODEPAGE_869 is not set -# CONFIG_FATFS_CODEPAGE_932 is not set -# CONFIG_FATFS_CODEPAGE_936 is not set -# CONFIG_FATFS_CODEPAGE_949 is not set -# CONFIG_FATFS_CODEPAGE_950 is not set -CONFIG_FATFS_CODEPAGE=437 -CONFIG_FATFS_LFN_NONE=y -# CONFIG_FATFS_LFN_HEAP is not set -# CONFIG_FATFS_LFN_STACK is not set -CONFIG_FATFS_FS_LOCK=0 -CONFIG_FATFS_TIMEOUT_MS=10000 -CONFIG_FATFS_PER_FILE_CACHE=y -# end of FAT Filesystem support - -# -# Modbus configuration -# -CONFIG_FMB_COMM_MODE_RTU_EN=y -CONFIG_FMB_COMM_MODE_ASCII_EN=y -CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 -CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 -CONFIG_FMB_QUEUE_LENGTH=20 -CONFIG_FMB_SERIAL_TASK_STACK_SIZE=2048 -CONFIG_FMB_SERIAL_BUF_SIZE=256 -CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 -CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 -CONFIG_FMB_SERIAL_TASK_PRIO=10 -# CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT is not set -CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 -CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 -CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 -CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 -CONFIG_FMB_TIMER_PORT_ENABLED=y -CONFIG_FMB_TIMER_GROUP=0 -CONFIG_FMB_TIMER_INDEX=0 -# CONFIG_FMB_TIMER_ISR_IN_IRAM is not set -# end of Modbus configuration - -# -# FreeRTOS -# -CONFIG_FREERTOS_UNICORE=y -CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF -CONFIG_FREERTOS_CORETIMER_0=y -# CONFIG_FREERTOS_CORETIMER_1 is not set -CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y -CONFIG_FREERTOS_HZ=100 -CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y -# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set -# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set -CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y -# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set -CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y -CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 -CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y -# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set -# CONFIG_FREERTOS_ASSERT_DISABLE is not set -CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 -CONFIG_FREERTOS_ISR_STACKSIZE=1536 -# CONFIG_FREERTOS_LEGACY_HOOKS is not set -CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 -CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y -# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set -CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 -CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 -CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 -CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 -# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set -# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set -CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y -CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y -# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set -CONFIG_FREERTOS_DEBUG_OCDAWARE=y -# end of FreeRTOS - -# -# Heap memory debugging -# -CONFIG_HEAP_POISONING_DISABLED=y -# CONFIG_HEAP_POISONING_LIGHT is not set -# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set -CONFIG_HEAP_TRACING_OFF=y -# CONFIG_HEAP_TRACING_STANDALONE is not set -# CONFIG_HEAP_TRACING_TOHOST is not set -# end of Heap memory debugging - -# -# jsmn -# -# CONFIG_JSMN_PARENT_LINKS is not set -# CONFIG_JSMN_STRICT is not set -# end of jsmn - -# -# libsodium -# -# end of libsodium - -# -# Log output -# -# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set -# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set -# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set -CONFIG_LOG_DEFAULT_LEVEL_INFO=y -# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set -# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set -CONFIG_LOG_DEFAULT_LEVEL=3 -CONFIG_LOG_COLORS=y -CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y -# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set -# end of Log output - -# -# LWIP -# -CONFIG_LWIP_LOCAL_HOSTNAME="espressif" -CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y -# CONFIG_LWIP_L2_TO_L3_COPY is not set -# CONFIG_LWIP_IRAM_OPTIMIZATION is not set -CONFIG_LWIP_TIMERS_ONDEMAND=y -CONFIG_LWIP_MAX_SOCKETS=10 -# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set -CONFIG_LWIP_SO_REUSE=y -CONFIG_LWIP_SO_REUSE_RXTOALL=y -# CONFIG_LWIP_SO_RCVBUF is not set -# CONFIG_LWIP_NETBUF_RECVINFO is not set -CONFIG_LWIP_IP_FRAG=y -# CONFIG_LWIP_IP_REASSEMBLY is not set -# CONFIG_LWIP_STATS is not set -# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set -CONFIG_LWIP_ESP_GRATUITOUS_ARP=y -CONFIG_LWIP_GARP_TMR_INTERVAL=60 -CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 -CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y -# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set - -# -# DHCP server -# -CONFIG_LWIP_DHCPS_LEASE_UNIT=60 -CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 -# end of DHCP server - -# CONFIG_LWIP_AUTOIP is not set -# CONFIG_LWIP_IPV6_AUTOCONFIG is not set -CONFIG_LWIP_NETIF_LOOPBACK=y -CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 - -# -# TCP -# -CONFIG_LWIP_MAX_ACTIVE_TCP=16 -CONFIG_LWIP_MAX_LISTENING_TCP=16 -CONFIG_LWIP_TCP_MAXRTX=12 -CONFIG_LWIP_TCP_SYNMAXRTX=6 -CONFIG_LWIP_TCP_MSS=1440 -CONFIG_LWIP_TCP_TMR_INTERVAL=250 -CONFIG_LWIP_TCP_MSL=60000 -CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 -CONFIG_LWIP_TCP_WND_DEFAULT=5744 -CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 -CONFIG_LWIP_TCP_QUEUE_OOSEQ=y -# CONFIG_LWIP_TCP_SACK_OUT is not set -# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set -CONFIG_LWIP_TCP_OVERSIZE_MSS=y -# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set -# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set -# end of TCP - -# -# UDP -# -CONFIG_LWIP_MAX_UDP_PCBS=16 -CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 -# end of UDP - -CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 -CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y -# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set -CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF -# CONFIG_LWIP_PPP_SUPPORT is not set - -# -# ICMP -# -# CONFIG_LWIP_MULTICAST_PING is not set -# CONFIG_LWIP_BROADCAST_PING is not set -# end of ICMP - -# -# LWIP RAW API -# -CONFIG_LWIP_MAX_RAW_PCBS=16 -# end of LWIP RAW API - -# -# SNTP -# -CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 -CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 -# end of SNTP - -CONFIG_LWIP_ESP_LWIP_ASSERT=y -# end of LWIP - -# -# mbedTLS -# -CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y -# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set -# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set -CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y -CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 -CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 -# CONFIG_MBEDTLS_DEBUG is not set - -# -# Certificate Bundle -# -CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y -CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y -# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set -# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set -# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set -# end of Certificate Bundle - -# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set -# CONFIG_MBEDTLS_CMAC_C is not set -CONFIG_MBEDTLS_HARDWARE_AES=y -CONFIG_MBEDTLS_AES_USE_INTERRUPT=y -CONFIG_MBEDTLS_HARDWARE_GCM=y -CONFIG_MBEDTLS_HARDWARE_MPI=y -CONFIG_MBEDTLS_HARDWARE_SHA=y -CONFIG_MBEDTLS_HAVE_TIME=y -# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set -CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y -# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set -# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set -# CONFIG_MBEDTLS_TLS_DISABLED is not set -CONFIG_MBEDTLS_TLS_SERVER=y -CONFIG_MBEDTLS_TLS_CLIENT=y -CONFIG_MBEDTLS_TLS_ENABLED=y - -# -# TLS Key Exchange Methods -# -CONFIG_MBEDTLS_PSK_MODES=y -CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y -CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK=y -CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y -CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y -CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y -CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y -CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y -CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y -CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y -CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y -CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y -# end of TLS Key Exchange Methods - -CONFIG_MBEDTLS_SSL_RENEGOTIATION=y -# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set -CONFIG_MBEDTLS_SSL_PROTO_TLS1=y -CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y -CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y -CONFIG_MBEDTLS_SSL_PROTO_DTLS=y -CONFIG_MBEDTLS_SSL_ALPN=y -CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y -CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y - -# -# Symmetric Ciphers -# -CONFIG_MBEDTLS_AES_C=y -# CONFIG_MBEDTLS_CAMELLIA_C is not set -# CONFIG_MBEDTLS_DES_C is not set -CONFIG_MBEDTLS_RC4_DISABLED=y -# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set -# CONFIG_MBEDTLS_RC4_ENABLED is not set -# CONFIG_MBEDTLS_BLOWFISH_C is not set -# CONFIG_MBEDTLS_XTEA_C is not set -CONFIG_MBEDTLS_CCM_C=y -CONFIG_MBEDTLS_GCM_C=y -# end of Symmetric Ciphers - -# CONFIG_MBEDTLS_RIPEMD160_C is not set - -# -# Certificates -# -CONFIG_MBEDTLS_PEM_PARSE_C=y -CONFIG_MBEDTLS_PEM_WRITE_C=y -CONFIG_MBEDTLS_X509_CRL_PARSE_C=y -CONFIG_MBEDTLS_X509_CSR_PARSE_C=y -# end of Certificates - -CONFIG_MBEDTLS_ECP_C=y -CONFIG_MBEDTLS_ECDH_C=y -CONFIG_MBEDTLS_ECDSA_C=y -CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y -CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y -CONFIG_MBEDTLS_ECP_NIST_OPTIM=y -# CONFIG_MBEDTLS_SECURITY_RISKS is not set -# end of mbedTLS - -# -# mDNS -# -CONFIG_MDNS_MAX_SERVICES=10 -CONFIG_MDNS_TASK_PRIORITY=1 -# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set -CONFIG_MDNS_TASK_AFFINITY_CPU0=y -CONFIG_MDNS_TASK_AFFINITY=0x0 -CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 -CONFIG_MDNS_TIMER_PERIOD_MS=100 -# end of mDNS - -# -# ESP-MQTT Configurations -# -CONFIG_MQTT_PROTOCOL_311=y -CONFIG_MQTT_TRANSPORT_SSL=y -CONFIG_MQTT_TRANSPORT_WEBSOCKET=y -CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y -# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set -# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set -# CONFIG_MQTT_CUSTOM_OUTBOX is not set -# end of ESP-MQTT Configurations - -# -# Newlib -# -CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y -# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set -# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set -# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set -# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set -CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y -# CONFIG_NEWLIB_NANO_FORMAT is not set -# end of Newlib - -# -# NVS -# -# end of NVS - -# -# OpenSSL -# -# CONFIG_OPENSSL_DEBUG is not set -# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set -CONFIG_OPENSSL_ASSERT_EXIT=y -# end of OpenSSL - -# -# PThreads -# -CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 -CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 -CONFIG_PTHREAD_STACK_MIN=768 -CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 -CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" -# end of PThreads - -# -# SPI Flash driver -# -# CONFIG_SPI_FLASH_VERIFY_WRITE is not set -# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set -CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y -CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y -# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set -# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set -# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set - -# -# Auto-detect flash chips -# -CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y -CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y -# end of Auto-detect flash chips -# end of SPI Flash driver - -# -# SPIFFS Configuration -# -CONFIG_SPIFFS_MAX_PARTITIONS=3 - -# -# SPIFFS Cache Configuration -# -CONFIG_SPIFFS_CACHE=y -CONFIG_SPIFFS_CACHE_WR=y -# CONFIG_SPIFFS_CACHE_STATS is not set -# end of SPIFFS Cache Configuration - -CONFIG_SPIFFS_PAGE_CHECK=y -CONFIG_SPIFFS_GC_MAX_RUNS=10 -# CONFIG_SPIFFS_GC_STATS is not set -CONFIG_SPIFFS_PAGE_SIZE=256 -CONFIG_SPIFFS_OBJ_NAME_LEN=32 -# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set -CONFIG_SPIFFS_USE_MAGIC=y -CONFIG_SPIFFS_USE_MAGIC_LENGTH=y -CONFIG_SPIFFS_META_LENGTH=4 -CONFIG_SPIFFS_USE_MTIME=y - -# -# Debug Configuration -# -# CONFIG_SPIFFS_DBG is not set -# CONFIG_SPIFFS_API_DBG is not set -# CONFIG_SPIFFS_GC_DBG is not set -# CONFIG_SPIFFS_CACHE_DBG is not set -# CONFIG_SPIFFS_CHECK_DBG is not set -# CONFIG_SPIFFS_TEST_VISUALISATION is not set -# end of Debug Configuration -# end of SPIFFS Configuration - -# -# TinyUSB -# -# CONFIG_USB_ENABLED is not set - -# -# Descriptor configuration -# -CONFIG_USB_DESC_CUSTOM_VID=0x1234 -CONFIG_USB_DESC_CUSTOM_PID=0x5678 -# end of Descriptor configuration -# end of TinyUSB - -# -# Unity unit testing library -# -CONFIG_UNITY_ENABLE_FLOAT=y -CONFIG_UNITY_ENABLE_DOUBLE=y -# CONFIG_UNITY_ENABLE_COLOR is not set -CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y -# CONFIG_UNITY_ENABLE_FIXTURE is not set -# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set -# end of Unity unit testing library - -# -# Virtual file system -# -CONFIG_VFS_SUPPORT_IO=y -CONFIG_VFS_SUPPORT_DIR=y -CONFIG_VFS_SUPPORT_SELECT=y -CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y -CONFIG_VFS_SUPPORT_TERMIOS=y - -# -# Host File System I/O (Semihosting) -# -CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 -CONFIG_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 -# end of Host File System I/O (Semihosting) -# end of Virtual file system - -# -# Wear Levelling -# -# CONFIG_WL_SECTOR_SIZE_512 is not set -CONFIG_WL_SECTOR_SIZE_4096=y -CONFIG_WL_SECTOR_SIZE=4096 -# end of Wear Levelling - -# -# Wi-Fi Provisioning Manager -# -CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 -CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 -# end of Wi-Fi Provisioning Manager - -# -# Supplicant -# -CONFIG_WPA_MBEDTLS_CRYPTO=y -# CONFIG_WPA_DEBUG_PRINT is not set -# end of Supplicant -# end of Component config - -# -# Compatibility options -# -# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set -# end of Compatibility options - -# Deprecated options for backward compatibility -CONFIG_TOOLPREFIX="xtensa-esp32s2-elf-" -# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set -# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set -# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set -CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y -# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set -# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set -CONFIG_LOG_BOOTLOADER_LEVEL=3 -# CONFIG_APP_ROLLBACK_ENABLE is not set -# CONFIG_FLASH_ENCRYPTION_ENABLED is not set -# CONFIG_FLASHMODE_QIO is not set -# CONFIG_FLASHMODE_QOUT is not set -CONFIG_FLASHMODE_DIO=y -# CONFIG_FLASHMODE_DOUT is not set -# CONFIG_MONITOR_BAUD_9600B is not set -# CONFIG_MONITOR_BAUD_57600B is not set -CONFIG_MONITOR_BAUD_115200B=y -# CONFIG_MONITOR_BAUD_230400B is not set -# CONFIG_MONITOR_BAUD_921600B is not set -# CONFIG_MONITOR_BAUD_2MB is not set -# CONFIG_MONITOR_BAUD_OTHER is not set -CONFIG_MONITOR_BAUD_OTHER_VAL=115200 -CONFIG_MONITOR_BAUD=115200 -CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y -# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set -CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y -# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set -# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set -# CONFIG_CXX_EXCEPTIONS is not set -CONFIG_STACK_CHECK_NONE=y -# CONFIG_STACK_CHECK_NORM is not set -# CONFIG_STACK_CHECK_STRONG is not set -# CONFIG_STACK_CHECK_ALL is not set -# CONFIG_WARN_WRITE_STRINGS is not set -# CONFIG_DISABLE_GCC8_WARNINGS is not set -# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set -CONFIG_ESP32_APPTRACE_DEST_NONE=y -CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y -CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 -CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 -CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 -CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 -CONFIG_ADC2_DISABLE_DAC=y -CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 -CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_MAIN_TASK_STACK_SIZE=3584 -CONFIG_IPC_TASK_STACK_SIZE=1024 -CONFIG_CONSOLE_UART_DEFAULT=y -# CONFIG_CONSOLE_UART_CUSTOM is not set -# CONFIG_CONSOLE_UART_NONE is not set -CONFIG_CONSOLE_UART_NUM=0 -CONFIG_CONSOLE_UART_TX_GPIO=43 -CONFIG_CONSOLE_UART_RX_GPIO=44 -CONFIG_CONSOLE_UART_BAUDRATE=115200 -CONFIG_INT_WDT=y -CONFIG_INT_WDT_TIMEOUT_MS=300 -CONFIG_TASK_WDT=y -# CONFIG_TASK_WDT_PANIC is not set -CONFIG_TASK_WDT_TIMEOUT_S=5 -CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y -# CONFIG_EVENT_LOOP_PROFILING is not set -CONFIG_POST_EVENTS_FROM_ISR=y -CONFIG_POST_EVENTS_FROM_IRAM_ISR=y -# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set -CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y -# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set -# CONFIG_ESP32S2_PANIC_GDBSTUB is not set -CONFIG_TIMER_TASK_STACK_SIZE=3584 -CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 -CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 -CONFIG_MB_QUEUE_LENGTH=20 -CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 -CONFIG_MB_SERIAL_BUF_SIZE=256 -CONFIG_MB_SERIAL_TASK_PRIO=10 -# CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set -CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 -CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 -CONFIG_MB_CONTROLLER_STACK_SIZE=4096 -CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 -CONFIG_MB_TIMER_PORT_ENABLED=y -CONFIG_MB_TIMER_GROUP=0 -CONFIG_MB_TIMER_INDEX=0 -CONFIG_SUPPORT_STATIC_ALLOCATION=y -# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set -CONFIG_TIMER_TASK_PRIORITY=1 -CONFIG_TIMER_TASK_STACK_DEPTH=2048 -CONFIG_TIMER_QUEUE_LENGTH=10 -# CONFIG_L2_TO_L3_COPY is not set -# CONFIG_USE_ONLY_LWIP_SELECT is not set -CONFIG_ESP_GRATUITOUS_ARP=y -CONFIG_GARP_TMR_INTERVAL=60 -CONFIG_TCPIP_RECVMBOX_SIZE=32 -CONFIG_TCP_MAXRTX=12 -CONFIG_TCP_SYNMAXRTX=6 -CONFIG_TCP_MSS=1440 -CONFIG_TCP_MSL=60000 -CONFIG_TCP_SND_BUF_DEFAULT=5744 -CONFIG_TCP_WND_DEFAULT=5744 -CONFIG_TCP_RECVMBOX_SIZE=6 -CONFIG_TCP_QUEUE_OOSEQ=y -# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set -CONFIG_TCP_OVERSIZE_MSS=y -# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set -# CONFIG_TCP_OVERSIZE_DISABLE is not set -CONFIG_UDP_RECVMBOX_SIZE=6 -CONFIG_TCPIP_TASK_STACK_SIZE=3072 -CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y -# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set -CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF -# CONFIG_PPP_SUPPORT is not set -CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 -CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 -CONFIG_ESP32_PTHREAD_STACK_MIN=768 -CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 -CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" -CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y -# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set -# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set -CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y -CONFIG_SUPPORT_TERMIOS=y -# End of deprecated options diff --git a/examples/device/cdc_msc_freertos/sdkconfig.defaults b/examples/device/cdc_msc_freertos/sdkconfig.defaults new file mode 100644 index 000000000..34991d70c --- /dev/null +++ b/examples/device/cdc_msc_freertos/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET="esp32s2" +CONFIG_IDF_TARGET_ESP32S2=y + From 6a9f9718821138ca0f667246406444bc957c2424 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 13:42:48 +0700 Subject: [PATCH 26/61] add saola button pin support, esp32 build with board_test --- examples/device/board_test/CMakeLists.txt | 14 ++++++++++++++ examples/device/board_test/sdkconfig.defaults | 4 ++++ examples/device/board_test/src/CMakeLists.txt | 19 +++++++++++++++++++ examples/device/board_test/src/main.c | 7 +++++++ examples/device/board_test/src/tusb_config.h | 5 ++++- .../device/cdc_msc_freertos/CMakeLists.txt | 4 ++++ .../cdc_msc_freertos/src/CMakeLists.txt | 4 ---- hw/bsp/esp32s2_saola/esp32s2_saola.c | 12 ++++++++++-- 8 files changed, 62 insertions(+), 7 deletions(-) create mode 100644 examples/device/board_test/CMakeLists.txt create mode 100644 examples/device/board_test/sdkconfig.defaults create mode 100644 examples/device/board_test/src/CMakeLists.txt diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt new file mode 100644 index 000000000..1d8f2fe32 --- /dev/null +++ b/examples/device/board_test/CMakeLists.txt @@ -0,0 +1,14 @@ +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +# example src directory +set(EXTRA_COMPONENT_DIRS "src") + +# TOP is absolute path to root directory of TinyUSB git repo +set(TOP "../../..") +get_filename_component(TOP "${TOP}" REALPATH) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(board_test) diff --git a/examples/device/board_test/sdkconfig.defaults b/examples/device/board_test/sdkconfig.defaults new file mode 100644 index 000000000..34991d70c --- /dev/null +++ b/examples/device/board_test/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET="esp32s2" +CONFIG_IDF_TARGET_ESP32S2=y + diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt new file mode 100644 index 000000000..66746502c --- /dev/null +++ b/examples/device/board_test/src/CMakeLists.txt @@ -0,0 +1,19 @@ +idf_component_register(SRCS "main.c" + INCLUDE_DIRS "." + REQUIRES freertos soc) + +target_compile_options(${COMPONENT_TARGET} PUBLIC + "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" + "-DCFG_TUSB_OS=OPT_OS_FREERTOS" +) + +idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) +target_include_directories(${COMPONENT_TARGET} PUBLIC + "${FREERTOS_ORIG_INCLUDE_PATH}" + "${TOP}/hw" + "${TOP}/src" +) + +target_sources(${COMPONENT_TARGET} PUBLIC + "${TOP}/hw/bsp/esp32s2_saola/esp32s2_saola.c" +) diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 584ff799d..71665550f 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -73,3 +73,10 @@ int main(void) return 0; } + +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 +void app_main(void) +{ + main(); +} +#endif diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 1a52cc348..0587d48e3 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -39,8 +39,11 @@ #error CFG_TUSB_MCU must be defined #endif +#ifndef CFG_TUSB_OS + #define CFG_TUSB_OS OPT_OS_NONE +#endif + #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE -#define CFG_TUSB_OS OPT_OS_NONE // CFG_TUSB_DEBUG is defined by compiler in DEBUG build // #define CFG_TUSB_DEBUG 0 diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index f2e711944..2f1f6a950 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -5,6 +5,10 @@ cmake_minimum_required(VERSION 3.5) # example src directory set(EXTRA_COMPONENT_DIRS "src") +# TOP is absolute path to root directory of TinyUSB git repo +set(TOP "../../..") +get_filename_component(TOP "${TOP}" REALPATH) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(cdc_msc_freertos) diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index 3d2010ed2..d24bc2e41 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -1,7 +1,3 @@ -# TOP is absolute path to root directory of TinyUSB git repo -set(TOP "../../../..") -get_filename_component(TOP "${TOP}" REALPATH) - idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c" INCLUDE_DIRS "." REQUIRES freertos soc) diff --git a/hw/bsp/esp32s2_saola/esp32s2_saola.c b/hw/bsp/esp32s2_saola/esp32s2_saola.c index 06590c684..16d054f75 100644 --- a/hw/bsp/esp32s2_saola/esp32s2_saola.c +++ b/hw/bsp/esp32s2_saola/esp32s2_saola.c @@ -32,7 +32,10 @@ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -#define LED_PIN 21 +#define LED_PIN 21 + +#define BUTTON_PIN 0 +#define BUTTON_STATE_ACTIVE 0 // Initialize on-board peripherals : led, button, uart and USB void board_init(void) @@ -41,6 +44,11 @@ void board_init(void) gpio_pad_select_gpio(LED_PIN); gpio_set_direction(LED_PIN, GPIO_MODE_OUTPUT); + // Button + gpio_pad_select_gpio(BUTTON_PIN); + gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT); + gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY); + // USB Controller Hal init usb_hal_context_t hal = { .use_external_phy = false // use built-in PHY @@ -58,7 +66,7 @@ void board_led_write(bool state) // a '1' means active (pressed), a '0' means inactive. uint32_t board_button_read(void) { - return 0; + return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE; } // Get characters from UART From 3c724251f01300601e197f7b6646a5968b1d98df Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 13:45:26 +0700 Subject: [PATCH 27/61] clean up --- examples/device/cdc_msc_freertos/src/main.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index f673a7932..350358a68 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -88,10 +88,8 @@ int main(void) // Create a task for tinyusb device stack (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, stack_usbd, &static_task_usbd); - // Create task -#if CFG_TUD_CDC + // Create CDC task (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, stack_cdc, &static_task_cdc); -#endif // skip starting scheduler (and return) for ESP32-S2 #if CFG_TUSB_MCU != OPT_MCU_ESP32S2 @@ -151,7 +149,6 @@ void tud_resume_cb(void) //--------------------------------------------------------------------+ // USB CDC //--------------------------------------------------------------------+ -#if CFG_TUD_CDC void cdc_task(void* params) { (void) params; @@ -204,8 +201,6 @@ void tud_cdc_rx_cb(uint8_t itf) (void) itf; } -#endif // CFG_TUD_CDC - //--------------------------------------------------------------------+ // BLINKING TASK //--------------------------------------------------------------------+ From 73941137481e64897ee18fe63a7829dbed9af9d5 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 15:34:05 +0700 Subject: [PATCH 28/61] example clean up --- examples/device/cdc_msc_freertos/src/main.c | 45 ++++++++++--------- .../cdc_msc_freertos/src/usb_descriptors.h | 34 -------------- examples/device/hid_composite/src/main.c | 1 - 3 files changed, 23 insertions(+), 57 deletions(-) delete mode 100644 examples/device/cdc_msc_freertos/src/usb_descriptors.h diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 350358a68..d7217f964 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -52,18 +52,18 @@ enum { }; // static timer -StaticTimer_t static_blink; -TimerHandle_t blink_tm; +StaticTimer_t blinky_tmdef; +TimerHandle_t blinky_tm; // static task for usbd #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) -StackType_t stack_usbd[USBD_STACK_SIZE]; -StaticTask_t static_task_usbd; +StackType_t usb_device_stack[USBD_STACK_SIZE]; +StaticTask_t usb_device_taskdef; // static task for cdc #define CDC_STACK_SZIE configMINIMAL_STACK_SIZE -StackType_t stack_cdc[CDC_STACK_SZIE]; -StaticTask_t static_task_cdc; +StackType_t cdc_stack[CDC_STACK_SZIE]; +StaticTask_t cdc_taskdef; void led_blinky_cb(TimerHandle_t xTimer); @@ -71,25 +71,20 @@ void usb_device_task(void* param); void cdc_task(void* params); /*------------- MAIN -------------*/ -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 -void app_main(void) -#else int main(void) -#endif { board_init(); - - // soft timer for blinky - blink_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &static_blink); - xTimerStart(blink_tm, 0); - tusb_init(); + // soft timer for blinky + blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); + xTimerStart(blinky_tm, 0); + // Create a task for tinyusb device stack - (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, stack_usbd, &static_task_usbd); + (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); // Create CDC task - (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, stack_cdc, &static_task_cdc); + (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); // skip starting scheduler (and return) for ESP32-S2 #if CFG_TUSB_MCU != OPT_MCU_ESP32S2 @@ -97,9 +92,15 @@ int main(void) NVIC_SystemReset(); return 0; #endif - } +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 +void app_main(void) +{ + main(); +} +#endif + // USB Device Driver task // This top level thread process all usb events and invoke callbacks void usb_device_task(void* param) @@ -121,13 +122,13 @@ void usb_device_task(void* param) // Invoked when device is mounted void tud_mount_cb(void) { - xTimerChangePeriod(blink_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); } // Invoked when device is unmounted void tud_umount_cb(void) { - xTimerChangePeriod(blink_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); } // Invoked when usb bus is suspended @@ -136,13 +137,13 @@ void tud_umount_cb(void) void tud_suspend_cb(bool remote_wakeup_en) { (void) remote_wakeup_en; - xTimerChangePeriod(blink_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0); + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0); } // Invoked when usb bus is resumed void tud_resume_cb(void) { - xTimerChangePeriod(blink_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); } diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.h b/examples/device/cdc_msc_freertos/src/usb_descriptors.h deleted file mode 100644 index 6992d3349..000000000 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef USB_DESCRIPTORS_H_ -#define USB_DESCRIPTORS_H_ - -enum -{ - REPORT_ID_KEYBOARD = 1, - REPORT_ID_MOUSE -}; - -#endif /* USB_DESCRIPTORS_H_ */ diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index 4529e24f1..7207e4d4c 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -56,7 +56,6 @@ void hid_task(void); int main(void) { board_init(); - tusb_init(); while (1) From ccfc058646ef214836de3186b4e48ef22e4117c9 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 16:19:47 +0700 Subject: [PATCH 29/61] add hid_composite_freertos example --- examples/device/cdc_msc_freertos/src/main.c | 6 +- .../device/hid_composite_freertos/Makefile | 27 ++ .../src/FreeRTOSConfig.h | 233 ++++++++++++++++ .../src/freertos_hook.c | 95 +++++++ .../device/hid_composite_freertos/src/main.c | 251 ++++++++++++++++++ .../hid_composite_freertos/src/tusb_config.h | 90 +++++++ .../src/usb_descriptors.c | 169 ++++++++++++ .../src/usb_descriptors.h | 34 +++ 8 files changed, 903 insertions(+), 2 deletions(-) create mode 100644 examples/device/hid_composite_freertos/Makefile create mode 100644 examples/device/hid_composite_freertos/src/FreeRTOSConfig.h create mode 100644 examples/device/hid_composite_freertos/src/freertos_hook.c create mode 100644 examples/device/hid_composite_freertos/src/main.c create mode 100644 examples/device/hid_composite_freertos/src/tusb_config.h create mode 100644 examples/device/hid_composite_freertos/src/usb_descriptors.c create mode 100644 examples/device/hid_composite_freertos/src/usb_descriptors.h diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index d7217f964..f093d8ea0 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -70,7 +70,10 @@ void led_blinky_cb(TimerHandle_t xTimer); void usb_device_task(void* param); void cdc_task(void* params); -/*------------- MAIN -------------*/ +//--------------------------------------------------------------------+ +// Main +//--------------------------------------------------------------------+ + int main(void) { board_init(); @@ -146,7 +149,6 @@ void tud_resume_cb(void) xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); } - //--------------------------------------------------------------------+ // USB CDC //--------------------------------------------------------------------+ diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile new file mode 100644 index 000000000..cef1af5a6 --- /dev/null +++ b/examples/device/hid_composite_freertos/Makefile @@ -0,0 +1,27 @@ +include ../../../tools/top.mk +include ../../make.mk + +FREERTOS_SRC = lib/FreeRTOS/FreeRTOS/Source + +INC += \ + src \ + $(TOP)/hw \ + $(TOP)/$(FREERTOS_SRC)/include \ + $(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT) + +# Example source +EXAMPLE_SOURCE += $(wildcard src/*.c) +SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) + +# FreeRTOS source, all files in port folder +SRC_C += \ + $(FREERTOS_SRC)/list.c \ + $(FREERTOS_SRC)/queue.c \ + $(FREERTOS_SRC)/tasks.c \ + $(FREERTOS_SRC)/timers.c \ + $(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c)) + +# FreeRTOS (lto + Os) linker issue +LDFLAGS += -Wl,--undefined=vTaskSwitchContext + +include ../../rules.mk diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h new file mode 100644 index 000000000..0945baf1f --- /dev/null +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h @@ -0,0 +1,233 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// for OPT_MCU_ +#include "tusb_option.h" + +#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || \ + CFG_TUSB_MCU == OPT_MCU_LPC15XX || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \ + CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ + CFG_TUSB_MCU == OPT_MCU_LPC40XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX + #include "chip.h" + +#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ + CFG_TUSB_MCU == OPT_MCU_LPC55XX + #include "fsl_device_registers.h" + +#elif CFG_TUSB_MCU == OPT_MCU_NRF5X + #include "nrf.h" + +#elif CFG_TUSB_MCU == OPT_MCU_SAMD21 || CFG_TUSB_MCU == OPT_MCU_SAMD51 + #include "sam.h" + +#elif CFG_TUSB_MCU == OPT_MCU_SAMG + #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined + #include "sam.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F0 + #include "stm32f0xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 + #include "stm32f1xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F2 + #include "stm32f2xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F3 + #include "stm32f3xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F4 + #include "stm32f4xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 + #include "stm32f7xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32H7 + #include "stm32h7xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L0 + #include "stm32l0xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L1 + #include "stm32l1xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 + #include "stm32l4xx.h" + +#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + #include "fsl_device_registers.h" + +#elif CFG_TUSB_MCU == OPT_MCU_NUC120 + #include "NUC100Series.h" + +#elif CFG_TUSB_MCU == OPT_MCU_NUC121 || CFG_TUSB_MCU == OPT_MCU_NUC126 + #include "NuMicro.h" + +#elif CFG_TUSB_MCU == OPT_MCU_NUC505 + #include "NUC505Series.h" + +#else + #error "FreeRTOSConfig.h need to include low level mcu header for configuration" +#endif + +extern uint32_t SystemCoreClock; + + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( 0*1024 ) // dynamic is not used +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 2 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in core_cmx.h */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #error "This port requires __NVIC_PRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" +#include "semphr.h" + +#include "bsp/board.h" +#include "tusb.h" + +#include "usb_descriptors.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTYPES +//--------------------------------------------------------------------+ + +/* Blink pattern + * - 250 ms : device not mounted + * - 1000 ms : device mounted + * - 2500 ms : device is suspended + */ +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; + +// static timer +StaticTimer_t blinky_tmdef; +TimerHandle_t blinky_tm; + +// static task for usbd +#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) +StackType_t usb_device_stack[USBD_STACK_SIZE]; +StaticTask_t usb_device_taskdef; + +// static task for hid +#define HID_STACK_SZIE configMINIMAL_STACK_SIZE +StackType_t hid_stack[HID_STACK_SZIE]; +StaticTask_t hid_taskdef; + + +void led_blinky_cb(TimerHandle_t xTimer); +void usb_device_task(void* param); +void hid_task(void* params); + +//--------------------------------------------------------------------+ +// Main +//--------------------------------------------------------------------+ + +int main(void) +{ + board_init(); + tusb_init(); + + // soft timer for blinky + blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); + xTimerStart(blinky_tm, 0); + + // Create a task for tinyusb device stack + (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); + + // Create HID task + (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef); + + // skip starting scheduler (and return) for ESP32-S2 +#if CFG_TUSB_MCU != OPT_MCU_ESP32S2 + vTaskStartScheduler(); + NVIC_SystemReset(); + return 0; +#endif +} + +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 +void app_main(void) +{ + main(); +} +#endif + +// USB Device Driver task +// This top level thread process all usb events and invoke callbacks +void usb_device_task(void* param) +{ + (void) param; + + // RTOS forever loop + while (1) + { + // tinyusb device task + tud_task(); + } +} + +//--------------------------------------------------------------------+ +// Device callbacks +//--------------------------------------------------------------------+ + +// Invoked when device is mounted +void tud_mount_cb(void) +{ + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); +} + +// Invoked when device is unmounted +void tud_umount_cb(void) +{ + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); +} + +// Invoked when usb bus is suspended +// remote_wakeup_en : if host allow us to perform remote wakeup +// Within 7ms, device must draw an average of current less than 2.5 mA from bus +void tud_suspend_cb(bool remote_wakeup_en) +{ + (void) remote_wakeup_en; + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0); +} + +// Invoked when usb bus is resumed +void tud_resume_cb(void) +{ + xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); +} + +//--------------------------------------------------------------------+ +// USB HID +//--------------------------------------------------------------------+ + +void hid_task(void* param) +{ + (void) param; + + while(1) + { + // Poll every 10ms + vTaskDelay(pdMS_TO_TICKS(10)); + + uint32_t const btn = board_button_read(); + + // Remote wakeup + if ( tud_suspended() && btn ) + { + // Wake up host if we are in suspend mode + // and REMOTE_WAKEUP feature is enabled by host + tud_remote_wakeup(); + } + + /*------------- Mouse -------------*/ + if ( tud_hid_ready() ) + { + if ( btn ) + { + int8_t const delta = 5; + + // no button, right + down, no scroll pan + tud_hid_mouse_report(REPORT_ID_MOUSE, 0x00, delta, delta, 0, 0); + + // delay a bit before attempt to send keyboard report + vTaskDelay(pdMS_TO_TICKS(10)); + } + } + + /*------------- Keyboard -------------*/ + if ( tud_hid_ready() ) + { + // use to avoid send multiple consecutive zero report for keyboard + static bool has_key = false; + + if ( btn ) + { + uint8_t keycode[6] = { 0 }; + keycode[0] = HID_KEY_A; + + tud_hid_keyboard_report(REPORT_ID_KEYBOARD, 0, keycode); + + has_key = true; + }else + { + // send empty key report if previously has key pressed + if (has_key) tud_hid_keyboard_report(REPORT_ID_KEYBOARD, 0, NULL); + has_key = false; + } + } + } +} + +// Invoked when received GET_REPORT control request +// Application must fill buffer report's content and return its length. +// Return zero will cause the stack to STALL request +uint16_t tud_hid_get_report_cb(uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen) +{ + // TODO not Implemented + (void) report_id; + (void) report_type; + (void) buffer; + (void) reqlen; + + return 0; +} + +// Invoked when received SET_REPORT control request or +// received data on OUT endpoint ( Report ID = 0, Type = 0 ) +void tud_hid_set_report_cb(uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize) +{ + // TODO set LED based on CAPLOCK, NUMLOCK etc... + (void) report_id; + (void) report_type; + (void) buffer; + (void) bufsize; +} + +//--------------------------------------------------------------------+ +// BLINKING TASK +//--------------------------------------------------------------------+ +void led_blinky_cb(TimerHandle_t xTimer) +{ + (void) xTimer; + static bool led_state = false; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle +} diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h new file mode 100644 index 000000000..e7aea1863 --- /dev/null +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -0,0 +1,90 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU + #error CFG_TUSB_MCU must be defined +#endif + +#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_NUC505 +#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED) +#else +#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#endif + +#define CFG_TUSB_OS OPT_OS_FREERTOS + +// CFG_TUSB_DEBUG is defined by compiler in DEBUG build +// #define CFG_TUSB_DEBUG 0 + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_HID 1 +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 + +// HID buffer size Should be sufficient to hold ID (if any) + Data +#define CFG_TUD_HID_BUFSIZE 16 + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c new file mode 100644 index 000000000..6bde2ff7a --- /dev/null +++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c @@ -0,0 +1,169 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "tusb.h" +#include "usb_descriptors.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] HID | MSC | CDC [LSB] + */ +#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) ) +#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = +{ + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const * tud_descriptor_device_cb(void) +{ + return (uint8_t const *) &desc_device; +} + +//--------------------------------------------------------------------+ +// HID Report Descriptor +//--------------------------------------------------------------------+ + +uint8_t const desc_hid_report[] = +{ + TUD_HID_REPORT_DESC_KEYBOARD( HID_REPORT_ID(REPORT_ID_KEYBOARD), ), + TUD_HID_REPORT_DESC_MOUSE ( HID_REPORT_ID(REPORT_ID_MOUSE), ) +}; + +// Invoked when received GET HID REPORT DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_hid_descriptor_report_cb(void) +{ + return desc_hid_report; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +enum +{ + ITF_NUM_HID, + ITF_NUM_TOTAL +}; + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_HID_DESC_LEN) + +#define EPNUM_HID 0x81 + +uint8_t const desc_configuration[] = +{ + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, protocol, report descriptor len, EP In & Out address, size & polling interval + TUD_HID_DESCRIPTOR(ITF_NUM_HID, 0, HID_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, CFG_TUD_HID_BUFSIZE, 10) +}; + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + return desc_configuration; +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// array of pointer to string descriptors +char const* string_desc_arr [] = +{ + (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + "123456", // 3: Serials, should use chip ID +}; + +static uint16_t _desc_str[32]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) +{ + (void) langid; + + uint8_t chr_count; + + if ( index == 0) + { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + }else + { + // Convert ASCII string into UTF-16 + + if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL; + + const char* str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + if ( chr_count > 31 ) chr_count = 31; + + for(uint8_t i=0; i Date: Tue, 7 Apr 2020 16:23:27 +0700 Subject: [PATCH 30/61] skip freertos example for cxd56 msp430 and fomu --- examples/device/hid_composite_freertos/.skip.MCU_CXD56 | 0 examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx | 0 .../device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI | 0 tools/build_all.py | 4 ++-- 4 files changed, 2 insertions(+), 2 deletions(-) create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_CXD56 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI diff --git a/examples/device/hid_composite_freertos/.skip.MCU_CXD56 b/examples/device/hid_composite_freertos/.skip.MCU_CXD56 new file mode 100644 index 000000000..e69de29bb diff --git a/examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx b/examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx new file mode 100644 index 000000000..e69de29bb diff --git a/examples/device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI b/examples/device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI new file mode 100644 index 000000000..e69de29bb diff --git a/tools/build_all.py b/tools/build_all.py index c78192d63..25cdc9778 100644 --- a/tools/build_all.py +++ b/tools/build_all.py @@ -11,8 +11,8 @@ exit_status = 0 total_time = time.monotonic() -build_format = '| {:20} | {:30} | {:9} | {:7} | {:6} | {:6} |' -build_separator = '-' * 97 +build_format = '| {:23} | {:30} | {:9} | {:7} | {:6} | {:6} |' +build_separator = '-' * 100 # 1st Argument is Example, build all examples if not existed all_examples = [] From 62c14a686654db7ee34ac88c1dcf33d67736da4c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 16:35:02 +0700 Subject: [PATCH 31/61] esp32s2 work with hid_composite_freertos --- .../cdc_msc_freertos/src/CMakeLists.txt | 3 +- .../hid_composite_freertos/CMakeLists.txt | 14 +++++++++ .../hid_composite_freertos/sdkconfig.defaults | 4 +++ .../hid_composite_freertos/src/CMakeLists.txt | 31 +++++++++++++++++++ 4 files changed, 50 insertions(+), 2 deletions(-) create mode 100644 examples/device/hid_composite_freertos/CMakeLists.txt create mode 100644 examples/device/hid_composite_freertos/sdkconfig.defaults create mode 100644 examples/device/hid_composite_freertos/src/CMakeLists.txt diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index d24bc2e41..ab4c1aa6d 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -1,7 +1,7 @@ idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c" INCLUDE_DIRS "." REQUIRES freertos soc) - + target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" ) @@ -29,4 +29,3 @@ target_sources(${COMPONENT_TARGET} PUBLIC "${TOP}/src/class/vendor/vendor_device.c" "${TOP}/src/portable/espressif/esp32s2/dcd_esp32s2.c" ) - diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt new file mode 100644 index 000000000..ebc087b22 --- /dev/null +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -0,0 +1,14 @@ +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +# example src directory +set(EXTRA_COMPONENT_DIRS "src") + +# TOP is absolute path to root directory of TinyUSB git repo +set(TOP "../../..") +get_filename_component(TOP "${TOP}" REALPATH) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(hid_composite_freertos) diff --git a/examples/device/hid_composite_freertos/sdkconfig.defaults b/examples/device/hid_composite_freertos/sdkconfig.defaults new file mode 100644 index 000000000..34991d70c --- /dev/null +++ b/examples/device/hid_composite_freertos/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET="esp32s2" +CONFIG_IDF_TARGET_ESP32S2=y + diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt new file mode 100644 index 000000000..fbe5f6389 --- /dev/null +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -0,0 +1,31 @@ +idf_component_register(SRCS "main.c" "usb_descriptors.c" + INCLUDE_DIRS "." + REQUIRES freertos soc) + +target_compile_options(${COMPONENT_TARGET} PUBLIC + "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" +) + +idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) +target_include_directories(${COMPONENT_TARGET} PUBLIC + "${FREERTOS_ORIG_INCLUDE_PATH}" + "${TOP}/hw" + "${TOP}/src" +) + +target_sources(${COMPONENT_TARGET} PUBLIC + "${TOP}/hw/bsp/esp32s2_saola/esp32s2_saola.c" + "${TOP}/src/tusb.c" + "${TOP}/src/common/tusb_fifo.c" + "${TOP}/src/device/usbd.c" + "${TOP}/src/device/usbd_control.c" + "${TOP}/src/class/cdc/cdc_device.c" + "${TOP}/src/class/dfu/dfu_rt_device.c" + "${TOP}/src/class/hid/hid_device.c" + "${TOP}/src/class/midi/midi_device.c" + "${TOP}/src/class/msc/msc_device.c" + "${TOP}/src/class/net/net_device.c" + "${TOP}/src/class/usbtmc/usbtmc_device.c" + "${TOP}/src/class/vendor/vendor_device.c" + "${TOP}/src/portable/espressif/esp32s2/dcd_esp32s2.c" +) From 353aa8081495e0a5ccf970513bbcff495dc5f71d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 16:49:17 +0700 Subject: [PATCH 32/61] add ci build_esp32s.py --- .github/workflows/build.yml | 5 +- tools/build_esp32s.py | 100 ++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 tools/build_esp32s.py diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 584ee1d70..0174b9cb7 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -27,7 +27,7 @@ jobs: fail-fast: false matrix: example: ['board_test', 'cdc_dual_ports', 'cdc_msc', 'cdc_msc_freertos', 'dfu_rt', - 'hid_composite', 'hid_generic_inout', 'midi_test', 'msc_dual_lun', 'net_lwip_webserver', + 'hid_composite', 'hid_composite_freertos', 'hid_generic_inout', 'midi_test', 'msc_dual_lun', 'net_lwip_webserver', 'usbtmc', 'webusb_serial'] steps: - name: Setup Python @@ -97,5 +97,4 @@ jobs: - name: Build run: | . $HOME/esp-idf/export.sh - cd examples/device/cdc_msc_freertos - idf.py build + python3 tools/build_esp32s.py diff --git a/tools/build_esp32s.py b/tools/build_esp32s.py new file mode 100644 index 000000000..33b122ea6 --- /dev/null +++ b/tools/build_esp32s.py @@ -0,0 +1,100 @@ +import os +import glob +import sys +import subprocess +import time + +success_count = 0 +fail_count = 0 +skip_count = 0 +exit_status = 0 + +total_time = time.monotonic() + +build_format = '| {:23} | {:30} | {:9} | {:7} | {:6} | {:6} |' +build_separator = '-' * 100 + +# 1st Argument is Example, build all examples if not existed +all_examples = [] +if len(sys.argv) > 1: + all_examples.append(sys.argv[1]) +else: + for entry in os.scandir("examples/device"): + # Only includes example with CMakeLists.txt for esp32s + if entry.is_dir() and os.path.exists(entry.path + "/CMakeLists.txt"): + all_examples.append(entry.name) +all_examples.sort() + +# 2nd Argument is Board, build all boards if not existed +all_boards = [] +if len(sys.argv) > 2: + all_boards.append(sys.argv[2]) +else: + for entry in os.scandir("hw/bsp"): + if entry.is_dir(): + with open(entry.path + '/board.mk') as mk: + # Only includes ESP32-S2 board + if 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk.read(): + all_boards.append(entry.name) + +all_boards.sort() + +def build_example(example, board): + subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, + stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + return subprocess.run("make -j 4 -C examples/device/{} BOARD={} all".format(example, board), shell=True, + stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + +def build_size(example, board): + #elf_file = 'examples/device/{}/_build/build-{}/{}-firmware.elf'.format(example, board, board) + elf_file = 'examples/device/{}/_build/build-{}/*.elf'.format(example, board) + size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8") + size_list = size_output.split('\n')[1].split('\t') + flash_size = int(size_list[0]) + sram_size = int(size_list[1]) + int(size_list[2]) + return (flash_size, sram_size) + +def skip_example(example, board): + return 0 + +print(build_separator) +print(build_format.format('Example', 'Board', 'Result', 'Time', 'Flash', 'SRAM')) + +for example in all_examples: + for board in all_boards: + start_time = time.monotonic() + + flash_size = "-" + sram_size = "-" + + # Check if board is skipped + if skip_example(example, board): + success = "\033[33mskipped\033[0m " + skip_count += 1 + print(build_format.format(example, board, success, '-', flash_size, sram_size)) + else: + build_result = build_example(example, board) + + if build_result.returncode == 0: + success = "\033[32msucceeded\033[0m" + success_count += 1 + (flash_size, sram_size) = build_size(example, board) + else: + exit_status = build_result.returncode + success = "\033[31mfailed\033[0m " + fail_count += 1 + + build_duration = time.monotonic() - start_time + print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size)) + + if build_result.returncode != 0: + print(build_result.stdout.decode("utf-8")) + + + +total_time = time.monotonic() - total_time +print(build_separator) +print("Build Sumamary: {} \033[32msucceeded\033[0m, {} \033[31mfailed\033[0m, {} \033[33mskipped\033[0m and took {:.2f}s".format(success_count, fail_count, skip_count, total_time)) +print(build_separator) + +sys.exit(exit_status) From 4265dfb2dea33deb495e630f5085d190634bc11e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 21:47:24 +0700 Subject: [PATCH 33/61] minor clean up --- tools/build_esp32s.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/build_esp32s.py b/tools/build_esp32s.py index 33b122ea6..0708ced80 100644 --- a/tools/build_esp32s.py +++ b/tools/build_esp32s.py @@ -59,6 +59,7 @@ def skip_example(example, board): print(build_separator) print(build_format.format('Example', 'Board', 'Result', 'Time', 'Flash', 'SRAM')) +print(build_separator) for example in all_examples: for board in all_boards: From f6edb46c0a7fc9b32cf6931c4ba98b99d555de53 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 23:01:26 +0700 Subject: [PATCH 34/61] update docs for esp32s2 --- README.md | 1 + docs/boards.md | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/README.md b/README.md index 2bec2326e..86fd0d800 100644 --- a/README.md +++ b/README.md @@ -30,6 +30,7 @@ Special thanks to all the people who spent their precious time and effort to hel The stack supports the following MCUs: +- **Espressif:** ESP32-S2 - **MicroChip:** SAMD21, SAMD51 (device only) - **NordicSemi:** nRF52840, nRF52833 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505 diff --git a/docs/boards.md b/docs/boards.md index 558c6f97f..7a33bab8d 100644 --- a/docs/boards.md +++ b/docs/boards.md @@ -9,6 +9,10 @@ The board support code is only used for self-contained examples and testing. It This code base already had supported for a handful of following boards (sorted alphabetically) +### Espressif ESP32-S2 + +- [ESP32-S2-Saola-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html) + ### MicroChip SAMD - [Adafruit Circuit Playground Express](https://www.adafruit.com/product/3333) From a2dee7fb5041d19ace9078d295a2e4c95574d869 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Apr 2020 23:07:25 +0700 Subject: [PATCH 35/61] rename saola to saola_1 --- examples/device/board_test/src/CMakeLists.txt | 2 +- examples/device/cdc_msc_freertos/src/CMakeLists.txt | 2 +- examples/device/hid_composite_freertos/src/CMakeLists.txt | 2 +- hw/bsp/{esp32s2_saola => esp32s2_saola_1}/board.mk | 0 .../esp32s2_saola.c => esp32s2_saola_1/esp32s2_saola_1.c} | 0 5 files changed, 3 insertions(+), 3 deletions(-) rename hw/bsp/{esp32s2_saola => esp32s2_saola_1}/board.mk (100%) rename hw/bsp/{esp32s2_saola/esp32s2_saola.c => esp32s2_saola_1/esp32s2_saola_1.c} (100%) diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt index 66746502c..676159ac9 100644 --- a/examples/device/board_test/src/CMakeLists.txt +++ b/examples/device/board_test/src/CMakeLists.txt @@ -15,5 +15,5 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC ) target_sources(${COMPONENT_TARGET} PUBLIC - "${TOP}/hw/bsp/esp32s2_saola/esp32s2_saola.c" + "${TOP}/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c" ) diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index ab4c1aa6d..7f8eeca17 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -14,7 +14,7 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC ) target_sources(${COMPONENT_TARGET} PUBLIC - "${TOP}/hw/bsp/esp32s2_saola/esp32s2_saola.c" + "${TOP}/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c" "${TOP}/src/tusb.c" "${TOP}/src/common/tusb_fifo.c" "${TOP}/src/device/usbd.c" diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt index fbe5f6389..c674873b2 100644 --- a/examples/device/hid_composite_freertos/src/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -14,7 +14,7 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC ) target_sources(${COMPONENT_TARGET} PUBLIC - "${TOP}/hw/bsp/esp32s2_saola/esp32s2_saola.c" + "${TOP}/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c" "${TOP}/src/tusb.c" "${TOP}/src/common/tusb_fifo.c" "${TOP}/src/device/usbd.c" diff --git a/hw/bsp/esp32s2_saola/board.mk b/hw/bsp/esp32s2_saola_1/board.mk similarity index 100% rename from hw/bsp/esp32s2_saola/board.mk rename to hw/bsp/esp32s2_saola_1/board.mk diff --git a/hw/bsp/esp32s2_saola/esp32s2_saola.c b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c similarity index 100% rename from hw/bsp/esp32s2_saola/esp32s2_saola.c rename to hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c From 70df1aff132c691ae7d6ded98ffd20861ba9468d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Apr 2020 15:00:16 +0700 Subject: [PATCH 36/61] add TODO for saola on-board neopixel --- hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c index 16d054f75..ed855f727 100644 --- a/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c +++ b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c @@ -32,6 +32,7 @@ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ +// TODO use saola-1 on-board neopixel (WS2812) #define LED_PIN 21 #define BUTTON_PIN 0 From 7b7a78ab2e89a8f147bbe7210923a72560b601d8 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Apr 2020 15:29:12 +0700 Subject: [PATCH 37/61] disable SOF interrupt since it is not used for now --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 3361bde36..4cd682e12 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -42,6 +42,10 @@ #include "device/dcd.h" +// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) +// We disable SOF for now until needed later on +#define USE_SOF 0 + // FIFO size in bytes TODO need confirmation from Espressif #define EP_MAX USB_OUT_EP_NUM #define EP_FIFO_SIZE 1280 @@ -112,7 +116,7 @@ static void bus_reset(void) USB0.grxfsiz = 52; USB0.gintmsk = USB_MODEMISMSK_M | - USB_SOFMSK_M | + /* USB_SOFMSK_M | */ USB_RXFLVIMSK_M | USB_ERLYSUSPMSK_M | USB_USBSUSPMSK_M | @@ -154,7 +158,7 @@ static void enum_done_processing(void) xfer_status[0][TUSB_DIR_IN].max_size = 8; } - USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask +// USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask } @@ -202,7 +206,7 @@ void dcd_init(uint8_t rhport) USB0.gotgint = ~0U; //clear OTG ints USB0.gintsts = ~0U; //clear pending ints USB0.gintmsk = USB_MODEMISMSK_M | - USB_SOFMSK_M | + /*USB_SOFMSK_M |*/ USB_RXFLVIMSK_M | USB_ERLYSUSPMSK_M | USB_USBSUSPMSK_M | From 880595433ce6b75428dca30b72b41d865a4b89f4 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Apr 2020 15:41:16 +0700 Subject: [PATCH 38/61] use macro for easy enable/disable SOF --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 4cd682e12..8a11f57b0 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -116,7 +116,9 @@ static void bus_reset(void) USB0.grxfsiz = 52; USB0.gintmsk = USB_MODEMISMSK_M | - /* USB_SOFMSK_M | */ +#if USE_SOF + USB_SOFMSK_M | +#endif USB_RXFLVIMSK_M | USB_ERLYSUSPMSK_M | USB_USBSUSPMSK_M | @@ -157,8 +159,6 @@ static void enum_done_processing(void) xfer_status[0][TUSB_DIR_OUT].max_size = 8; xfer_status[0][TUSB_DIR_IN].max_size = 8; } - -// USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask } @@ -206,7 +206,9 @@ void dcd_init(uint8_t rhport) USB0.gotgint = ~0U; //clear OTG ints USB0.gintsts = ~0U; //clear pending ints USB0.gintmsk = USB_MODEMISMSK_M | - /*USB_SOFMSK_M |*/ +#if USE_SOF + USB_SOFMSK_M | +#endif USB_RXFLVIMSK_M | USB_ERLYSUSPMSK_M | USB_USBSUSPMSK_M | @@ -698,10 +700,12 @@ static void dcd_int_handler(void) dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); } +#if USE_SOF if (int_status & USB_SOF_M) { USB0.gintsts = USB_SOF_M; dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually } +#endif if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) { ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); From bfde988af3d848af7a5c29dee46030aa73630d43 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Apr 2020 23:20:05 +0700 Subject: [PATCH 39/61] update cmake --- examples/device/cdc_msc_freertos/CMakeLists.txt | 1 + examples/device/cdc_msc_freertos/src/CMakeLists.txt | 1 + examples/device/hid_composite_freertos/CMakeLists.txt | 1 + examples/device/hid_composite_freertos/src/CMakeLists.txt | 1 + 4 files changed, 4 insertions(+) diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 2f1f6a950..746270f10 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -10,5 +10,6 @@ set(TOP "../../..") get_filename_component(TOP "${TOP}" REALPATH) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(SUPPORTED_TARGETS esp32s2) project(cdc_msc_freertos) diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index 7f8eeca17..c757852a9 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -4,6 +4,7 @@ idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c" target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" + "-DCFG_TUSB_OS=OPT_OS_FREERTOS" ) idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt index ebc087b22..e5c265bf8 100644 --- a/examples/device/hid_composite_freertos/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -10,5 +10,6 @@ set(TOP "../../..") get_filename_component(TOP "${TOP}" REALPATH) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(SUPPORTED_TARGETS esp32s2) project(hid_composite_freertos) diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt index c674873b2..9e914e419 100644 --- a/examples/device/hid_composite_freertos/src/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -4,6 +4,7 @@ idf_component_register(SRCS "main.c" "usb_descriptors.c" target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" + "-DCFG_TUSB_OS=OPT_OS_FREERTOS" ) idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) From cefbd9579c7fb5a16a253d5d0f7c582142933c46 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Apr 2020 00:06:18 +0700 Subject: [PATCH 40/61] add neopixel led strip driver for saola, make saola as an component --- examples/device/board_test/CMakeLists.txt | 7 +- examples/device/board_test/src/CMakeLists.txt | 4 - hw/bsp/esp32s2_saola_1/CMakeLists.txt | 16 ++ hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c | 30 ++- .../led_strip/include/led_strip.h | 126 +++++++++++++ .../led_strip/src/led_strip_rmt_ws2812.c | 171 ++++++++++++++++++ 6 files changed, 340 insertions(+), 14 deletions(-) create mode 100644 hw/bsp/esp32s2_saola_1/CMakeLists.txt create mode 100644 hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h create mode 100644 hw/bsp/esp32s2_saola_1/led_strip/src/led_strip_rmt_ws2812.c diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index 1d8f2fe32..27f737d88 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -2,13 +2,14 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.5) -# example src directory -set(EXTRA_COMPONENT_DIRS "src") - # TOP is absolute path to root directory of TinyUSB git repo set(TOP "../../..") get_filename_component(TOP "${TOP}" REALPATH) +# Add example src and bsp directories +set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2_saola_1") + include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(SUPPORTED_TARGETS esp32s2) project(board_test) diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt index 676159ac9..29ae46a33 100644 --- a/examples/device/board_test/src/CMakeLists.txt +++ b/examples/device/board_test/src/CMakeLists.txt @@ -13,7 +13,3 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC "${TOP}/hw" "${TOP}/src" ) - -target_sources(${COMPONENT_TARGET} PUBLIC - "${TOP}/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c" -) diff --git a/hw/bsp/esp32s2_saola_1/CMakeLists.txt b/hw/bsp/esp32s2_saola_1/CMakeLists.txt new file mode 100644 index 000000000..379b2e3d0 --- /dev/null +++ b/hw/bsp/esp32s2_saola_1/CMakeLists.txt @@ -0,0 +1,16 @@ +idf_component_register(SRCS "esp32s2_saola_1.c" "led_strip/src/led_strip_rmt_ws2812.c" + INCLUDE_DIRS "led_strip/include" + PRIV_REQUIRES "driver" + REQUIRES freertos src) + +target_compile_options(${COMPONENT_TARGET} PUBLIC + "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" + "-DCFG_TUSB_OS=OPT_OS_FREERTOS" +) + +idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) +target_include_directories(${COMPONENT_TARGET} PUBLIC + "${FREERTOS_ORIG_INCLUDE_PATH}" + "${TOP}/hw" + "${TOP}/src" +) diff --git a/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c index ed855f727..ef70f1ee2 100644 --- a/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c +++ b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c @@ -24,26 +24,41 @@ * This file is part of the TinyUSB stack. */ -#include "bsp/board.h" +#include "../board.h" #include "driver/gpio.h" #include "hal/usb_hal.h" +#include "driver/rmt.h" +#include "led_strip/include/led_strip.h" + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -// TODO use saola-1 on-board neopixel (WS2812) -#define LED_PIN 21 +// Note: On the production version (v1.2) WS2812 is connected to GPIO 18, +// however earlier revision v1.1 WS2812 is connected to GPIO 17 +//#define LED_PIN 18 // v1.2 and later +#define LED_PIN 17 // v1.1 #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 + +static led_strip_t *strip; + // Initialize on-board peripherals : led, button, uart and USB void board_init(void) { - // LED - gpio_pad_select_gpio(LED_PIN); - gpio_set_direction(LED_PIN, GPIO_MODE_OUTPUT); + // WS2812 Neopixel driver with RMT peripheral + rmt_config_t config = RMT_DEFAULT_CONFIG_TX(LED_PIN, RMT_CHANNEL_0); + config.clk_div = 2; // set counter clock to 40MHz + + rmt_config(&config); + rmt_driver_install(config.channel, 0, 0); + + led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel); + strip = led_strip_new_rmt_ws2812(&strip_config); + strip->clear(strip, 100); // off led // Button gpio_pad_select_gpio(BUTTON_PIN); @@ -60,7 +75,8 @@ void board_init(void) // Turn LED on or off void board_led_write(bool state) { - gpio_set_level(LED_PIN, state); + strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00); + strip->refresh(strip, 100); } // Get the current state of button diff --git a/hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h b/hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h new file mode 100644 index 000000000..a9dffc325 --- /dev/null +++ b/hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h @@ -0,0 +1,126 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_err.h" + +/** +* @brief LED Strip Type +* +*/ +typedef struct led_strip_s led_strip_t; + +/** +* @brief LED Strip Device Type +* +*/ +typedef void *led_strip_dev_t; + +/** +* @brief Declare of LED Strip Type +* +*/ +struct led_strip_s { + /** + * @brief Set RGB for a specific pixel + * + * @param strip: LED strip + * @param index: index of pixel to set + * @param red: red part of color + * @param green: green part of color + * @param blue: blue part of color + * + * @return + * - ESP_OK: Set RGB for a specific pixel successfully + * - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters + * - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred + */ + esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue); + + /** + * @brief Refresh memory colors to LEDs + * + * @param strip: LED strip + * @param timeout_ms: timeout value for refreshing task + * + * @return + * - ESP_OK: Refresh successfully + * - ESP_ERR_TIMEOUT: Refresh failed because of timeout + * - ESP_FAIL: Refresh failed because some other error occurred + * + * @note: + * After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip. + */ + esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms); + + /** + * @brief Clear LED strip (turn off all LEDs) + * + * @param strip: LED strip + * @param timeout_ms: timeout value for clearing task + * + * @return + * - ESP_OK: Clear LEDs successfully + * - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout + * - ESP_FAIL: Clear LEDs failed because some other error occurred + */ + esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms); + + /** + * @brief Free LED strip resources + * + * @param strip: LED strip + * + * @return + * - ESP_OK: Free resources successfully + * - ESP_FAIL: Free resources failed because error occurred + */ + esp_err_t (*del)(led_strip_t *strip); +}; + +/** +* @brief LED Strip Configuration Type +* +*/ +typedef struct { + uint32_t max_leds; /*!< Maximum LEDs in a single strip */ + led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */ +} led_strip_config_t; + +/** + * @brief Default configuration for LED strip + * + */ +#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \ + { \ + .max_leds = number, \ + .dev = dev_hdl, \ + } + +/** +* @brief Install a new ws2812 driver (based on RMT peripheral) +* +* @param config: LED strip configuration +* @return +* LED strip instance or NULL +*/ +led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config); + +#ifdef __cplusplus +} +#endif diff --git a/hw/bsp/esp32s2_saola_1/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s2_saola_1/led_strip/src/led_strip_rmt_ws2812.c new file mode 100644 index 000000000..025d3c590 --- /dev/null +++ b/hw/bsp/esp32s2_saola_1/led_strip/src/led_strip_rmt_ws2812.c @@ -0,0 +1,171 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include +#include +#include +#include "esp_log.h" +#include "esp_attr.h" +#include "led_strip.h" +#include "driver/rmt.h" + +static const char *TAG = "ws2812"; +#define STRIP_CHECK(a, str, goto_tag, ret_value, ...) \ + do \ + { \ + if (!(a)) \ + { \ + ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ + ret = ret_value; \ + goto goto_tag; \ + } \ + } while (0) + +#define WS2812_T0H_NS (350) +#define WS2812_T0L_NS (1000) +#define WS2812_T1H_NS (1000) +#define WS2812_T1L_NS (350) +#define WS2812_RESET_US (280) + +static uint32_t ws2812_t0h_ticks = 0; +static uint32_t ws2812_t1h_ticks = 0; +static uint32_t ws2812_t0l_ticks = 0; +static uint32_t ws2812_t1l_ticks = 0; + +typedef struct { + led_strip_t parent; + rmt_channel_t rmt_channel; + uint32_t strip_len; + uint8_t buffer[0]; +} ws2812_t; + +/** + * @brief Conver RGB data to RMT format. + * + * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t) + * + * @param[in] src: source data, to converted to RMT format + * @param[in] dest: place where to store the convert result + * @param[in] src_size: size of source data + * @param[in] wanted_num: number of RMT items that want to get + * @param[out] translated_size: number of source data that got converted + * @param[out] item_num: number of RMT items which are converted from source data + */ +static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size, + size_t wanted_num, size_t *translated_size, size_t *item_num) +{ + if (src == NULL || dest == NULL) { + *translated_size = 0; + *item_num = 0; + return; + } + const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0 + const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1 + size_t size = 0; + size_t num = 0; + uint8_t *psrc = (uint8_t *)src; + rmt_item32_t *pdest = dest; + while (size < src_size && num < wanted_num) { + for (int i = 0; i < 8; i++) { + // MSB first + if (*psrc & (1 << (7 - i))) { + pdest->val = bit1.val; + } else { + pdest->val = bit0.val; + } + num++; + pdest++; + } + size++; + psrc++; + } + *translated_size = size; + *item_num = num; +} + +static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue) +{ + esp_err_t ret = ESP_OK; + ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent); + STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG); + uint32_t start = index * 3; + // In thr order of GRB + ws2812->buffer[start + 0] = green & 0xFF; + ws2812->buffer[start + 1] = red & 0xFF; + ws2812->buffer[start + 2] = blue & 0xFF; + return ESP_OK; +err: + return ret; +} + +static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms) +{ + esp_err_t ret = ESP_OK; + ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent); + STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK, + "transmit RMT samples failed", err, ESP_FAIL); + return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms)); +err: + return ret; +} + +static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms) +{ + ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent); + // Write zero to turn off all leds + memset(ws2812->buffer, 0, ws2812->strip_len * 3); + return ws2812_refresh(strip, timeout_ms); +} + +static esp_err_t ws2812_del(led_strip_t *strip) +{ + ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent); + free(ws2812); + return ESP_OK; +} + +led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config) +{ + led_strip_t *ret = NULL; + STRIP_CHECK(config, "configuration can't be null", err, NULL); + + // 24 bits per led + uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3; + ws2812_t *ws2812 = calloc(1, ws2812_size); + STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL); + + uint32_t counter_clk_hz = 0; + STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK, + "get rmt counter clock failed", err, NULL); + // ns -> ticks + float ratio = (float)counter_clk_hz / 1e9; + ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS); + ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS); + ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS); + ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS); + + // set ws2812 to rmt adapter + rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter); + + ws2812->rmt_channel = (rmt_channel_t)config->dev; + ws2812->strip_len = config->max_leds; + + ws2812->parent.set_pixel = ws2812_set_pixel; + ws2812->parent.refresh = ws2812_refresh; + ws2812->parent.clear = ws2812_clear; + ws2812->parent.del = ws2812_del; + + return &ws2812->parent; +err: + return ret; +} From 16dbbb2b4fc8fb730417a4cc61e2aaef0a2ef27c Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Apr 2020 11:19:08 +0700 Subject: [PATCH 41/61] make saola as cmake component, easier to add more esp32 board --- examples/device/board_test/CMakeLists.txt | 2 +- examples/device/cdc_msc_freertos/CMakeLists.txt | 6 +++--- examples/device/cdc_msc_freertos/src/CMakeLists.txt | 2 -- examples/device/hid_composite_freertos/CMakeLists.txt | 6 +++--- examples/device/hid_composite_freertos/src/CMakeLists.txt | 2 -- 5 files changed, 7 insertions(+), 11 deletions(-) diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index 27f737d88..4f0359922 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -6,7 +6,7 @@ cmake_minimum_required(VERSION 3.5) set(TOP "../../..") get_filename_component(TOP "${TOP}" REALPATH) -# Add example src and bsp directories +# Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2_saola_1") include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 746270f10..b0e2c2cea 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -2,13 +2,13 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.5) -# example src directory -set(EXTRA_COMPONENT_DIRS "src") - # TOP is absolute path to root directory of TinyUSB git repo set(TOP "../../..") get_filename_component(TOP "${TOP}" REALPATH) +# Add example src and bsp directories +set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2_saola_1") + include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(SUPPORTED_TARGETS esp32s2) diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index c757852a9..a7ece92c9 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -4,7 +4,6 @@ idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c" target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" - "-DCFG_TUSB_OS=OPT_OS_FREERTOS" ) idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) @@ -15,7 +14,6 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC ) target_sources(${COMPONENT_TARGET} PUBLIC - "${TOP}/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c" "${TOP}/src/tusb.c" "${TOP}/src/common/tusb_fifo.c" "${TOP}/src/device/usbd.c" diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt index e5c265bf8..bfd0677e0 100644 --- a/examples/device/hid_composite_freertos/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -2,13 +2,13 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.5) -# example src directory -set(EXTRA_COMPONENT_DIRS "src") - # TOP is absolute path to root directory of TinyUSB git repo set(TOP "../../..") get_filename_component(TOP "${TOP}" REALPATH) +# Add example src and bsp directories +set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2_saola_1") + include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(SUPPORTED_TARGETS esp32s2) diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt index 9e914e419..f79e8f845 100644 --- a/examples/device/hid_composite_freertos/src/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -4,7 +4,6 @@ idf_component_register(SRCS "main.c" "usb_descriptors.c" target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" - "-DCFG_TUSB_OS=OPT_OS_FREERTOS" ) idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) @@ -15,7 +14,6 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC ) target_sources(${COMPONENT_TARGET} PUBLIC - "${TOP}/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c" "${TOP}/src/tusb.c" "${TOP}/src/common/tusb_fifo.c" "${TOP}/src/device/usbd.c" From 11201f1a06396d4ab8302f2bb5ce579cb4ae7a6c Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Apr 2020 11:42:42 +0700 Subject: [PATCH 42/61] adding dcd_connect/disconnect --- src/device/dcd.h | 6 ++++++ src/device/usbd.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/device/dcd.h b/src/device/dcd.h index 143a2de34..487ddb3b6 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -106,6 +106,12 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num); // Wake up host void dcd_remote_wakeup(uint8_t rhport); +// disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK; + +// connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ diff --git a/src/device/usbd.h b/src/device/usbd.h index beeec7e1c..817af20e3 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -65,6 +65,20 @@ static inline bool tud_ready(void) // Remote wake up host, only if suspended and enabled by host bool tud_remote_wakeup(void); +static inline bool tud_disconnect(void) +{ + TU_VERIFY(dcd_disconnect); + dcd_disconnect(TUD_OPT_RHPORT); + return true; +} + +static inline bool tud_connect(void) +{ + TU_VERIFY(dcd_connect); + dcd_connect(TUD_OPT_RHPORT); + return true; +} + // Carry out Data and Status stage of control transfer // - If len = 0, it is equivalent to sending status only // - If len > wLength : it will be truncated From c1f3fbbc03256d303d5ce355bd0cf87a0d3c4f4c Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Apr 2020 11:47:02 +0700 Subject: [PATCH 43/61] implement dcd connect/disconnect for samd and nrf --- src/portable/microchip/samd/dcd_samd.c | 15 ++++++++++++++- src/portable/nordic/nrf5x/dcd_nrf5x.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 148995520..c3d2985d4 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -154,10 +154,23 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num) void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - USB->DEVICE.CTRLB.bit.UPRSM = 1; } +// disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + USB->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; +} + +// connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; +} + /*------------------------------------------------------------------*/ /* DCD Endpoint port *------------------------------------------------------------------*/ diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 2ce288d6c..c0dddef83 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -237,6 +237,20 @@ void dcd_remote_wakeup(uint8_t rhport) // We may manually raise DCD_EVENT_RESUME event here } +// disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + NRF_USBD->USBPULLUP = 0; +} + +// connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + NRF_USBD->USBPULLUP = 1; +} + //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ From d6578823bb405cacbda13a044b66ba0a4f16a3d4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Apr 2020 12:00:45 +0700 Subject: [PATCH 44/61] rename static function for dcd_cxd56 to prevent conflict --- src/portable/sony/cxd56/dcd_cxd56.c | 38 ++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index 638b2f979..320b7237e 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -46,22 +46,22 @@ struct usbdcd_driver_s static struct usbdcd_driver_s usbdcd_driver; static struct usbdev_s *usbdev; -static int dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); -static void dcd_unbind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); -static int dcd_setup(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev, - FAR const struct usb_ctrlreq_s *ctrl, FAR uint8_t *dataout, size_t outlen); -static void dcd_disconnect(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); -static void dcd_suspend(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); -static void dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); +static int _dcd_bind (FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); +static void _dcd_unbind (FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); +static int _dcd_setup (FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev, + FAR const struct usb_ctrlreq_s *ctrl, FAR uint8_t *dataout, size_t outlen); +static void _dcd_disconnect (FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); +static void _dcd_suspend (FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); +static void _dcd_resume (FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); static const struct usbdevclass_driverops_s g_driverops = { - dcd_bind, /* bind */ - dcd_unbind, /* unbind */ - dcd_setup, /* setup */ - dcd_disconnect, /* disconnect */ - dcd_suspend, /* suspend */ - dcd_resume, /* resume */ + _dcd_bind, /* bind */ + _dcd_unbind, /* unbind */ + _dcd_setup, /* setup */ + _dcd_disconnect, /* disconnect */ + _dcd_suspend, /* suspend */ + _dcd_resume, /* resume */ }; static void usbdcd_ep0incomplete(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) @@ -86,7 +86,7 @@ static void usbdcd_ep0incomplete(FAR struct usbdev_ep_s *ep, FAR struct usbdev_r } } -static int dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) +static int _dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) { (void) driver; @@ -111,13 +111,13 @@ static int dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s return 0; } -static void dcd_unbind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) +static void _dcd_unbind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) { (void) driver; (void) dev; } -static int dcd_setup(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev, +static int _dcd_setup(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev, FAR const struct usb_ctrlreq_s *ctrl, FAR uint8_t *dataout, size_t outlen) { (void) driver; @@ -130,7 +130,7 @@ static int dcd_setup(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_ return 0; } -static void dcd_disconnect(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) +static void _dcd_disconnect(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) { (void) driver; @@ -138,7 +138,7 @@ static void dcd_disconnect(FAR struct usbdevclass_driver_s *driver, FAR struct u DEV_CONNECT(dev); } -static void dcd_suspend(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) +static void _dcd_suspend(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) { (void) driver; (void) dev; @@ -146,7 +146,7 @@ static void dcd_suspend(FAR struct usbdevclass_driver_s *driver, FAR struct usbd dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } -static void dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) +static void _dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev) { (void) driver; (void) dev; From 715c4dbbf8fe7c6bb83013df626a201928704b30 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Wed, 8 Apr 2020 11:51:33 -0400 Subject: [PATCH 45/61] stm32fsdev: Implement dcd_connect. --- docs/porting.md | 6 ++++ src/device/dcd.h | 8 ++--- src/device/usbd.c | 1 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 30 +++++++++++++------ src/portable/template/dcd_template.c | 14 +++++++++ test/test/device/msc/test_msc_device.c | 1 + test/test/device/usbd/test_usbd.c | 1 + 7 files changed, 48 insertions(+), 13 deletions(-) diff --git a/docs/porting.md b/docs/porting.md index deb1b9efb..7d7d4cdb1 100644 --- a/docs/porting.md +++ b/docs/porting.md @@ -62,6 +62,8 @@ All of the code for the low-level device API is in `src/portable//CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; dcd_handle_bus_reset(); - - // And finally enable pull-up, which may trigger the RESET IRQ if the host is connected. - // (if this MCU has an internal pullup) -#if defined(USB_BCDR_DPPU) - USB->BCDR |= USB_BCDR_DPPU; -#else - // FIXME: callback to the user to ask them to twiddle a GPIO to disable/enable D+??? -#endif - + + // Data-line pull-up is left disconnected. } +// Define only on MCU with internal pull-up so BSP can override (needed on MCU without internal pull-up) +#if defined(USB_BCDR_DPPU) + +TU_ATTR_WEAK +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + USB->BCDR &= ~(USB_BCDR_DPPU); +} + +TU_ATTR_WEAK +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + USB->BCDR |= USB_BCDR_DPPU; +} + +#endif + // Enable device interrupt void dcd_int_enable (uint8_t rhport) { diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 102910509..d29c98e55 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -45,6 +45,20 @@ void dcd_init (uint8_t rhport) (void) rhport; } +#if HAS_INTERNAL_PULLUP +// Enable internal D+/D- pullup +void dcd_connect(uint8_t rhport) TU_ATTR_WEAK +{ + (void) rhport; +} + +// Disable internal D+/D- pullup +void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK +{ + (void) rhport; +} +#endif + // Enable device interrupt void dcd_int_enable (uint8_t rhport) { diff --git a/test/test/device/msc/test_msc_device.c b/test/test/device/msc/test_msc_device.c index 095c28170..62a36d3e3 100644 --- a/test/test/device/msc/test_msc_device.c +++ b/test/test/device/msc/test_msc_device.c @@ -199,6 +199,7 @@ void setUp(void) if ( !tusb_inited() ) { dcd_init_Expect(rhport); + dcd_connect_Expect(rhport); tusb_init(); } diff --git a/test/test/device/usbd/test_usbd.c b/test/test/device/usbd/test_usbd.c index 06372b2e4..1bb32c1e5 100644 --- a/test/test/device/usbd/test_usbd.c +++ b/test/test/device/usbd/test_usbd.c @@ -127,6 +127,7 @@ void setUp(void) { mscd_init_Expect(); dcd_init_Expect(rhport); + dcd_connect_Expect(rhport); tusb_init(); } } From 778db647c49da797c4d2d4d8bf62caa83ca1d6c7 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 13:53:57 +0700 Subject: [PATCH 46/61] add CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y --- examples/device/cdc_msc_freertos/sdkconfig.defaults | 2 +- examples/device/hid_composite_freertos/sdkconfig.defaults | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/device/cdc_msc_freertos/sdkconfig.defaults b/examples/device/cdc_msc_freertos/sdkconfig.defaults index 34991d70c..23de48ebd 100644 --- a/examples/device/cdc_msc_freertos/sdkconfig.defaults +++ b/examples/device/cdc_msc_freertos/sdkconfig.defaults @@ -1,4 +1,4 @@ CONFIG_IDF_CMAKE=y CONFIG_IDF_TARGET="esp32s2" CONFIG_IDF_TARGET_ESP32S2=y - +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y diff --git a/examples/device/hid_composite_freertos/sdkconfig.defaults b/examples/device/hid_composite_freertos/sdkconfig.defaults index 34991d70c..23de48ebd 100644 --- a/examples/device/hid_composite_freertos/sdkconfig.defaults +++ b/examples/device/hid_composite_freertos/sdkconfig.defaults @@ -1,4 +1,4 @@ CONFIG_IDF_CMAKE=y CONFIG_IDF_TARGET="esp32s2" CONFIG_IDF_TARGET_ESP32S2=y - +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y From 1b3d1b52c9351391f62dea374345c8de7f985b0f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 13:54:50 +0700 Subject: [PATCH 47/61] fix uint32_t format with log --- src/device/usbd.c | 2 +- src/tusb.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 125aa351c..397a681ed 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -421,7 +421,7 @@ void tud_task (void) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - TU_LOG2(" Endpoint: 0x%02X, Bytes: %lu\r\n", ep_addr, event.xfer_complete.len); + TU_LOG2(" Endpoint: 0x%02X, Bytes: %u\r\n", ep_addr, (unsigned int) event.xfer_complete.len); _usbd_dev.ep_status[epnum][ep_dir].busy = false; diff --git a/src/tusb.c b/src/tusb.c index 8e0022f4d..8f234455f 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -96,9 +96,9 @@ void tu_print_mem(void const *buf, uint16_t count, uint8_t indent) char format[] = "%00lX"; format[2] += 2*size; - const uint8_t item_per_line = 16 / size; + const uint8_t item_per_line = 16 / size; - for(uint32_t i=0; i Date: Fri, 10 Apr 2020 14:04:18 +0700 Subject: [PATCH 48/61] try to fix racing condition with setup --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 145 ++++++++++++------- 1 file changed, 93 insertions(+), 52 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 8a11f57b0..3aebd824e 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -60,18 +60,23 @@ typedef struct { static const char *TAG = "TUSB:DCD"; static intr_handle_t usb_ih; -static volatile TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6]; -static volatile uint8_t s_setup_phase = 0; /* 00 - got setup, - 01 - got done setup, - 02 - setup cmd sent*/ + + +static uint32_t _setup_packet[2]; #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] static xfer_ctl_t xfer_status[EP_MAX][2]; +#if 0 +static volatile uint8_t s_setup_phase = 0; /* 00 - got setup, + 01 - got done setup, + 02 - setup cmd sent*/ + static inline void readyfor1setup_pkg(int ep_num) { USB0.out_ep_reg[ep_num].doeptsiz |= (1 << USB_SUPCNT0_S); // doeptsiz 29:30 will decremented on every setup received } +#endif // Setup the control endpoint 0. static void bus_reset(void) @@ -83,6 +88,10 @@ static void bus_reset(void) USB0.dcfg &= ~USB_DEVADDR_M; // reset address + USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; + USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; + USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; + // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture // @@ -115,28 +124,16 @@ static void bus_reset(void) USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo USB0.grxfsiz = 52; - USB0.gintmsk = USB_MODEMISMSK_M | -#if USE_SOF - USB_SOFMSK_M | -#endif - USB_RXFLVIMSK_M | - USB_ERLYSUSPMSK_M | - USB_USBSUSPMSK_M | - USB_USBRSTMSK_M | - USB_ENUMDONEMSK_M | - USB_IEPINTMSK_M | - USB_OEPINTMSK_M | - USB_RESETDETMSK_M | - USB_DISCONNINTMSK_M; - - USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; - USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; - USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); +#if 0 readyfor1setup_pkg(0); +#else + USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M; +#endif + + USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M; } static void enum_done_processing(void) @@ -162,13 +159,13 @@ static void enum_done_processing(void) } - - /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ void dcd_init(uint8_t rhport) { + (void)rhport; + ESP_LOGV(TAG, "DCD init - Start"); // A. Disconnect @@ -198,9 +195,7 @@ void dcd_init(uint8_t rhport) for (int n = 0; n < USB_OUT_EP_NUM; n++) { USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK } - ESP_LOGV(TAG, "DCD init - Soft CONNECT"); - USB0.dctl &= ~USB_SFTDISCON_M; // Connect - + // D. Interruption masking USB0.gintmsk = 0; //mask all USB0.gotgint = ~0U; //clear OTG ints @@ -216,6 +211,10 @@ void dcd_init(uint8_t rhport) USB_ENUMDONEMSK_M | USB_RESETDETMSK_M | USB_DISCONNINTMSK_M; + + ESP_LOGV(TAG, "DCD init - Soft CONNECT"); + USB0.dctl &= ~USB_SFTDISCON_M; // Connect + ets_delay_us(100); } @@ -240,6 +239,18 @@ void dcd_remote_wakeup(uint8_t rhport) (void)rhport; } +// disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + USB0.dctl |= USB_SFTDISCON_M; +} + +// connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + USB0.dctl &= ~USB_SFTDISCON_M; +} + /*------------------------------------------------------------------*/ /* DCD Endpoint port *------------------------------------------------------------------*/ @@ -312,7 +323,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; uint8_t const epnum = tu_edpt_number(ep_addr); @@ -447,7 +457,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size) { ESP_EARLY_LOGV(TAG, "USB - receive_packet"); - uint32_t *rx_fifo = USB0.fifo[0]; + volatile uint32_t *rx_fifo = USB0.fifo[0]; // See above TODO // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos; @@ -549,35 +559,47 @@ static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, static void read_rx_fifo(void) { + volatile uint32_t *rx_fifo = USB0.fifo[0]; + // Pop control word off FIFO (completed xfers will have 2 control words, // we only pop one ctl word each interrupt). - uint32_t ctl_word = USB0.grxstsp; - uint8_t pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; - uint8_t epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S; - uint16_t bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S; + uint32_t const ctl_word = USB0.grxstsp; + uint8_t const pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; + uint8_t const epnum = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S; + uint16_t const bcnt = (ctl_word & USB_BCNT_M ) >> USB_BCNT_S; switch (pktsts) { - case 0x01: // Global OUT NAK (Interrupt) + case 0x01: // Global OUT NAK (Interrupt) ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); break; - case 0x02: { // Out packet recvd + + case 0x02: { // Out packet recvd ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet"); xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); receive_packet(xfer, bcnt); - } - break; - case 0x03: // Out packet done (Interrupt) + } + break; + + case 0x03: // Out packet done (Interrupt) ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done"); break; - case 0x04: // Setup packet done (Interrupt) + + case 0x04: // Step 2: Setup transaction completed (Interrupt) + // After this event, OEPINT interrupt will occur with SETUP bit set +#if 0 if (s_setup_phase == 0) { // only if setup is started - s_setup_phase = 1; - ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); + s_setup_phase = 1; + ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); } +#else + USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M; +#endif break; - case 0x06: { // Setup packet recvd + + case 0x06: { // Step1: Setup data packet received +#if 0 s_setup_phase = 0; ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 0"); // new setup process // For some reason, it's possible to get a mismatch between @@ -588,11 +610,18 @@ static void read_rx_fifo(void) // only accepting one setup packet at a time for now. _setup_packet[0] = (USB0.grxstsp); _setup_packet[1] = (USB0.grxstsp); - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", - _setup_packet[0], _setup_packet[1]); - } - break; - default: // Invalid, do something here, like breakpoint? + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); +#else + // We can receive up to three setup packets in succession, but + // only the last one is valid. Therefore we just overwrite it + _setup_packet[0] = (*rx_fifo); + _setup_packet[1] = (*rx_fifo); +#endif + } + break; + + default: // Invalid, do something here, like breakpoint? + TU_BREAKPOINT(); break; } } @@ -604,9 +633,11 @@ static void handle_epout_ints(void) // DOEPINT will be cleared when DAINT's out bits are cleared. for (int n = 0; n < USB_OUT_EP_NUM; n++) { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + if (USB0.daint & (1 << (16 + n))) { // SETUP packet Setup Phase done. if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) { +#if 0 USB0.out_ep_reg[n].doepint |= USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear if (s_setup_phase == 1) { // only if setup is done, but not handled s_setup_phase = 2; @@ -615,6 +646,10 @@ static void handle_epout_ints(void) dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); } readyfor1setup_pkg(0); +#else + USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear + dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); +#endif } // OUT XFER complete (single packet).q @@ -668,18 +703,21 @@ static void handle_epin_ints(void) } -static void dcd_int_handler(void) +static void dcd_int_handler(void* arg) { + (void) arg; + const uint32_t int_status = USB0.gintsts; - const uint32_t int_msk = USB0.gintmsk; + //const uint32_t int_msk = USB0.gintmsk; if (int_status & USB_DISCONNINT_M) { ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); USB0.gintsts = USB_DISCONNINT_M; + dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); } if (int_status & USB_USBRST_M) { - + // start of reset ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); USB0.gintsts = USB_USBRST_M; bus_reset(); @@ -707,9 +745,12 @@ static void dcd_int_handler(void) } #endif - if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) { + if ((int_status & USB_RXFLVI_M) /*& (int_msk & USB_RXFLVIMSK_M)*/) { ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); + USB0.gintmsk &= ~USB_RXFLVIMSK_M; read_rx_fifo(); + USB0.gintmsk |= USB_RXFLVIMSK_M; + USB0.gintsts = USB_RXFLVI_M; } // OUT endpoint interrupt handling. From d122d7de88819b744c192c2b3ab76b2a3d6cfda8 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 14:45:55 +0700 Subject: [PATCH 49/61] remove commented code --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 57 +++----------------- 1 file changed, 6 insertions(+), 51 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 3aebd824e..ed01c7877 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -67,17 +67,6 @@ static uint32_t _setup_packet[2]; #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] static xfer_ctl_t xfer_status[EP_MAX][2]; -#if 0 -static volatile uint8_t s_setup_phase = 0; /* 00 - got setup, - 01 - got done setup, - 02 - setup cmd sent*/ - -static inline void readyfor1setup_pkg(int ep_num) -{ - USB0.out_ep_reg[ep_num].doeptsiz |= (1 << USB_SUPCNT0_S); // doeptsiz 29:30 will decremented on every setup received -} -#endif - // Setup the control endpoint 0. static void bus_reset(void) { @@ -127,11 +116,8 @@ static void bus_reset(void) // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); -#if 0 - readyfor1setup_pkg(0); -#else + // Ready to receive SETUP packet USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M; -#endif USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M; } @@ -559,8 +545,6 @@ static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, static void read_rx_fifo(void) { - volatile uint32_t *rx_fifo = USB0.fifo[0]; - // Pop control word off FIFO (completed xfers will have 2 control words, // we only pop one ctl word each interrupt). uint32_t const ctl_word = USB0.grxstsp; @@ -586,37 +570,19 @@ static void read_rx_fifo(void) case 0x04: // Step 2: Setup transaction completed (Interrupt) // After this event, OEPINT interrupt will occur with SETUP bit set -#if 0 - if (s_setup_phase == 0) { // only if setup is started - s_setup_phase = 1; - ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); - } -#else + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M; -#endif - break; case 0x06: { // Step1: Setup data packet received -#if 0 - s_setup_phase = 0; - ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 0"); // new setup process - // For some reason, it's possible to get a mismatch between - // how many setup packets were received versus the location - // of the Setup packet done word. This leads to situations - // where stale setup packets are in the RX FIFO that were received - // after the core loaded the Setup packet done word. Workaround by - // only accepting one setup packet at a time for now. - _setup_packet[0] = (USB0.grxstsp); - _setup_packet[1] = (USB0.grxstsp); - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); -#else + volatile uint32_t *rx_fifo = USB0.fifo[0]; + // We can receive up to three setup packets in succession, but // only the last one is valid. Therefore we just overwrite it _setup_packet[0] = (*rx_fifo); _setup_packet[1] = (*rx_fifo); -#endif + + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); } break; @@ -637,19 +603,8 @@ static void handle_epout_ints(void) if (USB0.daint & (1 << (16 + n))) { // SETUP packet Setup Phase done. if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) { -#if 0 - USB0.out_ep_reg[n].doepint |= USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear - if (s_setup_phase == 1) { // only if setup is done, but not handled - s_setup_phase = 2; - ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 2"); // sending to a handling queue - ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - Setup Phase done (irq-s 0x%08x)", USB0.out_ep_reg[n].doepint); - dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); - } - readyfor1setup_pkg(0); -#else USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); -#endif } // OUT XFER complete (single packet).q From cec747776dd08452e2cd446262e407c60f4bfd7a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 14:47:02 +0700 Subject: [PATCH 50/61] rename dcd_init_handler to dcd_irq_handler to consistent with other ports --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index ed01c7877..27312824e 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -125,7 +125,7 @@ static void bus_reset(void) static void enum_done_processing(void) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); // On current silicon on the Full Speed core, speed is fixed to Full Speed. // However, keep for debugging and in case Low Speed is ever supported. uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); @@ -658,28 +658,28 @@ static void handle_epin_ints(void) } -static void dcd_int_handler(void* arg) +void dcd_irq_handler(uint32_t rhport) { - (void) arg; + (void) rhport; const uint32_t int_status = USB0.gintsts; //const uint32_t int_msk = USB0.gintmsk; if (int_status & USB_DISCONNINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected"); USB0.gintsts = USB_DISCONNINT_M; dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); } if (int_status & USB_USBRST_M) { // start of reset - ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset"); USB0.gintsts = USB_USBRST_M; bus_reset(); } if (int_status & USB_RESETDET_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend"); USB0.gintsts = USB_RESETDET_M; bus_reset(); } @@ -701,7 +701,7 @@ static void dcd_int_handler(void* arg) #endif if ((int_status & USB_RXFLVI_M) /*& (int_msk & USB_RXFLVIMSK_M)*/) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); USB0.gintmsk &= ~USB_RXFLVIMSK_M; read_rx_fifo(); USB0.gintmsk |= USB_RXFLVIMSK_M; @@ -710,13 +710,13 @@ static void dcd_int_handler(void* arg) // OUT endpoint interrupt handling. if (int_status & USB_OEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!"); handle_epout_ints(); } // IN endpoint interrupt handling. if (int_status & USB_IEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!"); handle_epin_ints(); } @@ -741,7 +741,7 @@ static void dcd_int_handler(void* arg) void dcd_int_enable(uint8_t rhport) { (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih); + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih); } void dcd_int_disable(uint8_t rhport) From 933e3cdfc754c42936e5be7e84bf1c55f77b8bd0 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 15:01:12 +0700 Subject: [PATCH 51/61] change indent from 4 -> 2 spaces --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 1012 +++++++++--------- 1 file changed, 507 insertions(+), 505 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 27312824e..e0a2c2454 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -70,78 +70,76 @@ static xfer_ctl_t xfer_status[EP_MAX][2]; // Setup the control endpoint 0. static void bus_reset(void) { + for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) { + USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK + } - for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) { - USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK - } + USB0.dcfg &= ~USB_DEVADDR_M; // reset address - USB0.dcfg &= ~USB_DEVADDR_M; // reset address + USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; + USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; + USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; - USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; - USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; - USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO MAX | + // --------------- + // | ... | + // --------------- y + x + 16 + GRXFSIZ + // | IN FIFO 2 | + // --------------- x + 16 + GRXFSIZ + // | IN FIFO 1 | + // --------------- 16 + GRXFSIZ + // | IN FIFO 0 | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN + // + // - All EP OUT shared a unique OUT FIFO which uses + // * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets). + // * 2 locations for OUT endpoint control words. + // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) + // * 1 location for global NAK (not required/used here). + // * It is recommended to allocate 2 times the largest packet size, therefore + // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52 + USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10, + USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo + USB0.grxfsiz = 52; - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO MAX | - // --------------- - // | ... | - // --------------- y + x + 16 + GRXFSIZ - // | IN FIFO 2 | - // --------------- x + 16 + GRXFSIZ - // | IN FIFO 1 | - // --------------- 16 + GRXFSIZ - // | IN FIFO 0 | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): - // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN - // - // - All EP OUT shared a unique OUT FIFO which uses - // * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets). - // * 2 locations for OUT endpoint control words. - // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) - // * 1 location for global NAK (not required/used here). - // * It is recommended to allocate 2 times the largest packet size, therefore - // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52 - USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10, - USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo - USB0.grxfsiz = 52; + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); + // Ready to receive SETUP packet + USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M; - // Ready to receive SETUP packet - USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M; - - USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M; + USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M; } static void enum_done_processing(void) { + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + // On current silicon on the Full Speed core, speed is fixed to Full Speed. + // However, keep for debugging and in case Low Speed is ever supported. + uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); - // On current silicon on the Full Speed core, speed is fixed to Full Speed. - // However, keep for debugging and in case Low Speed is ever supported. - uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); - - // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL - if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz) - USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V; // 64 bytes - USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - } else { - USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V; // 8 bytes - USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall - xfer_status[0][TUSB_DIR_OUT].max_size = 8; - xfer_status[0][TUSB_DIR_IN].max_size = 8; - } + // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL + if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz) + USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V; // 64 bytes + USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + } else { + USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V; // 8 bytes + USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall + xfer_status[0][TUSB_DIR_OUT].max_size = 8; + xfer_status[0][TUSB_DIR_IN].max_size = 8; + } } @@ -150,79 +148,79 @@ static void enum_done_processing(void) *------------------------------------------------------------------*/ void dcd_init(uint8_t rhport) { - (void)rhport; + (void)rhport; - ESP_LOGV(TAG, "DCD init - Start"); + ESP_LOGV(TAG, "DCD init - Start"); - // A. Disconnect - ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up"); - USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect + // A. Disconnect + ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up"); + USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect - // B. Programming DCFG - /* If USB host misbehaves during status portion of control xfer + // B. Programming DCFG + /* If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard. Full speed. */ - USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL - (3 << 0); // dev speed: fullspeed 1.1 on 48 mhz // TODO no value in usb_reg.h (IDF-1476) + USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL + (3 << 0); // dev speed: fullspeed 1.1 on 48 mhz // TODO no value in usb_reg.h (IDF-1476) - USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON - USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode + USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON + USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode - USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides + USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides #ifdef CONFIG_IDF_TARGET_ESP32S2BETA // needed for beta chip only - //C. chip 7.2.2 hack - ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack"); - USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value - ets_delay_us(20); - USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable - ets_delay_us(20); + //C. chip 7.2.2 hack + ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack"); + USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value + ets_delay_us(20); + USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable + ets_delay_us(20); #endif - // C. Setting SNAKs, then connect - for (int n = 0; n < USB_OUT_EP_NUM; n++) { - USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK - } - - // D. Interruption masking - USB0.gintmsk = 0; //mask all - USB0.gotgint = ~0U; //clear OTG ints - USB0.gintsts = ~0U; //clear pending ints - USB0.gintmsk = USB_MODEMISMSK_M | -#if USE_SOF - USB_SOFMSK_M | -#endif - USB_RXFLVIMSK_M | - USB_ERLYSUSPMSK_M | - USB_USBSUSPMSK_M | - USB_USBRSTMSK_M | - USB_ENUMDONEMSK_M | - USB_RESETDETMSK_M | - USB_DISCONNINTMSK_M; + // C. Setting SNAKs, then connect + for (int n = 0; n < USB_OUT_EP_NUM; n++) { + USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK + } - ESP_LOGV(TAG, "DCD init - Soft CONNECT"); - USB0.dctl &= ~USB_SFTDISCON_M; // Connect + // D. Interruption masking + USB0.gintmsk = 0; //mask all + USB0.gotgint = ~0U; //clear OTG ints + USB0.gintsts = ~0U; //clear pending ints + USB0.gintmsk = USB_MODEMISMSK_M | + #if USE_SOF + USB_SOFMSK_M | + #endif + USB_RXFLVIMSK_M | + USB_ERLYSUSPMSK_M | + USB_USBSUSPMSK_M | + USB_USBRSTMSK_M | + USB_ENUMDONEMSK_M | + USB_RESETDETMSK_M | + USB_DISCONNINTMSK_M; - ets_delay_us(100); + ESP_LOGV(TAG, "DCD init - Soft CONNECT"); + USB0.dctl &= ~USB_SFTDISCON_M; // Connect + + ets_delay_us(100); } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)rhport; - ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr); - USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S); - // Response with status after changing device address - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + (void)rhport; + ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr); + USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S); + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } void dcd_set_config(uint8_t rhport, uint8_t config_num) { - (void)rhport; - (void)config_num; - // Nothing to do + (void)rhport; + (void)config_num; + // Nothing to do } void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; + (void)rhport; } // disconnect by disabling internal pull-up resistor on D+/D- @@ -243,511 +241,515 @@ void dcd_connect(uint8_t rhport) bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { + ESP_LOGV(TAG, "DCD endpoint opened"); + (void)rhport; - ESP_LOGV(TAG, "DCD endpoint opened"); - (void)rhport; + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64); + TU_ASSERT(epnum < EP_MAX); - TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64); - TU_ASSERT(epnum < EP_MAX); + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = desc_edpt->wMaxPacketSize.size; - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = desc_edpt->wMaxPacketSize.size; + if (dir == TUSB_DIR_OUT) { + out_ep[epnum].doepctl |= USB_USBACTEP0_M | + desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S | + desc_edpt->wMaxPacketSize.size << USB_MPS0_S; + USB0.daintmsk |= (1 << (16 + epnum)); + } else { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO MAX | + // --------------- + // | ... | + // --------------- y + x + 16 + GRXFSIZ + // | IN FIFO 2 | + // --------------- x + 16 + GRXFSIZ + // | IN FIFO 1 | + // --------------- 16 + GRXFSIZ + // | IN FIFO 0 | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints + // - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1) + // - Offset: GRXFSIZ + 16 + Size*(epnum-1) + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - if (dir == TUSB_DIR_OUT) { - out_ep[epnum].doepctl |= USB_USBACTEP0_M | - desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S | - desc_edpt->wMaxPacketSize.size << USB_MPS0_S; - USB0.daintmsk |= (1 << (16 + epnum)); - } else { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO MAX | - // --------------- - // | ... | - // --------------- y + x + 16 + GRXFSIZ - // | IN FIFO 2 | - // --------------- x + 16 + GRXFSIZ - // | IN FIFO 1 | - // --------------- 16 + GRXFSIZ - // | IN FIFO 0 | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints - // - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1) - // - Offset: GRXFSIZ + 16 + Size*(epnum-1) - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + in_ep[epnum].diepctl |= USB_D_USBACTEP1_M | + epnum << USB_D_TXFNUM1_S | + desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | + desc_edpt->wMaxPacketSize.size << 0; + USB0.daintmsk |= (1 << (0 + epnum)); - in_ep[epnum].diepctl |= USB_D_USBACTEP1_M | - epnum << USB_D_TXFNUM1_S | - desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | - desc_edpt->wMaxPacketSize.size << 0; - USB0.daintmsk |= (1 << (0 + epnum)); + // Both TXFD and TXSA are in unit of 32-bit words. + // IN FIFO 0 was configured during enumeration, hence the "+ 16". + uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16; + uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1); + uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1); - // Both TXFD and TXSA are in unit of 32-bit words. - // IN FIFO 0 was configured during enumeration, hence the "+ 16". - uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16; - uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1); - uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1); - - // DIEPTXF starts at FIFO #1. - USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset; - } - return true; + // DIEPTXF starts at FIFO #1. + USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset; + } + return true; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; + (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; - uint16_t num_packets = (total_bytes / xfer->max_size); - uint8_t short_packet_size = total_bytes % xfer->max_size; + uint16_t num_packets = (total_bytes / xfer->max_size); + uint8_t short_packet_size = total_bytes % xfer->max_size; - // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) { - num_packets++; - } + // Zero-size packet is special case. + if (short_packet_size > 0 || (total_bytes == 0)) { + num_packets++; + } - ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i", - epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"), - num_packets, total_bytes); + ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i", + epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"), + num_packets, total_bytes); - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them - // here. - if (dir == TUSB_DIR_IN) { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; - USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK - USB0.dtknqr4_fifoemptymsk |= (1 << epnum); - } else { - // Each complete packet for OUT xfers triggers XFRC. - USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M | - ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); - USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; - } - return true; + // IN and OUT endpoint xfers are interrupt-driven, we just schedule them + // here. + if (dir == TUSB_DIR_IN) { + // A full IN transfer (multiple packets, possibly) triggers XFRC. + USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; + USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK + USB0.dtknqr4_fifoemptymsk |= (1 << epnum); + } else { + // Each complete packet for OUT xfers triggers XFRC. + USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M | + ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; + } + return true; } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - if (dir == TUSB_DIR_IN) { - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) { - in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M); - } else { - // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].diepctl |= USB_DI_SNAK1_M; - while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) - ; - - // Disable the endpoint. Note that both SNAK and STALL are set here. - in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | - USB_D_EPDIS1_M); - while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) - ; - in_ep[epnum].diepint = USB_D_EPDISBLD0_M; - } - - // Flush the FIFO, and wait until we have confirmed it cleared. - USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S); - USB0.grstctl |= USB_TXFFLSH_M; - while ((USB0.grstctl & USB_TXFFLSH_M) != 0) - ; + if (dir == TUSB_DIR_IN) { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) { + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M); } else { - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) { - out_ep[epnum].doepctl |= USB_STALL0_M; - } else { - // Asserting GONAK is required to STALL an OUT endpoint. - // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt - // anyway, and it can't be cleared by user code. If this while loop never - // finishes, we have bigger problems than just the stack. - USB0.dctl |= USB_SGOUTNAK_M; - while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) - ; + // Stop transmitting packets and NAK IN xfers. + in_ep[epnum].diepctl |= USB_DI_SNAK1_M; + while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) + ; - // Ditto here- disable the endpoint. Note that only STALL and not SNAK - // is set here. - out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M); - while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) - ; - out_ep[epnum].doepint = USB_EPDISBLD0_M; - - // Allow other OUT endpoints to keep receiving. - USB0.dctl |= USB_CGOUTNAK_M; - } + // Disable the endpoint. Note that both SNAK and STALL are set here. + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | + USB_D_EPDIS1_M); + while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) + ; + in_ep[epnum].diepint = USB_D_EPDISBLD0_M; } + + // Flush the FIFO, and wait until we have confirmed it cleared. + USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S); + USB0.grstctl |= USB_TXFFLSH_M; + while ((USB0.grstctl & USB_TXFFLSH_M) != 0) + ; + } else { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) { + out_ep[epnum].doepctl |= USB_STALL0_M; + } else { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + USB0.dctl |= USB_SGOUTNAK_M; + while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) + ; + + // Ditto here- disable the endpoint. Note that only STALL and not SNAK + // is set here. + out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M); + while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) + ; + out_ep[epnum].doepint = USB_EPDISBLD0_M; + + // Allow other OUT endpoints to keep receiving. + USB0.dctl |= USB_CGOUTNAK_M; + } + } } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - if (dir == TUSB_DIR_IN) { - in_ep[epnum].diepctl &= ~USB_D_STALL1_M; + if (dir == TUSB_DIR_IN) { + in_ep[epnum].diepctl &= ~USB_D_STALL1_M; - uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S; - // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt - // and bulk endpoints. - if (eptype == 2 || eptype == 3) { - in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M; - } - } else { - out_ep[epnum].doepctl &= ~USB_STALL1_M; - - uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S; - // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt - // and bulk endpoints. - if (eptype == 2 || eptype == 3) { - out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M; - } + uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S; + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + if (eptype == 2 || eptype == 3) { + in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M; } + } else { + out_ep[epnum].doepctl &= ~USB_STALL1_M; + + uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S; + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + if (eptype == 2 || eptype == 3) { + out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M; + } + } } /*------------------------------------------------------------------*/ static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size) { - ESP_EARLY_LOGV(TAG, "USB - receive_packet"); - volatile uint32_t *rx_fifo = USB0.fifo[0]; + ESP_EARLY_LOGV(TAG, "USB - receive_packet"); + volatile uint32_t *rx_fifo = USB0.fifo[0]; - // See above TODO - // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos; - // xfer->queued_len = xfer->total_len - remaining; + // See above TODO + // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos; + // xfer->queued_len = xfer->total_len - remaining; - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint16_t to_recv_size; + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; - if (remaining <= xfer->max_size) { - // Avoid buffer overflow. - to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; - } else { - // Room for full packet, choose recv_size based on what the microcontroller - // claims. - to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + if (remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + uint8_t to_recv_rem = to_recv_size % 4; + uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem; + + // Do not assume xfer buffer is aligned. + uint8_t *base = (xfer->buffer + xfer->queued_len); + + // This for loop always runs at least once- skip if less than 4 bytes + // to collect. + if (to_recv_size >= 4) { + for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) { + uint32_t tmp = (*rx_fifo); + base[i] = tmp & 0x000000FF; + base[i + 1] = (tmp & 0x0000FF00) >> 8; + base[i + 2] = (tmp & 0x00FF0000) >> 16; + base[i + 3] = (tmp & 0xFF000000) >> 24; } + } - uint8_t to_recv_rem = to_recv_size % 4; - uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem; + // Do not read invalid bytes from RX FIFO. + if (to_recv_rem != 0) { + uint32_t tmp = (*rx_fifo); + uint8_t *last_32b_bound = base + to_recv_size_aligned; - // Do not assume xfer buffer is aligned. - uint8_t *base = (xfer->buffer + xfer->queued_len); - - // This for loop always runs at least once- skip if less than 4 bytes - // to collect. - if (to_recv_size >= 4) { - for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) { - uint32_t tmp = (*rx_fifo); - base[i] = tmp & 0x000000FF; - base[i + 1] = (tmp & 0x0000FF00) >> 8; - base[i + 2] = (tmp & 0x00FF0000) >> 16; - base[i + 3] = (tmp & 0xFF000000) >> 24; - } + last_32b_bound[0] = tmp & 0x000000FF; + if (to_recv_rem > 1) { + last_32b_bound[1] = (tmp & 0x0000FF00) >> 8; } - - // Do not read invalid bytes from RX FIFO. - if (to_recv_rem != 0) { - uint32_t tmp = (*rx_fifo); - uint8_t *last_32b_bound = base + to_recv_size_aligned; - - last_32b_bound[0] = tmp & 0x000000FF; - if (to_recv_rem > 1) { - last_32b_bound[1] = (tmp & 0x0000FF00) >> 8; - } - if (to_recv_rem > 2) { - last_32b_bound[2] = (tmp & 0x00FF0000) >> 16; - } + if (to_recv_rem > 2) { + last_32b_bound[2] = (tmp & 0x00FF0000) >> 16; } + } - xfer->queued_len += xfer_size; + xfer->queued_len += xfer_size; - // Per USB spec, a short OUT packet (including length 0) is always - // indicative of the end of a transfer (at least for ctl, bulk, int). - xfer->short_packet = (xfer_size < xfer->max_size); + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); } static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num) { - ESP_EARLY_LOGV(TAG, "USB - transmit_packet"); - volatile uint32_t *tx_fifo = USB0.fifo[fifo_num]; + ESP_EARLY_LOGV(TAG, "USB - transmit_packet"); + volatile uint32_t *tx_fifo = USB0.fifo[fifo_num]; - uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S; - xfer->queued_len = xfer->total_len - remaining; + uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S; + xfer->queued_len = xfer->total_len - remaining; - uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining; - uint8_t to_xfer_rem = to_xfer_size % 4; - uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem; + uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining; + uint8_t to_xfer_rem = to_xfer_size % 4; + uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem; - // Buffer might not be aligned to 32b, so we need to force alignment - // by copying to a temp var. - uint8_t *base = (xfer->buffer + xfer->queued_len); + // Buffer might not be aligned to 32b, so we need to force alignment + // by copying to a temp var. + uint8_t *base = (xfer->buffer + xfer->queued_len); - // This for loop always runs at least once- skip if less than 4 bytes - // to send off. - if (to_xfer_size >= 4) { - for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) { - uint32_t tmp = base[i] | (base[i + 1] << 8) | - (base[i + 2] << 16) | (base[i + 3] << 24); - (*tx_fifo) = tmp; - } + // This for loop always runs at least once- skip if less than 4 bytes + // to send off. + if (to_xfer_size >= 4) { + for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) { + uint32_t tmp = base[i] | (base[i + 1] << 8) | + (base[i + 2] << 16) | (base[i + 3] << 24); + (*tx_fifo) = tmp; + } + } + + // Do not read beyond end of buffer if not divisible by 4. + if (to_xfer_rem != 0) { + uint32_t tmp = 0; + uint8_t *last_32b_bound = base + to_xfer_size_aligned; + + tmp |= last_32b_bound[0]; + if (to_xfer_rem > 1) { + tmp |= (last_32b_bound[1] << 8); + } + if (to_xfer_rem > 2) { + tmp |= (last_32b_bound[2] << 16); } - // Do not read beyond end of buffer if not divisible by 4. - if (to_xfer_rem != 0) { - uint32_t tmp = 0; - uint8_t *last_32b_bound = base + to_xfer_size_aligned; - - tmp |= last_32b_bound[0]; - if (to_xfer_rem > 1) { - tmp |= (last_32b_bound[1] << 8); - } - if (to_xfer_rem > 2) { - tmp |= (last_32b_bound[2] << 16); - } - - (*tx_fifo) = tmp; - } + (*tx_fifo) = tmp; + } } static void read_rx_fifo(void) { - // Pop control word off FIFO (completed xfers will have 2 control words, - // we only pop one ctl word each interrupt). - uint32_t const ctl_word = USB0.grxstsp; - uint8_t const pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; - uint8_t const epnum = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S; - uint16_t const bcnt = (ctl_word & USB_BCNT_M ) >> USB_BCNT_S; + // Pop control word off FIFO (completed xfers will have 2 control words, + // we only pop one ctl word each interrupt). + uint32_t const ctl_word = USB0.grxstsp; + uint8_t const pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; + uint8_t const epnum = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S; + uint16_t const bcnt = (ctl_word & USB_BCNT_M ) >> USB_BCNT_S; - switch (pktsts) { - case 0x01: // Global OUT NAK (Interrupt) - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); - break; - - case 0x02: { // Out packet recvd - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet"); - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - receive_packet(xfer, bcnt); - } + switch (pktsts) { + case 0x01: // Global OUT NAK (Interrupt) + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); break; - case 0x03: // Out packet done (Interrupt) - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done"); - break; - - case 0x04: // Step 2: Setup transaction completed (Interrupt) - // After this event, OEPINT interrupt will occur with SETUP bit set - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); - USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M; - break; - - case 0x06: { // Step1: Setup data packet received - volatile uint32_t *rx_fifo = USB0.fifo[0]; - - // We can receive up to three setup packets in succession, but - // only the last one is valid. Therefore we just overwrite it - _setup_packet[0] = (*rx_fifo); - _setup_packet[1] = (*rx_fifo); - - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); - } - break; - - default: // Invalid, do something here, like breakpoint? - TU_BREAKPOINT(); - break; + case 0x02: { // Out packet recvd + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet"); + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + receive_packet(xfer, bcnt); } + break; + + case 0x03: // Out packet done (Interrupt) + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done"); + break; + + case 0x04: // Step 2: Setup transaction completed (Interrupt) + // After this event, OEPINT interrupt will occur with SETUP bit set + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); + USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M; + break; + + case 0x06: { // Step1: Setup data packet received + volatile uint32_t *rx_fifo = USB0.fifo[0]; + + // We can receive up to three setup packets in succession, but + // only the last one is valid. Therefore we just overwrite it + _setup_packet[0] = (*rx_fifo); + _setup_packet[1] = (*rx_fifo); + + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); + } + break; + + default: // Invalid, do something here, like breakpoint? + TU_BREAKPOINT(); + break; + } } static void handle_epout_ints(void) { - // GINTSTS will be cleared with DAINT == 0 - // DAINT for a given EP clears when DOEPINTx is cleared. - // DOEPINT will be cleared when DAINT's out bits are cleared. - for (int n = 0; n < USB_OUT_EP_NUM; n++) { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + // GINTSTS will be cleared with DAINT == 0 + // DAINT for a given EP clears when DOEPINTx is cleared. + // DOEPINT will be cleared when DAINT's out bits are cleared. + for (int n = 0; n < USB_OUT_EP_NUM; n++) { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if (USB0.daint & (1 << (16 + n))) { - // SETUP packet Setup Phase done. - if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) { - USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear - dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); - } + if (USB0.daint & (1 << (16 + n))) { + // SETUP packet Setup Phase done. + if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) { + USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear + dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); + } - // OUT XFER complete (single packet).q - if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) { + // OUT XFER complete (single packet).q + if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)"); - USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M; + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)"); + USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M; - // Transfer complete if short packet or total len is transferred - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } else { - // Schedule another packet to be received. - USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M | - ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); - USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M; - } - } + // Transfer complete if short packet or total len is transferred + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } else { + // Schedule another packet to be received. + USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M | + ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M; } + } } + } } static void handle_epin_ints(void) { + // GINTSTS will be cleared with DAINT == 0 + // DAINT for a given EP clears when DIEPINTx is cleared. + // IEPINT will be cleared when DAINT's out bits are cleared. + for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) { + xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN]; - // GINTSTS will be cleared with DAINT == 0 - // DAINT for a given EP clears when DIEPINTx is cleared. - // IEPINT will be cleared when DAINT's out bits are cleared. - for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) { - xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN]; + if (USB0.daint & (1 << (0 + n))) { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n); + // IN XFER complete (entire xfer). + if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!"); + USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M; + USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive. + dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } - if (USB0.daint & (1 << (0 + n))) { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n); - // IN XFER complete (entire xfer). - if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!"); - USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M; - USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive. - dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - - // XFER FIFO empty - if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!"); - USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M; - transmit_packet(xfer, &USB0.in_ep_reg[n], n); - } - } + // XFER FIFO empty + if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!"); + USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M; + transmit_packet(xfer, &USB0.in_ep_reg[n], n); + } } + } } void dcd_irq_handler(uint32_t rhport) { - (void) rhport; + (void) rhport; - const uint32_t int_status = USB0.gintsts; - //const uint32_t int_msk = USB0.gintmsk; + const uint32_t int_status = USB0.gintsts; + //const uint32_t int_msk = USB0.gintmsk; - if (int_status & USB_DISCONNINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected"); - USB0.gintsts = USB_DISCONNINT_M; - dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); - } + if (int_status & USB_DISCONNINT_M) { + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected"); + USB0.gintsts = USB_DISCONNINT_M; + dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); + } - if (int_status & USB_USBRST_M) { - // start of reset - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset"); - USB0.gintsts = USB_USBRST_M; - bus_reset(); - } + if (int_status & USB_USBRST_M) { + // start of reset + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset"); + USB0.gintsts = USB_USBRST_M; + bus_reset(); + } - if (int_status & USB_RESETDET_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend"); - USB0.gintsts = USB_RESETDET_M; - bus_reset(); - } + if (int_status & USB_RESETDET_M) { + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend"); + USB0.gintsts = USB_RESETDET_M; + bus_reset(); + } - if (int_status & USB_ENUMDONE_M) { - // ENUMDNE detects speed of the link. For full-speed, we - // always expect the same value. This interrupt is considered - // the end of reset. - USB0.gintsts = USB_ENUMDONE_M; - enum_done_processing(); - dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); - } + if (int_status & USB_ENUMDONE_M) { + // ENUMDNE detects speed of the link. For full-speed, we + // always expect the same value. This interrupt is considered + // the end of reset. + USB0.gintsts = USB_ENUMDONE_M; + enum_done_processing(); + dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); + } #if USE_SOF - if (int_status & USB_SOF_M) { - USB0.gintsts = USB_SOF_M; - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually - } + if (int_status & USB_SOF_M) { + USB0.gintsts = USB_SOF_M; + dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually + } #endif - if ((int_status & USB_RXFLVI_M) /*& (int_msk & USB_RXFLVIMSK_M)*/) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); - USB0.gintmsk &= ~USB_RXFLVIMSK_M; - read_rx_fifo(); - USB0.gintmsk |= USB_RXFLVIMSK_M; - USB0.gintsts = USB_RXFLVI_M; - } + if (int_status & USB_RXFLVI_M) { + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); - // OUT endpoint interrupt handling. - if (int_status & USB_OEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!"); - handle_epout_ints(); - } + // disable RXFLVI interrupt until we read data from FIFO + USB0.gintmsk &= ~USB_RXFLVIMSK_M; - // IN endpoint interrupt handling. - if (int_status & USB_IEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!"); - handle_epin_ints(); - } + read_rx_fifo(); - // Without handling - USB0.gintsts |= USB_CURMOD_INT_M | - USB_MODEMIS_M | - USB_OTGINT_M | - USB_NPTXFEMP_M | - USB_GINNAKEFF_M | - USB_GOUTNAKEFF | - USB_ERLYSUSP_M | - USB_USBSUSP_M | - USB_ISOOUTDROP_M | - USB_EOPF_M | - USB_EPMIS_M | - USB_INCOMPISOIN_M | - USB_INCOMPIP_M | - USB_FETSUSP_M | - USB_PTXFEMP_M; + // re-enable RXFLVI + USB0.gintmsk |= USB_RXFLVIMSK_M; + + USB0.gintsts = USB_RXFLVI_M; + } + + // OUT endpoint interrupt handling. + if (int_status & USB_OEPINT_M) { + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!"); + handle_epout_ints(); + } + + // IN endpoint interrupt handling. + if (int_status & USB_IEPINT_M) { + ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!"); + handle_epin_ints(); + } + + // Without handling + USB0.gintsts |= USB_CURMOD_INT_M | + USB_MODEMIS_M | + USB_OTGINT_M | + USB_NPTXFEMP_M | + USB_GINNAKEFF_M | + USB_GOUTNAKEFF | + USB_ERLYSUSP_M | + USB_USBSUSP_M | + USB_ISOOUTDROP_M | + USB_EOPF_M | + USB_EPMIS_M | + USB_INCOMPISOIN_M | + USB_INCOMPIP_M | + USB_FETSUSP_M | + USB_PTXFEMP_M; } -void dcd_int_enable(uint8_t rhport) +void dcd_int_enable (uint8_t rhport) { - (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih); + (void) rhport; + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) dcd_irq_handler, NULL, &usb_ih); } -void dcd_int_disable(uint8_t rhport) +void dcd_int_disable (uint8_t rhport) { - (void)rhport; - esp_intr_free(usb_ih); + (void) rhport; + esp_intr_free(usb_ih); } #endif // OPT_MCU_ESP32S2 From c0695b4b55ba0a01117d7e9f544735c117fcb14b Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 15:13:12 +0700 Subject: [PATCH 52/61] clear USB_RXFLVI_M before read_rx_fifo() more format clean up --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 21 +++++++------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index e0a2c2454..d34e1c123 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -362,22 +362,18 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) } else { // Stop transmitting packets and NAK IN xfers. in_ep[epnum].diepctl |= USB_DI_SNAK1_M; - while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) - ; + while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) ; // Disable the endpoint. Note that both SNAK and STALL are set here. - in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | - USB_D_EPDIS1_M); - while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) - ; + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | USB_D_EPDIS1_M); + while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) ; in_ep[epnum].diepint = USB_D_EPDISBLD0_M; } // Flush the FIFO, and wait until we have confirmed it cleared. USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S); USB0.grstctl |= USB_TXFFLSH_M; - while ((USB0.grstctl & USB_TXFFLSH_M) != 0) - ; + while ((USB0.grstctl & USB_TXFFLSH_M) != 0) ; } else { // Only disable currently enabled non-control endpoint if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) { @@ -388,14 +384,12 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. USB0.dctl |= USB_SGOUTNAK_M; - while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) - ; + while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) ; // Ditto here- disable the endpoint. Note that only STALL and not SNAK // is set here. out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M); - while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) - ; + while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) ; out_ep[epnum].doepint = USB_EPDISBLD0_M; // Allow other OUT endpoints to keep receiving. @@ -698,6 +692,7 @@ void dcd_irq_handler(uint32_t rhport) if (int_status & USB_RXFLVI_M) { ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); + USB0.gintsts = USB_RXFLVI_M; // disable RXFLVI interrupt until we read data from FIFO USB0.gintmsk &= ~USB_RXFLVIMSK_M; @@ -706,8 +701,6 @@ void dcd_irq_handler(uint32_t rhport) // re-enable RXFLVI USB0.gintmsk |= USB_RXFLVIMSK_M; - - USB0.gintsts = USB_RXFLVI_M; } // OUT endpoint interrupt handling. From 30945ab9f3f7c96725e1cabbe084836b48a113b5 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 15:27:23 +0700 Subject: [PATCH 53/61] revert name to dcd_int_handler due to function prototype warning --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index d34e1c123..328ec2fb9 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -123,7 +123,7 @@ static void bus_reset(void) static void enum_done_processing(void) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); // On current silicon on the Full Speed core, speed is fixed to Full Speed. // However, keep for debugging and in case Low Speed is ever supported. uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); @@ -648,28 +648,28 @@ static void handle_epin_ints(void) } -void dcd_irq_handler(uint32_t rhport) +static void dcd_int_handler(void* arg) { - (void) rhport; + (void) arg; const uint32_t int_status = USB0.gintsts; //const uint32_t int_msk = USB0.gintmsk; if (int_status & USB_DISCONNINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); USB0.gintsts = USB_DISCONNINT_M; dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); } if (int_status & USB_USBRST_M) { // start of reset - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); USB0.gintsts = USB_USBRST_M; bus_reset(); } if (int_status & USB_RESETDET_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); USB0.gintsts = USB_RESETDET_M; bus_reset(); } @@ -691,7 +691,7 @@ void dcd_irq_handler(uint32_t rhport) #endif if (int_status & USB_RXFLVI_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); USB0.gintsts = USB_RXFLVI_M; // disable RXFLVI interrupt until we read data from FIFO @@ -705,13 +705,13 @@ void dcd_irq_handler(uint32_t rhport) // OUT endpoint interrupt handling. if (int_status & USB_OEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); handle_epout_ints(); } // IN endpoint interrupt handling. if (int_status & USB_IEPINT_M) { - ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!"); + ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); handle_epin_ints(); } @@ -736,7 +736,7 @@ void dcd_irq_handler(uint32_t rhport) void dcd_int_enable (uint8_t rhport) { (void) rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) dcd_irq_handler, NULL, &usb_ih); + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) dcd_int_handler, NULL, &usb_ih); } void dcd_int_disable (uint8_t rhport) From 978eec73b350ae5a52e47036c0dec163172944fa Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 15:39:59 +0700 Subject: [PATCH 54/61] remove 100us delay at the end of dcd_init() --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 328ec2fb9..26895c204 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -198,8 +198,6 @@ void dcd_init(uint8_t rhport) ESP_LOGV(TAG, "DCD init - Soft CONNECT"); USB0.dctl &= ~USB_SFTDISCON_M; // Connect - - ets_delay_us(100); } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) From c545cfc0bc9c4828c4b60515014386f770622166 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 15:42:50 +0700 Subject: [PATCH 55/61] Correct dedicated FIFO SRAM size to 1024 add note for up to 5 active IN endpoints (including EP0 IN) --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 26895c204..099f3af3e 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -46,9 +46,13 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -// FIFO size in bytes TODO need confirmation from Espressif +// Max number of bi-directional endpoints including EP0 +// Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0 +// We should probably prohibit enabling Endpoint IN > 4 (not done yet) #define EP_MAX USB_OUT_EP_NUM -#define EP_FIFO_SIZE 1280 + +// FIFO size in bytes +#define EP_FIFO_SIZE 1024 typedef struct { uint8_t *buffer; From d8d5902ccb24a29aebde009dfe388c23ffd8a6d3 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 15:44:50 +0700 Subject: [PATCH 56/61] change saola-1 led to pin 18 by default --- hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c index ef70f1ee2..8515e10e2 100644 --- a/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c +++ b/hw/bsp/esp32s2_saola_1/esp32s2_saola_1.c @@ -37,8 +37,8 @@ // Note: On the production version (v1.2) WS2812 is connected to GPIO 18, // however earlier revision v1.1 WS2812 is connected to GPIO 17 -//#define LED_PIN 18 // v1.2 and later -#define LED_PIN 17 // v1.1 +#define LED_PIN 18 // v1.2 and later +//#define LED_PIN 17 // v1.1 #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 From 8953bc9255712cace4eb3e66b1e89961952bb639 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 20:25:53 +0700 Subject: [PATCH 57/61] added comment note for beta chip walkaround --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index 099f3af3e..d1e670358 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -170,7 +170,17 @@ void dcd_init(uint8_t rhport) USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides -#ifdef CONFIG_IDF_TARGET_ESP32S2BETA // needed for beta chip only + +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA + // needed for beta chip only + // there was a bug in the phy logic that made the chip reset as soon as it transmitted anything. + // Setting the B override value made it ignore resets (any resets, generated by the faulty logic or not), + // which 'fixed' the problem well enough to test usb with it. + // Also, do note that the beta silicon run was very small and software support for it is not in mainstream esp-idf, + // as such you may consider phasing out support for it alltogether somewhere in the future + + // TODO we could safely remove this later (maybe after 2020) + //C. chip 7.2.2 hack ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack"); USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value From 5bd9d14fc14d9130d7d879800bd46e4ca08e3d5f Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Fri, 10 Apr 2020 10:23:56 -0400 Subject: [PATCH 58/61] stm32fsdev: set dcd_connect API definitions to strong, Modify documentation. --- docs/porting.md | 4 ++-- src/device/dcd.h | 4 ++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/porting.md b/docs/porting.md index 7d7d4cdb1..d3408aebd 100644 --- a/docs/porting.md +++ b/docs/porting.md @@ -62,7 +62,7 @@ All of the code for the low-level device API is in `src/portable//BCDR &= ~(USB_BCDR_DPPU); } -TU_ATTR_WEAK +// Enable internal D+ PU void dcd_connect(uint8_t rhport) { (void) rhport; From a37a56acd3ca70e0330d68da866d56faf00e82ce Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Apr 2020 23:38:36 +0700 Subject: [PATCH 59/61] remove CONFIG_IDF_TARGET_ESP32S2BETA per review --- src/portable/espressif/esp32s2/dcd_esp32s2.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index d1e670358..de9ef6b6d 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -168,27 +168,8 @@ void dcd_init(uint8_t rhport) USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode - USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides -#ifdef CONFIG_IDF_TARGET_ESP32S2BETA - // needed for beta chip only - // there was a bug in the phy logic that made the chip reset as soon as it transmitted anything. - // Setting the B override value made it ignore resets (any resets, generated by the faulty logic or not), - // which 'fixed' the problem well enough to test usb with it. - // Also, do note that the beta silicon run was very small and software support for it is not in mainstream esp-idf, - // as such you may consider phasing out support for it alltogether somewhere in the future - - // TODO we could safely remove this later (maybe after 2020) - - //C. chip 7.2.2 hack - ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack"); - USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value - ets_delay_us(20); - USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable - ets_delay_us(20); -#endif - // C. Setting SNAKs, then connect for (int n = 0; n < USB_OUT_EP_NUM; n++) { USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK From ae1314f1c77bb043789d54bf8a7fa30ff7efd1e2 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 11 Apr 2020 12:55:45 +0700 Subject: [PATCH 60/61] fix incorrect setup packet also increase usbd stack in example when debug is enabled --- examples/device/cdc_msc_freertos/src/main.c | 8 +++++++- src/portable/espressif/esp32s2/dcd_esp32s2.c | 8 +++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index f093d8ea0..77184ff58 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -56,7 +56,13 @@ StaticTimer_t blinky_tmdef; TimerHandle_t blinky_tm; // static task for usbd -#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) +// Increase stack size when debug log is enabled +#if CFG_TUSB_DEBUG + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE) +#else + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) +#endif + StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c index de9ef6b6d..126f3ea20 100644 --- a/src/portable/espressif/esp32s2/dcd_esp32s2.c +++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c @@ -331,9 +331,8 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to USB0.dtknqr4_fifoemptymsk |= (1 << epnum); } else { // Each complete packet for OUT xfers triggers XFRC. - USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M | - ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); - USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; + USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; } return true; } @@ -603,8 +602,7 @@ static void handle_epout_ints(void) dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); } else { // Schedule another packet to be received. - USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M | - ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[n].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M; } } From 1751064f705f92396863074487d1aaf83bba61d6 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 11 Apr 2020 13:40:40 +0700 Subject: [PATCH 61/61] print correct example name --- examples/device/cdc_msc_freertos/src/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 77184ff58..a847f4915 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -200,7 +200,7 @@ void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) if ( dtr && rts ) { // print initial message when connected - tud_cdc_write_str("\r\nTinyUSB CDC MSC HID device with FreeRTOS example\r\n"); + tud_cdc_write_str("\r\nTinyUSB CDC MSC device with FreeRTOS example\r\n"); } }