lib: update repo

make dragon kicad compatible
add old and new year logo
2024-03-18 23:44:10 +01:00 · 2024-03-18 23:43:19 +01:00 · 2024-03-08 07:24:21 +01:00 · 2024-03-08 07:14:50 +01:00 · 2024-03-08 07:14:21 +01:00 · 2024-03-08 07:14:21 +01:00
51 changed files with 8203 additions and 1611 deletions
--- a/.gitignore
+++ b/.gitignore
@ -1,18 +1,37 @@
+# schematic lepton-EDA
+*.sch
+
+# board layout pcb-rnd
+*.lht
 *.lht.*
-*.versioned.lht
+
+# KiCAD
+*.kicad_prl
+*.kicad_pro-bak
+*.xml
+fp-info-cache
+
+# temporary files
 *~
-*.versioned.sch
+\#*\#
+~*.lck
+
+# outputs
 *.svg
+*.png
 *.pdf
 *.ps
 *.zip
-*.brd.*
-*.tdx
-\#*\#
-*.notes.txt
 *.bom.csv
-*.cost.csv
 *.cpl.csv
+*.3d.step
+*.versioned.*
+fabrication
+
+# scripts and utilities
 *.json
 *.rb
-geda/footprints/
+
+# panel files
+panel.*
+panel
--- a/.gitmodules
+++ b/.gitmodules
@ -1,3 +1,3 @@
 [submodule "library"]
 	path = library
-	url = http://git.cuvoodoo.info/qeda_library
+	url = https://git.cuvoodoo.info/kingkevin/qeda_library
--- a/.qeda.yaml
+++ b/.qeda.yaml
@ -1,9 +1,16 @@
 config:
-  output: coraleda
+  nodate: true
+  output: kicad7
+  symbol:
+    pinIcon: false
  pattern:
    densityLevel: 'N'
    lineWidth:
      silkscreen: 0.2
+    polarityMark: none
    preferManufacturer: false
    smoothPadCorners: false
 library:
+  - resistor/r0603
+  - capacitor/c0603
+  - diode/led0805
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
--- a/DEVELOPMENT.md
+++ b/DEVELOPMENT.md
@ -0,0 +1,108 @@
+this will describe how to generate the output files form the sources.
+
+requirements
+============
+
+to be able to generate the outputs, you need following software:
+
+- [QEDA](http://qeda.org/): to generate footprints for the parts
+- [KiCad v7](https://www.kicad.org/): EDA software used for schematic capture and board layout
+- [PcbDraw](https://github.com/yaqwsx/PcbDraw): to generate board layout rendering
+- [KiKit](https://github.com/yaqwsx/KiKit): to generate fabrications files (Gerber, Excellon)
+- [KiBoM](https://github.com/SchrodingersGat/KiBoM): to generate Bill of Material (CSV)
+- [Interactive HTML BOM](https://github.com/openscopeproject/InteractiveHtmlBom): to generate placement guide
+
+install Interactive HTML BOM using KiCad's Plugin and Content Manager.
+
+for the others:
+
+~~~
+npm install qeda
+pip install pcbdraw kibom kikit
+~~~
+
+you can additionally install  KiKit using KiCad's Plugin and Content Manager for an integrated GUI.
+
+compiling
+=========
+
+to generate schematic, BoM, board render, and fabrication output, run `make`.
+
+library
+-------
+
+almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software.
+the `library` folder contains the QEDA parts definitions.
+
+to install QEDA using NPM from the official repository:
+
+~~~
+sudo npm install -g qeda
+~~~
+
+to install QEDA from the sources:
+
+~~~
+git clone https://github.com/qeda/qeda
+cd qeda
+npm install
+sudo npm install --global
+~~~
+
+to generate the parts:
+
+~~~
+make lib
+~~~
+
+this will use the parts definition (.yaml files) in the `library` to generate the symbols (.sym files) and footprints used by KiCAD in the `kicad` folder.
+
+schematic
+---------
+
+the `.kicad_sch` file is the schematic source file.
+it has been drawn using the [KiCAD eeschema](https://www.kicad.org/) schematic editor.
+
+it uses standard symbols, and the ones in the `kicad/` folder.
+most symbols are generated by QEDA as described above.
+
+to export as pdf:
+
+~~~
+make print
+~~~
+
+BOM
+---
+
+to export the bill of material (as CSV):
+
+~~~
+make bom
+~~~
+
+board
+-----
+
+the `.kicad_brd` file is the board layout source file.
+it has been drawn using the [KiCAD pcbnew](https://docs.kicad.org/6.0/en/pcbnew/pcbnew.html) PCB editor.
+
+it uses the footprints from the `kicad/` folder.
+most symbols are generated by QEDA as described above.
+
+to export gerber files for PCB manufacturer (and photo preview + overview document):
+
+~~~
+make fabrication
+~~~
+
+versioning
+----------
+
+the source schematic and board layout do not include version information.
+when generating schematic or board fabrication output, a copy of the source files with date and version information is done as `.versioned.` files.
+the date corresponds to the last changes (i.e. commit).
+the version is formatted as `v.r`:
+
+- `v` corresponds to the major version information defined in `version`
+- `r` corresponds to the total number of changes done to the source files
--- a/KiBOM_CLI.py
+++ b/KiBOM_CLI.py
@ -0,0 +1,28 @@
+#!/usr/bin/env python3
+"""
+    @package
+    KiBOM - Bill of Materials generation for KiCad
+
+    Generate BOM in xml, csv, txt, tsv, html or xlsx formats.
+
+    - Components are automatically grouped into BoM rows (grouping is configurable)
+    - Component groups count number of components and list component designators
+    - Rows are automatically sorted by component reference(s)
+    - Supports board variants
+
+    Extended options are available in the "bom.ini" config file in the PCB directory
+    (this file is auto-generated with default options the first time the script is executed).
+
+    For usage help:
+    python KiBOM_CLI.py -h
+"""
+
+import sys
+import os
+
+here = os.path.abspath(os.path.dirname(__file__))
+sys.path.insert(0, here)
+
+from kibom.__main__ import main  # noqa: E402
+
+main()
--- a/100
+++ b/100
@ -0,0 +1,100 @@
+# project file name (use for schematic and board layout)
+NAME ?= template
+SUBSHEET ?= 
+# path to KiCad CLI
+KICAD = kicad-cli
+# path to qeda
+QEDA := qeda
+# path to KiBOM
+KIBOM := kibom
+# path to InteractiveHtmlBom
+IBOMGEN := ~/.local/share/kicad/7.0/3rdparty/plugins/org_openscopeproject_InteractiveHtmlBom/generate_interactive_bom.py
+
+# read project version
+VERSION := $(shell cat version)
+# current date for stamping output
+DATE = $(shell date +%Y-%m-%d)
+# revision based on number of changes on schematic or board layout
+REVISION := $(shell git log --pretty=oneline "${NAME}.kicad_sch" "${NAME}.kicad_pcb" | wc -l)
+
+# generate file with version information
+VERSIONED_EXT = kicad_sch kicad_pcb kicad_pro json
+define version_rule
+%.versioned.$1: %.$1
+	cp $$< $$@
+	sed --in-place 's/\$$$$version\$$$$/${VERSION}/g' $$@
+	sed --in-place 's/\$$$$date\$$$$/${DATE}/g' $$@
+	sed --in-place 's/\$$$$revision\$$$$/${REVISION}/g' $$@
+	sed --in-place 's/\.kicad_sch/.versioned.kicad_sch/g' $$@
+endef
+$(foreach EXT,$(VERSIONED_EXT),$(eval $(call version_rule,$(EXT))))
+VERSIONED_SHEET = $(foreach SHEET,$(NAME) $(SUBSHEET),$(SHEET).versioned.kicad_sch)
+
+FABRICATION_DIR := fabrication
+IBOM := ${FABRICATION_DIR}/ibom.html
+
+all: $(VERSIONED_SHEET) ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.bom.csv ${NAME}.3d.step fab
+
+fab: ${FABRICATION_DIR} ${IBOM}
+
+# generate fabrication files (gerbers/drill/BoM/PnP)
+${FABRICATION_DIR}: ${NAME}.versioned.kicad_sch ${NAME}.versioned.kicad_pcb
+	kikit fab jlcpcb --no-drc --assembly --field JLCPCB,LCSC --schematic $^ $@
+
+# generate fabrication files (gerbers/drill/uncorrected PnP)
+#${FABRICATION_DIR}: ${NAME}.versioned.kicad_pcb
+#	mkdir -p ${FABRICATION_DIR}
+#	$(KICAD) pcb export gerbers --output ${FABRICATION_DIR} $<
+#	$(KICAD) pcb export drill --output ${FABRICATION_DIR}/ $<
+#	$(KICAD) pcb export pos --output ${FABRICATION_DIR}/${NAME}.versioned.pos $<
+
+# generate interactive BoM
+${IBOM}: ${NAME}.versioned.kicad_pcb
+	python $(IBOMGEN) --no-browser --dest-dir `dirname $@` --name-format `basename $@ ".html"` --show-fields "Value" $< &>/dev/null
+
+# generate symbols and footprints from parts
+lib:
+	$(QEDA) generate qeda
+
+# generate printable version (PDF) of schematic
+%.sch.pdf: %.versioned.kicad_sch %.versioned.kicad_pro
+	$(KICAD) sch export pdf --output $@ $<
+
+# generate render from layout (top side)
+%.brd-top.png: %.versioned.kicad_pcb
+	pcbdraw plot --silent --no-components --dpi 600 --side front $< $@
+
+# generate render from layout (bottom side)
+%.brd-bot.png: %.versioned.kicad_pcb
+	pcbdraw plot --silent --no-components --dpi 600 --side back $< $@
+
+# export Bill of Material (as CSV)
+%.bom.xml: %.versioned.kicad_sch %.versioned.kicad_pro
+	$(KICAD) sch export python-bom --output $@ $<
+
+# export 3D model
+%.3d.step: %.versioned.kicad_pcb
+	$(KICAD) pcb export step --output $@ $<
+
+# export Bill of Material (as CSV)
+%.bom.csv: %.bom.xml
+	$(KIBOM) $< $@
+
+# generate panel
+PANEL_DIR := panel
+panel: panel.kicad_pcb
+panel.kicad_pcb: ${NAME}.versioned.kicad_pcb ${NAME}.versioned.kicad_pro ${NAME}.versioned.kicad_sch ${NAME}.versioned.json
+	kikit panelize -p ${NAME}.versioned.json ${NAME}.versioned.kicad_pcb $@
+	sed --in-place 's/\"missing_courtyard\": \"warning\"/\"missing_courtyard\": \"ignore\"/g' $(patsubst %.kicad_pcb,%.kicad_pro,$@) # the mouse bites don't have a courtyard
+	kikit fab jlcpcb --assembly --missingError --field JLCPCB,LCSC --schematic ${NAME}.versioned.kicad_sch $@ ${PANEL_DIR}
+	pcbdraw --silent $@ --dpi 600 panel.brd-top.png
+	pcbdraw --silent $@ --dpi 600 --back panel.brd-bot.png
+
+clean:
+	rm -f $(foreach EXT,$(VERSIONED_EXT),${NAME}.versioned.$(EXT))
+	rm -f ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.versioned.xml ${NAME}.bom.csv
+	rm -f ${NAME}.versioned.kicad_prl ${NAME}.versioned.kicad_pro-bak ${NAME}.versioned.xml ${NAME}.versioned.csv
+	rm -f ${IBOM}
+	rm -rf ${FABRICATION_DIR}
+	rm -f panel.kicad_pcb panel.kicad_pro 
+	rm -rf ${PANEL_DIR}
--- a/README.md
+++ b/README.md
@ -5,84 +5,3 @@ purpose

 usage
 =====
-
-requirements
-============
-
-to be able to generate the outputs you need following software:
-
- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files)
- [QEDA](http://qeda.org/): to generate footprints for the parts
- [Lepton EDA](https://github.com/lepton-eda/lepton-eda): for the schematic capture
- [pcb-rnd](http://repo.hu/projects/pcb-rnd/): for the board layout
-the output generation is automatized.
-
-compiling
-=========
-
-library
-------
-
-almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software.
-the `library` folder contains the QEDA parts definitions.
-
-to install QEDA using NPM from the official repository:
-~~~
-sudo npm install -g qeda
-~~~
-
-to install QEDA from the sources:
-~~~
-git clone https://github.com/qeda/qeda
-cd qeda
-npm install
-sudo npm install --global
-~~~
-
-to generate the parts:
-~~~
-rake library
-~~~
-
-this will use the parts definition (.yaml files) in the `library` to generate [gEDA gschem](http://wiki.geda-project.org/geda:gaf)/[Lepton EDA](https://github.com/lepton-eda/lepton-eda) symbols (.sym files) in the `geda/symbols` folder, and [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/) footprints (.lht files) in the `coraleda/subc` folder.
-
-only the QEDA parts in subfolders within `library` come from the [QEDA library](https://doc.qeda.org/library/), but the files are included in this project for simplicity and archiving purposes.
-all other parts are custom and written for this project.
-
-schematic
---------
-
-the `.sch` file is the schematic source file.
-it has been drawn using [Lepton EDA](https://github.com/lepton-eda/lepton-eda).
-
-it uses standard symbols, and the ones in the `geda/symbols/` folder.
-most symbols are generated by QEDA as described above.
-
-to export as pdf:
-~~~
-rake print
-~~~
-
-BOM
---
-
-to export the bill of material (as CSV):
-~~~
-rake bom
-~~~
-
-board
-----
-
-the `.lht` file is the board layout source file.
-it has been drawn using  [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/).
-
-it uses the symbols from the `coraleda/subc/` folder.
-most symbols are generated by QEDA as described above.
-`oshw_logo.lht` is just the Open Source Hardware Logo.
-it been generated from https://oshwlogo.cuvoodoo.info/.
-
-to export gerber files for PCB manufacturer (and photo preview + overview document):
-~~~
-rake fabrication
-~~~
--- a/176
+++ b/176
@ -1,176 +0,0 @@
-# encoding: utf-8
-# ruby: 2.1.0
-=begin
-Rakefile to manage hardware projects
-
-uses Lepton EDA for schematic and pcb-rnd for board layouts.
-Rakefile instead of Makefile for better text file parsing capabilities.
-=end
-require 'rake/clean'
-require 'csv' # to export BOM and costs
-
-# =================
-# project variables
-# =================
-
-# common name used for file names
-name = "template"
-# project version, read from "version" file
-raise "define project version in 'version' file" unless File.exist? "version"
-version = IO.read("version").split("\n")[0]
-# current date for stamping output
-date = Time.now.strftime("%Y-%m-%d")
-# revision based on number of changes on schematic or board layout and current git commit
-changes = `git log --pretty=oneline "#{name}.sch" "#{name}.lht" | wc -l`.chomp.to_i
-commit = `git rev-parse --short HEAD`.chomp
-revision = "#{changes} (#{commit})"
-
-# path to qeda"
-qeda = "qeda"
-
-# ==========
-# main tasks
-# ==========
-
-desc "main building task"
-task :default => [:print, :fabrication, :bom, :pnp]
-
-desc "print schematic and layout (as pdf)"
-prints = [ "#{name}.sch.pdf", "#{name}.brd.pdf", "#{name}.brd-top.svg", "#{name}.brd-bottom.svg" ]
-task :print => prints
-CLEAN.include([ "#{name}.versioned.sch", "#{name}.versioned.lht" ])
-CLOBBER.include(prints)
-
-desc "generate fabrication gerbers (as archive)"
-gerbers = [ "#{name}.brd.asb", "#{name}.brd.ast", "#{name}.brd.gbl", "#{name}.brd.gbo", "#{name}.brd.gbp", "#{name}.brd.gbs", "#{name}.brd.gko", "#{name}.brd.gtl", "#{name}.brd.gto", "#{name}.brd.gtp", "#{name}.brd.gts", "#{name}.brd.xln", "#{name}.brd.g2l", "#{name}.brd.g3l" ]
-fab = [ "#{name}.brd.zip" ]
-task :fabrication => fab
-CLEAN.include(gerbers)
-CLOBBER.include(fab)
-
-desc "generate symbols and footprints from parts"
-task :library do
-  sh "#{qeda} config output geda"
-  sh "#{qeda} generate ."
-  sh "#{qeda} config output coraleda"
-  sh "#{qeda} generate ."
-end
-
-desc "export BOMs from schematic"
-boms = [ "#{name}.bom.csv" ]
-task :bom => boms
-CLOBBER.include(boms)
-
-desc "export PnP placement"
-pnps = [ "#{name}.cpl.csv" ]
-task :pnp => pnps
-CLOBBER.include(pnps)
-
-# ===============
-# file generation
-# ===============
-
-desc "generate schematic with version information all symbols embedded"
-rule ".versioned.sch" => ".sch" do |t|
-  sh "cp #{t.source} #{t.name}"
-  sh "lepton-embed --embed #{t.name} 2> /dev/null"
-  sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
-  sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
-  sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
-end
-
-desc "generate board layout with version information"
-rule ".versioned.lht" => ".lht" do |t|
-  sh "cp #{t.source} #{t.name}"
-  sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
-  sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
-  sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
-end
-
-desc "generate printable version (PDF) of schematic"
-rule ".sch.pdf" => ".versioned.sch" do |t|
-  sh "lepton-cli export --color --paper iso_a4 --layout landscape --output #{t.name} #{t.source} 2> /dev/null"
-end
-
-desc "generate printable version (PostScript) of board layout"
-rule ".brd.ps" => ".versioned.lht" do |t|
-  sh "pcb-rnd -x ps --ps-color --media A4 --psfile #{t.name} #{t.source} 2> /dev/null"
-end
-
-desc "generate printable version (PDF) of board layout"
-rule ".brd.pdf" => ".brd.ps" do |t|
-  sh "ps2pdf -sPAPERSIZE=a4 -dEPSCrop #{t.source} #{t.name}"
-end
-
-desc "generate photo realistic picture from layout (top side)"
-rule ".brd-top.svg" => ".versioned.lht" do |t|
-  sh "pcb-rnd -x svg --photo-mode --outfile #{t.name} #{t.source} 2> /dev/null"
-end
-
-desc "generate photo realistic picture from layout (bottom side)"
-rule ".brd-bottom.svg" => ".versioned.lht" do |t|
-  sh "pcb-rnd -x svg --photo-mode --flip --outfile #{t.name} #{t.source} 2> /dev/null"
-end
-
-desc "archive gerbers"
-rule ".brd.zip" => ".versioned.lht" do |t|
-  base = File.basename(t.source, ".versioned.lht")
-  puts base
-  sh "pcb-rnd -x cam gerber:JLC_PCB --outfile #{base}.brd #{t.source} 2> /dev/null"
-  sh "zip --quiet #{t.name} #{base}.brd.xln #{base}.brd.a* #{base}.brd.g*"
-end
-
-desc "generate BOM file from schematic"
-rule ".bom.csv" => ".sch" do |t|
-  attributes = ["device", "value", "description", "footprint", "manufacturer", "mpn", "datasheet", "lcsc", "digikey"]
-  bom_data = bom2(t.prerequisites[0],attributes)
-  CSV.open(t.name, "wb") do |csv|
-    all_attributes = ["refdes","qty"]+attributes
-    csv << all_attributes
-    bom_data.each do |line|
-      csv << all_attributes.collect{|attribute| line[attribute]}
-    end
-  end
-end
-
-desc "generate pick-and-place file from board"
-rule ".cpl.csv" => [".versioned.lht", "mass_prop.sh", "pnp_fab.tab"] do |t|
-  sh "./mass_prop.sh #{t.prerequisites[0]} pnp_fab.tab" # add fab placement offsets
-  sh "pcb-rnd -x XY --xyfile #{t.name} --xy-unit mm --format 'JLCPCB' --vendor jlcpcb #{t.prerequisites[0]}" # export XY file in JLCPCB format
-end
-
-# ================
-# helper functions
-# ================
-
-# generate gnetlist bom2 and parse them
-# arguments: schematic=schematic to use, attributes=attributes to use for generating bom2
-# returns an array of hash. key is the attribute name, value is the attribute value
-def bom2(schematic, attributes)
-  to_return = []
-  # force attributes to be an array
-  attributes = case attributes
-  when String
-   [attributes]
-  when Array
-    attributes
-  else
-    [attributes.to_s]
-  end
-  # generate bom2
-  list = `lepton-netlist --backend bom2 --backend-option attribs=#{attributes*','} --quiet --output - #{schematic} 2> /dev/null`
-  list = list.each_line {|l| '"' + l + '"' + '\n' }
-  list.gsub!(/^(.+)/, '"\1')
-  list.gsub!(/(.+)$/, '\1"')
-  list.gsub!(/(?!http):(?!\/\/)/, '\1":"\2') # protect the values between ':' (such as URLs)
-  # parse bom2
-  csv = CSV.parse(list, col_sep: ":", quote_char: '"')
-  csv[1..-1].each do |row|
-    line = {}
-    row.each_index do |col|
-      line[csv[0][col]] = row[col] unless row[col] == "unknown"
-    end
-    to_return << line
-  end
-  return to_return
-end
--- a/bom.ini
+++ b/bom.ini
@ -0,0 +1,108 @@
+[BOM_OPTIONS]
+; General BoM options here
+; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
+ignore_dnf = 0
+; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
+html_generate_dnf = 1
+; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
+use_alt = 0
+; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
+alt_wrap = 0
+; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
+number_rows = 1
+; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
+group_connectors = 1
+; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
+test_regex = 1
+; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
+merge_blank_fields = 1
+; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
+output_file_name = %O%V
+; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
+variant_file_name_format = _(%V)
+; Field name used to determine if a particular part is to be fitted
+fit_field = Config
+; Make a backup of the bom before generating the new one, using the following template
+;make_backup = %O.tmp
+; Default number of boards to produce if none given on CLI with -n
+number_boards = 1
+; Default PCB variant if none given on CLI with -r
+board_variant = ['default']
+; Whether to hide headers from output file
+hide_headers = False
+; Whether to hide PCB info from output file
+hide_pcb_info = False
+
+[IGNORE_COLUMNS]
+; Any column heading that appears here will be excluded from the Generated BoM
+; Titles are case-insensitive
+Part
+Part Lib
+Footprint
+Footprint Lib
+Build Quantity
+sheetpath
+qeda_part
+qeda_variant
+name
+JLCPCB_CORRECTION
+Rating
+
+[COLUMN_ORDER]
+; Columns will appear in the order they are listed here
+; Titles are case-insensitive
+References
+Value
+Quantity Per PCB
+Description
+Part
+Part Lib
+Footprint
+Footprint Lib
+Build Quantity
+Manufacturer
+MPN
+DigiKey
+LCSC
+JLCPCB
+Datasheet
+
+[GROUP_FIELDS]
+; List of fields used for sorting individual components into groups
+; Components which match (comparing *all* fields) will be grouped together
+; Field names are case-insensitive
+Value
+Footprint
+Footprint Lib
+
+[COMPONENT_ALIASES]
+; A series of values which are considered to be equivalent for the part name
+; Each line represents a list of equivalent component name values separated by white space
+; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
+; Aliases are case-insensitive
+c	c_small	cap	capacitor
+r	r_small	res	resistor
+sw	switch
+l	l_small	inductor
+zener	zenersmall
+d	diode	d_small
+
+[REGEX_INCLUDE]
+; A series of regular expressions used to include parts in the BoM
+; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
+; Column names are case-insensitive
+; Format is: "[ColumName] [Regex]" (white-space separated)
+
+[REGEX_EXCLUDE]
+; A series of regular expressions used to exclude parts from the BoM
+; If a component matches ANY of these, it will be excluded from the BoM
+; Column names are case-insensitive
+; Format is: "[ColumName] [Regex]" (white-space separated)
+References	^TP[0-9]*
+References	^FID
+Part	mount.*hole
+Part	solder.*bridge
+Part	test.*point
+Footprint	test.*point
+Footprint	mount.*hole
+Footprint	fiducial
--- a/coraleda/subc/oshw_logo.lht
+++ b/coraleda/subc/oshw_logo.lht
@ -1,421 +0,0 @@
-# footprint generated from CuVoodoo Land Pattern
-# author: King Kévin
-# version: 1
-# date: 2019-05-13
-li:pcb-rnd-subcircuit-v6 {
- ha:subc.1 {
-  uid = any_24_ASCII_characters_
-  ha:attributes {
-   footprint = open source hardware logo
-  }
-  ha:data {
-   li:padstack_prototypes {
-   }
-   li:objects {
-   }
-   li:layers {
-    ha:top-silkscreen {
-     lid = 1
-     ha:type {
-      top = 1
-      silk = 1
-     }
-     li:objects {
-      ha:line.2{
-       clearance = 0
-       x1 = 0.15mm
-       y1 = 1.8mm
-       x2 = 0.75mm
-       y2 = 1.8mm
-       thickness = 0.3mm
-      }
-      ha:line.3{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 5.8500000000000005mm
-       x2 = 1.8mm
-       y2 = 6.45mm
-       thickness = 0.3mm
-      }
-      ha:line.4{
-       clearance = 0
-       x1 = 5.8500000000000005mm
-       y1 = 1.8mm
-       x2 = 6.45mm
-       y2 = 1.8mm
-       thickness = 0.3mm
-      }
-      ha:line.5{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 0.15mm
-       x2 = 1.8mm
-       y2 = 0.75mm
-       thickness = 0.3mm
-      }
-      ha:line.6{
-       clearance = 0
-       x1 = 0.15mm
-       y1 = 2.4mm
-       x2 = 0.75mm
-       y2 = 2.4mm
-       thickness = 0.3mm
-      }
-      ha:line.7{
-       clearance = 0
-       x1 = 2.4mm
-       y1 = 5.8500000000000005mm
-       x2 = 2.4mm
-       y2 = 6.45mm
-       thickness = 0.3mm
-      }
-      ha:line.8{
-       clearance = 0
-       x1 = 5.8500000000000005mm
-       y1 = 2.4mm
-       x2 = 6.45mm
-       y2 = 2.4mm
-       thickness = 0.3mm
-      }
-      ha:line.9{
-       clearance = 0
-       x1 = 2.4mm
-       y1 = 0.15mm
-       x2 = 2.4mm
-       y2 = 0.75mm
-       thickness = 0.3mm
-      }
-      ha:line.10{
-       clearance = 0
-       x1 = 0.15mm
-       y1 = 3mm
-       x2 = 0.75mm
-       y2 = 3mm
-       thickness = 0.3mm
-      }
-      ha:line.11{
-       clearance = 0
-       x1 = 3mm
-       y1 = 5.8500000000000005mm
-       x2 = 3mm
-       y2 = 6.45mm
-       thickness = 0.3mm
-      }
-      ha:line.12{
-       clearance = 0
-       x1 = 5.8500000000000005mm
-       y1 = 3mm
-       x2 = 6.45mm
-       y2 = 3mm
-       thickness = 0.3mm
-      }
-      ha:line.13{
-       clearance = 0
-       x1 = 3mm
-       y1 = 0.15mm
-       x2 = 3mm
-       y2 = 0.75mm
-       thickness = 0.3mm
-      }
-      ha:line.14{
-       clearance = 0
-       x1 = 0.15mm
-       y1 = 3.5999999999999996mm
-       x2 = 0.75mm
-       y2 = 3.5999999999999996mm
-       thickness = 0.3mm
-      }
-      ha:line.15{
-       clearance = 0
-       x1 = 3.5999999999999996mm
-       y1 = 5.8500000000000005mm
-       x2 = 3.5999999999999996mm
-       y2 = 6.45mm
-       thickness = 0.3mm
-      }
-      ha:line.16{
-       clearance = 0
-       x1 = 5.8500000000000005mm
-       y1 = 3.5999999999999996mm
-       x2 = 6.45mm
-       y2 = 3.5999999999999996mm
-       thickness = 0.3mm
-      }
-      ha:line.17{
-       clearance = 0
-       x1 = 3.5999999999999996mm
-       y1 = 0.15mm
-       x2 = 3.5999999999999996mm
-       y2 = 0.75mm
-       thickness = 0.3mm
-      }
-      ha:line.18{
-       clearance = 0
-       x1 = 0.15mm
-       y1 = 4.2mm
-       x2 = 0.75mm
-       y2 = 4.2mm
-       thickness = 0.3mm
-      }
-      ha:line.19{
-       clearance = 0
-       x1 = 4.2mm
-       y1 = 5.8500000000000005mm
-       x2 = 4.2mm
-       y2 = 6.45mm
-       thickness = 0.3mm
-      }
-      ha:line.20{
-       clearance = 0
-       x1 = 5.8500000000000005mm
-       y1 = 4.2mm
-       x2 = 6.45mm
-       y2 = 4.2mm
-       thickness = 0.3mm
-      }
-      ha:line.21{
-       clearance = 0
-       x1 = 4.2mm
-       y1 = 0.15mm
-       x2 = 4.2mm
-       y2 = 0.75mm
-       thickness = 0.3mm
-      }
-      ha:line.22{
-       clearance = 0
-       x1 = 0.15mm
-       y1 = 4.8mm
-       x2 = 0.75mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.23{
-       clearance = 0
-       x1 = 4.8mm
-       y1 = 5.8500000000000005mm
-       x2 = 4.8mm
-       y2 = 6.45mm
-       thickness = 0.3mm
-      }
-      ha:line.24{
-       clearance = 0
-       x1 = 5.8500000000000005mm
-       y1 = 4.8mm
-       x2 = 6.45mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.25{
-       clearance = 0
-       x1 = 4.8mm
-       y1 = 0.15mm
-       x2 = 4.8mm
-       y2 = 0.75mm
-       thickness = 0.3mm
-      }
-      ha:line.26{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 1.35mm
-       x2 = 4.8mm
-       y2 = 1.35mm
-       thickness = 0.3mm
-      }
-      ha:line.27{
-       clearance = 0
-       x1 = 5.25mm
-       y1 = 1.8mm
-       x2 = 5.25mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.28{
-       clearance = 0
-       x1 = 4.8mm
-       y1 = 5.25mm
-       x2 = 1.8mm
-       y2 = 5.25mm
-       thickness = 0.3mm
-      }
-      ha:line.29{
-       clearance = 0
-       x1 = 1.35mm
-       y1 = 4.8mm
-       x2 = 1.35mm
-       y2 = 1.8mm
-       thickness = 0.3mm
-      }
-      ha:arc.30{
-       clearance = 0
-       x = 1.8mm
-       y = 1.8mm
-       width = 0.45mm
-       height = 0.45mm
-       thickness = 0.3mm
-       astart = 0
-       adelta = -90
-      }
-      ha:arc.31{
-       clearance = 0
-       x = 4.8mm
-       y = 1.8mm
-       width = 0.45mm
-       height = 0.45mm
-       thickness = 0.3mm
-       astart = -90
-       adelta = -90
-      }
-      ha:arc.32{
-       clearance = 0
-       x = 4.8mm
-       y = 4.8mm
-       width = 0.45mm
-       height = 0.45mm
-       thickness = 0.3mm
-       astart = 180
-       adelta = -90
-      }
-      ha:arc.33{
-       clearance = 0
-       x = 1.8mm
-       y = 4.8mm
-       width = 0.45mm
-       height = 0.45mm
-       thickness = 0.3mm
-       astart = 90
-       adelta = -90
-      }
-      ha:line.34{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 1.8mm
-       x2 = 3mm
-       y2 = 1.8mm
-       thickness = 0.3mm
-      }
-      ha:line.35{
-       clearance = 0
-       x1 = 3mm
-       y1 = 1.8mm
-       x2 = 3mm
-       y2 = 3mm
-       thickness = 0.3mm
-      }
-      ha:line.36{
-       clearance = 0
-       x1 = 3mm
-       y1 = 3mm
-       x2 = 1.8mm
-       y2 = 3mm
-       thickness = 0.3mm
-      }
-      ha:line.37{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 3mm
-       x2 = 1.8mm
-       y2 = 1.8mm
-       thickness = 0.3mm
-      }
-      ha:line.38{
-       clearance = 0
-       x1 = 4.8mm
-       y1 = 1.8mm
-       x2 = 3.5999999999999996mm
-       y2 = 1.8mm
-       thickness = 0.3mm
-      }
-      ha:line.39{
-       clearance = 0
-       x1 = 3.5999999999999996mm
-       y1 = 1.8mm
-       x2 = 3.5999999999999996mm
-       y2 = 2.4mm
-       thickness = 0.3mm
-      }
-      ha:line.40{
-       clearance = 0
-       x1 = 3.5999999999999996mm
-       y1 = 2.4mm
-       x2 = 4.8mm
-       y2 = 2.4mm
-       thickness = 0.3mm
-      }
-      ha:line.41{
-       clearance = 0
-       x1 = 4.8mm
-       y1 = 2.4mm
-       x2 = 4.8mm
-       y2 = 3mm
-       thickness = 0.3mm
-      }
-      ha:line.42{
-       clearance = 0
-       x1 = 4.8mm
-       y1 = 3mm
-       x2 = 3.5999999999999996mm
-       y2 = 3mm
-       thickness = 0.3mm
-      }
-      ha:line.43{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 3.5999999999999996mm
-       x2 = 1.8mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.44{
-       clearance = 0
-       x1 = 1.8mm
-       y1 = 4.199999999999999mm
-       x2 = 3mm
-       y2 = 4.199999999999999mm
-       thickness = 0.3mm
-      }
-      ha:line.45{
-       clearance = 0
-       x1 = 3mm
-       y1 = 3.5999999999999996mm
-       x2 = 3mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.46{
-       clearance = 0
-       x1 = 3.5999999999999996mm
-       y1 = 3.5999999999999996mm
-       x2 = 3.5999999999999996mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.47{
-       clearance = 0
-       x1 = 3.5999999999999996mm
-       y1 = 4.8mm
-       x2 = 4.199999999999999mm
-       y2 = 4.2mm
-       thickness = 0.3mm
-      }
-      ha:line.48{
-       clearance = 0
-       x1 = 4.199999999999999mm
-       y1 = 4.2mm
-       x2 = 4.799999999999999mm
-       y2 = 4.8mm
-       thickness = 0.3mm
-      }
-      ha:line.49{
-       clearance = 0
-       x1 = 4.799999999999999mm
-       y1 = 4.8mm
-       x2 = 4.799999999999999mm
-       y2 = 3.5999999999999996mm
-       thickness = 0.3mm
-      }
-     }
-    }
-   }
-  }
- }
-}
--- a/coraleda/subc/qr
+++ b/coraleda/subc/qr
@ -1,39 +0,0 @@
-#!/bin/sh
-
-#@@example qr(hello world, 1mm)
-
-#@@purpose Generate QR code on silk
-
-#@@desc Generate the specified QR code as silk lines
-#@@params text,pixel_size,level
-#@@thumbsize 2
-
-#@@param:text ASCII text to encode
-
-#@@param:pixel_size width and height of each pixel
-#@@dim:pixel_size
-
-#@@param:level error correction level
-#@@optional:level
-#@@enum:level:L low
-#@@enum:level:H high
-#@@default:L
-
-libdir=""
-for n in  $PCB_RND_PCBLIB/parametric `dirname $0` /usr/local/share/pcb-rnd/pcblib/parametric /usr/share/pcb-rnd/pcblib/parametric
-do
-	if test -f "$n/common.awk"
-	then
-		libdir="$n"
-		break
-	fi
-done
-
-if test -z "$libdir"
-then
-	echo "pcblib/parametric/common.awk not found." >&2
-	exit 1
-fi
-
-awk -f $libdir/common.awk -f `dirname $0`/qr.awk -v "args=$*" -v gen=`basename $0` -v "genfull=$0"
-
--- a/coraleda/subc/qr.awk
+++ b/coraleda/subc/qr.awk
@ -1,62 +0,0 @@
-function flush_line(x1, x2, y, w     ,n,yy)
-{
-	x1/=2
-	x2/=2
-	for(n = 0; n < 3; n++) {
-		yy = y*w + w/6 + w/3 * n
-		element_line(x1*w + w/6, yy, x2*w - w/6, yy, w/3)
-	}
-
-	element_line(x1*w + w/6, y*w + w/6, x1*w + w/6, (y+1)*w - w/6, w/3)
-	element_line(x2*w - w/6, y*w + w/6, x2*w - w/6, (y+1)*w - w/6, w/3)
-
-}
-
-BEGIN {
-	help_auto()
-	set_arg(P, "?pixel_size", "1mm")
-
-	proc_args(P, "text,pixel_size,level", "text")
-
-	pixel_size = parse_dim(P["pixel_size"])
-
-	element_begin("", "QR1", "qr(" P["text"] "," P["pixel_size"] "," P["level"] ")"  ,0,0, 0,-mil(50))
-
-	print "# text=" P["text"]
-	cmd = "echo '" P["text"] "' | qrencode -t ASCII"
-
-	if (P["level"] != "") {
-		if (tolower(P["level"]) == "h")
-			cmd = cmd " -l H"
-		else if (tolower(P["level"]) == "l")
-			cmd = cmd " -l L"
-	}
-
-	y = 0;
-	while((cmd | getline line) > 0) {
-		line = line "-"
-#		print line
-		len = length(line)
-		start = ""
-		for(x = 1; x < len; x++) {
-			if (substr(line, x, 1) == "#") {
-				if (start == "")
-					start = x;
-			}
-			else {
-				if (start != "") {
-					flush_line(start, x, y, pixel_size)
-					start = ""
-				}
-			}
-		}
-		if (start != "")
-			flush_line(start, x, y, pixel_size)
-		y++;
-	}
-
-
-#	dimension(+spacing/aspect, -dia, +spacing/aspect, dia, "@" spacing*1.2 ";0", "dia")
-
-	element_end()
-}
--- a/6
+++ b/6
@ -0,0 +1,6 @@
+(fp_lib_table
+  (version 7)
+  (lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.pretty")(options "")(descr ""))
+  (lib (name "kikit")(type "KiCad")(uri "${KIPRJMOD}/kicad/kikit.pretty")(options "")(descr ""))
+  (lib (name "logo")(type "KiCad")(uri "${KIPRJMOD}/kicad/logo.pretty")(options "")(descr ""))
+)
--- a/2
+++ b/2
@ -1,2 +0,0 @@
-(source-library  ".")
-(component-library "./geda/symbols/")
--- a/geda/symbols/1V8.sym
+++ b/geda/symbols/1V8.sym
@ -1,18 +0,0 @@
-v 20210407 2
-P 200 0 200 200 1 0 0
-{
-T 250 50 5 6 0 1 0 0 1
-pinnumber=1
-T 250 50 5 6 0 0 0 0 1
-pinseq=1
-T 250 50 5 6 0 1 0 0 1
-pinlabel=1
-T 250 50 5 6 0 1 0 0 1
-pintype=pwr
-}
-T 200 250 9 8 1 0 0 3 1
-1V8
-T 300 0 8 8 0 0 0 0 1
-net=1V8:1
-L 150 100 200 200 3 10 1 0 -1 -1
-L 200 200 250 100 3 10 1 0 -1 -1
--- a/geda/symbols/3V3.sym
+++ b/geda/symbols/3V3.sym
@ -1,18 +0,0 @@
-v 20210407 2
-P 200 0 200 200 1 0 0
-{
-T 250 50 5 6 0 1 0 0 1
-pinnumber=1
-T 250 50 5 6 0 0 0 0 1
-pinseq=1
-T 250 50 5 6 0 1 0 0 1
-pinlabel=1
-T 250 50 5 6 0 1 0 0 1
-pintype=pwr
-}
-T 200 250 9 8 1 0 0 3 1
-3V3
-T 300 0 8 8 0 0 0 0 1
-net=3V3:1
-L 150 100 200 200 3 10 1 0 -1 -1
-L 200 200 250 100 3 10 1 0 -1 -1
--- a/geda/symbols/5V.sym
+++ b/geda/symbols/5V.sym
@ -1,18 +0,0 @@
-v 20210407 2
-P 200 0 200 200 1 0 0
-{
-T 250 50 5 6 0 1 0 0 1
-pinnumber=1
-T 250 50 5 6 0 0 0 0 1
-pinseq=1
-T 250 50 5 6 0 1 0 0 1
-pinlabel=1
-T 250 50 5 6 0 1 0 0 1
-pintype=pwr
-}
-T 200 250 9 8 1 0 0 3 1
-5V
-T 300 0 8 8 0 0 0 0 1
-net=5V:1
-L 150 100 200 200 3 10 1 0 -1 -1
-L 200 200 250 100 3 10 1 0 -1 -1
--- a/geda/symbols/GND.sym
+++ b/geda/symbols/GND.sym
@ -1,17 +0,0 @@
-v 20210407 2
-P 100 100 100 200 1 0 1
-{
-T 158 161 5 4 0 1 0 0 1
-pinnumber=1
-T 158 161 5 4 0 0 0 0 1
-pinseq=1
-T 158 161 5 4 0 1 0 0 1
-pinlabel=1
-T 158 161 5 4 0 1 0 0 1
-pintype=pwr
-}
-L 0 100 200 100 3 0 0 0 -1 -1
-T 300 50 8 10 0 0 0 0 1
-net=GND:1
-L 0 100 100 0 3 0 1 0 -1 -1
-L 200 100 100 0 3 0 1 0 -1 -1
--- a/geda/symbols/VCC.sym
+++ b/geda/symbols/VCC.sym
@ -1,18 +0,0 @@
-v 20210626 2
-P 200 0 200 200 1 0 0
-{
-T 250 50 5 6 0 1 0 0 1
-pinnumber=1
-T 250 50 5 6 0 0 0 0 1
-pinseq=1
-T 250 50 5 6 0 1 0 0 1
-pinlabel=1
-T 250 50 5 6 0 1 0 0 1
-pintype=pwr
-}
-T 200 250 9 8 1 0 0 3 1
-VCC
-T 300 0 8 8 0 0 0 0 1
-net=VCC:1
-L 150 100 200 200 3 10 1 0 -1 -1
-L 200 200 250 100 3 10 1 0 -1 -1
--- a/geda/symbols/VTRG.sym
+++ b/geda/symbols/VTRG.sym
@ -1,18 +0,0 @@
-v 20210407 2
-P 200 0 200 200 1 0 0
-{
-T 250 50 5 6 0 1 0 0 1
-pinnumber=1
-T 250 50 5 6 0 0 0 0 1
-pinseq=1
-T 250 50 5 6 0 1 0 0 1
-pinlabel=1
-T 250 50 5 6 0 1 0 0 1
-pintype=pwr
-}
-T 200 250 9 8 1 0 0 3 1
-VTRG
-T 300 0 8 8 0 0 0 0 1
-net=VTRG:1
-L 150 100 200 200 3 10 1 0 -1 -1
-L 200 200 250 100 3 10 1 0 -1 -1
--- a/geda/symbols/title.sym
+++ b/geda/symbols/title.sym
@ -1,40 +0,0 @@
-v 20210626 2
-L 3000 900 3000 0 15 0 0 0 -1 -1
-B 0 0 6000 1500 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-L 0 900 6000 900 15 0 0 0 -1 -1
-T 1000 700 9 10 1 1 0 0 1
-date=$date$
-T 4300 700 9 10 1 1 0 0 1
-org=$organisation$
-T 4300 400 9 10 1 1 0 0 1
-authors=$authors$
-T 3000 1200 9 14 1 1 0 4 1
-title=TITLE
-T 3100 400 15 8 1 0 0 0 1
-AUTHORS:
-T 3100 100 15 8 1 0 0 0 1
-LICENCE:
-T 100 100 15 8 1 0 0 0 1
-REVISION:
-T 100 1100 15 8 1 0 0 0 1
-TITLE:
-T 100 400 15 8 1 0 0 0 1
-VERSION:
-T 0 1600 8 10 0 0 0 0 1
-graphical=1
-T 3100 700 15 8 1 0 0 0 1
-ORGANISATION:
-T 100 700 15 8 1 0 0 0 1
-DATE:
-T 1000 400 9 10 1 1 0 0 1
-version=$version$
-T 1000 100 9 10 1 1 0 0 1
-revision=$revision$
-T 4300 100 9 10 1 1 0 0 1
-licence=$licence$
-T 0 1800 8 10 0 0 0 0 1
-device=none
-T 0 2000 8 10 0 0 0 0 1
-footprint=none
-T 0 2200 8 10 0 0 0 0 1
-refdes=none
--- a/kicad/kikit.pretty/Board.kicad_mod
+++ b/kicad/kikit.pretty/Board.kicad_mod
@ -0,0 +1,14 @@
+(module Board (layer F.Cu) (tedit 605A21C1)
+  (descr "Mark board for extraction")
+  (attr virtual)
+  (fp_text reference REF** (at -4.5 -5) (layer Dwgs.User)
+    (effects (font (size 1 1) (thickness 0.15)) (justify left))
+  )
+  (fp_text value Board (at -7.25 -5) (layer Dwgs.User)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start 0 0) (end -1.25 -4) (layer Dwgs.User) (width 0.2))
+  (fp_line (start -1.25 -4) (end -9.25 -4) (layer Dwgs.User) (width 0.2))
+  (fp_line (start 0 0) (end 0.5 -1) (layer Dwgs.User) (width 0.2))
+  (fp_line (start 0 0) (end -1 -0.5) (layer Dwgs.User) (width 0.2))
+)
--- a/kicad/kikit.pretty/Fiducial.kicad_mod
+++ b/kicad/kikit.pretty/Fiducial.kicad_mod
@ -0,0 +1,13 @@
+(module Fiducial:Fiducial (layer F.Cu) (tedit 5EA93A7C)
+  (descr "Circular Fiducial")
+  (tags fiducial)
+  (attr smd)
+  (fp_text reference REF** (at 0 -1.5) (layer F.SilkS) hide
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value Fiducial (at 0 1.5) (layer F.Fab) hide
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (pad "" smd circle (at 0 0) (size 0.5 0.5) (layers F.Cu F.Mask)
+    (solder_mask_margin 0.25) (clearance 0.25))
+)
--- a/kicad/kikit.pretty/NPTH.kicad_mod
+++ b/kicad/kikit.pretty/NPTH.kicad_mod
@ -0,0 +1,9 @@
+(module NPTH (layer F.Cu) (tedit 618E7E16)
+  (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value NPTH (at 0 -0.5) (layer F.Fab) hide
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 1) (layers *.Cu *.Mask))
+)
--- a/kicad/kikit.pretty/Tab.kicad_mod
+++ b/kicad/kikit.pretty/Tab.kicad_mod
@ -0,0 +1,17 @@
+(module Tab (layer F.Cu) (tedit 60708B1A)
+  (descr "A symbol representing annotation for tab placement")
+  (attr virtual)
+  (fp_text reference REF** (at 0 -2) (layer F.SilkS) hide
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value Tab (at -2.75 -1) (layer Dwgs.User)
+    (effects (font (size 1.2 1.2) (thickness 0.2)))
+  )
+  (fp_line (start 0.25 0) (end -0.75 1) (layer Dwgs.User) (width 0.3))
+  (fp_line (start 0.25 0) (end -0.75 -1) (layer Dwgs.User) (width 0.3))
+  (fp_line (start 0.25 0) (end -2.75 0) (layer Dwgs.User) (width 0.3))
+  (fp_line (start 0.25 1) (end 0.25 -1) (layer Dwgs.User) (width 0.3))
+  (fp_text user "KIKIT: width: 3mm" (at -5.5 0 90) (layer Dwgs.User)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+)
--- a/kicad/logo.pretty/CuVoodoo_copper.kicad_mod
+++ b/kicad/logo.pretty/CuVoodoo_copper.kicad_mod
@ -0,0 +1,950 @@
+(footprint "CuVoodoo_copper" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (descr "CuVoodoo logo")
+  (attr smd board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
+  (fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.1)))
+    (tstamp f846a54a-9ddc-4bbc-be16-9ad293284767)
+  )
+  (fp_text value "CuVoodoo_copper" (at 0 1 unlocked) (layer "F.Fab") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp a2d5c5b6-08b2-4c1d-af6a-961acdb63b34)
+  )
+  (fp_line (start 6 5) (end 6 4)
+    (stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp db907c8a-7c13-47f0-8576-f8342c6fc43f))
+  (fp_line (start 8.75 3.75) (end 6.25 3.75)
+    (stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp 375d8ca2-9b58-471f-b2aa-d5a472f93281))
+  (fp_arc (start 6 4) (mid 6.073223 3.823223) (end 6.25 3.75)
+    (stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp 0af9ea9b-3856-4e16-89c4-11bf31d4c0f6))
+  (fp_poly
+    (pts
+      (xy 1.25 3.999999)
+      (xy 0.5 3.999999)
+      (xy 0.5 3.499999)
+      (xy 1.25 3.499999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp d164f9a4-dbe2-44e7-8ad8-2d914a8f7a6c))
+  (fp_poly
+    (pts
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+      (xy 3.499999 9.499998)
+      (xy 3.499999 8.999998)
+      (xy 3.749999 8.999998)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 028a1ea9-a14e-4d86-884a-794e4e371399))
+  (fp_poly
+    (pts
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+      (xy 5.999999 8.999998)
+      (xy 6.249999 8.999998)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 6183cedd-1b0c-488e-b67c-11b1d2d2911f))
+  (fp_poly
+    (pts
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+      (xy 8.749998 3.999999)
+      (xy 8.749998 3.499999)
+      (xy 9.499998 3.499999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 9f335a7b-79ff-4f78-b12d-8e0ae29f952f))
+  (fp_poly
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+      (xy 4.499999 4.249999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp b5fef6d2-7e7e-4965-bcdc-f4722e8267a7))
+  (fp_poly
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+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 8bb02f0d-c4a1-49c9-a185-6c1be76e4313))
+  (fp_poly
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+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 3d4db89c-b5bd-4689-87d8-3730cf8df8f4))
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+  (fp_poly
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--- a/kicad/logo.pretty/CuVoodoo_silk.kicad_mod
+++ b/kicad/logo.pretty/CuVoodoo_silk.kicad_mod
@ -0,0 +1,617 @@
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--- a/kicad/logo.pretty/OSHW.kicad_mod
+++ b/kicad/logo.pretty/OSHW.kicad_mod
@ -0,0 +1,108 @@
+(footprint "OSHW" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (attr board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
+  (fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.1)))
+    (tstamp f1e067ff-287b-4a60-b936-f32f4b57d565)
+  )
+  (fp_text value "OSHW" (at 0 1 unlocked) (layer "F.Fab") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp b22282bc-de50-4908-a3c5-ad7501a68e4a)
+  )
+  (fp_line (start 0.227273 2.727273) (end 1.136364 2.727273)
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+  (fp_line (start 0.227273 3.636364) (end 1.136364 3.636364)
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+  (fp_line (start 0.227273 4.545455) (end 1.136364 4.545455)
+    (stroke (width 0.454544) (type solid)) (layer "F.SilkS") (tstamp 76e9343e-0e40-4f34-a90b-b087051025c3))
+  (fp_line (start 0.227273 5.454545) (end 1.136364 5.454545)
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+  (fp_arc (start 2.727273 7.954545) (mid 2.245155 7.754845) (end 2.045455 7.272727)
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+  (fp_arc (start 7.272727 2.045455) (mid 7.754845 2.245155) (end 7.954545 2.727273)
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--- a/kicad/logo.pretty/bunny.kicad_mod
+++ b/kicad/logo.pretty/bunny.kicad_mod
@ -0,0 +1,599 @@
+(footprint "bunny" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (descr "design year indication")
+  (attr board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
+  (fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.1)))
+    (tstamp 4e2c9664-f6ac-467e-880e-cb2256b0c6f7)
+  )
+  (fp_text value "bunny" (at 0 1 unlocked) (layer "F.Fab") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 3d70715b-682b-4e83-9646-7a633830e583)
+  )
+  (fp_circle (center 4.78 7) (end 4.98 7)
+    (stroke (width 0.3) (type solid)) (fill solid) (layer "F.SilkS") (tstamp e8858466-1e07-465c-a413-8d5e1fa2b5d7))
+  (fp_circle (center 5 5) (end 9.85 5)
+    (stroke (width 0.3) (type default)) (fill none) (layer "F.SilkS") (tstamp ce22406d-653e-49a2-ab89-a1574fd0210e))
+  (fp_poly
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+      (xy 3.308544 0.646131)
+      (xy 3.445398 0.503908)
+      (xy 3.592803 0.362853)
+      (xy 3.764682 0.314037)
+      (xy 3.938065 0.27163)
+      (xy 4.112775 0.235657)
+      (xy 4.28863 0.206146)
+      (xy 4.465452 0.183125)
+      (xy 4.643061 0.166618)
+      (xy 4.821278 0.156654)
+      (xy 4.999922 0.153259)
+    )
+
+    (stroke (width 0.030656) (type solid)) (fill solid) (layer "F.SilkS") (tstamp 3dfa6f02-7e21-4feb-9fef-4f78bfeaddc9))
+)
--- a/kicad/logo/bunny.svg
+++ b/kicad/logo/bunny.svg
--- a/kicad/logo/dragon.svg
+++ b/kicad/logo/dragon.svg
--- a/kicad/partdb.kicad_dbl
+++ b/kicad/partdb.kicad_dbl
--- a/kicad/qeda.3dshapes/CAPC1608X92N.wrl
+++ b/kicad/qeda.3dshapes/CAPC1608X92N.wrl
@ -0,0 +1,35 @@
+#VRML V2.0 utf8
+Shape {
+  appearance Appearance {
+    material Material {
+    diffuseColor 0.37 0.37 0.37
+    emissiveColor 0.0 0.0 0.0
+    specularColor 1.0 1.0 1.0
+    ambientIntensity 1.0
+    transparency 0.5
+    shininess 1.0
+    }
+  }
+  geometry IndexedFaceSet {
+    coord Coordinate {
+      point [
+        -0.4 -0.8 0,
+        0.4 -0.8 0,
+        0.4 0.8 0,
+        -0.4 0.8 0,
+        -0.4 -0.8 0.92,
+        0.4 -0.8 0.92,
+        0.4 0.8 0.92,
+        -0.4 0.8 0.92
+      ]
+    }
+    coordIndex [
+      0,1,2,3,-1
+      4,5,6,7,-1
+      0,1,5,4,-1
+      2,3,7,6,-1
+      0,3,7,4,-1
+      1,2,6,5,-1
+    ]
+  }
+}
--- a/kicad/qeda.3dshapes/LEDC2012X80N.wrl
+++ b/kicad/qeda.3dshapes/LEDC2012X80N.wrl
@ -0,0 +1,35 @@
+#VRML V2.0 utf8
+Shape {
+  appearance Appearance {
+    material Material {
+    diffuseColor 0.37 0.37 0.37
+    emissiveColor 0.0 0.0 0.0
+    specularColor 1.0 1.0 1.0
+    ambientIntensity 1.0
+    transparency 0.5
+    shininess 1.0
+    }
+  }
+  geometry IndexedFaceSet {
+    coord Coordinate {
+      point [
+        -0.6 -1 0,
+        0.6 -1 0,
+        0.6 1 0,
+        -0.6 1 0,
+        -0.6 -1 0.8,
+        0.6 -1 0.8,
+        0.6 1 0.8,
+        -0.6 1 0.8
+      ]
+    }
+    coordIndex [
+      0,1,2,3,-1
+      4,5,6,7,-1
+      0,1,5,4,-1
+      2,3,7,6,-1
+      0,3,7,4,-1
+      1,2,6,5,-1
+    ]
+  }
+}
--- a/kicad/qeda.3dshapes/UC1608X55N.wrl
+++ b/kicad/qeda.3dshapes/UC1608X55N.wrl
@ -0,0 +1,35 @@
+#VRML V2.0 utf8
+Shape {
+  appearance Appearance {
+    material Material {
+    diffuseColor 0.37 0.37 0.37
+    emissiveColor 0.0 0.0 0.0
+    specularColor 1.0 1.0 1.0
+    ambientIntensity 1.0
+    transparency 0.5
+    shininess 1.0
+    }
+  }
+  geometry IndexedFaceSet {
+    coord Coordinate {
+      point [
+        -0.4 -0.8 0,
+        0.4 -0.8 0,
+        0.4 0.8 0,
+        -0.4 0.8 0,
+        -0.4 -0.8 0.55,
+        0.4 -0.8 0.55,
+        0.4 0.8 0.55,
+        -0.4 0.8 0.55
+      ]
+    }
+    coordIndex [
+      0,1,2,3,-1
+      4,5,6,7,-1
+      0,1,5,4,-1
+      2,3,7,6,-1
+      0,3,7,4,-1
+      1,2,6,5,-1
+    ]
+  }
+}
--- a/kicad/qeda.3dshapes/UPC2012X80N.wrl
+++ b/kicad/qeda.3dshapes/UPC2012X80N.wrl
@ -0,0 +1,35 @@
+#VRML V2.0 utf8
+Shape {
+  appearance Appearance {
+    material Material {
+    diffuseColor 0.37 0.37 0.37
+    emissiveColor 0.0 0.0 0.0
+    specularColor 1.0 1.0 1.0
+    ambientIntensity 1.0
+    transparency 0.5
+    shininess 1.0
+    }
+  }
+  geometry IndexedFaceSet {
+    coord Coordinate {
+      point [
+        -0.6 -1 0,
+        0.6 -1 0,
+        0.6 1 0,
+        -0.6 1 0,
+        -0.6 -1 0.8,
+        0.6 -1 0.8,
+        0.6 1 0.8,
+        -0.6 1 0.8
+      ]
+    }
+    coordIndex [
+      0,1,2,3,-1
+      4,5,6,7,-1
+      0,1,5,4,-1
+      2,3,7,6,-1
+      0,3,7,4,-1
+      1,2,6,5,-1
+    ]
+  }
+}
--- a/kicad/qeda.kicad_sym
+++ b/kicad/qeda.kicad_sym
@ -0,0 +1,142 @@
+(kicad_symbol_lib (version 20211014) (generator qeda)
+  (symbol "R0603" (pin_numbers hide) (pin_names hide) (in_bom yes) (on_board yes)
+    (property "Reference" "R"
+      (id 0)
+      (at 0.000 1.778 0)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Value" "R0603"
+      (id 1)
+      (at 0.000 -1.778 0)
+      (effects (font (size 1.27 1.27)) (justify top))
+    )
+    (property "Footprint" "qeda:UC1608X55N"
+      (id 2)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "resistor, chip, 1.6x0.8 mm"
+      (id 3)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (rectangle (start -2.540 1.016) (end 2.540 -1.016) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type background)))
+    (pin passive line
+      (at -3.810 0.000 0)
+      (length 1.270)
+      (name "L"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "1"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+    (pin passive line
+      (at 3.810 0.000 180)
+      (length 1.270)
+      (name "R"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "2"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+  )
+  (symbol "C0603" (pin_numbers hide) (pin_names hide) (in_bom yes) (on_board yes)
+    (property "Reference" "C"
+      (id 0)
+      (at 0.000 2.794 0)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Value" "C0603"
+      (id 1)
+      (at 0.000 -2.794 0)
+      (effects (font (size 1.27 1.27)) (justify top))
+    )
+    (property "Footprint" "qeda:CAPC1608X92N"
+      (id 2)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "Chip capacitor 1.6x0.8 mm"
+      (id 3)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_keywords" "Capacitor"
+      (id 4)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (polyline (pts (xy -0.381 2.032) (xy -0.381 -2.032)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 0.381 2.032) (xy 0.381 -2.032)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (pin passive line
+      (at -2.540 0.000 0)
+      (length 2.159)
+      (name "L"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "1"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+    (pin passive line
+      (at 2.540 0.000 180)
+      (length 2.159)
+      (name "R"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "2"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+  )
+  (symbol "LED0805" (pin_numbers hide) (pin_names hide) (in_bom yes) (on_board yes)
+    (property "Reference" "D"
+      (id 0)
+      (at 0.000 2.032 0)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Value" "LED0805"
+      (id 1)
+      (at 0.000 -2.032 0)
+      (effects (font (size 1.27 1.27)) (justify top))
+    )
+    (property "Footprint" "qeda:UPC2012X80N"
+      (id 2)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "diode, LED, chip, 2.0x1.2 mm"
+      (id 3)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (polyline (pts (xy -1.016 1.270) (xy 1.016 0.000) (xy -1.016 -1.270) (xy -1.016 1.270)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type background)))
+    (polyline (pts (xy 1.016 1.270) (xy 1.016 -1.270)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 1.270 1.905) (xy 2.540 3.175)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 1.725 2.720) (xy 2.540 3.175) (xy 2.085 2.360) (xy 1.725 2.720)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type outline)))
+    (polyline (pts (xy 1.905 1.270) (xy 3.175 2.540)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 2.360 2.085) (xy 3.175 2.540) (xy 2.720 1.725) (xy 2.360 2.085)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type outline)))
+    (pin passive line
+      (at -2.540 0.000 0)
+      (length 1.524)
+      (name "A"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "2"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+    (pin passive line
+      (at 2.540 0.000 180)
+      (length 1.524)
+      (name "C"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "1"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+  )
+)
--- a/kicad/qeda.pretty/CAPC1608X92N.kicad_mod
+++ b/kicad/qeda.pretty/CAPC1608X92N.kicad_mod
@ -0,0 +1,38 @@
+(module CAPC1608X92N (layer F.Cu)
+  (attr smd)
+  (pad 1 smd rect (at 0.000 -0.750) (size 1.250 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (pad 2 smd rect (at 0.000 0.750) (size 1.250 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (fp_text reference REF** (at 0.000 0.000) (layer F.SilkS)
+    (effects (font (size 1.200 1.200) (thickness 0.200)))
+  )
+  (fp_line (start -0.925 -0.900) (end -0.925 0.900) (layer F.SilkS) (width 0.200))
+  (fp_line (start 0.925 -0.900) (end 0.925 0.900) (layer F.SilkS) (width 0.200))
+  (fp_circle (center 0.000 0.000) (end 0.000 0.500) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.700 0.000) (end 0.700 0.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.000 -0.700) (end 0.000 0.700) (layer F.Fab) (width 0.100))
+  (fp_text value CAPC1608X92N (at 0.000 0.000 90) (layer F.Fab)
+    (effects (font (size 0.528 0.528) (thickness 0.100)))
+  )
+  (fp_text user REF** (at 0.000 0.000 90) hide (layer F.Fab)
+    (effects (font (size 0.528 0.528) (thickness 0.100)))
+  )
+  (fp_line (start -0.400 -0.800) (end 0.400 -0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.400 -0.800) (end 0.400 0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.400 0.800) (end -0.400 0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.400 0.800) (end -0.400 -0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.875 -1.550) (end -0.875 -1.050) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -0.875 -1.050) (end -0.875 1.050) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -0.875 1.050) (end -0.875 1.550) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -0.875 1.550) (end 0.875 1.550) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.875 1.550) (end 0.875 1.050) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.875 1.050) (end 0.875 -1.050) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.875 -1.050) (end 0.875 -1.550) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.875 -1.550) (end -0.875 -1.550) (layer F.CrtYd) (width 0.050))
+  (model CAPC1608X92N.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 0.3937 0.3937 0.3937))
+    (rotate (xyz 0 0 0 ))
+  )
+)
--- a/kicad/qeda.pretty/LEDC2012X80N.kicad_mod
+++ b/kicad/qeda.pretty/LEDC2012X80N.kicad_mod
@ -0,0 +1,42 @@
+(module LEDC2012X80N (layer F.Cu)
+  (attr smd)
+  (pad 1 smd rect (at 0.000 -0.900) (size 1.600 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (pad 2 smd rect (at 0.000 0.900) (size 1.600 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (fp_text reference REF** (at 0.000 0.000) (layer F.SilkS)
+    (effects (font (size 1.200 1.200) (thickness 0.200)))
+  )
+  (fp_line (start -1.100 -1.100) (end -1.100 1.100) (layer F.SilkS) (width 0.200))
+  (fp_line (start 1.100 -1.100) (end 1.100 1.100) (layer F.SilkS) (width 0.200))
+  (fp_line (start -1.100 -1.100) (end -1.100 -1.750) (layer F.SilkS) (width 0.200))
+  (fp_line (start -1.100 -1.750) (end 1.100 -1.750) (layer F.SilkS) (width 0.200))
+  (fp_line (start 1.100 -1.750) (end 1.100 -1.100) (layer F.SilkS) (width 0.200))
+  (fp_circle (center 0.000 0.000) (end 0.000 0.500) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.700 0.000) (end 0.700 0.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.000 -0.700) (end 0.000 0.700) (layer F.Fab) (width 0.100))
+  (fp_text value LEDC2012X80N (at 0.000 0.000 90) (layer F.Fab)
+    (effects (font (size 0.792 0.792) (thickness 0.100)))
+  )
+  (fp_text user REF** (at 0.000 0.000 90) hide (layer F.Fab)
+    (effects (font (size 0.792 0.792) (thickness 0.100)))
+  )
+  (fp_line (start 0.000 -1.000) (end 0.600 -1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.600 -1.000) (end 0.600 1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.600 1.000) (end -0.600 1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.600 1.000) (end -0.600 -0.400) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.600 -0.400) (end 0.000 -1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start -1.050 -1.700) (end -1.050 -1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 -1.250) (end -1.050 1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 1.250) (end -1.050 1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 1.700) (end 1.050 1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 1.700) (end 1.050 1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 1.250) (end 1.050 -1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 -1.250) (end 1.050 -1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 -1.700) (end -1.050 -1.700) (layer F.CrtYd) (width 0.050))
+  (model LEDC2012X80N.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 0.3937 0.3937 0.3937))
+    (rotate (xyz 0 0 0 ))
+  )
+)
--- a/kicad/qeda.pretty/UC1608X55N.kicad_mod
+++ b/kicad/qeda.pretty/UC1608X55N.kicad_mod
@ -0,0 +1,38 @@
+(module UC1608X55N (layer F.Cu)
+  (attr smd)
+  (pad 1 smd rect (at 0.000 -0.700) (size 1.100 0.750) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (pad 2 smd rect (at 0.000 0.700) (size 1.100 0.750) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (fp_text reference REF** (at 0.000 0.000) (layer F.SilkS)
+    (effects (font (size 1.200 1.200) (thickness 0.200)))
+  )
+  (fp_line (start -0.850 -0.900) (end -0.850 0.900) (layer F.SilkS) (width 0.200))
+  (fp_line (start 0.850 -0.900) (end 0.850 0.900) (layer F.SilkS) (width 0.200))
+  (fp_circle (center 0.000 0.000) (end 0.000 0.500) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.700 0.000) (end 0.700 0.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.000 -0.700) (end 0.000 0.700) (layer F.Fab) (width 0.100))
+  (fp_text value UC1608X55N (at 0.000 0.000 90) (layer F.Fab)
+    (effects (font (size 0.528 0.528) (thickness 0.100)))
+  )
+  (fp_text user REF** (at 0.000 0.000 90) hide (layer F.Fab)
+    (effects (font (size 0.528 0.528) (thickness 0.100)))
+  )
+  (fp_line (start -0.400 -0.800) (end 0.400 -0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.400 -0.800) (end 0.400 0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.400 0.800) (end -0.400 0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.400 0.800) (end -0.400 -0.800) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.730 -1.255) (end -0.730 -0.980) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -0.730 -0.980) (end -0.730 0.980) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -0.730 0.980) (end -0.730 1.255) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -0.730 1.255) (end 0.730 1.255) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.730 1.255) (end 0.730 0.980) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.730 0.980) (end 0.730 -0.980) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.730 -0.980) (end 0.730 -1.255) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 0.730 -1.255) (end -0.730 -1.255) (layer F.CrtYd) (width 0.050))
+  (model UC1608X55N.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 0.3937 0.3937 0.3937))
+    (rotate (xyz 0 0 0 ))
+  )
+)
--- a/kicad/qeda.pretty/UPC2012X80N.kicad_mod
+++ b/kicad/qeda.pretty/UPC2012X80N.kicad_mod
@ -0,0 +1,42 @@
+(module UPC2012X80N (layer F.Cu)
+  (attr smd)
+  (pad 1 smd rect (at 0.000 -0.900) (size 1.600 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (pad 2 smd rect (at 0.000 0.900) (size 1.600 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (fp_text reference REF** (at 0.000 0.000) (layer F.SilkS)
+    (effects (font (size 1.200 1.200) (thickness 0.200)))
+  )
+  (fp_line (start -1.100 -1.100) (end -1.100 1.100) (layer F.SilkS) (width 0.200))
+  (fp_line (start 1.100 -1.100) (end 1.100 1.100) (layer F.SilkS) (width 0.200))
+  (fp_line (start -1.100 -1.100) (end -1.100 -1.750) (layer F.SilkS) (width 0.200))
+  (fp_line (start -1.100 -1.750) (end 1.100 -1.750) (layer F.SilkS) (width 0.200))
+  (fp_line (start 1.100 -1.750) (end 1.100 -1.100) (layer F.SilkS) (width 0.200))
+  (fp_circle (center 0.000 0.000) (end 0.000 0.500) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.700 0.000) (end 0.700 0.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.000 -0.700) (end 0.000 0.700) (layer F.Fab) (width 0.100))
+  (fp_text value UPC2012X80N (at 0.000 0.000 90) (layer F.Fab)
+    (effects (font (size 0.792 0.792) (thickness 0.100)))
+  )
+  (fp_text user REF** (at 0.000 0.000 90) hide (layer F.Fab)
+    (effects (font (size 0.792 0.792) (thickness 0.100)))
+  )
+  (fp_line (start 0.000 -1.000) (end 0.600 -1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.600 -1.000) (end 0.600 1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.600 1.000) (end -0.600 1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.600 1.000) (end -0.600 -0.400) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.600 -0.400) (end 0.000 -1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start -1.050 -1.700) (end -1.050 -1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 -1.250) (end -1.050 1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 1.250) (end -1.050 1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 1.700) (end 1.050 1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 1.700) (end 1.050 1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 1.250) (end 1.050 -1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 -1.250) (end 1.050 -1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 -1.700) (end -1.050 -1.700) (layer F.CrtYd) (width 0.050))
+  (model UPC2012X80N.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 0.3937 0.3937 0.3937))
+    (rotate (xyz 0 0 0 ))
+  )
+)
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit e482148d18ad4d94d476c68798828ac647141b06
+Subproject commit e5b0ca3a0f7bb2f5766f3702089849c8915a0f99
--- a/mass_prop.sh
+++ b/mass_prop.sh
@ -1,58 +0,0 @@
-#!/bin/sh
-
-if test ! $# -eq 2
-then
-	echo "Need two arguments: a board file name and a tab file name" >&2
-	exit 1
-fi
-
-board="$1"
-tab="$2"
-
-if test ! -f "$board"
-then
-	echo "Board file $board not found" >&2
-	exit 1
-fi
-
-if test ! -f "$tab"
-then
-	echo "Tab file $tab not found" >&2
-	exit 1
-fi
-
-btmp=.tmp.$board
-
-awk -F "[ \t]*[;][ \t]*" -v "outfn=$btmp" '
-
-BEGIN { sq = "'\''" }
-
-# quote s with single quotes and remove any single quote from it
-# (pcb-rnd action syntax does not have escaping)
-function squote(s)
-{
-	gsub("[" sq "]", ".", s)
-	return sq s sq
-}
-
-# ignore comments
-/^[ \t]*#/ { next }
-
-# generate an unselect-query-propset sequence for each line
-(NF > 1) {
-	print "Unselect(all)"
-	print "query(select, " squote($1) ")"
-	for(n = 2; n <= NF; n++) {
-		if (split($n, A, "=") == 2)
-			print "propset(selection, " squote(A[1]) "," squote(A[2]) ")"
-	}
-}
-
-END {
-	print "Unselect(all)"
-	print "Save(LayoutAs, " squote(outfn) ")"
-}
-
-' < "$tab" | pcb-rnd --gui batch "$board" && mv "$btmp" "$board"
-
-
--- a/pnp_fab.tab
+++ b/pnp_fab.tab
@ -1,5 +0,0 @@
-@.a.footprint == "LEDC2012X80N.lht"; a/xy::jlcpcb::rotate=270;
-@.a.footprint == "RESC1608X55N.lht"; a/xy::jlcpcb::rotate=90;
-@.a.footprint == "CONNECTOR_USB_MICRO-B_C10418.lht"; a/xy::jlcpcb::translate=-1.2mm,0mm;
-@.a.footprint == "CONNECTOR_USB_MICRO-B_C10418.lht"; a/xy::jlcpcb::rotate=270;
-@.a.footprint == "CONNECTOR_USB-A-2.0_RECEPTACLE_C42428.lht"; a/xy::jlcpcb::translate=0mm,-1.7mm;
--- a/6
+++ b/6
@ -0,0 +1,6 @@
+(sym_lib_table
+  (version 7)
+  (lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.kicad_sym")(options "")(descr ""))
+  (lib (name "partdb")(type "Database")(uri "${KIPRJMOD}/kicad/partdb.kicad_dbl")(options "")(descr ""))
+  (lib (name "Connector_Audio")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Connector_Audio.kicad_sym")(options "")(descr ""))
+)
--- a/template.kicad_pcb
+++ b/template.kicad_pcb
@ -0,0 +1,83 @@
+(kicad_pcb (version 20221018) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "A4")
+  (title_block
+    (date "$date$")
+    (rev "$version$.$revision$")
+    (company "CuVoodoo")
+    (comment 1 "King Kévin")
+    (comment 2 "CERN-OHL-S")
+  )
+
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (33 "F.Adhes" user "F.Adhesive")
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+  )
+
+  (setup
+    (stackup
+      (layer "F.SilkS" (type "Top Silk Screen") (color "White"))
+      (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
+      (layer "F.Cu" (type "copper") (thickness 0.035))
+      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+      (layer "B.Cu" (type "copper") (thickness 0.035))
+      (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
+      (layer "B.SilkS" (type "Bottom Silk Screen") (color "White"))
+      (copper_finish "None")
+      (dielectric_constraints no)
+    )
+    (pad_to_mask_clearance 0)
+    (pcbplotparams
+      (layerselection 0x00010fc_ffffffff)
+      (plot_on_all_layers_selection 0x0000000_00000000)
+      (disableapertmacros false)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (dashed_line_dash_ratio 12.000000)
+      (dashed_line_gap_ratio 3.000000)
+      (svgprecision 6)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory "")
+    )
+  )
+
+  (net 0 "")
+
+)
--- a/template.kicad_pro
+++ b/template.kicad_pro
@ -0,0 +1,483 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.049999999999999996,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": true,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "warning",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.127,
+        "min_copper_edge_clearance": 0.19999999999999998,
+        "min_hole_clearance": 0.254,
+        "min_hole_to_hole": 0.254,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.127,
+        "min_via_annular_width": 0.13,
+        "min_via_diameter": 0.5,
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "simulation_model_issue": "error",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "template.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.2,
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Thick",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.5,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Thin",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "via_diameter": 0.5,
+        "via_drill": 0.3,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 3
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "43fc3289-82a7-492c-a423-3030e10115dc",
+      ""
+    ]
+  ],
+  "text_variables": {}
+}
--- a/template.kicad_sch
+++ b/template.kicad_sch
@ -0,0 +1,22 @@
+(kicad_sch (version 20230121) (generator eeschema)
+
+  (uuid 43fc3289-82a7-492c-a423-3030e10115dc)
+
+  (paper "A4")
+
+  (title_block
+    (date "$date$")
+    (rev "$version$.$revision$")
+    (company "CuVoodoo")
+    (comment 1 "King Kévin")
+    (comment 2 "CERN-OHL-S")
+  )
+
+  (lib_symbols
+  )
+
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+)
--- a/template.lht
+++ b/template.lht
@ -1,587 +0,0 @@
-ha:pcb-rnd-board-v8 {
-
- li:styles {
-   ha:Signal {
-    via_proto = 0
-    thickness = 6.0mil
-    text_thick = 0.0
-    text_scale = 100
-    clearance = 6.0mil
-   }
-   ha:Power {
-    via_proto = 1
-    thickness = 10.0mil
-    text_thick = 0.0
-    text_scale = 100
-    clearance = 10.0mil
-   }
-   ha:Fat {
-    via_proto = 2
-    thickness = 80.0mil
-    text_thick = 0.0
-    text_scale = 100
-    clearance = 25.0mil
-   }
-   ha:Sig-tight {
-    via_proto = 3
-    thickness = 10.0mil
-    text_thick = 0.0
-    text_scale = 100
-    clearance = 12.0mil
-   }
- }
-
- ha:meta {
-   ha:size {
-    thermal_scale = 0.500000
-    x = 100.0mm
-    y = 100.0mm
-   }
-   ha:grid {
-    spacing = 0.5mm
-    offs_x = 0.0
-    offs_y = 0.0
-   }
- }
-
- ha:data {
-  li:padstack_prototypes {
-
-   ha:ps_proto_v6.0 {
-     hdia=0.3mm; hplated=1; htop=0; hbottom=0;
-     li:shape {
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=0.6mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         top = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=0.6mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         bottom = 1
-         copper = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=0.6mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         intern = 1
-        }
-        clearance=0.0
-       }
-     }
-   }
-
-   ha:ps_proto_v6.1 {
-     hdia=0.5mm; hplated=1; htop=0; hbottom=0;
-     li:shape {
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=0.8mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         top = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=0.8mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         bottom = 1
-         copper = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=0.8mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         intern = 1
-        }
-        clearance=0.0
-       }
-     }
-   }
-
-   ha:ps_proto_v6.2 {
-     hdia=1.2mm; hplated=1; htop=0; hbottom=0;
-     li:shape {
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=3.5mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         top = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=3.5mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         bottom = 1
-         copper = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=3.5mm;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         intern = 1
-        }
-        clearance=0.0
-       }
-     }
-   }
-
-   ha:ps_proto_v6.3 {
-     hdia=0.8mm; hplated=1; htop=0; hbottom=0;
-     li:shape {
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=64.0mil;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         top = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=64.0mil;        }
-        ha:combining {        }
-        ha:layer_mask {
-         bottom = 1
-         copper = 1
-        }
-        clearance=0.0
-       }
-
-       ha:ps_shape_v4 {
-        ha:ps_circ { x=0.0; y=0.0; dia=64.0mil;        }
-        ha:combining {        }
-        ha:layer_mask {
-         copper = 1
-         intern = 1
-        }
-        clearance=0.0
-       }
-     }
-   }
-  }
-
-   li:objects {
-   }
-   li:layers {
-
-    ha:top-sig {
-     lid=0
-     group=3
-     ha:combining {     }
-
-      ha:attributes {
-        {pcb-rnd::key::vis}={<Key>l; Shift<Key>t}
-        {pcb-rnd::key::select}={<Key>l; <Key>t}
-      }
-
-      li:objects {
-      }
-      color = {#238b27}
-    }
-
-    ha:bottom-sig {
-     lid=1
-     group=10
-     ha:combining {     }
-
-      ha:attributes {
-        {pcb-rnd::key::vis}={<Key>l; Shift<Key>b}
-        {pcb-rnd::key::select}={<Key>l; <Key>b}
-      }
-
-      li:objects {
-      }
-      color = {#38ee39}
-    }
-
-    ha:top-gnd {
-     lid=2
-     group=3
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#104e8b}
-    }
-
-    ha:bottom-gnd {
-     lid=3
-     group=10
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#6164ff}
-    }
-
-    ha:outline {
-     lid=4
-     group=7
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#00868b}
-    }
-
-    ha:bottom-silk {
-     lid=5
-     group=12
-     ha:combining { auto=1;     }
-
-      ha:attributes {
-        {pcb-rnd::key::vis}={<Key>l; Shift<Key>x}
-        {pcb-rnd::key::select}={<Key>l; <Key>x}
-      }
-
-      li:objects {
-      }
-      color = {#000000}
-    }
-
-    ha:top-silk {
-     lid=6
-     group=1
-     ha:combining { auto=1;     }
-
-      ha:attributes {
-        {pcb-rnd::key::vis}={<Key>l; Shift<Key>s}
-        {pcb-rnd::key::select}={<Key>l; <Key>s}
-      }
-
-      li:objects {
-      }
-      color = {#000000}
-    }
-
-    ha:top-paste {
-     lid=7
-     group=0
-     ha:combining { auto=1;     }
-
-      li:objects {
-      }
-      color = {#cd00cd}
-    }
-
-    ha:top-mask {
-     lid=8
-     group=2
-     ha:combining { sub=1; auto=1;     }
-
-      li:objects {
-      }
-      color = {#ff0000}
-    }
-
-    ha:bottom-mask {
-     lid=9
-     group=11
-     ha:combining { sub=1; auto=1;     }
-
-      li:objects {
-      }
-      color = {#ff0000}
-    }
-
-    ha:bottom-paste {
-     lid=10
-     group=13
-     ha:combining { auto=1;     }
-
-      li:objects {
-      }
-      color = {#cd00cd}
-    }
-
-    ha:slot-plated {
-     lid=11
-     group=14
-     ha:combining { auto=1;     }
-
-      li:objects {
-      }
-      color = {#8b7355}
-    }
-
-    ha:slot-unplated {
-     lid=12
-     group=15
-     ha:combining { auto=1;     }
-
-      li:objects {
-      }
-      color = {#00868b}
-    }
-
-    ha:top-assy {
-     lid=13
-     group=16
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#444444}
-    }
-
-    ha:bot-assy {
-     lid=14
-     group=17
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#444444}
-    }
-
-    ha:fab {
-     lid=15
-     group=18
-     ha:combining { auto=1;     }
-
-      li:objects {
-      }
-      color = {#222222}
-    }
-
-    ha:top-courtyard {
-     lid=16
-     group=8
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#104e8b}
-    }
-
-    ha:bot-courtyard {
-     lid=17
-     group=9
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#cd3700}
-    }
-
-    ha:top-pwr {
-     lid=18
-     group=3
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#c24744}
-    }
-
-    ha:bottom-pwr {
-     lid=19
-     group=10
-     ha:combining {     }
-
-      li:objects {
-      }
-      color = {#ff5759}
-    }
-   }
- }
- ha:layer_stack {
-  li:groups {
-   ha:0 {
-    name = top_paste
-    ha:type { top=1; paste=1;    }
-    li:layers { 7;    }
-   }
-   ha:1 {
-    name = top_silk
-    ha:type { silk=1; top=1;    }
-    li:layers { 6;    }
-   }
-   ha:2 {
-    name = top_mask
-    ha:type { top=1; mask=1;    }
-    li:layers { 8;    }
-   }
-   ha:3 {
-    name = top_copper
-    ha:type { copper=1; top=1;    }
-    li:layers { 0; 18; 2;    }
-   }
-   ha:4 {
-    name = grp_4
-    ha:type { substrate=1; intern=1;    }
-    li:layers {    }
-    ha:attributes {
-     thickness={0.7375mm }
-    }
-   }
-   ha:5 {
-    name = grp_6
-    ha:type { substrate=1; intern=1;    }
-    li:layers {    }
-    ha:attributes {
-     thickness={0.125mm }
-    }
-   }
-   ha:6 {
-    name = grp_8
-    ha:type { substrate=1; intern=1;    }
-    li:layers {    }
-    ha:attributes {
-     thickness={0.7375mm }
-    }
-   }
-   ha:7 {
-    name = global_outline
-    ha:type { boundary=1;    }
-    li:layers { 4;    }
-    purpose = uroute
-   }
-   ha:8 {
-    name = top-courtyard
-    ha:type { top=1; doc=1;    }
-    li:layers { 16;    }
-    ha:attributes {
-     init-invis=true
-    }
-    purpose = ko.courtyard
-   }
-   ha:9 {
-    name = bot-courtyard
-    ha:type { bottom=1; doc=1;    }
-    li:layers { 17;    }
-    ha:attributes {
-     init-invis=true
-    }
-    purpose = ko.courtyard
-   }
-   ha:10 {
-    name = bottom_copper
-    ha:type { bottom=1; copper=1;    }
-    li:layers { 1; 19; 3;    }
-   }
-   ha:11 {
-    name = bottom_mask
-    ha:type { bottom=1; mask=1;    }
-    li:layers { 9;    }
-   }
-   ha:12 {
-    name = bottom_silk
-    ha:type { silk=1; bottom=1;    }
-    li:layers { 5;    }
-   }
-   ha:13 {
-    name = bottom_paste
-    ha:type { bottom=1; paste=1;    }
-    li:layers { 10;    }
-   }
-   ha:14 {
-    name = pmech
-    ha:type { mech=1;    }
-    li:layers { 11;    }
-    purpose = proute
-   }
-   ha:15 {
-    name = umech
-    ha:type { mech=1;    }
-    li:layers { 12;    }
-    purpose = uroute
-   }
-   ha:16 {
-    name = top_assy
-    ha:type { top=1; doc=1;    }
-    li:layers { 13;    }
-    ha:attributes {
-     init-invis=1
-    }
-    purpose = assy
-   }
-   ha:17 {
-    name = bot_assy
-    ha:type { bottom=1; doc=1;    }
-    li:layers { 14;    }
-    ha:attributes {
-     init-invis=1
-    }
-    purpose = assy
-   }
-   ha:18 {
-    name = fab
-    ha:type { top=1; doc=1;    }
-    li:layers { 15;    }
-    ha:attributes {
-     init-invis=1
-    }
-    purpose = fab
-   }
-  }
- }
- li:pcb-rnd-conf-v1 {
-  ha:overwrite {
-   ha:design {
-    via_proto = 1
-    text_font_id = 0
-    text_scale = 100
-    min_slk = 0.15240000 mm
-    text_thickness = 0
-    line_thickness = 10.00 mil
-    ha:drc {
-     min_ring = 0.15 mm
-     min_copper_overlap = 6.0 mil
-     min_drill = 0.3 mm
-    }
-    min_wid = 0.15240000 mm
-    bloat = 0.15240000 mm
-    clearance = 10.00 mil
-   }
-   ha:editor {
-    grid_unit = mm
-    grids_idx = 11
-    grid = 500.00 um
-   }
-   ha:rc {
-    li:library_search_paths {
-     $(rc.path.design)/coraleda/subc  
-     $(rc.path.design)/coraleda/subc  
-     ?../pcblib  
-     ?~/pcblib/  
-     $(rc.path.share)/pcblib  
-    }
-   }
-  }
- }
- ha:pixmaps {
- }
-}
--- a/template.sch
+++ b/template.sch
@ -1,22 +0,0 @@
-v 20210626 2
-C 0 0 1 0 0 title.sym
-{
-T 1000 700 5 10 1 1 0 0 1
-date=$date$
-T 4300 700 5 10 1 1 0 0 1
-org=CuVoodoo
-T 4300 400 5 10 1 1 0 0 1
-authors=King Kévin
-T 3000 1200 5 14 1 1 0 4 1
-title=TITLE
-T 1000 400 5 10 1 1 0 0 1
-version=$version$
-T 1000 100 5 10 1 1 0 0 1
-revision=$revision$
-T 4300 100 5 10 1 1 0 0 1
-licence=CERN-OHL-S
-T 0 1800 5 10 0 0 0 0 1
-device=none
-T 0 2000 5 10 0 0 0 0 1
-footprint=none
-}
Author	SHA1	Message	Date
King Kévin	88deb003a6	lib: update repo	2024-03-18 23:44:10 +01:00
King Kévin	529880abb4	make dragon kicad compatible	2024-03-18 23:43:19 +01:00
King Kévin	fa16059e46	add old and new year logo	2024-03-08 07:24:21 +01:00
King Kévin	200f8b179d	make: remove components from 2d rendering	2024-03-08 07:14:50 +01:00
King Kévin	07570f2911	make: update bom tool	2024-03-08 07:14:21 +01:00
King Kévin	0830600044	make: include DNF parts	2024-03-08 07:14:21 +01:00
King Kévin	3933cbccf8	make: export 3d model	2024-03-08 07:14:21 +01:00
King Kévin	89b65b72de	make: add MPN in BoM	2024-03-08 07:13:47 +01:00
King Kévin	9e186892e5	make: ignore DRC	2024-03-08 07:12:31 +01:00
King Kévin	ddf9deb7fc	lib: update repo	2024-03-08 07:07:09 +01:00
King Kévin	0d73e5171d	remove refdes2fab.py and this is a just a gloabal plugin for me	2023-12-18 20:47:12 +01:00
King Kévin	3e78d6beb5	lib: update logo properties	2023-10-01 10:12:16 +02:00
King Kévin	c133c944de	lib: add silk logo (less DRC errors)	2023-10-01 10:12:16 +02:00
King Kévin	16b19cc0d4	lib: update repo	2023-10-01 10:09:52 +02:00
King Kévin	7310a8173a	lib: update repo	2023-09-19 05:12:28 +02:00
King Kévin	e97b5bf01f	lib: update part database	2023-09-19 05:11:40 +02:00
King Kévin	4aef742dc5	lib: generate Kicad7 library	2023-09-19 05:11:17 +02:00
King Kévin	f84deb30b8	lib: remove JLCPCB correction info as it is in the database now	2023-09-19 05:10:41 +02:00
King Kévin	50444cd555	bom: ignore some fields	2023-08-11 11:06:14 +02:00
King Kévin	cedd9571ee	lib: update repo	2023-08-11 11:05:29 +02:00
King Kévin	7ba4b33939	make: use JLCPCB field in bom fabrication export	2023-08-11 11:04:37 +02:00
King Kévin	6fe5a0e425	make: prevent bom backup	2023-08-11 11:04:37 +02:00
King Kévin	6eb31f0646	ignore kicad lock files	2023-08-11 11:04:37 +02:00
King Kévin	b893e7b57d	make: ignore DRC for export	2023-08-11 11:04:37 +02:00
King Kévin	ffbdffdf48	kicad: update files to v7	2023-03-30 22:32:40 +02:00
King Kévin	59b145d66e	doc: better list dependencies	2023-03-30 22:30:26 +02:00
King Kévin	c63fbf1689	make: use kikit again to generate fabrication	2023-03-30 22:30:26 +02:00
King Kévin	d0d4203d20	make: add bom generator (not included in pip)	2023-03-30 22:30:26 +02:00
King Kévin	cacdcb4ceb	make: update bom generation	2023-03-30 22:30:26 +02:00
King Kévin	87cb8cb49b	make: now use ibom plugin	2023-03-30 22:30:26 +02:00
King Kévin	99ab15f5eb	make: switch back from kicad nightly	2023-03-30 22:30:26 +02:00
King Kévin	253f301eb0	lib: update database	2023-03-30 22:30:26 +02:00
King Kévin	f1227afdcb	make: fabrication does not need schematic	2023-03-30 22:30:26 +02:00
King Kévin	33f9b2cb87	make: add subsheet support	2023-03-30 22:29:07 +02:00
King Kévin	8fa5152b25	make: use kicad-cli to export fabrication (kikit does not support v7 yet)	2023-03-30 22:26:57 +02:00
King Kévin	b066d8b473	make: update pcbdraw call	2023-03-30 22:26:57 +02:00
King Kévin	d6ed8e8f86	make: use kicad-cli to generate bom	2023-03-30 22:26:57 +02:00
King Kévin	ad93fccfcd	make: use kicad-cli to render schematic	2023-03-30 22:26:54 +02:00
King Kévin	5849e04d54	lib: update partdb library	2023-03-30 22:25:49 +02:00
King Kévin	0b268fef02	lib: add logos	2023-03-30 22:25:49 +02:00
King Kévin	cf6e95493f	lib: switch kicad footprint to v7	2023-03-30 22:25:49 +02:00
King Kévin	58e504ea47	lib: disable qeda pin shapes	2023-03-30 22:23:41 +02:00
King Kévin	87819cd3e6	lib: add partdb library	2023-03-30 22:23:41 +02:00
King Kévin	5d9a596047	lib: enable audio connector library	2023-03-30 22:23:41 +02:00
King Kévin	8992163da1	lib: switch to version 7	2023-03-30 22:23:41 +02:00
King Kévin	4e8d15f64c	sch: set kicad6 library	2022-12-24 03:09:46 +01:00
King Kévin	9b313a227c	lib: update repo	2022-12-24 03:08:33 +01:00
King Kévin	283b18e1e9	lib: switch output to KiCad 6	2022-12-24 03:08:20 +01:00
King Kévin	9490a25e50	lib: add JLCPCB corrections for USB connectors	2022-12-24 03:05:45 +01:00
King Kévin	f69a88300f	brd: add material propertires	2022-09-13 12:19:22 +02:00
King Kévin	f558b68515	add script to put refdes in fab layer	2022-09-13 12:14:21 +02:00
King Kévin	b612622310	make: specify ibom generator	2022-08-10 17:43:30 +02:00
King Kévin	c3ce63cbcd	make: output iteractive bom	2022-08-10 14:45:31 +02:00
King Kévin	1d561046dd	doc: add JLCPCB position correction	2022-08-10 12:39:29 +02:00
King Kévin	4636a6508b	doc: replace rake with make	2022-08-10 12:37:46 +02:00
King Kévin	e787a3412e	add parts placement corrections	2022-07-13 11:10:43 +02:00
King Kévin	dc767e3e37	make: output panel fab sooner	2022-07-13 11:10:21 +02:00
King Kévin	ac4807e5ac	make: remove git hash from revision	2022-07-04 10:17:51 +02:00
King Kévin	df2e0df1d7	lib: update repo	2022-06-22 09:13:01 +02:00
King Kévin	54dfc1d55d	rake: replace with more common make file	2022-06-22 09:12:23 +02:00
King Kévin	991fb55439	lib: rename generated lib to qeda	2022-06-17 18:06:46 +02:00
King Kévin	d00955e75d	brd: add net sizes	2022-06-17 17:55:41 +02:00
King Kévin	025d70af1b	sch/brd: add template kicad schematic and board layout	2022-06-10 19:56:34 +02:00
King Kévin	8b216cf9ff	lib: add most common components	2022-06-10 19:55:18 +02:00
King Kévin	b1c719eebb	git: remove cache file	2022-06-10 19:54:18 +02:00
King Kévin	4fdef09f30	sch/brd: remove lepton and ringdove files	2022-06-10 19:32:19 +02:00
King Kévin	4699c6b609	lib: update repo	2022-06-10 19:32:19 +02:00
King Kévin	88b9e8eb72	doc: update development doc for kicad toolchain	2022-06-10 19:32:19 +02:00
King Kévin	ecb253e18b	save JLC PnP corrections	2022-06-10 19:32:19 +02:00
King Kévin	2e982048c5	lib: document correction	2022-06-10 19:32:19 +02:00
King Kévin	fc17a5abe3	rake: version panel configuration	2022-06-10 19:32:19 +02:00
King Kévin	0d85bfb90a	rake: add panelization target	2022-06-10 19:32:19 +02:00
King Kévin	2882cb46c8	lib: remove date information	2022-06-10 19:32:19 +02:00
King Kévin	834f8c6f51	rake: use custom bom generator configuration	2022-06-10 19:32:19 +02:00
King Kévin	118fcf108c	rake: change Rakefile for KiCAD processing	2022-06-10 19:32:13 +02:00
King Kévin	932d8f9a39	git: ignore KiCAD output and cache	2022-06-10 19:31:54 +02:00
King Kévin	097ceb5efc	lib: add kikit footprints	2022-06-10 19:31:54 +02:00
King Kévin	26d6478b5c	lib: add kicad library config	2022-06-10 19:31:54 +02:00
King Kévin	acabbdfa31	lib: remove lepton and ringdove files	2022-06-10 19:31:49 +02:00
King Kévin	baecb40eaf	lib: allow generating kicad library	2022-06-10 19:31:41 +02:00
King Kévin	2f285de510	doc: add empty changelog file	2022-06-10 19:14:56 +02:00
King Kévin	479d64bc6a	rake: export gerber in a directory	2022-05-18 17:42:13 +02:00
King Kévin	531206e2b3	rake: ignore stdout when exporting svg	2022-05-18 17:42:13 +02:00
King Kévin	b9d4fabffd	lib: update repo	2022-05-17 11:14:21 +02:00
King Kévin	5d0de1ee87	brd: fix footprint paths	2022-03-27 16:26:01 +02:00
King Kévin	865d7a899e	README: development moved to other file	2022-03-23 10:49:07 +01:00
King Kévin	38466530e1	pnp: fix USB-C orientation	2022-03-23 10:34:20 +01:00
King Kévin	6e6ff34b51	pnp: adjust USB-C and CR1220 offset	2022-03-23 10:34:20 +01:00
King Kévin	b3200d6e6e	fab: add rotation for SOT23	2022-03-23 10:34:20 +01:00
King Kévin	93783e1682	qeda: set polarity mark to none	2022-03-23 10:34:20 +01:00
King Kévin	832e954f1e	put development instructions in seperate file	2022-03-23 10:32:24 +01:00
King Kévin	9298df7acf	update library	2022-03-07 14:42:51 +01:00
King Kévin	2e69c48388	update library url	2022-03-07 14:40:01 +01:00
King Kévin	bb05a4bf7a	lib: update to master	2022-02-02 16:42:09 +01:00
King Kévin	fd34b256e2	Makefile: fix lepton CLI call	2022-02-02 16:42:09 +01:00
King Kévin	e62773bfa1	Rakefile: minor, show error on empty BOM	2022-02-02 16:42:09 +01:00
King Kévin	b38e271a1e	Rakefile: minor, improve readability	2022-02-02 16:42:09 +01:00
King Kévin	8b0c84366a	ignore other manual fabrication export (not from Rakefile)	2022-02-02 15:29:48 +01:00