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29 Commits

Author SHA1 Message Date
King Kévin 39dbceee73 doc: add smaller picutres 2022-06-27 15:27:52 +02:00
King Kévin 57cdeed762 doc: capitalize 2022-06-27 15:22:50 +02:00
King Kévin f1b16e644a doc: add v1 changes 2022-06-27 15:21:34 +02:00
King Kévin 832af46f21 doc: add pictures 2022-06-27 15:19:45 +02:00
King Kévin 9c6284cdde doc: update for v1 2022-06-27 15:19:28 +02:00
King Kévin 2006dc0a0a doc: mention EasyEDA 2022-06-27 15:13:52 +02:00
King Kévin 4b1abc9f33 brd: add completed EasyEDA board export 2022-06-27 15:11:51 +02:00
King Kévin 41cad366a6 sch: add completed EasyEDA schematic export 2022-06-27 15:09:35 +02:00
King Kévin 6ebc12417b remove geda settings 2022-06-27 15:05:10 +02:00
King Kévin af07a497fc switch to version 1 2022-06-27 15:02:31 +02:00
King Kévin e28a91654e doc: remove ununsed notes 2022-06-27 14:34:50 +02:00
King Kévin 909e6e1b58 doc: fix typo 2022-06-27 14:33:03 +02:00
King Kévin 11d0b83a0b doc add picture 2022-06-27 14:25:40 +02:00
King Kévin 734fe1d991 doc: add v0 details 2022-06-27 14:14:32 +02:00
King Kévin 52ed0b685c doc: add type-A information 2022-06-27 14:10:15 +02:00
King Kévin 02566303d8 doc: put development instructions in seperate file 2022-06-27 14:05:42 +02:00
King Kévin 930ef658b1 lib: update CR2032 footprint 2022-06-27 13:57:47 +02:00
King Kévin 3820f2cb43 readme: add power consumption 2021-07-22 18:35:20 +02:00
King Kévin 8191a4bf03 describe project in README 2021-07-22 18:13:40 +02:00
King Kévin 6038861fa2 use correct schematic and board 2021-07-22 13:19:34 +02:00
King Kévin 84e591ca4a sch: fix R/S swap 2021-07-22 13:13:20 +02:00
King Kévin 387d010064 brd: fix R/S swap 2021-07-22 13:13:03 +02:00
King Kévin d17f1843f8 sch: fix title symbol text for automatic substitution 2021-07-22 13:13:00 +02:00
King Kévin 6b664dfbb5 brd: fix typo 2021-07-22 13:11:46 +02:00
King Kévin 598455d14d brd: add initial completed layout 2021-07-22 13:11:40 +02:00
King Kévin e1bb7f4fba sch: add initial completed draft 2021-07-22 13:11:38 +02:00
King Kévin b1d0702c72 lib: add generated symbols and footprints 2021-07-22 13:11:32 +02:00
King Kévin 44601f120b lib: add hand made footprint (CR2032 battery holder) 2021-07-22 13:11:03 +02:00
King Kévin 546ab7fafd lib: add used parts 2021-07-22 13:10:45 +02:00
24 changed files with 383 additions and 1443 deletions

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@ -7,3 +7,11 @@ config:
preferManufacturer: false
smoothPadCorners: false
library:
- resistor/r0603
- capacitor/c0603
- diode/led0603
- ic/nor-gate_ti_sn74hc02@soic
- ic/nor-gate_ti_sn74lvc1g02@dbv
- ic/nor-gate_ti_sn74lvc1g02@dck
- mechanical/smd-button_hyp_1ts002e
- connector/usb-a-2.0-receptacle

12
CHANGELOG.md Normal file
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@ -0,0 +1,12 @@
v1
==
uses smaller coin cell (CR1220).
use only one type of NOR-gate.
remove READY LED.
v0
==
working proof of concept prototype.
it allows populating NOR gates in different packages.

1
DEVELOPMENT.md Normal file
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@ -0,0 +1 @@
the JSON files are the source schematic and board layout made using [EasyEDA](https://easyeda.com/).

0
NOTES
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119
README.md
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@ -1,96 +1,51 @@
these are the hardware design files for **insert project name here**.
The USB bug detector identifies USB type-A cables (or devices) with integrated circuits.
purpose
=======
<img src="picture/v1_front.webp" title="front" height="250"/>
<img src="picture/v1_back.webp" title="back" height="250"/>
usage
=====
requirements
============
To use the USB bug detector, follow the steps provided on the back of the board:
to be able to generate the outputs you need following software:
- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files)
- [QEDA](http://qeda.org/): to generate footprints for the parts
- [Lepton EDA](https://github.com/lepton-eda/lepton-eda): for the schematic capture
- [pcb-rnd](http://repo.hu/projects/pcb-rnd/): for the board layout
the output generation is automatized.
- insert a CR1220 coin cell battery in the USB bug detector for it to be operational
- press on the RESET button to arm the test
- the BUGGED LED should be off
- plug the USB cable in the USB receptacle
- if the BUGGED LED switches on, the USB cable embeds an integrated circuit (e.g. a bug)
- if the BUGGED LED remains off, the cable is same to use
schematic
=========
After the test, to save power, press again on the RESET button.
library
-------
To ensure that the USB bug detector works, after pressing on the RESET button, press on the SIMULATE button.
This will simulate a USB plug with integrated circuit.
The BUGGED LED should switch on.
This also ensures the battery is not empty.
almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software.
the `library` folder contains the QEDA parts definitions.
When the LED is on, the USB bug detector draws 3 mA.
When the LED is off, the USB bug detector draws 64 nA.
This results in a idle battery life of 62 years (for a typical 35 mAh CR1220 battery).
This is on par with the self life of the battery (~ 1%/year).
to install QEDA using NPM from the official repository:
~~~
sudo npm install -g qeda
~~~
mode of operation
=================
to install QEDA from the sources:
~~~
git clone https://github.com/qeda/qeda
cd qeda
npm install
sudo npm install --global
~~~
An NOR-gate-based SR-latch is used.
The RESET button triggers the R signal to reset the latch.
When a USB cable is plugged, power is provided by the battery to the cable.
If an integrated circuits is present, current will flow through.
A 1 kOhm resistor on the low side (e.g. ground) will create a voltage.
If the plug draws more than 1.6 mA, the resulting 1.6 V will trigger the S signal to set the latch.
The BUG LED will indicate when the SR-latch is set.
The latch remains set until the RESET button is present.
Thus, even if the plug stops drawing power, the LED remains on.
to generate the parts:
~~~
rake library
~~~
This minimum 1.6 mA current draw is often caused by the decoupling/bypass capacitor required by integrated circuit, or accompanying voltage regulator.
When charging, the capacitor acts as a short for a small time, allowing current to flow.
On USB plugs with just resistors, or LEDs, the resulting current flow is not large enough.
this will use the parts definition (.yaml files) in the `library` to generate [gEDA gschem](http://wiki.geda-project.org/geda:gaf)/[Lepton EDA](https://github.com/lepton-eda/lepton-eda) symbols (.sym files) in the `geda/symbols` folder, and [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/) footprints (.lht files) in the `coraleda/subc` folder.
only the QEDA parts in subfolders within `library` come from the [QEDA library](https://doc.qeda.org/library/), but the files are included in this project for simplicity and archiving purposes.
all other parts are custom and written for this project.
schematic
---------
the `.sch` file is the schematic source file.
it has been drawn using [Lepton EDA](https://github.com/lepton-eda/lepton-eda).
it uses standard symbols, and the ones in the `geda/symbols/` folder.
most symbols are generated by QEDA as described above.
to export the netlist (in tEDAx format):
~~~
rake netlist
~~~
to export as pdf:
~~~
rake print
~~~
BOM
---
to export the bill of material (as CSV):
~~~
rake bom
~~~
board
=====
the `.lht` file is the board layout source file.
it has been drawn using [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/).
it uses the symbols from the `coraleda/subc/` folder.
most symbols are generated by QEDA as described above.
`oshw_logo.lht` is just the Open Source Hardware Logo.
it been generated from https://oshwlogo.cuvoodoo.info/.
to export gerber files for PCB manufacturer (and photo preview + overview document):
~~~
rake fabrication
~~~
fabrication
===========
The SIMULATE circuit simulates an integrated circuit by putting a 100 nF capacitor across the USB receptacle.
Because of the 1 kOhm inline resistor, and limited 3.3 V provided by the battery, a maximum of 3.3 mA can be drawn by the USB plug.
This is often not enough to power up integrated circuit properly, particularly if they use a radio interface.
Thus it is safe to use the USB bug detector on bugs, without activating it.

181
Rakefile
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@ -1,181 +0,0 @@
# encoding: utf-8
# ruby: 2.1.0
=begin
Rakefile to manage hardware projects
uses Lepton EDA for schematic and pcb-rnd for board layouts.
Rakefile instead of Makefile for better text file parsing capabilities.
=end
require 'rake/clean'
require 'csv' # to export BOM and costs
# =================
# project variables
# =================
# common name used for file names
name = "template"
# project version, read from "version" file
raise "define project version in 'version' file" unless File.exist? "version"
version = IO.read("version").split("\n")[0]
# current date for stamping output
date = Time.now.strftime("%Y-%m-%d")
# revision based on number of changes on schematic or board layout and current git commit
changes = `git log --pretty=oneline "#{name}.sch" "#{name}.lht" | wc -l`.chomp.to_i
commit = `git rev-parse --short HEAD`.chomp
revision = "#{changes} (#{commit})"
# path to qeda"
qeda = "qeda"
# ==========
# main tasks
# ==========
desc "main building task"
task :default => [:print, :fabrication, :bom]
desc "print schematic and layout (as pdf)"
prints = [ "#{name}.sch.pdf", "#{name}.brd.pdf", "#{name}.brd-top.svg", "#{name}.brd-bottom.svg" ]
task :print => prints
CLEAN.include([ "#{name}.versioned.sch", "#{name}.versioned.lht" ])
CLOBBER.include(prints)
desc "generate fabrication gerbers (as archive)"
gerbers = [ "#{name}.brd.asb", "#{name}.brd.ast", "#{name}.brd.gbl", "#{name}.brd.gbo", "#{name}.brd.gbp", "#{name}.brd.gbs", "#{name}.brd.gko", "#{name}.brd.gtl", "#{name}.brd.gto", "#{name}.brd.gtp", "#{name}.brd.gts", "#{name}.brd.xln", "#{name}.brd.g2l", "#{name}.brd.g3l" ]
fab = [ "#{name}.brd.zip" ]
task :fabrication => fab
CLEAN.include(gerbers)
CLOBBER.include(fab)
desc "generate symbols and footprints from parts"
task :library do
sh "#{qeda} config output geda"
sh "#{qeda} generate ."
sh "#{qeda} config output coraleda"
sh "#{qeda} generate ."
end
desc "export netlist from schematic"
net = [ "#{name}.tdx" ]
task :netlist => net
CLOBBER.include(net)
desc "export notes from schematic"
notes = [ "#{name}.notes.txt" ]
task :notes => notes
CLOBBER.include(notes)
desc "export BOMs from schematic"
boms = [ "#{name}.bom.csv" ]
task :bom => boms
CLOBBER.include(boms)
# ===============
# file generation
# ===============
desc "generate schematic with version information all symbols embedded"
rule ".versioned.sch" => ".sch" do |t|
sh "cp #{t.source} #{t.name}"
sh "lepton-embed --embed #{t.name} 2> /dev/null"
sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
end
desc "generate board layout with version information"
rule ".versioned.lht" => ".lht" do |t|
sh "cp #{t.source} #{t.name}"
sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
end
desc "generate printable version (PDF) of schematic"
rule ".sch.pdf" => ".versioned.sch" do |t|
sh "lepton-cli export --color --paper iso_a4 --layout landscape --output #{t.name} #{t.source} 2> /dev/null"
end
desc "generate printable version (PostScript) of board layout"
rule ".brd.ps" => ".versioned.lht" do |t|
sh "pcb-rnd -x ps --ps-color --media A4 --psfile #{t.name} #{t.source} 2> /dev/null"
end
desc "generate printable version (PDF) of board layout"
rule ".brd.pdf" => ".brd.ps" do |t|
sh "ps2pdf -sPAPERSIZE=a4 -dEPSCrop #{t.source} #{t.name}"
end
desc "generate photo realistic picture from layout (top side)"
rule ".brd-top.svg" => ".versioned.lht" do |t|
sh "pcb-rnd -x svg --photo-mode --outfile #{t.name} #{t.source} 2> /dev/null"
end
desc "generate photo realistic picture from layout (bottom side)"
rule ".brd-bottom.svg" => ".versioned.lht" do |t|
sh "pcb-rnd -x svg --photo-mode --flip --outfile #{t.name} #{t.source} 2> /dev/null"
end
desc "archive gerbers"
rule ".brd.zip" => ".versioned.lht" do |t|
base = File.basename(t.source, ".versioned.lht")
puts base
sh "pcb-rnd -x cam gerber:JLC_PCB --outfile #{base}.brd #{t.source} 2> /dev/null"
sh "zip --quiet #{t.name} #{base}.brd.xln #{base}.brd.a* #{base}.brd.g*"
end
desc "export netlist from schematic"
rule ".tdx" => ".sch" do |t|
sh "lepton-netlist -g tEDAx -o #{t.name} #{t.source} 2> /dev/null"
end
desc "generate BOM file from schematic"
rule ".bom.csv" => ".sch" do |t|
attributes = ["device", "value", "description", "footprint", "manufacturer", "mpn", "datasheet", "lcsc-sku", "digikey-sku", "aliexpress-sku"]
bom_data = bom2(t.prerequisites[0],attributes)
CSV.open(t.name, "wb") do |csv|
all_attributes = ["refdes","qty"]+attributes
csv << all_attributes
bom_data.each do |line|
csv << all_attributes.collect{|attribute| line[attribute]}
end
end
end
# ================
# helper functions
# ================
# generate gnetlist bom2 and parse them
# arguments: schematic=schematic to use, attributes=attributes to use for generating bom2
# returns an array of hash. key is the attribute name, value is the attribute value
def bom2(schematic, attributes)
to_return = []
# force attributes to be an array
attributes = case attributes
when String
[attributes]
when Array
attributes
else
[attributes.to_s]
end
# generate bom2
list = `lepton-netlist --backend bom2 --backend-option attribs=#{attributes*','} --quiet --output - #{schematic} 2> /dev/null`
list = list.each_line {|l| '"' + l + '"' + '\n' }
list.gsub!(/^(.+)/, '"\1')
list.gsub!(/(.+)$/, '\1"')
list.gsub!(/(?!http):(?!\/\/)/, '\1":"\2') # protect the values between ':' (such as URLs)
# parse bom2
csv = CSV.parse(list, col_sep: ":", quote_char: '"')
csv[1..-1].each do |row|
line = {}
row.each_index do |col|
line[csv[0][col]] = row[col] unless row[col] == "unknown"
end
to_return << line
end
return to_return
end

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@ -1,421 +0,0 @@
# footprint generated from CuVoodoo Land Pattern
# author: King Kévin
# version: 1
# date: 2019-05-13
li:pcb-rnd-subcircuit-v6 {
ha:subc.1 {
uid = any_24_ASCII_characters_
ha:attributes {
footprint = open source hardware logo
}
ha:data {
li:padstack_prototypes {
}
li:objects {
}
li:layers {
ha:top-silkscreen {
lid = 1
ha:type {
top = 1
silk = 1
}
li:objects {
ha:line.2{
clearance = 0
x1 = 0.15mm
y1 = 1.8mm
x2 = 0.75mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.3{
clearance = 0
x1 = 1.8mm
y1 = 5.8500000000000005mm
x2 = 1.8mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.4{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 1.8mm
x2 = 6.45mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.5{
clearance = 0
x1 = 1.8mm
y1 = 0.15mm
x2 = 1.8mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.6{
clearance = 0
x1 = 0.15mm
y1 = 2.4mm
x2 = 0.75mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.7{
clearance = 0
x1 = 2.4mm
y1 = 5.8500000000000005mm
x2 = 2.4mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.8{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 2.4mm
x2 = 6.45mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.9{
clearance = 0
x1 = 2.4mm
y1 = 0.15mm
x2 = 2.4mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.10{
clearance = 0
x1 = 0.15mm
y1 = 3mm
x2 = 0.75mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.11{
clearance = 0
x1 = 3mm
y1 = 5.8500000000000005mm
x2 = 3mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.12{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 3mm
x2 = 6.45mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.13{
clearance = 0
x1 = 3mm
y1 = 0.15mm
x2 = 3mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.14{
clearance = 0
x1 = 0.15mm
y1 = 3.5999999999999996mm
x2 = 0.75mm
y2 = 3.5999999999999996mm
thickness = 0.3mm
}
ha:line.15{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 5.8500000000000005mm
x2 = 3.5999999999999996mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.16{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 3.5999999999999996mm
x2 = 6.45mm
y2 = 3.5999999999999996mm
thickness = 0.3mm
}
ha:line.17{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 0.15mm
x2 = 3.5999999999999996mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.18{
clearance = 0
x1 = 0.15mm
y1 = 4.2mm
x2 = 0.75mm
y2 = 4.2mm
thickness = 0.3mm
}
ha:line.19{
clearance = 0
x1 = 4.2mm
y1 = 5.8500000000000005mm
x2 = 4.2mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.20{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 4.2mm
x2 = 6.45mm
y2 = 4.2mm
thickness = 0.3mm
}
ha:line.21{
clearance = 0
x1 = 4.2mm
y1 = 0.15mm
x2 = 4.2mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.22{
clearance = 0
x1 = 0.15mm
y1 = 4.8mm
x2 = 0.75mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.23{
clearance = 0
x1 = 4.8mm
y1 = 5.8500000000000005mm
x2 = 4.8mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.24{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 4.8mm
x2 = 6.45mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.25{
clearance = 0
x1 = 4.8mm
y1 = 0.15mm
x2 = 4.8mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.26{
clearance = 0
x1 = 1.8mm
y1 = 1.35mm
x2 = 4.8mm
y2 = 1.35mm
thickness = 0.3mm
}
ha:line.27{
clearance = 0
x1 = 5.25mm
y1 = 1.8mm
x2 = 5.25mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.28{
clearance = 0
x1 = 4.8mm
y1 = 5.25mm
x2 = 1.8mm
y2 = 5.25mm
thickness = 0.3mm
}
ha:line.29{
clearance = 0
x1 = 1.35mm
y1 = 4.8mm
x2 = 1.35mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:arc.30{
clearance = 0
x = 1.8mm
y = 1.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = 0
adelta = -90
}
ha:arc.31{
clearance = 0
x = 4.8mm
y = 1.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = -90
adelta = -90
}
ha:arc.32{
clearance = 0
x = 4.8mm
y = 4.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = 180
adelta = -90
}
ha:arc.33{
clearance = 0
x = 1.8mm
y = 4.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = 90
adelta = -90
}
ha:line.34{
clearance = 0
x1 = 1.8mm
y1 = 1.8mm
x2 = 3mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.35{
clearance = 0
x1 = 3mm
y1 = 1.8mm
x2 = 3mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.36{
clearance = 0
x1 = 3mm
y1 = 3mm
x2 = 1.8mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.37{
clearance = 0
x1 = 1.8mm
y1 = 3mm
x2 = 1.8mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.38{
clearance = 0
x1 = 4.8mm
y1 = 1.8mm
x2 = 3.5999999999999996mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.39{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 1.8mm
x2 = 3.5999999999999996mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.40{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 2.4mm
x2 = 4.8mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.41{
clearance = 0
x1 = 4.8mm
y1 = 2.4mm
x2 = 4.8mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.42{
clearance = 0
x1 = 4.8mm
y1 = 3mm
x2 = 3.5999999999999996mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.43{
clearance = 0
x1 = 1.8mm
y1 = 3.5999999999999996mm
x2 = 1.8mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.44{
clearance = 0
x1 = 1.8mm
y1 = 4.199999999999999mm
x2 = 3mm
y2 = 4.199999999999999mm
thickness = 0.3mm
}
ha:line.45{
clearance = 0
x1 = 3mm
y1 = 3.5999999999999996mm
x2 = 3mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.46{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 3.5999999999999996mm
x2 = 3.5999999999999996mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.47{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 4.8mm
x2 = 4.199999999999999mm
y2 = 4.2mm
thickness = 0.3mm
}
ha:line.48{
clearance = 0
x1 = 4.199999999999999mm
y1 = 4.2mm
x2 = 4.799999999999999mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.49{
clearance = 0
x1 = 4.799999999999999mm
y1 = 4.8mm
x2 = 4.799999999999999mm
y2 = 3.5999999999999996mm
thickness = 0.3mm
}
}
}
}
}
}
}

2
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(source-library ".")
(component-library "./geda/symbols/")

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v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
1V8
T 300 0 8 8 0 0 0 0 1
net=1V8:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

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v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
3V3
T 300 0 8 8 0 0 0 0 1
net=3V3:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

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v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
5V
T 300 0 8 8 0 0 0 0 1
net=5V:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

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v 20210407 2
P 100 100 100 200 1 0 1
{
T 158 161 5 4 0 1 0 0 1
pinnumber=1
T 158 161 5 4 0 0 0 0 1
pinseq=1
T 158 161 5 4 0 1 0 0 1
pinlabel=1
T 158 161 5 4 0 1 0 0 1
pintype=pwr
}
L 0 100 200 100 3 0 0 0 -1 -1
T 300 50 8 10 0 0 0 0 1
net=GND:1
L 0 100 100 0 3 0 1 0 -1 -1
L 200 100 100 0 3 0 1 0 -1 -1

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v 20210626 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
VCC
T 300 0 8 8 0 0 0 0 1
net=VCC:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

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v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
VTRG
T 300 0 8 8 0 0 0 0 1
net=VTRG:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

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v 20210626 2
L 3000 900 3000 0 15 0 0 0 -1 -1
B 0 0 6000 1500 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 0 900 6000 900 15 0 0 0 -1 -1
T 1000 700 9 10 1 1 0 0 1
date=$date$
T 4300 700 9 10 1 1 0 0 1
org=$organisation$
T 4300 400 9 10 1 1 0 0 1
authors=$authors$
T 3000 1200 9 14 1 1 0 4 1
title=TITLE
T 3100 400 15 8 1 0 0 0 1
AUTHORS:
T 3100 100 15 8 1 0 0 0 1
LICENCE:
T 100 100 15 8 1 0 0 0 1
REVISION:
T 100 1100 15 8 1 0 0 0 1
TITLE:
T 100 400 15 8 1 0 0 0 1
VERSION:
T 0 1600 8 10 0 0 0 0 1
graphical=1
T 3100 700 15 8 1 0 0 0 1
ORGANISATION:
T 100 700 15 8 1 0 0 0 1
DATE:
T 1000 400 9 10 1 1 0 0 1
version=$version$
T 1000 100 9 10 1 1 0 0 1
revision=$revision$
T 4300 100 9 10 1 1 0 0 1
licence=$licence$
T 0 1800 8 10 0 0 0 0 1
device=none
T 0 2000 8 10 0 0 0 0 1
footprint=none
T 0 2200 8 10 0 0 0 0 1
refdes=none

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ha:pcb-rnd-board-v8 {
li:styles {
ha:Signal {
via_proto = 0
thickness = 6.0mil
text_thick = 0.0
text_scale = 100
clearance = 6.0mil
}
ha:Power {
via_proto = 1
thickness = 10.0mil
text_thick = 0.0
text_scale = 100
clearance = 10.0mil
}
ha:Fat {
via_proto = 2
thickness = 80.0mil
text_thick = 0.0
text_scale = 100
clearance = 25.0mil
}
ha:Sig-tight {
via_proto = 3
thickness = 10.0mil
text_thick = 0.0
text_scale = 100
clearance = 12.0mil
}
}
ha:meta {
ha:size {
thermal_scale = 0.500000
x = 100.0mm
y = 100.0mm
}
ha:grid {
spacing = 0.5mm
offs_x = 0.0
offs_y = 0.0
}
}
ha:data {
li:padstack_prototypes {
ha:ps_proto_v6.0 {
hdia=0.3mm; hplated=1; htop=0; hbottom=0;
li:shape {
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=0.6mm; }
ha:combining { }
ha:layer_mask {
copper = 1
top = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=0.6mm; }
ha:combining { }
ha:layer_mask {
bottom = 1
copper = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=0.6mm; }
ha:combining { }
ha:layer_mask {
copper = 1
intern = 1
}
clearance=0.0
}
}
}
ha:ps_proto_v6.1 {
hdia=0.5mm; hplated=1; htop=0; hbottom=0;
li:shape {
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=0.8mm; }
ha:combining { }
ha:layer_mask {
copper = 1
top = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=0.8mm; }
ha:combining { }
ha:layer_mask {
bottom = 1
copper = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=0.8mm; }
ha:combining { }
ha:layer_mask {
copper = 1
intern = 1
}
clearance=0.0
}
}
}
ha:ps_proto_v6.2 {
hdia=1.2mm; hplated=1; htop=0; hbottom=0;
li:shape {
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=3.5mm; }
ha:combining { }
ha:layer_mask {
copper = 1
top = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=3.5mm; }
ha:combining { }
ha:layer_mask {
bottom = 1
copper = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=3.5mm; }
ha:combining { }
ha:layer_mask {
copper = 1
intern = 1
}
clearance=0.0
}
}
}
ha:ps_proto_v6.3 {
hdia=0.8mm; hplated=1; htop=0; hbottom=0;
li:shape {
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=64.0mil; }
ha:combining { }
ha:layer_mask {
copper = 1
top = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=64.0mil; }
ha:combining { }
ha:layer_mask {
bottom = 1
copper = 1
}
clearance=0.0
}
ha:ps_shape_v4 {
ha:ps_circ { x=0.0; y=0.0; dia=64.0mil; }
ha:combining { }
ha:layer_mask {
copper = 1
intern = 1
}
clearance=0.0
}
}
}
}
li:objects {
}
li:layers {
ha:top-sig {
lid=0
group=3
ha:combining { }
ha:attributes {
{pcb-rnd::key::vis}={<Key>l; Shift<Key>t}
{pcb-rnd::key::select}={<Key>l; <Key>t}
}
li:objects {
}
color = {#238b27}
}
ha:bottom-sig {
lid=1
group=10
ha:combining { }
ha:attributes {
{pcb-rnd::key::vis}={<Key>l; Shift<Key>b}
{pcb-rnd::key::select}={<Key>l; <Key>b}
}
li:objects {
}
color = {#38ee39}
}
ha:top-gnd {
lid=2
group=3
ha:combining { }
li:objects {
}
color = {#104e8b}
}
ha:bottom-gnd {
lid=3
group=10
ha:combining { }
li:objects {
}
color = {#6164ff}
}
ha:outline {
lid=4
group=7
ha:combining { }
li:objects {
}
color = {#00868b}
}
ha:bottom-silk {
lid=5
group=12
ha:combining { auto=1; }
ha:attributes {
{pcb-rnd::key::vis}={<Key>l; Shift<Key>x}
{pcb-rnd::key::select}={<Key>l; <Key>x}
}
li:objects {
}
color = {#000000}
}
ha:top-silk {
lid=6
group=1
ha:combining { auto=1; }
ha:attributes {
{pcb-rnd::key::vis}={<Key>l; Shift<Key>s}
{pcb-rnd::key::select}={<Key>l; <Key>s}
}
li:objects {
}
color = {#000000}
}
ha:top-paste {
lid=7
group=0
ha:combining { auto=1; }
li:objects {
}
color = {#cd00cd}
}
ha:top-mask {
lid=8
group=2
ha:combining { sub=1; auto=1; }
li:objects {
}
color = {#ff0000}
}
ha:bottom-mask {
lid=9
group=11
ha:combining { sub=1; auto=1; }
li:objects {
}
color = {#ff0000}
}
ha:bottom-paste {
lid=10
group=13
ha:combining { auto=1; }
li:objects {
}
color = {#cd00cd}
}
ha:slot-plated {
lid=11
group=14
ha:combining { auto=1; }
li:objects {
}
color = {#8b7355}
}
ha:slot-unplated {
lid=12
group=15
ha:combining { auto=1; }
li:objects {
}
color = {#00868b}
}
ha:top-assy {
lid=13
group=16
ha:combining { }
li:objects {
}
color = {#444444}
}
ha:bot-assy {
lid=14
group=17
ha:combining { }
li:objects {
}
color = {#444444}
}
ha:fab {
lid=15
group=18
ha:combining { auto=1; }
li:objects {
}
color = {#222222}
}
ha:top-courtyard {
lid=16
group=8
ha:combining { }
li:objects {
}
color = {#104e8b}
}
ha:bot-courtyard {
lid=17
group=9
ha:combining { }
li:objects {
}
color = {#cd3700}
}
ha:top-pwr {
lid=18
group=3
ha:combining { }
li:objects {
}
color = {#c24744}
}
ha:bottom-pwr {
lid=19
group=10
ha:combining { }
li:objects {
}
color = {#ff5759}
}
}
}
ha:layer_stack {
li:groups {
ha:0 {
name = top_paste
ha:type { top=1; paste=1; }
li:layers { 7; }
}
ha:1 {
name = top_silk
ha:type { silk=1; top=1; }
li:layers { 6; }
}
ha:2 {
name = top_mask
ha:type { top=1; mask=1; }
li:layers { 8; }
}
ha:3 {
name = top_copper
ha:type { copper=1; top=1; }
li:layers { 0; 18; 2; }
}
ha:4 {
name = grp_4
ha:type { substrate=1; intern=1; }
li:layers { }
ha:attributes {
thickness={0.7375mm }
}
}
ha:5 {
name = grp_6
ha:type { substrate=1; intern=1; }
li:layers { }
ha:attributes {
thickness={0.125mm }
}
}
ha:6 {
name = grp_8
ha:type { substrate=1; intern=1; }
li:layers { }
ha:attributes {
thickness={0.7375mm }
}
}
ha:7 {
name = global_outline
ha:type { boundary=1; }
li:layers { 4; }
purpose = uroute
}
ha:8 {
name = top-courtyard
ha:type { top=1; doc=1; }
li:layers { 16; }
ha:attributes {
init-invis=true
}
purpose = ko.courtyard
}
ha:9 {
name = bot-courtyard
ha:type { bottom=1; doc=1; }
li:layers { 17; }
ha:attributes {
init-invis=true
}
purpose = ko.courtyard
}
ha:10 {
name = bottom_copper
ha:type { bottom=1; copper=1; }
li:layers { 1; 19; 3; }
}
ha:11 {
name = bottom_mask
ha:type { bottom=1; mask=1; }
li:layers { 9; }
}
ha:12 {
name = bottom_silk
ha:type { silk=1; bottom=1; }
li:layers { 5; }
}
ha:13 {
name = bottom_paste
ha:type { bottom=1; paste=1; }
li:layers { 10; }
}
ha:14 {
name = pmech
ha:type { mech=1; }
li:layers { 11; }
purpose = proute
}
ha:15 {
name = umech
ha:type { mech=1; }
li:layers { 12; }
purpose = uroute
}
ha:16 {
name = top_assy
ha:type { top=1; doc=1; }
li:layers { 13; }
ha:attributes {
init-invis=1
}
purpose = assy
}
ha:17 {
name = bot_assy
ha:type { bottom=1; doc=1; }
li:layers { 14; }
ha:attributes {
init-invis=1
}
purpose = assy
}
ha:18 {
name = fab
ha:type { top=1; doc=1; }
li:layers { 15; }
ha:attributes {
init-invis=1
}
purpose = fab
}
}
}
li:pcb-rnd-conf-v1 {
ha:overwrite {
ha:design {
via_proto = 1
text_font_id = 0
text_scale = 100
min_slk = 0.15240000 mm
text_thickness = 0
line_thickness = 10.00 mil
ha:drc {
min_ring = 0.15 mm
min_copper_overlap = 6.0 mil
min_drill = 0.3 mm
}
min_wid = 0.15240000 mm
bloat = 0.15240000 mm
clearance = 10.00 mil
}
ha:editor {
grid_unit = mm
grids_idx = 11
grid = 500.00 um
}
ha:rc {
li:library_search_paths {
$(rc.path.design)/coraleda/subc
$(rc.path.design)/coraleda/subc
?../pcblib
?~/pcblib/
$(rc.path.share)/pcblib
}
}
}
}
ha:pixmaps {
}
}

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v 20210626 2
C 0 0 1 0 0 title.sym
{
T 1000 700 5 10 1 1 0 0 1
date=$date$
T 4300 700 5 10 1 1 0 0 1
org=CuVoodoo
T 4300 400 5 10 1 1 0 0 1
authors=King Kévin
T 3000 1200 5 14 1 1 0 4 1
title=TITLE
T 1000 400 5 10 1 1 0 0 1
version=$version$
T 1000 100 5 10 1 1 0 0 1
revision=$revision$
T 4300 100 5 10 1 1 0 0 1
licence=CERN-OHL-S
T 0 1800 5 10 0 0 0 0 1
device=none
T 0 2000 5 10 0 0 0 0 1
footprint=none
}

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0
1