diff --git a/rsim.kicad_pro b/rsim.kicad_pro index 172983d..abcd02e 100644 --- a/rsim.kicad_pro +++ b/rsim.kicad_pro @@ -477,6 +477,30 @@ [ "43fc3289-82a7-492c-a423-3030e10115dc", "" + ], + [ + "d5dac990-0b7a-4f62-8f53-dbf06970abe9", + "serial (USB+UART)" + ], + [ + "e4308a9f-87e7-4a4f-b1f1-ac2c2a217f4e", + "power" + ], + [ + "df84ae28-e731-4d68-9a84-c3604d666e38", + "MCU_ESP32S2" + ], + [ + "691e0eb1-974c-4886-8654-259a57e14a4e", + "MCU_ESP32S3" + ], + [ + "14d0a727-d0b2-42b0-916b-97a48e3bc7f3", + "SIM1" + ], + [ + "f6ddd395-7b3c-45ea-86d0-9bb5f5c50188", + "SIM2" ] ], "text_variables": {} diff --git a/rsim.kicad_sch b/rsim.kicad_sch index 1c8b031..9415024 100644 --- a/rsim.kicad_sch +++ b/rsim.kicad_sch @@ -2,7 +2,7 @@ (uuid 43fc3289-82a7-492c-a423-3030e10115dc) - (paper "A3") + (paper "A5") (title_block (title "rSIM") @@ -11,9317 +11,398 @@ (company "CuVoodoo") (comment 1 "King Kévin") (comment 2 "CERN-OHL-S") + (comment 3 "overview") ) (lib_symbols - (symbol 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- ) - (wire (pts (xy 104.775 150.495) (xy 104.775 154.94)) - (stroke (width 0) (type default)) - (uuid fae9ba47-3892-4c08-94b7-5fe99f4c39bf) - ) - (wire (pts (xy 54.61 57.15) (xy 57.15 57.15)) - (stroke (width 0) (type default)) - (uuid fcd67c0a-80a4-43a5-8789-85fccc76183f) - ) - (wire (pts (xy 47.625 75.565) (xy 50.165 75.565)) - (stroke (width 0) (type default)) - (uuid fd44f46e-1536-42d0-8b37-5dc1518d6fd1) - ) - (wire (pts (xy 233.045 102.235) (xy 233.045 104.775)) - (stroke (width 0) (type default)) - (uuid fdaf3fdf-8786-4076-b006-78d15a62a94e) - ) - (wire (pts (xy 50.8 222.25) (xy 35.56 222.25)) - (stroke (width 0) (type default)) - (uuid feb733c5-4a9f-4627-bd47-1def1846580b) - ) - (wire (pts (xy 316.23 114.935) (xy 314.325 114.935)) - (stroke (width 0) (type default)) - (uuid ffff4d7e-213c-4f14-9aa0-37b85949f970) - ) - - (text "press while booting to\nstart DFU mode\nhold while running to\nerase settings" - (at 102.87 104.14 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 07137c2a-82fc-4367-9b57-b2282e1d5b70) - ) - (text "ESP32-S3:\nhas one UART more than ESP32-S3\nallowing second card emulation\n\nit also adds Bluetooth\nfor possiblt BT SAP feature\n\nbut it's as alterative to S2\nbecause previous PoC uses S2" - (at 271.78 202.565 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 1d43f52e-fa3e-497b-8bfa-2f25bff8b004) - ) - (text "strapping pins:\nIO45, internal pull-down, VDD_SPI = 3.3V\nIO46, internal pull-down, must be 0\nIO0, external pull-up, boot 1=SPI 0=download\n\nIO18: U1RX pull up high to avoid dl error\nIO39-42: JTAG" - (at 210.82 154.94 90) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 3086c913-405d-44bb-ae15-e48165a74b84) - ) - (text "strapping pins:\nIO3, no-pull, JTAG signal 1=USB\nIO45, internal pull-down, VDD_SPI=3.3V\nIO46, internal pull-down, 0 for download\nIO0, internal pull-up, boot 1=SPI 0=download\n\nIO39-42: JTAG" - (at 294.64 153.035 90) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 426d5b37-bfa6-4e23-8b0f-dd1113d0bbd2) - ) - (text "SIM taps:\npin header to attach other tools,\nsuch as logic analyzer." - (at 36.195 197.485 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 4e072ab6-3bb8-49e2-9c90-e8db2d4bbea2) - ) - (text "pulse counter:\nESP32-S2/S3 has only one PCTN\n\nwe use a GPIO for easy clock\nactivation/stop using ISR,\ninstead of shared with PCTN\n\npulse counter control signals:\n- 1x LED controller output per precise periodic pulse\n- 1x GPIO IST input to detect end of pulse\n- 1x PCTN input to gate pulse counter" - (at 187.325 230.505 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 61452891-f29f-4426-9688-520d01aa3e6f) - ) - (text "press to\nreset MCU" (at 103.505 61.595 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 7b121296-c9c1-48d6-aaa3-df4e1b0c4219) - ) - (text "L=DL" (at 40.64 73.66 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 82abccea-b395-4e68-ae46-d1b5079e3a51) - ) - (text "UART:\nwe alway use UART0 for debuging\ndisabling it, including boot log, is not used\n\nESP32-S2 has 2 UARTs, allowing to simulate only one SIM\nESP32-S3 has 3 UARTs, allowing to simulate a second SIM\n\ndon't use UART1 pins IO17/IO18,\nso we can disable pins using GPIO matrix\nUART2 has no dedicated pins\n\nUART TX/RX could be shared, but requires more code\nESP32 has no half-duplex handling" - (at 187.325 204.47 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 98e0f0f6-b22a-4ccb-bea8-1da05d42d40c) - ) - (text "ADC:\nmax. volage is Vref = 1.1V (1.0-1.2V)\nwith 11dB attenuation it's 2.6V" - (at 271.78 212.725 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid a61c8d68-49fb-48f3-b494-11198a497bb5) - ) - (text "kOhm=mA\n1.2=1000\n2=580\n3=400\n4=300\n5=250\n10=130" (at 194.31 50.8 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid b4e52796-7998-4d4b-8f96-ccdc09bedfc1) - ) - (text "press while booting to\nstart ESP download mode" (at 103.505 81.28 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid c6d66edd-9b70-48eb-88ec-162d375b1131) - ) - (text "level shifting:\nSIM cards can operate at several voltages,\nnamed classes:\nA = 5.0V, B = 3.0V, C = 1.8V, D = 1.2V.\nthe MCU only operates at 3.3V,\nthus we need level shifters.\nI/O is a bi-directional signal,\nothers are uni-directional.\nI could not find any bi-directional\nlevel shifter with auto-direction\ndetection that can handle\nhigher and lower voltages on side B.\nthis is why we use translators with a direction pin.\nwe re-use this part for uni-directional signal\nto consolidate part counts\n" - (at 130.81 199.39 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid cf097806-3f62-439f-b1ea-71c5b1a41d0b) - ) - (text "H=ON" (at 69.85 73.66 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid e0454526-bf66-4e30-9491-a63ee217fcba) - ) - (text "min. 0.5A" (at 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44.45 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 6a33fb99-0aad-4ee6-9c23-16a612d44c7e) + ) + (text "pulse counter:\nESP32 has only one PCTN\n\nwe use a GPIO for easy clock\nactivation/stop using ISR,\ninstead of shared with PCTN\n\npulse counter control signals:\n- 1x LED controller output for precise periodic pulse\n- 1x GPIO interrupt input to detect end of pulse\n- 1x PCTN input to gate pulse counter" + (at 144.145 99.695 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 7010e21e-e788-4be1-b425-1c537026c6af) + ) + (text "press to\nreset MCU" (at 126.365 24.765 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 76d935ea-040f-407e-8620-850617f50768) + ) + (text "press while booting to\nstart DFU mode\nhold while running to\nerase settings" + (at 125.73 67.31 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid a7602ef7-b5c9-47be-afb6-b2c2b70f5837) + ) + (text "ADC:\nmax. volage is Vref = 1.1V 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