From 142e59867df18c5ce060d72baf230e478eef0a34 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?King=20K=C3=A9vin?= Date: Fri, 3 Feb 2023 11:12:55 +0100 Subject: [PATCH] sch: started draft (card signal to esp missing) --- rsim.kicad_pro | 40 +- rsim.kicad_sch | 7941 +++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 7966 insertions(+), 15 deletions(-) diff --git a/rsim.kicad_pro b/rsim.kicad_pro index 3ecedb5..172983d 100644 --- a/rsim.kicad_pro +++ b/rsim.kicad_pro @@ -1,5 +1,6 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { "board_outline_line_width": 0.049999999999999996, @@ -130,7 +131,8 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -314,18 +316,23 @@ "rule_severities": { "bus_definition_conflict": "error", "bus_entry_needed": "error", - "bus_label_syntax": "error", "bus_to_bus_conflict": "error", "bus_to_net_conflict": "error", + "conflicting_netclasses": "error", "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -335,6 +342,7 @@ "pin_to_pin": "warning", "power_pin_not_driven": "error", "similar_labels": "warning", + "simulation_model_issue": "error", "unannotated": "error", "unit_value_mismatch": "error", "unresolved_variable": "error", @@ -346,13 +354,13 @@ "pinned_symbol_libs": [] }, "meta": { - "filename": "template.kicad_pro", + "filename": "rsim.kicad_pro", "version": 1 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -366,10 +374,10 @@ "track_width": 0.2, "via_diameter": 0.6, "via_drill": 0.3, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -378,16 +386,15 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Thick", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.5, "via_diameter": 0.8, "via_drill": 0.4, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.15, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -396,19 +403,20 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Thin", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.15, "via_diameter": 0.5, "via_drill": 0.3, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 3 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [] }, "pcbnew": { "last_paths": { @@ -424,6 +432,8 @@ "schematic": { "annotate_start_num": 0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -455,7 +465,11 @@ "page_layout_descr_file": "", "plot_directory": "", "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_voltages": false, "subpart_first_id": 65, "subpart_id_separator": 0 }, diff --git a/rsim.kicad_sch b/rsim.kicad_sch index 39d5e82..11c98ca 100644 --- a/rsim.kicad_sch +++ b/rsim.kicad_sch @@ -1,8 +1,8 @@ -(kicad_sch (version 20211123) (generator eeschema) +(kicad_sch (version 20230121) (generator eeschema) (uuid 43fc3289-82a7-492c-a423-3030e10115dc) - (paper "A4") + (paper "A3") (title_block (date "$date$") @@ -13,8 +13,7945 @@ ) (lib_symbols + (symbol "Connector_Audio:AudioJack3" (in_bom yes) (on_board yes) + (property "Reference" "J7" (at -1.905 7.62 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "AudioJack3" (at -1.905 5.08 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "~" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_keywords" "audio jack receptacle stereo headphones phones TRS connector" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_description" "Audio Jack, 3 Poles (Stereo / TRS)" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "Jack*" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "AudioJack3_0_1" + (rectangle (start -5.08 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(wire (pts (xy 50.8 222.25) (xy 35.56 222.25)) + (stroke (width 0) (type default)) + (uuid feb733c5-4a9f-4627-bd47-1def1846580b) + ) + + (text "press while booting to\nstart DFU mode\nhold while running to\nerase settings" + (at 102.87 103.505 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 07137c2a-82fc-4367-9b57-b2282e1d5b70) + ) + (text "ESP32-S3:\nhas one UART more than ESP32-S3\nallowing second card emulation\n\nit also adds Bluetooth\nfor possiblt BT SAP feature\n\nbut it's as alterative to S2\nbecause previous PoC uses S2" + (at 314.96 196.85 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 1d43f52e-fa3e-497b-8bfa-2f25bff8b004) + ) + (text "ESP32S2 strapping pins:\nIO45, internal pull-down, VDD_SPI = 3.3V\nIO46, internal pull-down, must be 0\nIO0, external pull-up, boot 1=SPI 0=download" + (at 205.105 155.575 90) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 3086c913-405d-44bb-ae15-e48165a74b84) + ) + (text "ESP32S3 strapping pins:\nIO3, no-pull, JTAG signal 1=USB\nIO45, internal pull-down, VDD_SPI=3.3V\nIO46, internal pull-down, 0 for download\nIO0, internal pull-up, boot 1=SPI 0=download" + (at 290.195 153.035 90) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 426d5b37-bfa6-4e23-8b0f-dd1113d0bbd2) + ) + (text "pulse counter:\nESP32-S2/S3 has only one PCTN\n\nwe use a GPIO for easy clock\nactivation/stop using ISR,\ninstead of shared with PCTN\n\npulse counter control signals:\n- 1x LED controller output per precise periodic pulse\n- 1x GPIO IST input to detect end of pulse\n- 1x PCTN input to gate pulse counter" + (at 252.095 201.295 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 61452891-f29f-4426-9688-520d01aa3e6f) + ) + (text "press to\nreset MCU" (at 103.505 69.215 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 7b121296-c9c1-48d6-aaa3-df4e1b0c4219) + ) + (text "L=DL" (at 40.64 73.66 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 82abccea-b395-4e68-ae46-d1b5079e3a51) + ) + (text "UART:\nwe alway use UART0 for debuging\ndisabling it, including boot log, is not used\n\nESP32-S2 has 2 UARTs, allowing to simulate only one SIM\nESP32-S3 has 3 UARTs, allowing to simulate a second SIM\n\ndon't use UART1 pins IO17/IO18,\nso we can disable pins using GPIO matrix\nUART2 has no dedicated pins\n\nUART TX/RX could be shared, but requires more code\nESP32 has no half-duplex handling" + (at 187.96 205.105 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 98e0f0f6-b22a-4ccb-bea8-1da05d42d40c) + ) + (text "ADC:\nmax. volage is Vref = 1.1V (1.0-1.2V)\nwith 11dB attenuation it's 2.6V" + (at 252.095 211.455 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid a61c8d68-49fb-48f3-b494-11198a497bb5) + ) + (text "kOhm=mA\n1.2=1000\n2=580\n3=400\n4=300\n5=250\n10=130" (at 194.31 50.8 0) + (effects (font (size 1.27 1.27)) (justify left bottom)) + (uuid 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